Diode device and method of manufacturing the same

Abstract

The application provides a diode device and a manufacturing method thereof. The diode device comprises a frame, a chip set and a connecting piece. The chip set comprises at least two chips stacked in a stacking direction, and the chip set is connected to the frame on one side in the stacking direction. The chip comprises a first end face and a second end face opposite to each other in the stacking direction. The polarities of the first end face and the second end face are opposite, and the areas of the first end face and the second end face are different. The connecting piece is connected between each two chips in the chip set. The connecting piece comprises a first surface and a second surface opposite to each other in the stacking direction. The first surface is connected to the first end face of one chip of the two chips, and the second surface is connected to the second end face of the other chip of the two chips. The area of the first surface matches the area of the first end face, and the area of the second surface matches the area of the second end face. According to the embodiment of the application, the connection firmness of the series-connected chips in the diode device can be effectively improved, and the resistance of the series-connected chips can be reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a diode device and a method for manufacturing the same. Background Technology

[0002] A diode is an electronic device made of semiconductor materials. With the advancement of technology and the development of information science, the market demands for diodes are increasing. They are often used in high-voltage circuits. However, current diodes are generally made of a single chip or two chips connected in parallel, which has insufficient voltage withstand capability. When used in high-voltage circuit structures, diodes are easily broken down.

[0003] The current conventional solution is to connect the internal chips of a diode device in series using a conductive metal. However, the anode and cathode terminals of the chip have different area sizes, and the contact area between the conductive metal and the chip depends on the smaller of the anode and cathode areas. This results in suboptimal contact area, leading to higher resistance in the series connection, weaker connections, and a risk of breakage at the connection points. Therefore, improvements to diode devices are urgently needed. Summary of the Invention

[0004] In view of the above problems, this application provides a diode device and a method for manufacturing the same, which can effectively improve the connection strength of series chips in the diode device and reduce the resistance of series chips.

[0005] In a first aspect, embodiments of this application provide a diode device, including a frame, a chipset, and a connector. The chipset includes at least two chips stacked together. One side of the chipset along the stacking direction is connected to the frame. Each chip includes a first end face and a second end face opposite to each other along the stacking direction. The first end face and the second end face have opposite polarities and different areas. The connector connects two adjacent chips in the chipset. The connector includes a first surface and a second surface opposite to each other along the stacking direction. The first surface is connected to the first end face of one of the two chips, and the second surface is connected to the second end face of the other chip. The area of ​​the first surface matches the area of ​​the first end face, and the area of ​​the second surface matches the area of ​​the second end face.

[0006] In some embodiments of the first aspect, along the stacking direction, the orthographic projection area of ​​the first surface on the frame is smaller than the orthographic projection area of ​​the first end face on the frame, and the orthographic projection area of ​​the second surface on the frame is larger than the orthographic projection area of ​​the second end face on the frame.

[0007] In some embodiments of the first aspect, the connector includes a base and a boss, the boss protruding from one side surface of the base in the stacking direction, the side surface of the boss away from the base being configured as a first surface, and the side surface of the base away from the boss being configured as a second surface.

[0008] In some embodiments of the first aspect, along the stacking direction, the first thickness dimension h1 of the substrate and the second thickness dimension h2 of the boss satisfy the relationship: h1≤h2.

[0009] In some embodiments of the first aspect, the second thickness dimension h2 satisfies: 0.1mm ≤ h2 ≤ 0.25mm.

[0010] In some embodiments of the first aspect, the base and the boss are integrally formed.

[0011] In some embodiments of the first aspect, both the first and second surfaces are coated with a metal adhesive layer having weld affinity.

[0012] In some embodiments of the first aspect, the frame includes a base plate, a first pin, and a second pin. One end of the chipset along the stacking direction is connected to the base plate, and the other end is connected to the first pin via a conductive element. The second pin is connected to the base plate.

[0013] In some embodiments of the first aspect, the conductive element is a sheet-like structure.

[0014] Secondly, embodiments of this application provide a method for manufacturing a diode device, the method comprising:

[0015] A chip is provided with a first end face and a second end face with opposite polarities and unequal areas, and the first end face of the chip is connected to a frame;

[0016] A connector is provided, and the second surface of the connector is connected to the second end face of the chip, wherein the area of ​​the second end face of the chip matches the area of ​​the second surface;

[0017] A first end face of another chip is connected to a first surface of a connector, wherein the area of ​​the first end face of the other chip matches the area of ​​the first surface.

[0018] The diode device and its manufacturing method provided in this application connect chips in series using connectors. The area of ​​the first surface of the connector matches the area of ​​the first end face of the chip, and the area of ​​the second surface of the connector matches the area of ​​the second end face of the chip, so as to maximize the contact area between the chip and the connector, thereby effectively improving the connection strength of the series chips in the diode device and reducing the resistance of the series chips.

[0019] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0020] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0021] Figure 1 This is a schematic diagram of the structure of a diode device provided in some embodiments of this application;

[0022] Figure 2 for Figure 1 A schematic diagram of the AA cross-sectional structure;

[0023] Figure 3 A schematic diagram of the structure of a diode device chip provided in some embodiments of this application;

[0024] Figure 4 This is a schematic diagram of the structure of a connector for a diode device provided in some embodiments of this application;

[0025] Figure 5 This is a schematic diagram of the structure of another diode device provided in some embodiments of this application;

[0026] Figure 6 This is a schematic flowchart illustrating a method for manufacturing a diode device according to some embodiments of this application.

[0027] The reference numerals in the detailed embodiments are as follows:

[0028] 10. Frame; 11. Base plate; 12. First pin; 13. Second pin; 20. Chipset; 21. Chip; 21a. First chip; 21b. Second chip; 211. First end face; 212. Second end face; 30. Connector; 31. First surface; 32. Second surface; 301. Substrate; 302. Boss; 40. Conductive component; 50. Insulating component; X. Stacking direction. Detailed Implementation

[0029] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0030] It should be noted that, unless otherwise stated, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by those skilled in the art to which the embodiments of this application pertain.

[0031] In the description of the embodiments in this application, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", and "bottom" are used.

[0032] The orientations or positional relationships indicated by terms such as "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", and "circumferential" are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the purpose of facilitating the description of the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0033] Furthermore, technical terms such as "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. In the description of the embodiments of this application, "a plurality of" means two or more, unless otherwise explicitly defined.

[0034] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0035] In the description of the embodiments of this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0036] A diode is an electronic device made of semiconductor materials. With the advancement of technology and the development of information science, the market demands for diodes are increasing. They are often used in high-voltage circuits. However, current diodes are generally made of a single chip or two chips connected in parallel, which has insufficient voltage withstand capability. When used in high-voltage circuit structures, diodes are easily broken down.

[0037] The inventors of this application have noted that the conventional solution is to connect the internal chips of a diode device in series using a conductive metal. However, the anode and cathode terminals of the chip have different areas, and the contact area between the conductive metal and the chip depends on the smaller of the anode and cathode terminals. This results in suboptimal contact area, leading to higher resistance in the series connection, weak connections, and a risk of breakage at the connection points. Therefore, improvements to diode devices are urgently needed.

[0038] The inventors of this application have discovered that a connector with a special shape can be designed to connect chips in series. The area of ​​the first surface of the connector matches the area of ​​the first end face of the chip, and the area of ​​the second surface of the connector matches the area of ​​the second end face of the chip, so as to maximize the contact area between the chip and the connector, thereby effectively improving the connection strength of series chips in diode devices and reducing the resistance of series chips.

[0039] To address the problems of the prior art, embodiments of this application provide a diode device that can effectively improve the connection strength of series-connected chips and reduce the resistance of the series-connected chips. The diode device provided in this application embodiment is described below.

[0040] Figure 1 This is a schematic diagram of the structure of a diode device provided in some embodiments of this application. Figure 2 for Figure 1 A schematic diagram of the AA cross-sectional structure. Figure 3 This is a schematic diagram of the structure of a diode device chip provided in some embodiments of this application. Figure 4 This is a schematic diagram of the structure of a connector for a diode device provided in some embodiments of this application.

[0041] like Figure 1 and Figure 4As shown in the figure, this application provides a diode device, which includes a frame 10, a chipset 20, and a connector 30. The chipset 20 includes at least two stacked chips 21. The chipset 20 is connected to the frame 10 on one side along the stacking direction X of the chips. Each chip 21 includes a first end face 211 and a second end face 212 that are opposite to each other along the stacking direction X. The first end face 211 and the second end face 212 have opposite polarities and different areas. The connector 30 connects two adjacent chips 21 in the chipset 20. The connector 30 includes a first surface 31 and a second surface 32 that are opposite to each other along the stacking direction X. The first surface 31 is connected to the first end face 211 of one of the two chips 21, and the second surface 32 is connected to the second end face 212 of the other chip 21. The area of ​​the first surface 31 matches the area of ​​the first end face 211, and the area of ​​the second surface 32 matches the area of ​​the second end face 212.

[0042] The frame 10 is used to fix the chip 21, provide space for the chip 21 to be installed, and provide an environment for the chip 21 to connect to external circuits. It also provides heat dissipation. The frame 10 can be made of a metal material, such as copper. Copper can conduct heat generated by the chip 21 during operation, reduce the internal temperature of the structure, and ensure normal operation.

[0043] Chipset 20 includes at least two chips 21 stacked together. Exemplarily, the number of chips 21 in chipset 20 may be, but is not limited to, two, three, or four. This application embodiment does not limit the specific number of chips 21 in chipset 20, and the number can be selected according to the actual situation.

[0044] Chip 21 includes a first end face 211 and a second end face 212 facing away from each other along the stacking direction X. The first end face 211 and the second end face 212 have opposite polarities and different areas. For example, the first end face 211 of chip 21 is the cathode end face and the second end face 212 is the anode end face. An insulating member 50 is disposed around the anode end face of chip 21 to isolate the anode end face from the cathode end face, so as to prevent short circuit between the anode end face and the cathode end face of chip 21. Thus, the area of ​​the anode end face of chip 21 is smaller than the area of ​​the cathode end face.

[0045] Connector 30 is connected between every two chips 21 in chipset 20 to connect every two chips 21 in series. Connector 30 may be made of a metal material, such as copper. To more clearly describe the embodiments of this application, an example is given where chipset 20 includes two chips 21, namely, chipset 20 includes a first chip 21a and a second chip 21b. It should be noted that technical terms such as "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0046] For example, the connector 30 includes a first surface 31 and a second surface 32 facing away from each other along the stacking direction X. The first surface 31 is connected to the first end face 211 of the first chip 21a in the chipset 20, and the second surface 32 is connected to the second end face 212 of the second chip 21b in the chipset 20. The area of ​​the first surface 31 matches the area of ​​the first end face 211, so that the contact area between the first surface 31 of the connector 30 and the first end face 211 of the chip 21 achieves an optimal effect; the area of ​​the second surface 32 matches the area of ​​the second end face 212, so that the contact area between the second surface 32 of the connector 30 and the second end face 212 of the chip 21 achieves an optimal effect. That is, the matching of the area of ​​the first surface 31 with the area of ​​the first end face 211 and the matching of the area of ​​the second surface 32 with the area of ​​the second end face 212 maximizes the contact area between the chip 21 and the connector 30. It is understandable that when the chipset 20 includes multiple chips 21, the specific connection method between the connector and the chip 21 is the same as the above scheme, and will not be repeated here for the sake of simplicity.

[0047] In the above technical solution, the chips 21 are connected in series by the connector 30. The area of ​​the first surface 31 of the connector 30 matches the area of ​​the first end face 211 of the chip 21, and the area of ​​the second surface 32 of the connector 30 matches the area of ​​the second end face 212 of the chip 21, so as to maximize the contact area between the chip 21 and the connector 30, thereby effectively improving the connection strength of the series chips 21 in the diode device and reducing the resistance of the series chips 21.

[0048] In some embodiments, along the stacking direction X, the orthographic projection area of ​​the first surface 31 on the frame 10 is greater than the orthographic projection area of ​​the first end face 211 on the frame 10, and the orthographic projection area of ​​the second surface 32 on the frame 10 is less than the orthographic projection area of ​​the second end face 212 on the frame 10.

[0049] As shown above, the first surface 31 of the connector 30 is connected to the first end face 211 of the chip 21, and the first end face 211 is the cathode end face. The second surface 32 of the connector 30 is connected to the second end face 212 of the chip 21, and the second end face 212 is the anode end face. An insulating member 50 is provided around the anode end face, and the area of ​​the anode end face is smaller than the area of ​​the cathode end face.

[0050] In this embodiment of the application, along the stacking direction X, the orthographic projection area of ​​the first surface 31 of the connector 30 on the frame 10 is greater than the orthographic projection area of ​​the first end face 211 of the chip 21 on the frame 10. That is, the area of ​​the first surface 31 of the connector 30 is greater than the area of ​​the cathode end face of the chip 21, which enables the cathode end face of the chip 21 to have the largest contact area after being connected to the connector 30.

[0051] Along the stacking direction X, the projected area of ​​the second surface 32 of the connector 30 on the frame 10 is smaller than the projected area of ​​the second end face 212 of the chip 21 on the frame 10. That is, the area of ​​the second surface 32 of the connector 30 is smaller than the area of ​​the anode end face of the chip 21. After the connector 30 is connected to the anode end face of the chip 21, it can prevent the connector 30 from contacting the insulating member 50 around the anode end face, thereby reducing the occurrence of short circuits between the cathode end face and the anode end face of a single chip 21.

[0052] In the above technical solution, by setting the area of ​​the first surface 31 of the connector 30 to be larger than the area of ​​the first end face 211 of the chip 21, and setting the area of ​​the second surface 32 of the connector 30 to be smaller than the area of ​​the anode end face of the chip 21, the chip 21 can achieve the maximum contact area after being connected in series. At the same time, it can reduce the occurrence of short circuits between the cathode end face and the anode end face of a single chip 21.

[0053] In some embodiments, the connector 30 includes a base 301 and a boss 302. The boss 302 protrudes from one side surface of the base 301 along the stacking direction X. The side surface of the base 301 away from the boss 302 is configured as a first surface 31, and the side surface of the boss 302 away from the base 301 is configured as a second surface 32.

[0054] In this embodiment, both the base 301 and the boss 302 can be plate-like structures, and the connection method between the base 301 and the boss 302 can be, but is not limited to, welding or bonding. The specific shape of the orthographic projection of the base 301 and the boss 302 along the thickness direction of the frame 10 can be rectangular, circular, or triangular, etc.

[0055] The surface of the substrate 301 away from the boss 302 is configured as the first surface 31, and the surface of the boss 302 away from the substrate 301 is configured as the second surface 32. This technical solution allows for flexible adjustment of the area of ​​the first surface 31 and the second surface 32 of the connector 30, thereby facilitating the fabrication of the connector 30 and also facilitating the installation between the connector 30 and the chip 21.

[0056] In some alternative embodiments, the base 301 and the boss 302 are integrally formed structures.

[0057] The connector 30 is manufactured using a one-piece molding process, resulting in a monolithic structure between the base 301 and the boss 302. This simplifies the manufacturing process by eliminating the need for additional welding or bonding processes to connect the base 301 and the boss 302. Furthermore, compared to welding or bonding, the monolithic structure of the base 301 and the boss 302 provides a stronger connection, thereby enhancing the overall structural strength of the connector 30.

[0058] In the above technical solution, by integrally forming the base 301 and the boss 302 of the connector 30, not only can the manufacturing process of the connector 30 be simplified, but the overall structural strength of the connector 30 can also be improved, thereby further improving the connection firmness of the series chip 21 in the diode device.

[0059] In some embodiments, along the stacking direction X, the first thickness dimension h1 of the substrate 301 and the second thickness dimension h2 of the boss 302 satisfy the relationship: h1≤h2.

[0060] As shown above, an insulating element 50 is provided around the anode end face of chip 21. The insulating element 50 is used to isolate the anode end face from the cathode end face to prevent short circuit between the anode end face and the cathode end face of chip 21.

[0061] Understandably, the boss 302 is located between the substrate 301 and the chip 21, and the boss 302 can act as a spacer between the substrate 301 and the chip 21. Thus, the larger the second thickness dimension h2 of the boss 302 along the stacking direction X, the less likely the substrate 301 is to come into contact with the insulating member 50, thereby further reducing the occurrence of short circuits between the cathode and anode of a single chip 21.

[0062] In the above technical solution, along the stacking direction X, the second thickness dimension h2 of the boss 302 is greater than or equal to the first thickness dimension h1 of the substrate 301. Without changing the overall thickness of the connector 30, the boss 302 can have a larger dimension along the stacking direction X, while the substrate 301 can have a smaller dimension along the stacking direction X. This can further reduce the occurrence of short circuits between the cathode and anode of a single chip 21 while reducing the overall thickness of the series-connected chips 21.

[0063] In some embodiments, the second thickness dimension h2 satisfies: 0.1mm ≤ h2 ≤ 0.25mm.

[0064] In the above embodiments, the second thickness dimension h2 of the boss 302 can be understood as the thickness of the boss 302 along the stacking direction X. The second thickness dimension h2 of the boss 302 is set within the above range, which can further reduce the occurrence of short circuit between the cathode end face and the anode end face of a single chip 21, thereby improving the stability of the series-connected chips 21.

[0065] For example, the second thickness dimension h2 of the boss 302 may be, but is not limited to, 0.1mm, 0.15mm, 0.2mm, or 0.25mm.

[0066] In some embodiments, both the first surface 31 and the second surface 32 are coated with a metal adhesive layer, which has solder affinity.

[0067] The metal adhesive layer has solder affinity, which can be understood as the metal adhesive layer having the property of being able to bond with the soldering material. The metal adhesive layer and the soldering material are easy to bond during the soldering process, thereby effectively improving the connection strength between the connector 30 and the chip 21.

[0068] In some embodiments, the metal adhesive layer is a titanium-nickel-silver alloy layer. The nickel-silver alloy has good adhesive and electrical properties, which can provide good connection performance for the series connection of the chips 21.

[0069] Figure 5 This is a schematic diagram of the structure of another diode device provided in some embodiments of this application.

[0070] Continue to refer to Figure 5 In some embodiments, the frame 10 includes a base plate 11, a first pin 12 and a second pin 13. One end of the chipset 20 along the stacking direction X is connected to the base plate 11, and the other end is connected to the input terminal of the first pin 12 through a conductive element 40. The input terminal of the second pin 13 is connected to the base plate 11.

[0071] The base plate 11 of the frame 10 is used to fix the chip 21 and provide space for the chip 21 to be installed, while also providing heat dissipation. The shape of the base plate 11 can be, but is not limited to, square, circular, or triangular. The base plate 11 can be made of a metal material, such as copper, which can better conduct the heat generated by the chip 21 during operation, reduce the internal temperature of the structure, and ensure normal operation.

[0072] The first pin 12 and the second pin 13 are used to provide an environment for the chip 21 to connect to external circuits. One end of the chipset 20 along the stacking direction X is connected to the base plate 11, and the other end is connected to the input terminal of the first pin 12 through a conductive element 40. Exemplarily, the chipset 20 includes at least two chips 21 stacked in series. To more clearly describe the embodiments of this application, the chipset 20 is described as including two chips 21. The first end face 211 of the first chip 21a is connected to the base plate 11, the first end face 211 of the second chip 21b is connected to the second end face 212 of the first chip 21a through a connector 30, and the second end face 212 of the second chip 21b is connected to the input terminal of the first pin 12 through a conductive element 40.

[0073] The conductive element 40 is used to establish an electrical connection between the chip 21 and the input terminal of the first pin 12. Optionally, the conductive element 40 may be made of a metal material with conductive properties, which may be, but is not limited to, copper, aluminum, or silver.

[0074] The input terminal of the second pin 13 is connected to the base plate 11, and the first end face 211 of the first chip 21a is connected to the base plate 11. Thus, the first end face 211 of the first chip 21a is electrically connected to the input terminal of the second pin 13. In this embodiment, the first end face 211 is the cathode end face, and the second end face 212 is the anode end face. Through the above-described connection relationship between the chipset 20, the base plate 11, the first pin 12, and the second pin 13, the anode end face of the chipset 20 is electrically connected to the input terminal of the first pin 12, and the cathode end face of the chipset 20 is electrically connected to the input terminal of the second pin 13.

[0075] In some alternative embodiments, the conductive element 40 is a sheet structure. Compared to the connection between the chip 21 and the first pin 12 via a metal wire, the contact area at the connection between the sheet structure and the chip 21 and the connection between the sheet structure and the first pin 12 is larger. This can reduce the resistance after the chip 21 and the first pin 12 are connected, improve the stability of the connection between the chip 21 and the first pin 12, and improve the surge capability of the chip 21, thus ensuring the stability of the diode device.

[0076] Figure 6 This is a schematic flowchart illustrating a method for manufacturing a diode device according to some embodiments of this application.

[0077] Continue to refer to Figure 6 Based on the diode device provided in the above embodiments of this application, this application also provides a method for manufacturing a diode device. The method for manufacturing a diode device can be applied to the diode device described in the embodiments of this application. The method for manufacturing a diode device includes steps 110 to 130.

[0078] Step 110: Provide a chip 21 having a first end face 211 with opposite polarities and a second end face 212 with different areas, and connect the first end face 211 of the chip 21 to the frame 10.

[0079] Step 120: Provide a connector 30 and connect the second surface 32 of the connector 30 to the second end face 212 of the chip 21, wherein the area of ​​the second end face 212 of the chip 21 matches the area of ​​the second surface 32;

[0080] Step 130, providing a first end face 211 of another chip 21 connected to a first surface 31 of the connector 30, wherein the area of ​​the first end face 211 of the other chip 21 matches the area of ​​the first surface 31.

[0081] In this embodiment, the chipset 20 includes at least two chips 21. Exemplarily, the chips 21 in the chipset 20 may be, but are not limited to, two, three, or four, etc. This embodiment does not limit the specific number of chips 21 in the chipset 20; the number can be selected according to actual circumstances. To more clearly describe this embodiment, we will use a chipset 20 including two chips 21 as an example, that is, the chipset 20 includes a first chip 21a and a second chip 21b. It should be noted that the technical terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0082] Exemplarily, solder is applied to the frame 10, wherein the solder can be solder paste. The first end face 211 of the first chip 21a is soldered to the frame 10. The first end face 211 can be the cathode end face. Solder is applied to the second end face 212 of the first chip 21a, and the second surface 32 of the connector 30 is soldered to the second end face 212 of the first chip 21a, wherein the second end face 212 can be the anode end face. Solder is applied to the first surface 31 of the connector 30, and the first surface 31 of the second chip 21b is soldered to the first surface 31 of the connector 30. Thus, the first chip 21a and the second chip 21b are connected in series via the connector 30, with the first end face 211 of the first chip 21a serving as the cathode end face of the chip group 20, and the second end face 212 of the second chip 21b serving as the anode end face of the chip group 20. In this embodiment, the second end face 212 of the second chip 21b is connected to the first pin 12 of the frame 10 via a conductive member 40. It is understandable that when the chipset 20 includes multiple chips 21, the specific connection method between the connector and the chip 21 is the same as the above scheme, and will not be repeated here for the sake of simplicity.

[0083] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other.

[0084] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application, and they should all be covered within the scope of the claims and specification of this application. In particular, as long as there is no structural conflict, the various technical features mentioned in the embodiments can be combined in any way. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A diode device, characterized in that, include: frame; A chipset includes at least two chips stacked together. The chipset is connected to the frame on one side along the stacking direction of the chips. Each chip includes a first end face and a second end face opposite to each other along the stacking direction. The first end face and the second end face have opposite polarities and different areas. A connector is provided between two adjacent chips in the chipset. The connector includes a first surface and a second surface that are opposite to each other along the stacking direction. The first surface is connected to a first end face of one of the two chips, and the second surface is connected to a second end face of the other chip. The area of ​​the first surface matches the area of ​​the first end face, and the area of ​​the second surface matches the area of ​​the second end face. Wherein, along the stacking direction, the orthographic projection area of ​​the first surface on the frame is greater than the orthographic projection area of ​​the first end face on the frame, and the orthographic projection area of ​​the second surface on the frame is smaller than the orthographic projection area of ​​the second end face on the frame; The connector includes a base and a boss, the boss protruding from one side surface of the base along the stacking direction, the side surface of the boss away from the base being configured as the first surface, and the side surface of the base away from the boss being configured as the second surface.

2. The diode device according to claim 1, characterized in that, Along the stacking direction, the first thickness dimension h1 of the substrate and the second thickness dimension h2 of the boss satisfy the relationship: h1≤h2.

3. The diode device according to claim 2, characterized in that, The second thickness dimension h2 satisfies: 0.1mm≤h2≤0.25mm.

4. The diode device according to claim 1, characterized in that, The base and the boss are integrally formed.

5. The diode device according to claim 1, characterized in that, Both the first and second surfaces are coated with a metal adhesive layer, which has weld affinity.

6. The diode device according to claim 1, characterized in that, The frame includes a base plate, a first pin, and a second pin. One end of the chipset along the stacking direction is connected to the base plate, and the other end is connected to the first pin through a conductive element. The second pin is connected to the base plate.

7. The diode device according to claim 6, characterized in that, The conductive element is a sheet-like structure.

8. A method for manufacturing a diode device, characterized in that, The method for manufacturing a diode device as described in any one of claims 1-7 comprises: A chip is provided having a first end face and a second end face with opposite polarities and unequal areas, and the first end face of the chip is connected to a frame; A connector is provided, and a second surface of the connector is connected to a second end face of the chip, wherein the area of ​​the second end face of the chip matches the area of ​​the second surface; A first end face of another chip is provided to be connected to a first surface of the connector, wherein the area of ​​the first end face of the other chip matches the area of ​​the first surface.

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