Sensor array substrate motherboard, array substrate and manufacturing method, and piezoelectric device

Abstract

The present application provides an array substrate motherboard, an array substrate and a manufacturing method, and a piezoelectric device of a sensor. The array substrate motherboard includes an array substrate area and a peripheral area surrounding the array substrate area. The array substrate area includes a base substrate and multiple groups of thin film transistors, each group of thin film transistors includes at least a reset thin film transistor, a switch thin film transistor, a signal amplification thin film transistor and a reading thin film transistor; a plurality of ITO overlap blocks are arranged in a direction away from the base substrate; each ITO overlap block is electrically connected to the source or drain of the reset thin film transistor or the switch thin film transistor; a plurality of polarization pads located on the first side of the base substrate are arranged in the peripheral area of ​​the array substrate area; the ITO overlap block is electrically connected to the polarization pad and grounded; the array substrate area also includes a piezoelectric layer and an emitting electrode arranged in sequence along a direction away from the base substrate, the piezoelectric layer and the emitting electrode cover the thin film transistors in the sensing area, and the emitting electrode is used to be electrically connected to a high voltage power supply to polarize the piezoelectric layer.

Description

Technical Field

[0001] The present invention relates to the technical field of ultrasonic imaging piezoelectric sensors, and in particular to an array substrate motherboard of a sensor, an array substrate and a manufacturing method, and a piezoelectric device. Background Art

[0002] Ultrasonic imaging is a technology that uses ultrasonic sound beams to scan the human body and obtain images of organs in the body by receiving and processing reflected signals. Ultrasonic imaging piezoelectric sensors are key components for realizing ultrasonic imaging technology. After ultrasonic waves are emitted into the human body, they will be reflected and refracted when they encounter interfaces in the body, and may be absorbed and attenuated in human tissues. Because the morphology and structure of various tissues in the human body are different, their degree of reflection, refraction and absorption of ultrasonic waves are also different. After receiving these different vibration signals, the piezoelectric sensor can convert them into different electrical signals, and after processing, a visual image can be obtained.

[0003] The ultrasonic imaging piezoelectric sensor mainly includes a TFT backplane, a receiving electrode, a piezoelectric functional layer and a transmitting electrode, wherein the TFT backplane includes a substrate and a plurality of groups of thin film transistors arranged on one side of the substrate, which can also be called an array substrate. Among them, the piezoelectric functional layer is generally made of piezoelectric material, which is a functional material that can realize the mutual conversion between electrical signals and mechanical vibration signals. When it is used as a piezoelectric functional layer, it often needs to be polarized first. During the polarization process, it is necessary to apply high voltage to the transmitting electrode above the piezoelectric functional layer. In order to prevent the ultrasonic imaging piezoelectric sensor from being broken down during the polarization process, it is usually necessary to take protective measures for its internal devices, namely the thin film transistors on the TFT backplane. However, the protection measures currently taken during the polarization process have led to complicated manufacturing processes for the TFT backplane. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a sensor array substrate motherboard, an array substrate and a manufacturing method, and a piezoelectric device to simplify the manufacturing process of the array substrate and ensure that the array substrate is not broken down during the polarization process. The specific technical solution is as follows:

[0005] The embodiment of the first aspect of the present application proposes an array substrate motherboard of a sensor, comprising an array substrate area and a peripheral area surrounding the array substrate area, wherein the array substrate area comprises a base substrate and a plurality of groups of thin film transistors arranged on a first side of the base substrate and located in a sensing area, wherein each group of thin film transistors comprises at least an electrically connected reset thin film transistor, a switch thin film transistor, a signal amplifying thin film transistor and a reading thin film transistor; a plurality of ITO overlapping blocks arranged in an array along the length direction and the width direction of the array substrate area are arranged in a direction away from the base substrate, wherein the ITO overlapping blocks cover at least a portion of each group of thin film transistors; each of the ITO overlapping blocks is electrically connected to a source electrode or a drain electrode of the reset thin film transistor or the switch thin film transistor; connection; a plurality of polarization pads located on the first side of the substrate are provided in the peripheral area of ​​the array substrate area; the ITO strapping blocks corresponding to the sub-areas of the sensing area that receive or send the same signal are electrically connected to each other, and then electrically connected to the polarization pad close to the sub-area of ​​the sensing area through a conductive trace and grounded; or, the ITO strapping blocks of each group of thin film transistors are individually electrically connected to the polarization pad close to the group of thin film transistors through the conductive trace and grounded; the array substrate area also includes a piezoelectric layer and an emitting electrode arranged in sequence along a direction away from the substrate, the piezoelectric layer and the emitting electrode cover the multiple groups of thin film transistors in the sensing area, and the emitting electrode is used to be electrically connected to a high voltage power supply to polarize the piezoelectric layer.

[0006] In the embodiment of the present application, the array substrate motherboard of the sensor includes an array substrate area and a peripheral area. The array substrate area includes a base substrate and multiple groups of thin film transistors. The peripheral area surrounds the array substrate area. Dividing the array substrate motherboard into the array substrate area and the peripheral area can facilitate the removal of the peripheral area after polarization is completed, and then carry out subsequent processes. Multiple groups of thin film transistors are arranged on the first side of the base substrate and are located in the sensing area of ​​the base substrate. The sensing area is the area corresponding to the piezoelectric layer. The multiple groups of thin film transistors are used to process the electrical signals received by each and change the size of the output current. Among them, the reset thin film transistor is used to transmit the reset signal to the switch thin film transistor, so as to clear the previous frame signal before the next frame signal arrives. The switch thin film transistor is used to transmit the data signal to the signal amplification thin film transistor. The signal amplification thin film transistor can amplify the electrical signal transmitted from the switch thin film transistor. The amplified electrical signal is read by the signal reading thin film transistor, and then the read electrical signal is subsequently processed.

[0007] A plurality of ITO overlap blocks are arranged on the array substrate area. The ITO overlap blocks are arranged in an array along the length direction and the width direction of the array substrate area in a direction away from the plurality of groups of thin film transistors. The ITO overlap blocks can be used as receiving electrodes to receive signals from the outside world, wherein each ITO overlap block corresponds to a group of thin film transistors and is electrically connected to the source or drain of the reset thin film transistor or the switch thin film transistor. An ITO overlap block corresponds to a signal acquisition pixel circuit. Each ITO overlap block is used to collect electrical signals from different areas of the human body, such as the valleys and ridges of fingers. The ITO is arranged in an array, and each ITO overlap block corresponds to a different sub-area, so that different electrical signals from different sub-areas are collected respectively. The electrical signals received or sent in the same sub-area are the same. A plurality of polarization pads are provided in the peripheral area, and the plurality of polarization pads are located on the first side of the substrate, so as to be connected to the ITO bridge blocks. After the ITO bridge blocks corresponding to the sensing area sub-areas receiving or sending the same signal are electrically connected to each other, they are electrically connected to the polarization pads close to the sensing area sub-areas of the column through conductive traces and grounded. By connecting the adjacent thin film transistors, the materials of the traces can be saved, which not only plays a role in saving costs, but also saves the space occupied by the traces. Alternatively, the ITO bridge blocks of each group of thin film transistors can also be electrically connected to the polarization pads close to the group of thin film transistors and grounded separately.

[0008] By electrically connecting and grounding the ITO bridge block to the source or drain of the reset thin film transistor or the switch thin film transistor, the polarization process can be completed normally while ensuring that the thin film transistor is not damaged during the polarization process. There is no need to electrically connect each thin film transistor to the PIN diode for grounding, which can simplify the manufacturing process of the array substrate motherboard, thereby simplifying the manufacturing process of the array substrate.

[0009] In addition, the array substrate motherboard according to the embodiment of the present application may also have the following technical features:

[0010] In some embodiments, each of the thin film transistors includes an active layer, a gate layer, and a source and a drain electrically connected to the gate layer, the drain of the reset thin film transistor is electrically connected to the source of the switching thin film transistor, the ITO strapping block is electrically connected to the drain of the switching thin film transistor and the gate of the signal amplifying thin film transistor, respectively, and the drain of the signal amplifying thin film transistor is electrically connected to the source of the reading thin film transistor.

[0011] In some embodiments, the peripheral area is further provided with an ITO ring, and the ITO strapping blocks corresponding to the sensing area sub-areas that receive or send the same signal are electrically connected to each other and then electrically connected to the ITO ring, and are electrically connected to the polarization pad close to the sensing area sub-area and grounded through the ITO ring; or, the ITO strapping blocks of each group of thin film transistors are individually electrically connected to the ITO ring, and are electrically connected to the polarization pad close to the group of thin film transistors through the ITO ring and grounded.

[0012] In some embodiments, each of the ITO strapping blocks is provided with a metal trace, and the ITO strapping blocks corresponding to the sensing area sub-regions that receive or send the same signal are electrically connected to each other through the metal trace, and the metal trace is electrically connected to the polarization pad close to the sensing area sub-region and grounded; or, the ITO strapping blocks of each group of thin film transistors are individually electrically connected to the ITO ring through the metal traces of each of the ITO strapping blocks, and are electrically connected to the polarization pad close to the group of thin film transistors and grounded.

[0013] In some embodiments, the peripheral region is further provided with an ITO ring, and the metal wirings are electrically connected to the polarization pads close to the sensing region sub-region or the group of thin film transistors through the ITO ring.

[0014] In some embodiments, the polarization pad, the source electrode, and the drain electrode are made of the same metal.

[0015] In some embodiments, the polarization pad is provided in plurality and is distributed at least on two sides of the array substrate region.

[0016] In some embodiments, the switch thin film transistor is an indium gallium zinc oxide thin film transistor, and the signal amplifying thin film transistor has a dual-gate structure.

[0017] A second aspect of the embodiments of the present application provides an array substrate, wherein the array substrate is obtained by cutting off the peripheral area from the array substrate motherboard.

[0018] A third aspect of the embodiments of the present application provides a piezoelectric device, which includes the array substrate.

[0019] A fourth aspect of the embodiments of the present application provides a method for manufacturing an array substrate, comprising the following steps:

[0020] A plurality of groups of thin film transistors are prepared in the sensing area on the first side of the base substrate in the array substrate area, and the plurality of groups of thin film transistors are arranged in an array along the length direction and the width direction of the array substrate area, and the plurality of groups of thin film transistors at least include a reset thin film transistor, a switch thin film transistor, a signal amplifying thin film transistor and a reading thin film transistor, and each of the thin film transistors includes an active layer, a gate layer, and a source and a drain electrically connected to the gate layer, and the ITO bridge block is made between the source and drain of the switch thin film transistor and the gate of the signal amplifying thin film transistor, and the ITO bridge block electrically connects the source and drain of the switch thin film transistor and the gate of the signal amplifying thin film transistor;

[0021] Fabricate a plurality of polarization pads and ITO rings on a first side of the base substrate in a peripheral region of the array substrate;

[0022] The ITO bridge blocks corresponding to the sensing area sub-areas receiving or sending the same signal are electrically connected to each other and then electrically connected to the ITO ring, and the ITO ring is electrically connected to the polarization pad close to the sensing area sub-area and grounded; or, the ITO bridge blocks of each group of thin film transistors are electrically connected to the ITO ring separately, and the ITO ring is electrically connected to the polarization pad close to the group of thin film transistors and grounded;

[0023] The piezoelectric layer and the emitting electrode are sequentially prepared on a first side away from the substrate, wherein the piezoelectric layer and the emitting electrode cover the sensing area;

[0024] applying a high voltage to the transmitting electrode to polarize the piezoelectric layer;

[0025] After polarization is completed, the peripheral area of ​​the array substrate, including the ITO ring, the polarization pad and the metal wires connected thereto located in the peripheral area, is cut off to obtain the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0027] Figure 1 A perspective view of an array substrate motherboard and a piezoelectric layer provided in an embodiment of the present application;

[0028] Figure 2 A perspective view of an array substrate motherboard provided in an embodiment of the present application;

[0029] Figure 3-Figure 6A top view of the array substrate motherboard provided in an embodiment of the present application;

[0030] Figure 7(a)-Figure 7(l) A cross-sectional view of the manufacturing process of the array substrate provided in an embodiment of the present application;

[0031] Figure 8-Figure 9 The schematic diagram of the in-situ electric field polarization provided in the embodiment of the present application;

[0032] Fig.10 A cross-sectional view of an array substrate provided in an embodiment of the present application.

[0033] Reference numerals:

[0034] 10-array substrate area; 20-peripheral area; 11-array substrate; 110-base substrate; 12-ITO overlapping block; 13-piezoelectric layer; 14-conductive trace; 15-metal trace; 21-polarization pad; 22-ITO ring; T1-reset thin film transistor; T2-switch thin film transistor; T3-signal amplification thin film transistor; T4-read thin film transistor; S1-source; P1-active layer; N1-drain; G1-gate layer; V1-first passivation layer; V2-second passivation layer. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field based on this application belong to the scope of protection of the present invention.

[0036] It should be understood that the terms used herein are only for the purpose of describing specific example embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" as used herein may also be meant to include plural forms. The terms "include", "comprise", "contain", and "have" are inclusive, and therefore specify the existence of stated features, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The method steps, processes, and operations described herein are not interpreted as necessarily requiring them to be performed in the specific order described or illustrated, unless the execution order is clearly indicated. It should also be understood that additional or alternative steps may be used.

[0037] Although the terms first, second, third, etc. can be used in the text to describe multiple elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms can only be used to distinguish an element, component, region, layer or section from another region, layer or section. Unless the context clearly indicates, terms such as "first", "second" and other numerical terms do not imply order or sequence when used in the text. Therefore, the first element, component, region, layer or section discussed below can be referred to as the second element, component, region, layer or section without departing from the teaching of the example embodiments.

[0038] For ease of description, spatial relative terms may be used in the text to describe the relationship of one element or feature relative to another element or feature as shown in the figure, such as "inside", "outside", "inner side", "outer side", "below", "below", "above", "above", etc. Such spatial relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the figure. For example, if the device in the figure is turned over, the element described as "below other elements or features" or "below other elements or features" will then be oriented as "above other elements or features" or "above other elements or features". Therefore, the example term "below..." can include both upper and lower orientations. The device can be oriented otherwise, such as rotated 90 degrees or in other directions, and the spatial relative descriptors used in the text are interpreted accordingly.

[0039] To polarize the piezoelectric layer 13, Figure 1 to Figure 7(l)As shown, in a first aspect, an embodiment of the present application provides an array substrate motherboard of a sensor, wherein the array substrate motherboard includes an array substrate area 10 and a peripheral area 20 surrounding the array substrate area 10, the array substrate area 10 includes a base substrate 110 and a plurality of groups of thin film transistors arranged on a first side of the base substrate 110 and located in a sensing area, each group of thin film transistors at least includes an electrically connected reset thin film transistor T1, a switch thin film transistor T2, a signal amplifying thin film transistor T3 and a reading thin film transistor T4; a plurality of ITO bridge blocks 12 arranged in an array along a length direction L and a width direction W of the array substrate area 10 are arranged in a direction away from the base substrate 110, the ITO bridge blocks 12 cover at least a portion of each group of thin film transistors; each ITO bridge block 12 is connected to the reset thin film transistor T1 or the switch thin film transistor T2. The source S1 or drain N1 of the body transistor T2 is electrically connected; the peripheral area 20 of the array substrate area 10 is provided with a plurality of polarization pads 21 located on the first side of the base substrate 110; the ITO strapping blocks 12 corresponding to the sensing area sub-areas that receive or send the same signal are electrically connected to each other, and then electrically connected to the polarization pad 21 close to the sensing area sub-area through the conductive trace 14 and grounded; or, the ITO strapping blocks 12 of each group of thin film transistors are individually electrically connected to the polarization pad 21 close to the group of thin film transistors and grounded; the array substrate area 10 also includes a piezoelectric layer 13 and an emitting electrode (not shown in the figure) arranged in sequence in a direction away from the base substrate 110, the piezoelectric layer 13 and the emitting electrode cover the multiple groups of thin film transistors in the sensing area, and the emitting electrode is used to be electrically connected to a high voltage power supply to polarize the piezoelectric layer 13.

[0040] In the embodiment of the present application, the array substrate motherboard of the sensor includes an array substrate area 10 and a peripheral area 20, the array substrate area 10 includes a base substrate 110 and a plurality of thin film transistors, the peripheral area 20 surrounds the array substrate area 10, and the array substrate motherboard is divided into the array substrate area 10 and the peripheral area 20 to facilitate the removal of the peripheral area 20 after the polarization is completed, and then the subsequent process is carried out. The plurality of thin film transistors are arranged on the first side of the base substrate 110 and are located in the sensing area of ​​the base substrate 110, and the sensing area is the area corresponding to the piezoelectric layer 13, and the plurality of thin film transistors are used to process the electrical signals received by each other and change the magnitude of the output current. Among them, the reset thin film transistor T1 is used to transmit the reset signal to the switch thin film transistor T2, so as to clear the previous frame signal before the next frame signal comes, and the switch thin film transistor T2 is used to transmit the data signal to the signal amplification thin film transistor T3, and the signal amplification thin film transistor T3 can amplify the electrical signal transmitted from the switch thin film transistor T2, and the amplified electrical signal is read by the signal reading thin film transistor T4, and then the read electrical signal is subsequently processed.

[0041] A plurality of ITO overlap blocks 12 are arranged on the array substrate area 10. The ITO overlap blocks 12 are arranged in an array along the length direction L and the width direction W of the array substrate area 10 in a direction away from the plurality of groups of thin film transistors. The ITO overlap blocks 12 can be used as receiving electrodes to receive signals from the outside world, wherein each ITO overlap block 12 corresponds to a group of thin film transistors and is electrically connected to the source S1 or the drain N1 of the reset thin film transistor T1 or the switch thin film transistor T2. One ITO overlap block 12 corresponds to a signal acquisition pixel circuit, and each ITO overlap block 12 is used to collect electrical signals from different areas of the human body, such as the valleys and ridges of fingers. The ITO is arranged in an array, and each ITO overlap block 12 corresponds to a different area, so that different electrical signals from different areas are collected respectively. Among them, the sensing area is divided into multiple sub-areas according to whether the received or sent electrical signals are the same, and the electrical signals received or sent by the ITO overlap blocks 12 in the same sub-area are the same. A plurality of polarization pads 21 are provided in the peripheral area 20, and the plurality of polarization pads 21 are located on the first side of the base substrate 110, so as to be connected to the ITO bridge block 12. After the ITO bridge blocks 12 corresponding to the sensing area sub-areas receiving or sending the same signal are electrically connected to each other, they are then electrically connected to the polarization pad 21 near the sensing area sub-area through the conductive trace 14 and grounded. By connecting the adjacent thin film transistors, the material of the trace can be saved, which not only plays a role in saving costs, but also saves the space occupied by the trace. Alternatively, the ITO bridge block 12 of each group of thin film transistors can also be electrically connected to the polarization pad 21 near the group of thin film transistors and grounded separately.

[0042] By electrically connecting the ITO bridge block 12 to the source S1 or drain N1 of the reset thin film transistor T1 or the switch thin film transistor T2 and grounding it, the polarization process can be completed normally while ensuring that the thin film transistor is not damaged during the polarization process. Moreover, there is no need to electrically connect each thin film transistor to the PIN diode for grounding, which can simplify the manufacturing process of the array substrate motherboard, thereby simplifying the manufacturing process of the array substrate 11.

[0043] Among them, when the sub-region corresponds to two adjacent columns of thin film transistors, such as Figure 1 , Figure 2 , Figure 3 As shown, the thin film transistors in the two adjacent columns can be electrically connected one by one, and then electrically connected to the polarization pad 21 close to the two adjacent columns of thin film transistors and grounded. It is not difficult to understand that when the sub-region corresponds to two or three groups of thin film transistors, the ITO bonding blocks 12 corresponding to the two or three adjacent groups of thin film transistors can be electrically connected, and then electrically connected to the polarization pad 21 close to the two or three groups of thin film transistors and grounded. Of course, multiple ITO bonding blocks 12 in the sub-region that receive or send the same signal can also be electrically connected to the polarization pad 21 and grounded separately, and this application does not limit this.

[0044] The array substrate area 10 also includes a piezoelectric layer 13 and an emitter electrode (not shown) sequentially arranged in a direction away from the base substrate 110. The emitter electrode is a metal material located above the piezoelectric layer 13. The piezoelectric layer 13 and the emitter electrode cover the sensing area. The emitter electrode is used to be electrically connected to a high-voltage power supply to polarize the piezoelectric layer 13. By polarizing the piezoelectric layer 13, the piezoelectric layer 13 can have piezoelectric properties. The polarized piezoelectric layer 13, the emitter electrode, and the ITO bridge block 12 form a piezoelectric sensor. When the piezoelectric layer 13 senses a pressure change, it can be converted into an electrical signal, which is applied to the thin film transistor through the ITO bridge block 12, and finally changes the magnitude of the output current.

[0045] Specifically, a thin film transistor is a type of field effect transistor, and thin film transistors are of great significance to improving the working performance of displays.

[0046] Specifically, the polarization process mainly orients the randomly oriented molecular dipole moments in the piezoelectric material in a consistent manner along a specific direction under certain conditions, thereby giving the piezoelectric material piezoelectric properties, that is, the mutual conversion between electrical signals and vibration signals can be achieved. Moreover, the polarization process only needs to be carried out once, and the piezoelectric material can always maintain the oriented structure after the polarization is completed, so that the sensor always maintains the functionality of the piezoelectric performance. There are four main polarization methods for piezoelectric materials: tensile polarization, high temperature polarization, corona polarization and in-situ electric field polarization. Compared with the first three polarization methods, the in-situ electric field polarization method has better polarization effect and polarization uniformity, and is suitable for continuous production.

[0047] In-situ electric field polarization process and principle Figure 8 and Fig. 9 As shown in the figure, the process of in-situ electric field polarization is mainly divided into the following steps: ① Before polarization, the lower surface of the PVDF film to be polarized is grounded to make its potential 0; ② The surrounding gas is ionized under the action of the high-voltage electrode (Source electrode) to generate Plasma; ③ The Plasma moves and gathers on the surface of the PVDF film to be polarized under the potential difference formed by the high-voltage electrode (Source electrode) and the low-voltage electrode (Grid electrode); ④ The Plasma moved to the upper surface of PVDF and the grounded lower surface of PVDF form an intra-film electric field along the thickness direction of the PVDF film to be polarized, thereby polarizing the PVDF film.

[0048] The material of the base substrate 110 may be a transparent substrate such as glass or polyimide.

[0049] As shown in Figures 7(i) and 7(j), in some embodiments of the present application, each thin film transistor includes an active layer P1, a gate layer G1, and a source S1 and a drain N1 electrically connected to the gate layer G1, the drain N1 of the reset thin film transistor T1 is electrically connected to the source S1 of the switching thin film transistor T2, the ITO strapping block 12 is electrically connected to the drain N1 of the switching thin film transistor T2 and the gate layer G1 of the signal amplifying thin film transistor T3, respectively, and the drain N1 of the signal amplifying thin film transistor T3 is electrically connected to the source S1 of the reading thin film transistor T4.

[0050] In the embodiment of the present application, the source and drain N1 of the switching thin film transistor T2 are electrically connected to the gate layer G1 of the signal amplifying thin film transistor T3 through the ITO bridge block 12, that is, in addition to being used to electrically connect the source S1 or drain N1 of the reset thin film transistor T1 or the switching thin film transistor T2, the ITO bridge block 12 can also be used to electrically connect the drain N1 of the switching thin film transistor T2 to the gate layer G1 of the signal amplifying thin film transistor T3. The polarized piezoelectric layer 13 converts the pressure signal into an electrical signal and can be applied to the gate of the signal amplifying thin film transistor T3, and ultimately changes the size of the output current. The drain N1 of the signal amplifying thin film transistor T3 is electrically connected to the source S1 of the reading thin film transistor T4, and the current signal of the signal amplifying thin film transistor T3 can be read.

[0051] In some embodiments of the present application, Figures 1 to 4 As shown, the peripheral area 20 is also provided with an ITO ring 22, and the ITO strapping blocks 12 corresponding to the sensing area sub-areas that receive or send the same signal are electrically connected to each other and then electrically connected to the ITO ring 22, and are electrically connected to the polarization pad 21 close to the sensing area sub-area through the ITO ring 22 and grounded; or, the ITO strapping blocks 12 of each group of thin film transistors are electrically connected to the ITO ring 22 separately, and are electrically connected to the polarization pad 21 close to the group of thin film transistors through the ITO ring 22 and grounded.

[0052] In the embodiment of the present application, the peripheral area 20 of the array substrate motherboard is provided with an ITO ring 22. The ITO ring 22 can be provided to collect the wiring extending from the ITO bridge block 12, and then the ITO bridge block 12 is connected to the polarization pad 21, so that the charge distribution between the ITO bridge block 12 and the polarization pad 21 is more uniform. In the embodiment of the present application, the ITO ring 22 is directly connected to the polarization pad 21 and grounded. Compared with the related art, the ITO ring 22 does not need to be electrically connected to the polarization pad 21 through a PIN diode, which can simplify the manufacturing process of the array substrate motherboard, thereby simplifying the manufacturing process of the array substrate 11.

[0053] Specifically, the ITO ring 22 may be a circular ring or a square ring. Preferably, in the embodiment of the present application, Figures 1 to 4As shown, the ITO ring 22 is a square ring having a shape matching that of the array substrate 11 .

[0054] As shown in Figure 7(k), Figure 7(l) and Fig.10 As shown, in some embodiments of the present application, each ITO strapping block 12 is provided with a metal trace 15, and the ITO strapping blocks 12 corresponding to the sensing area sub-regions that receive or send the same signal are electrically connected to each other through the metal trace 15, and the metal trace 15 is electrically connected to the polarization pad 21 close to the sensing area sub-region and grounded; or, the ITO strapping blocks 12 of each group of thin-film transistors are electrically connected to the ITO ring 22 separately through the metal traces 15 of each ITO strapping block 12, and are electrically connected to the polarization pad 21 close to the group of thin-film transistors and grounded.

[0055] In the embodiment of the present application, a metal trace 15 is provided on each ITO bridge block 12. Considering the metal trace area of ​​the ITO layer and the ITO trace line width, a layer of trace metal with a relatively small resistance specifically used to connect the polarization pad can be provided on the ITO bridge block 12 layer. The ITO bridge block 12 can be electrically connected to the ITO ring 22 through the metal trace 15, and electrically connected to the ITO ring 22. The ITO bridge block 12 is connected to the polarization pad 21 through the metal trace 15, which can be used to protect the thin film transistor from breakdown during the polarization process, and can also achieve a good polarization effect on the piezoelectric layer 13. At the same time, compared with the prior art of using a Pin tube as an ESD TFT grounding during the polarization process, the number of mask layers for making thin film transistors can be saved, saving production costs.

[0056] In some embodiments of the present application, the peripheral region 20 is further provided with an ITO ring 22 , and the metal traces 15 are electrically connected to the polarization pad 21 close to the sensing region sub-region or the group of thin film transistors through the ITO ring 22 .

[0057] In the embodiment of the present application, as shown in FIG. 7(k), FIG. 7(l) and Fig.10 As shown, the metal trace 15 is connected to the polarization pad 21 through the ITO ring 22. The ITO ring 22 can first collect the metal trace 15 and then electrically connect the metal trace 15 to the polarization pad 21. Among them, the setting position and steps of the metal trace 15 are as follows Figure 7(j)-Figure 7(l) shown.

[0058] In some embodiments of the present application, the polarization pad 21 , the source S1 , and the drain N1 are made of the same metal.

[0059] In the embodiment of the present application, the polarization pad 21 and the source S1 and the drain N1 are made of the same metal, for example, the metal may be Cu. The connection of the same metal can ensure a good conductive effect and enable the polarization process to proceed smoothly.

[0060] In some embodiments of the present application, a plurality of polarization pads 21 are provided and distributed at least on two sides of the array substrate region 10 .

[0061] In the embodiment of the present application, a plurality of polarization pads 21 are provided, so as to flexibly arrange the positions of the polarization pads 21 according to the connection mode between the ITO bridge block 12 and the polarization pads 21. Figures 1 to 4 and Figure 6 As shown, there are four polarization pads 21, which are symmetrically distributed around the array substrate area 10. The polarization pads 21 are symmetrically distributed around the array substrate area 10 to ensure that the charge distribution in the array substrate 11 is uniform during the polarization process, thereby ensuring the smooth progress of the polarization process. Of course, the number of polarization pads 21 is not limited to four. Figure 5 As shown, three polarization pads 21 may be provided, or two polarization pads 21 may be provided. Figures 1 to 6 As shown, the shape of the polarization pad 21 can be square, rectangular, etc.

[0062] In some embodiments of the present application, the piezoelectric layer 13 is made of a material selected from the group consisting of piezoelectric ceramics, AlN, ZnO, and organic PVDF polymer.

[0063] In the embodiment of the present application, the material of the piezoelectric layer 13 is a piezoelectric material. The piezoelectric material is a functional material that can realize the mutual conversion between electrical signals and mechanical vibration signals. It is a key material for realizing the functionality of the sensor. It has positive piezoelectric effect and negative piezoelectric effect. According to the material category and properties, it is mainly divided into four types: piezoelectric ceramics, AlN, ZnO and organic PVDF polymers. At present, it is mainly used as a piezoelectric functional layer in ultrasonic fingerprint recognition, medical imaging, pressure sensors, transducers and other sensor devices.

[0064] Furthermore, organic PVDF polymer can be selected as piezoelectric material. PVDF mainly refers to ethylene homopolymer or copolymer of vinylidene fluoride and other small amounts of fluorine-containing vinyl monomers. It has the characteristics of both fluororesin and general resin, and has good chemical resistance, processability, fatigue resistance and creep resistance.

[0065] In some embodiments of the present application, as shown in FIG. 7( i ), the switch thin film transistor T2 is an indium gallium zinc oxide thin film transistor (IGZO), and the signal amplifying thin film transistor T3 has a dual-gate structure.

[0066] In the embodiment of the present application, since the indium gallium zinc oxide thin film transistor has a high mobility, it has a high resolution, and the switch thin film transistor T2 adopts the indium gallium zinc oxide thin film transistor to improve the switching sensitivity. The signal amplification thin film transistor T3 adopts a dual-gate structure, which can increase the on-state current and the current saturation, thereby improving the signal stability.

[0067] A second aspect of an embodiment of the present application provides an array substrate 11 , which is obtained by cutting off a peripheral area 20 from an array substrate motherboard.

[0068] In the embodiment of the present application, after the polarization process is completed, the ITO ring 22 of the peripheral area 20 and the conductive trace 14 connecting the ITO ring 22 are cut off together to obtain the array substrate 11. The piezoelectric layer 13 of the array substrate 11 has piezoelectric properties. When the piezoelectric layer 13 is subjected to mechanical vibration, the pressure signal can be converted into an electrical signal, and the signal is amplified through a thin film transistor, thereby finally changing the size of the output current and improving the detection sensitivity.

[0069] A third aspect of the embodiment of the present application provides a piezoelectric device, and the piezoelectric device includes an array substrate 11. In the embodiment of the present application, the piezoelectric device has piezoelectric properties and can be applied to an ultrasonic sensor.

[0070] As shown in FIG. 7( a) to FIG. 7( i), a fourth aspect of an embodiment of the present application provides a method for manufacturing an array substrate 11, comprising the following steps:

[0071] S1: A plurality of groups of thin film transistors are prepared in the sensing area on the first side of the base substrate 110 of the array substrate area 10. The plurality of groups of thin film transistors are arranged in an array along the length direction L and the width direction W of the array substrate area 10. The plurality of groups of thin film transistors at least include a reset thin film transistor T1, a switch thin film transistor T2, a signal amplifying thin film transistor T3 and a reading thin film transistor T4. Each thin film transistor includes an active layer P1, a gate layer G1 and a source S1 and a drain N1 electrically connected to the gate layer G1. An ITO bonding block 12 is made between the source and drain of the switch thin film transistor T2 and the gate of the signal amplifying thin film transistor T3. The ITO bonding block 12 electrically connects the source and drain N1 of the switch thin film transistor T2 and the gate of the signal amplifying thin film transistor T3.

[0072] S2 : manufacturing a plurality of polarization pads 21 and ITO rings 22 on a first side of the base substrate 110 in the peripheral region 20 of the array substrate 11 .

[0073] S3: The ITO bridge blocks 12 corresponding to the sensing area sub-areas that receive or send the same signal are electrically connected to each other and then electrically connected to the ITO ring 22, and the ITO ring 22 is electrically connected to the polarization pad 21 close to the sensing area sub-area and grounded; or, the ITO bridge blocks 12 of each group of thin film transistors are electrically connected to the ITO ring 22 separately, and the ITO ring 22 is electrically connected to the polarization pad 21 close to the group of thin film transistors and grounded.

[0074] S4: a piezoelectric layer 13 and an emitting electrode are sequentially prepared on the first side away from the base substrate 110 , wherein the piezoelectric layer 13 and the emitting electrode cover the sensing area.

[0075] S5: Apply high voltage to the emitter electrode to polarize the piezoelectric layer 13 .

[0076] S6: After polarization is completed, the peripheral area 20 of the array substrate 11 is cut off, including the ITO ring 22 located in the peripheral area 20, the polarization pad 21 and the metal wires connected thereto, so as to obtain the array substrate 11.

[0077] It should be noted that in order to facilitate the understanding of the actual structure of the array substrate 11, Figure 1 , Figure 2 The structure of the array substrate 11 after cutting is directly illustrated in the figure, and it only illustrates a connection relationship with the ITO ring 22 and the polarization pad 21 of the peripheral area 20, which is slightly different from the actual array basic motherboard described above. Figure 1 , Figure 2 In the embodiment, the ITO ring 22 and the polarization pad 21 are not located on the base substrate 110 .

[0078] In some embodiments, before the step of electrically connecting the ITO bridge blocks 12 corresponding to the sensing area sub-areas that receive or send the same signal to the ITO ring 22 or electrically connecting the ITO bridge blocks 12 of each group of thin film transistors to the ITO ring 22 individually, the step also includes: setting metal traces 15 on the ITO bridge blocks 12, and the ITO bridge blocks 12 corresponding to the sensing area sub-areas that receive or send the same signal are electrically connected to the ITO ring 22 through the metal traces 15, or the ITO bridge blocks 12 of each group of thin film transistors are electrically connected to the ITO ring 22 individually through the metal traces 15.

[0079] Specifically, as shown in FIG. 7( j), a first passivation layer V1 is deposited on multiple groups of thin film transistors and holes are punched, and then as shown in FIG. 7( k), an ITO layer is deposited, and a metal trace 15 is arranged above the ITO bridge block 12, and then as shown in FIG. 7( l), a second passivation layer V2 is deposited above the metal trace 15. The deposited first passivation layer V1 and second passivation layer V2 can protect the array substrate 11 from erosion by a high humidity environment, thereby protecting the array substrate 11.

[0080] The above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention are included in the protection scope of the present invention.

Claims

1. A sensor array substrate motherboard, characterized in that: The invention comprises an array substrate area and a peripheral area surrounding the array substrate area; the array substrate area comprises a base substrate and a plurality of groups of thin film transistors arranged on a first side of the base substrate and located in a sensing area, each group of thin film transistors at least comprises an electrically connected reset thin film transistor, a switch thin film transistor, a signal amplifying thin film transistor and a reading thin film transistor; a plurality of ITO overlapping blocks arranged in an array along the length direction and the width direction of the array substrate area are arranged in a direction away from the base substrate, and the ITO overlapping blocks cover at least a part of each group of thin film transistors; Each of the ITO bridge blocks is electrically connected to a source or a drain of the reset thin film transistor or the switch thin film transistor; A peripheral area of ​​the array substrate area is provided with a plurality of polarization pads located on a first side of the base substrate; After the ITO bridge blocks corresponding to the sub-areas of the sensing area receiving or sending the same signal are electrically connected to each other, they are electrically connected to the polarization pad of the sub-area close to the sensing area through a conductive trace and grounded; or, the ITO bridge blocks of each group of thin film transistors are individually electrically connected to the polarization pad close to the group of thin film transistors through the conductive trace and grounded; The array substrate area also includes a piezoelectric layer and an emitting electrode arranged in sequence in a direction away from the base substrate. The piezoelectric layer and the emitting electrode cover multiple groups of thin film transistors in the sensing area. The emitting electrode is used to be electrically connected to a high voltage power supply to polarize the piezoelectric layer.

2. The array substrate motherboard according to claim 1, characterized in that: Each of the thin film transistors includes an active layer, a gate layer, and a source and a drain electrically connected to the gate layer. The drain of the reset thin film transistor is electrically connected to the source of the switch thin film transistor. The ITO strapping block is electrically connected to the drain of the switch thin film transistor and the gate of the signal amplifying thin film transistor, respectively. The drain of the signal amplifying thin film transistor is electrically connected to the source of the reading thin film transistor.

3. The array substrate motherboard according to claim 1, characterized in that: The peripheral area is also provided with an ITO ring, and the ITO strapping blocks corresponding to the sensing area sub-areas that receive or send the same signal are electrically connected to each other and then electrically connected to the ITO ring, and are electrically connected to the polarization pad close to the sensing area sub-area and grounded through the ITO ring; or, the ITO strapping blocks of each group of thin film transistors are individually electrically connected to the ITO ring, and are electrically connected to the polarization pad close to the group of thin film transistors through the ITO ring and grounded.

4. The array substrate motherboard according to claim 3, characterized in that: A metal trace is provided on each of the ITO bridge blocks, and the ITO bridge blocks corresponding to the sensing area sub-regions that receive or send the same signal are electrically connected to each other through the metal traces, and the metal traces are electrically connected to the polarization pad close to the sensing area sub-region and grounded; or, the ITO bridge blocks of each group of thin film transistors are electrically connected to the ITO ring separately through the metal traces of each of the ITO bridge blocks, and are electrically connected to the polarization pad close to the group of thin film transistors and grounded.

5. The array substrate motherboard according to claim 4, characterized in that: The peripheral area is also provided with an ITO ring, and the metal wirings are electrically connected to the polarization pads close to the sensing area sub-area or the group of thin film transistors through the ITO ring.

6. The array substrate motherboard according to any one of claims 1 to 5, characterized in that: The polarization pad, the source electrode, and the drain electrode are made of the same metal.

7. The array substrate motherboard according to any one of claims 1 to 5, characterized in that: The polarization pads are provided in plurality and are distributed at least on two sides of the array substrate area.

8. The array substrate motherboard according to any one of claims 1 to 5, characterized in that: The switch thin film transistor is an indium gallium zinc oxide thin film transistor, and the signal amplifying thin film transistor has a double-gate structure.

9. An array substrate, characterized in that: The array substrate is obtained by cutting the peripheral area from the array substrate motherboard according to any one of claims 1 to 8.

10. A piezoelectric device, characterized in that: The piezoelectric device comprises the array substrate according to claim 9.

11. A method for manufacturing an array substrate, characterized in that: The following steps are involved: A plurality of groups of thin film transistors are prepared in the sensing area on the first side of the base substrate in the array substrate area, and the plurality of groups of thin film transistors are arranged in an array along the length direction and the width direction of the array substrate area, and the plurality of groups of thin film transistors at least include a reset thin film transistor, a switch thin film transistor, a signal amplifying thin film transistor and a reading thin film transistor, and each of the thin film transistors includes an active layer, a gate layer, and a source and a drain electrically connected to the gate layer, and an ITO bridge block is made between the source and drain of the switch thin film transistor and the gate of the signal amplifying thin film transistor, and the ITO bridge block electrically connects the source and drain of the switch thin film transistor and the gate of the signal amplifying thin film transistor; Fabricate a plurality of polarization pads and ITO rings on a first side of the base substrate in a peripheral region of the array substrate; The ITO bridge blocks corresponding to the sensing area sub-areas receiving or sending the same signal are electrically connected to each other and then electrically connected to the ITO ring, and the ITO ring is electrically connected to the polarization pad close to the sensing area sub-area and grounded; or, the ITO bridge blocks of each group of thin film transistors are electrically connected to the ITO ring separately, and the ITO ring is electrically connected to the polarization pad close to the group of thin film transistors and grounded; Sequentially preparing a piezoelectric layer and an emitting electrode on a first side away from the substrate, wherein the piezoelectric layer and the emitting electrode cover the sensing area; applying a high voltage to the transmitting electrode to polarize the piezoelectric layer; After polarization is completed, the peripheral area of ​​the array substrate, including the ITO ring, the polarization pad and the metal wires connected thereto located in the peripheral area, is cut off to obtain the array substrate.

Images