An epitaxial structure of a heterojunction bipolar transistor and a heterojunction bipolar transistor

Abstract

This invention discloses an epitaxial structure and a heterojunction bipolar transistor (HBT). The epitaxial structure includes a substrate, a buffer layer, a collector layer, a base layer, an emitter layer, and an emitter cap layer stacked together; wherein the substrate is a GaAs substrate, and the buffer layer is made of Al. x Ga 1‑x As 1‑y P y The current collector layer material includes GaAs. In this application, Al is used. x Ga 1‑x As 1‑ y P y The material forms a buffer layer, Al x Ga 1‑x As 1‑y P y The introduction of P in Al makes Al x Ga 1‑x As 1‑y P y Its lattice constant is closer to that of GaAs, utilizing Al x Ga 1‑x As 1‑y P y The material forms a buffer layer, which can reduce the lattice mismatch between the buffer layer and the substrate, and improve the quality of crystal growth; at the same time, the introduction of P can also increase the Al content. x Ga 1‑x As 1‑y P y The bandgap of the material makes Al x Ga 1‑x As 1‑y P y The required Al content is reduced, thereby reducing the density of Al-introduced defect centers and improving the device performance of heterojunction bipolar transistors.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to an epitaxial structure of a heterojunction bipolar transistor and a heterojunction bipolar transistor. Background Technology

[0002] Heterojunction bipolar transistors (HBTs) have attracted much attention due to their high frequency, high power density, high power gain, and good linearity. They are widely used in microwave, millimeter-wave bands, and high-speed integrated circuits, and are extensively applied in military, space, and civilian communications fields, such as millimeter-wave radar, electronic warfare, smart equipment, satellite communications, and radiation astronomy.

[0003] However, in the existing epitaxial structure of heterojunction bipolar transistors, there is a certain lattice mismatch between the substrate and the epitaxial film grown on the substrate. During the growth of the epitaxial film, certain mismatch defects will occur, which will reduce the growth quality of the epitaxial material and affect the performance of the transistor device. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide an epitaxial structure and a heterojunction bipolar transistor, thereby reducing lattice mismatch between the epitaxial film and the substrate and improving device performance.

[0005] In a first aspect, embodiments of the present invention provide an epitaxial structure for a heterojunction bipolar transistor, comprising a substrate, a buffer layer, a collector layer, a base layer, an emitter layer, and an emitter capping layer stacked together.

[0006] The substrate includes a GaAs substrate, and the buffer layer is made of Al. x Ga 1-x As 1-y P y The material of the current collector layer includes GaAs.

[0007] Optionally, in possible embodiments, the value of x ranges from 0 to 90%, and the value of y ranges from 0.5 to 10%.

[0008] Optionally, in a possible embodiment, the material of the collector layer comprises N-type doped GaAs with a doping concentration of 1 × 10⁻⁶. 15 ~2×10 18 cm -3 .

[0009] Optionally, in possible embodiments, the base layer material comprises one of P-type doped GaAs, P-type doped GaAsSb, or P-type doped InGaAs, with a doping concentration of 1 × 10⁻⁶. 19 ~8×10 19cm -3 .

[0010] Optionally, in a possible embodiment, the material of the emitter layer comprises N-type doped InGaP with a doping concentration of 5 × 10⁻⁶. 16 ~1×10 18 cm -3 .

[0011] Optionally, in a possible embodiment, the epitaxial structure further includes a lower ohmic contact layer and an upper ohmic contact layer; the lower ohmic contact layer is located between the buffer layer and the collector layer; the upper ohmic contact layer is located on the side surface of the emitter cap layer away from the emitter layer.

[0012] Optionally, in a possible embodiment, the material of the lower ohmic contact layer comprises N-type doped GaAs with a doping concentration of 1 × 10⁻⁶. 18 ~2×10 19 cm -3 The material of the upper ohmic contact layer is N-type doped GaAs or N-type doped InGaAs, with a doping concentration of 1×10⁻⁶. 18 ~1×10 20 cm -3 .

[0013] Optionally, in a possible embodiment, the epitaxial structure further includes an etch stop layer disposed between the collector layer and the lower ohmic contact layer.

[0014] Optionally, in a possible embodiment, the material of the etch stop layer comprises N-type doped InGaP with a doping concentration of 1×10⁻⁶. 17 ~5×10 18 cm -3 .

[0015] Secondly, embodiments of the present invention also provide a heterojunction bipolar transistor, which is fabricated using the epitaxial structure of the heterojunction bipolar transistor described in the first aspect of the present invention.

[0016] The epitaxial structure of the heterojunction bipolar transistor provided in this embodiment of the invention includes a substrate, a buffer layer, a collector layer, a base layer, an emitter layer, and an emitter cap layer stacked together; wherein the substrate includes a GaAs substrate, and the material of the buffer layer includes Al. x Ga 1-x As 1-y P y The current collector layer material includes GaAs. In this application, Al is used. x Ga 1-x As 1-y P y The material forms a buffer layer, Alx Ga 1-x As 1-y P y The introduction of P in Al makes Al x Ga 1-x As 1-y P y Its lattice constant is closer to that of GaAs, utilizing Al x Ga 1-x As 1-y P y The material forms a buffer layer, which can reduce the lattice mismatch between the buffer layer and the substrate, and improve the quality of crystal growth; at the same time, the introduction of P can also increase the Al content. x Ga 1-x As 1-y P y The bandgap of the material makes Al x Ga 1-x As 1-y P y The required Al content is reduced, thereby reducing the density of Al-introduced defect centers and improving the device performance of heterojunction bipolar transistors. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the epitaxial structure of a heterojunction bipolar transistor provided in an embodiment of the present invention;

[0018] Figure 2 This is a schematic diagram of the epitaxial structure of another heterojunction bipolar transistor provided in an embodiment of the present invention. Detailed Implementation

[0019] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0020] In the epitaxial structure of existing heterojunction bipolar transistors, the substrate is generally GaAs, and the buffer is typically made of GaAs or AlGaAs. When GaAs is used as the buffer layer, its small bandgap leads to significant leakage current, affecting device performance. While using AlGaAs as the buffer layer can increase the bandgap and reduce leakage current, there is a certain lattice mismatch between AlGaAs and the GaAs substrate. AlGaAs buffer layers grown on GaAs substrates exhibit mismatch defects, reducing the material's crystal quality. Furthermore, when the Al content in AlGaAs is high, defect centers are introduced into the material; the higher the Al content, the more defect centers there are, further degrading device performance. Based on these shortcomings of the prior art, the inventors propose the technical solution in this application.

[0021] This application provides an epitaxial structure for a heterojunction bipolar transistor, comprising a substrate, a buffer layer, a collector layer, a base layer, an emitter layer, and an emitter capping layer stacked together.

[0022] The substrate includes a GaAs substrate, and the buffer layer is made of Al. x Ga 1-x As 1-y P y The material of the current collector layer includes GaAs.

[0023] In this application, AI is used x Ga 1-x As 1-y P y The material forms a buffer layer, Al x Ga 1-x As 1-y P y The introduction of P in Al makes Al x Ga 1-x As 1-y P y Its lattice constant is closer to that of GaAs, utilizing Al x Ga 1-x As 1-y P y The material forms a buffer layer, which can reduce the lattice mismatch between the buffer layer and the substrate, and improve the quality of crystal growth; at the same time, the introduction of P can also increase the Al content. x Ga 1- x As 1-y P y The bandgap of the material makes Al x Ga 1-x As 1-y P yThe required Al content is reduced, thereby reducing the density of Al-introduced defect centers and improving the device performance of heterojunction bipolar transistors.

[0024] The above is the core idea of ​​this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0025] Figure 1 This is a schematic diagram of the epitaxial structure of a heterojunction bipolar transistor provided in an embodiment of the present invention, with reference to... Figure 1 This invention provides an epitaxial structure for a heterojunction bipolar transistor, comprising a substrate 1, a buffer layer 2, a collector layer 3, a base layer 4, an emitter layer 5, and an emitter cap layer 6 stacked together; wherein the substrate 1 comprises a GaAs substrate, and the material of the buffer layer 2 comprises Al. x Ga 1-x As 1-y P y The material of the collector layer 3 includes GaAs.

[0026] Specifically, such as Figure 1 As shown in the figure, the epitaxial structure in this application includes a substrate 1, a buffer layer 2, a collector layer 3, a base layer 4, an emitter layer 5, and an emitter capping layer 6. The substrate 1 is a GaAs substrate, and the buffer layer 2 is formed on the surface of the substrate 1. The buffer layer 2 is made of Al. x Ga 1-x As 1-y P y The buffer layer, that is, the material forming buffer layer 2, is Al. x Ga 1-x As 1-y P y In this structure, a collector layer 3 is disposed on the side of the buffer layer 2 away from the substrate 1. The collector layer 3 is also a GaAs layer, meaning that the material forming the collector layer 3 is GaAs. A base layer 4 is disposed on the side of the collector layer 3 away from the buffer layer 2. An emitter layer 5 is disposed on the side of the base layer 4 away from the collector layer 3. An emitter capping layer 6 is disposed on the side of the emitter layer 5 away from the base layer 4. In other words, the substrate 1, buffer layer 2, collector layer 3, base layer 4, emitter layer 5, and emitter capping layer 6 are stacked.

[0027] Using AI x Ga 1-x As 1-y P y The material forms a buffer layer 2, which, compared to the AlGaAs buffer layer in the prior art, has Al... x Ga1-x As 1-y P y Al has a lattice constant that is closer to that of GaAs. x Ga 1-x As 1-y P y The introduction of phosphorus (P) into the material can reduce the lattice mismatch between the buffer layer 2 and the substrate 1, thereby improving the quality of crystal growth; simultaneously, the introduction of P can also increase the Al content. x Ga 1-x As 1- y P y The bandgap of the material makes Al x Ga 1-x As 1-y P y The required Al content is reduced, thereby reducing the density of Al-introduced defect centers and improving the device performance of heterojunction bipolar transistors.

[0028] The direction of the emitter layer 5 can be defined as the upper layer of the epitaxial structure, and the film layer containing the substrate 1 is the lower layer of the transistor structure. In this proposal, the material of the collector layer 3 above the buffer layer 2 is also GaAs. The lattice matching between the buffer layer 2 and the adjacent film layers is good, further reducing the probability of defect growth.

[0029] In order to form a heterojunction bipolar transistor, the base layer 4 and the emitter layer 5 can be prepared using different semiconductor materials, so that the PN junction formed by the emitter layer 5 and the base layer 4 is a heterojunction. The specific materials used to prepare the emitter layer 5 and the base layer 4 are not limited in this embodiment of the invention, and those skilled in the art can make their own choices according to actual needs.

[0030] In this embodiment of the invention, the preparation method of the buffer layer 2, collector layer 3, base layer 4, emitter layer 5 and emitter cap layer 6 is not limited. Those skilled in the art can make selections according to actual needs. For example, the above-mentioned epitaxial films can be sequentially deposited on the surface of the substrate 1 by metal-organic chemical vapor deposition (MOCVD) technology, but it is not limited to this.

[0031] In addition, the specific preparation process of each of the above-mentioned epitaxial films can also be set by those skilled in the art according to actual needs, and the embodiments of the present invention will not elaborate on or limit this process.

[0032] The epitaxial structure of the heterojunction bipolar transistor provided in this embodiment of the invention includes a substrate, a buffer layer, a collector layer, a base layer, an emitter layer, and an emitter cap layer stacked together; wherein the substrate includes a GaAs substrate, and the material of the buffer layer includes Al. xGa 1-x As 1-y P y The current collector layer material includes GaAs. In this application, Al is used. x Ga 1-x As 1-y P y The material forms a buffer layer, Al x Ga 1-x As 1-y P y The introduction of P in Al makes Al x Ga 1-x As 1-y P y Its lattice constant is closer to that of GaAs, utilizing Al x Ga 1-x As 1-y P y The material forms a buffer layer, which can reduce the lattice mismatch between the buffer layer and the substrate, and improve the quality of crystal growth; at the same time, the introduction of P can also increase the Al content. x Ga 1-x As 1-y P y The bandgap of the material makes Al x Ga 1-x As 1-y P y The required Al content is reduced, thereby reducing the density of Al-introduced defect centers and improving the device performance of heterojunction bipolar transistors.

[0033] Optionally, in this embodiment of the invention, the material Al for forming the buffer layer 2 is not limited. x Ga 1-x As 1-y P y The proportions of each element component can be adjusted by those skilled in the art according to the actual situation.

[0034] For example, in one possible embodiment, the value of x ranges from 0 to 90%, and the value of y ranges from 0.5 to 10%.

[0035] Specifically, in this embodiment, Al can be set. x Ga 1-x As 1-y P y The content of Al component ranges from 0% to 90%, while the content of P component ranges from 0.5% to 10%. According to experimental tests, when the contents of Al and P components are within these two ranges respectively, based on the formation of Al... x Ga 1-x As 1-y P yThe buffer layer 2 has a large bandgap, which effectively reduces leakage current. At the same time, the lattice matching between the buffer layer 2 and the substrate 1 is also good, resulting in fewer defects inside the device and better overall performance of the heterojunction bipolar transistor device.

[0036] Optionally, the embodiments of the present invention do not limit the specific doping methods of the collector layer 3, base layer 4, emitter layer 5 and emitter cap layer 6, and those skilled in the art can set them according to the actual device fabrication requirements.

[0037] For example, in a possible embodiment, the material of the collector layer 3 comprises N-type doped GaAs with a doping concentration of 1 × 10⁻⁶. 15 ~2×10 18 cm -3 .

[0038] In this embodiment, the epitaxial structure of the heterojunction bipolar transistor can be used to fabricate an NPN semiconductor device. The collector layer 3 can be formed using N-type doped GaAs material, with an N-type doping concentration of 1×10⁻⁶. 15 ~2×10 18 cm -3 Internal regulation.

[0039] For example, in a possible embodiment, the material of the base layer 4 includes one of p-type doped GaAs, p-type doped GaAsSb, or p-type doped InGaAs, with a doping concentration of 1 × 10⁻⁶. 19 ~8×10 19 cm -3 .

[0040] When fabricating NPN semiconductor devices, a P-type doped material can be used to form the base layer 4, specifically one of P-type doped GaAs, P-type doped GaAsSb, or P-type doped InGaAs. The doping concentration can be controlled within the range of 1×10⁻⁶. 19 ~8×10 19 cm -3 Within this doping concentration range, the device exhibits good performance.

[0041] Alternatively, the material of the emitter layer 5 may include N-type doped InGaP with a doping concentration of 5 × 10⁻⁶. 16 ~1×10 18 cm -3 .

[0042] For example, in this embodiment, the emitter layer 5 can be prepared from N-type doped InGaP material, and the doping concentration can be controlled at 5 × 10⁻⁶. 16 ~1×10 18 cm -3 Within the range, to form heterojunction bipolar transistor devices.

[0043] Optional, still referencing Figure 1 In a possible embodiment, the epitaxial structure may further include a lower ohmic contact layer 7 and an upper ohmic contact layer 8; the lower ohmic contact layer 7 is located between the buffer layer 2 and the collector layer 3; the upper ohmic contact layer 8 is located on the side surface of the emitter cap layer 6 away from the emitter layer 5.

[0044] like Figure 1 As shown, the epitaxial structure also includes a lower ohmic contact layer 7 and an upper ohmic contact layer 8. The lower ohmic contact layer 7 is formed on the side surface of the buffer layer 2 away from the substrate 1. After the buffer layer 2 is prepared, the lower ohmic contact layer 7 is prepared on the upper surface of the buffer layer 2. Then, the collector layer 3 is prepared on the side surface of the lower ohmic contact layer 7 away from the buffer layer 2, i.e., the upper surface of the lower ohmic contact layer 7.

[0045] Correspondingly, the upper ohmic contact layer 8 is formed on the surface of the emitter cap layer 6 away from the emitter layer 5. After the emitter cap layer 6 is prepared, the upper ohmic contact layer 8 is prepared on the upper surface of the emitter cap layer 6.

[0046] When fabricating devices using epitaxial structures, the presence of the ohmic contact layer enables the metal electrode to form a low-resistance ohmic contact with the collector layer 3 and the emitter layer 5. A good ohmic contact is beneficial for current input and output, and helps to improve the performance of transistor devices.

[0047] The specific preparation process of each of the above-mentioned epitaxial films can be set by those skilled in the art according to actual needs, and the embodiments of the present invention will not elaborate on or limit this process.

[0048] Optionally, in one possible embodiment, the material of the lower ohmic contact layer 7 comprises N-type doped GaAs with a doping concentration of 1 × 10⁻⁶. 18 ~2×10 19 cm -3 The material of the upper ohmic contact layer 8 is N-type doped GaAs or N-type doped InGaAs, with a doping concentration of 1×10⁻⁶. 18 ~1×10 20 cm -3 .

[0049] For example, in this embodiment, each ohmic contact layer can be N-type doped, wherein the material forming the lower ohmic contact layer 7 can be N-type doped GaAs, and the doping concentration can be controlled at 1×10⁻⁶. 18 ~2×10 19 cm -3 Within this range, the material forming the upper ohmic contact layer 8 is N-type doped GaAs or N-type doped InGaAs, and the doping concentration can be controlled within 1×10⁻⁶. 18 ~1×10 20cm -3 Within the range.

[0050] Optional, Figure 2 This is a schematic diagram of the epitaxial structure of another heterojunction bipolar transistor provided in an embodiment of the present invention. (See reference...) Figure 2 In a possible embodiment, the epitaxial structure may further include an etching stop layer 9, which is disposed between the collector layer 3 and the lower ohmic contact layer 7.

[0051] like Figure 2 As shown, the epitaxial structure also includes an etching stop layer 9, which is located between the collector layer 3 and the lower ohmic contact layer 7. That is, after the lower ohmic contact layer 7 is prepared, the etching stop layer 9 is prepared on the side of the lower ohmic contact layer 7 away from the buffer layer 2. After the etching stop layer 9 is prepared, the collector layer 3 is prepared on the side of the etching stop layer 9 away from the lower ohmic contact layer 7.

[0052] In the fabrication process of heterojunction bipolar transistors, the etching stop layer 9 can play the role of etching stop, making it easier to control the precision during etching.

[0053] For the purposes of this invention, the specific material of the etching stop layer 9 is not limited, and those skilled in the art can select it according to actual needs.

[0054] For example, in one possible embodiment, the material of the etch stop layer 9 comprises N-type doped InGaP with a doping concentration of 1 × 10⁻⁶. 17 ~5×10 18 cm -3 .

[0055] In this embodiment, the material forming the etching stop layer 9 may include N-type doped InGaP, and the N-type doping concentration is controlled at 1×10⁻⁶. 17 ~5×10 18 cm -3 Within this range, according to experimental tests, controlling the doping concentration within this range can ensure the etching cutoff effect of the etching cutoff layer 9 without affecting the device performance.

[0056] Additionally, in a possible embodiment, the emitter capping layer 6 is made of N-type doped GaAs with a doping concentration of 1 × 10⁻⁶. 17 ~5×10 18 cm -3 .

[0057] The doping type and / or doping concentration of the epitaxial film can be adjusted by regulating parameters such as the type and / or rate of gas introduced during the growth of each epitaxial film. In specific preparation, those skilled in the art can set these parameters according to their needs. This embodiment of the invention does not elaborate on or limit these parameters.

[0058] The epitaxial structure of the heterojunction bipolar transistor provided in this embodiment of the invention may also include any other film structure known to those skilled in the art, which will not be elaborated or limited in this embodiment of the invention.

[0059] Based on the same concept, this embodiment of the invention also provides a heterojunction bipolar transistor, which adopts all the technical features and corresponding beneficial effects of the epitaxial structure of the heterojunction bipolar transistor provided in any embodiment of the invention, which will not be repeated here.

[0060] The heterojunction bipolar transistor provided in this embodiment of the invention may also include any other structures known to those skilled in the art, which are not described in detail or limited in this embodiment of the invention.

[0061] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. An epitaxial structure of a heterojunction bipolar transistor, characterized in that, It includes a substrate, a buffer layer, a collector layer, a base layer, an emitter layer, and an emitter cap layer that are stacked sequentially. The substrate includes a GaAs substrate, and the buffer layer is made of Al. x Ga 1-x As 1-y P y The material of the current collector layer includes GaAs; The Al x Ga 1-x As 1-y P y The material is used to reduce the lattice mismatch between the buffer layer and the GaAs substrate, while increasing the material bandgap and reducing the Al composition requirement, so as to reduce the density of Al-introduced defect centers. Among them, 0 <x≤90%,0.5%≤y≤10%。 2. The epitaxial structure of the heterojunction bipolar transistor according to claim 1, characterized in that, The current collector layer is made of N-type doped GaAs with a doping concentration of 1×10⁻⁶. 15 ~2×10 18 cm -3 .

3. The epitaxial structure of the heterojunction bipolar transistor according to claim 1, characterized in that, The base layer material includes one of P-type doped GaAs, P-type doped GaAsSb, or P-type doped InGaAs, with a doping concentration of 1×10⁻⁶. 19 ~8×10 19 cm -3 .

4. The epitaxial structure of the heterojunction bipolar transistor according to claim 1, characterized in that, The emitter layer is made of N-type doped InGaP with a doping concentration of 5 × 10⁻⁶. 16 ~1×10 18 cm -3 .

5. The epitaxial structure of the heterojunction bipolar transistor according to claim 1, characterized in that, It also includes a lower ohmic contact layer and an upper ohmic contact layer; the lower ohmic contact layer is located between the buffer layer and the collector layer; the upper ohmic contact layer is located on the side surface of the emitter cap layer away from the emitter layer.

6. The epitaxial structure of the heterojunction bipolar transistor according to claim 5, characterized in that, The material of the lower ohmic contact layer comprises N-type doped GaAs with a doping concentration of 1×10⁻⁶. 18 ~2×10 19 cm -3 The material of the upper ohmic contact layer is N-type doped GaAs or N-type doped InGaAs, with a doping concentration of 1×10⁻⁶. 18 ~1×10 20 cm -3 .

7. The epitaxial structure of the heterojunction bipolar transistor according to claim 5, characterized in that, It also includes an etching stop layer, which is disposed between the collector layer and the lower ohmic contact layer.

8. The epitaxial structure of the heterojunction bipolar transistor according to claim 7, characterized in that, The etching stop layer is made of N-type doped InGaP with a doping concentration of 1×10⁻⁶. 17 ~5×10 18 cm -3 .

9. A heterojunction bipolar transistor, characterized in that, It is fabricated using the epitaxial structure of the heterojunction bipolar transistor as described in any one of claims 1 to 8.

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