Semiconductor devices and their fabrication methods, memory systems and electronic devices

Abstract

This disclosure provides a semiconductor device and a method for fabricating the same. The semiconductor device includes a first semiconductor structure, which includes a core region. The core region includes a semiconductor layer, a stacked structure on the semiconductor layer, and a memory channel structure and a virtual channel structure extending through the stacked structure and into the semiconductor layer. The core region includes an adjacent first region and a second region, the first region including the memory channel structure and the second region including the virtual channel structure. The core region also includes an isolation structure located between the memory channel structure and the virtual channel structure and extending through the semiconductor layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and in particular to a semiconductor device, a method for fabricating the same, a storage system, and an electronic device. Background Technology

[0002] With the continuous development of semiconductor technology, memory manufacturing technology has gradually transitioned from simple planar structures to more complex three-dimensional structures, increasing integration density by arranging memory cells three-dimensionally on a substrate. The development of this three-dimensional memory device technology is one of the mainstream international research trends.

[0003] In the manufacturing process of 3D storage devices, storage channel structures and virtual channel structures are usually set up. However, virtual channel structures often have leakage problems, which can affect the performance of storage channel structures and thus affect product yield. Summary of the Invention

[0004] In view of the above, this disclosure provides a semiconductor device, a method for fabricating the same, a storage system, and an electronic device to solve at least one problem existing in the prior art.

[0005] To achieve the above objectives, the technical solution of this disclosure embodiment is implemented as follows:

[0006] A first aspect of this disclosure provides a semiconductor device, the semiconductor device comprising:

[0007] A first semiconductor structure, the first semiconductor structure including a core region;

[0008] The core region includes a semiconductor layer, a stacked structure located on the semiconductor layer, and a memory channel structure and a virtual channel structure that penetrate the stacked structure and extend into the semiconductor layer; the core region includes an adjacent first region and a second region, the first region including the memory channel structure, and the second region including the virtual channel structure;

[0009] The core region also includes an isolation structure located between the memory channel structure and the virtual channel structure, and extending through the semiconductor layer.

[0010] According to one embodiment of the present disclosure, the channel layer and the semiconductor layer in the virtual channel structure are in electrical contact; the channel layer and the semiconductor layer at the end of the memory channel structure away from the stacked structure are in electrical contact.

[0011] According to one embodiment of this disclosure, the isolation structure penetrates the semiconductor layer of the first region, or the isolation structure penetrates the semiconductor layer of the second region.

[0012] According to one embodiment of this disclosure, the core region further includes a source contact located in the first region and in contact with the side of the semiconductor layer away from the stacked structure; the isolation structure is located between the source contact and the virtual channel structure.

[0013] According to one embodiment of the present disclosure, the first semiconductor structure includes a plurality of memory blocks; the isolation structure is a ring structure, and each isolation structure surrounds all memory channel structures of at least one of the memory blocks.

[0014] According to one embodiment of this disclosure, the virtual channel structure includes a first virtual channel structure and a second virtual channel structure; the second region includes a first sub-region and a second sub-region located on the side of the first sub-region closer to the first region, the first sub-region includes the first virtual channel structure, and the second sub-region includes the second virtual channel structure; the distribution density of the first virtual channel structure is less than the distribution density of the storage channel structure.

[0015] According to one embodiment of this disclosure, the isolation structure is located between the storage channel structure of the first region and the second virtual channel structure of the second sub-region.

[0016] According to one embodiment of this disclosure, the virtual channel structure further includes a third virtual channel structure; the second region further includes a third sub-region located on the side of the first sub-region away from the second sub-region, the third sub-region including the third virtual channel; the distribution density of the third virtual channel structure is less than the distribution density of the first virtual channel structure.

[0017] According to one embodiment of the present disclosure, the method includes an isolation trench penetrating the semiconductor layer and an insulating material located within the isolation trench.

[0018] According to one embodiment of the present disclosure, the first semiconductor structure further includes a peripheral region; the peripheral region includes a peripheral contact penetrating the semiconductor layer; the width of the isolation structure is smaller than the width of the peripheral contact.

[0019] A second aspect of this disclosure provides a method for fabricating a semiconductor device, the method comprising:

[0020] A first semiconductor structure is formed on a first substrate. The first semiconductor structure includes a core region. The core region includes a semiconductor layer, a stacked structure formed on the semiconductor layer, and a memory channel structure and a virtual channel structure extending through the stacked structure and into the semiconductor layer. The core region includes an adjacent first region and a second region, the first region including the memory channel structure, and the second region including the virtual channel structure.

[0021] An isolation structure is formed between the memory channel structure and the virtual channel structure, extending through the semiconductor layer.

[0022] According to one embodiment of the present disclosure, the method further includes: forming a source contact on the first region that contacts the side of the semiconductor layer away from the stacked structure and is located on the side of the isolation structure away from the virtual channel structure.

[0023] According to one embodiment of this disclosure, the first semiconductor structure further includes a peripheral region; the step of forming an isolation structure penetrating the semiconductor layer between the memory channel structure and the virtual channel structure includes: forming a dielectric layer on the side of the semiconductor layer away from the stacked structure; etching the dielectric layer and the semiconductor layer through a first mask to form a peripheral contact trench in the peripheral region while simultaneously forming an isolation trench between the memory channel structure and the virtual channel structure; the peripheral contact trench and the isolation trench penetrating the dielectric layer and the semiconductor layer; and filling the peripheral contact trench and the isolation trench to respectively form a peripheral contact and the isolation structure.

[0024] According to one embodiment of this disclosure, etching the dielectric layer and the semiconductor layer through a first mask to form a peripheral contact trench in the peripheral region while simultaneously forming an isolation trench between the memory channel structure and the virtual channel structure includes: forming a patterned mask layer on the dielectric layer through the first mask, the patterned mask layer having a first opening in the peripheral region and a second opening in the core region; the first opening and the second opening exposing the dielectric layer; and etching the dielectric layer and the semiconductor layer through the patterned mask layer to simultaneously form a peripheral contact trench and an isolation trench penetrating the dielectric layer and the semiconductor layer.

[0025] According to one embodiment of this disclosure, forming the first semiconductor structure includes: forming a second semiconductor layer on a first substrate; forming the stacked structure and a memory channel structure and a virtual channel structure through the stacked structure on the second semiconductor layer; a portion of the virtual channel structure extends into the second semiconductor layer, and a portion extends through the second semiconductor layer and into the first substrate; the memory channel structure extends into the second semiconductor layer; removing the first substrate to expose the channel layer of the virtual channel structure extending into the first substrate; removing the second semiconductor layer in the first region and the memory film surrounding the channel layer at the end of the memory channel structure away from the stacked structure to expose the channel layer of the memory channel structure; forming a first semiconductor layer that covers the channel layer at the end of the memory channel structure and the channel layer of the virtual channel structure extending into the first substrate; the first semiconductor layer in the first region and the second semiconductor layer in the second region constitute the semiconductor layer.

[0026] According to one embodiment of the present disclosure, forming an isolation structure penetrating the semiconductor layer between the memory channel structure and the virtual channel structure includes: forming an isolation structure penetrating the first semiconductor layer between the memory channel structure and the virtual channel structure; or forming an isolation structure penetrating the first semiconductor layer and the second semiconductor layer between the memory channel structure and the virtual channel structure.

[0027] A third aspect of this disclosure provides a storage system, including: a semiconductor device as described in any of the first aspects; and a controller electrically connected to the semiconductor device.

[0028] A fourth aspect of this disclosure provides an electronic device, including: the storage system described in the third aspect.

[0029] This disclosure provides a semiconductor device and its fabrication method. The semiconductor device includes: a first semiconductor structure, the first semiconductor structure including a core region; the core region including a semiconductor layer, a stacked structure located on the semiconductor layer, and a memory channel structure and a virtual channel structure extending through the stacked structure and into the semiconductor layer; the core region includes adjacent first and second regions, the first region including the memory channel structure, and the second region including the virtual channel structure; the core region further includes an isolation structure located between the memory channel structure and the virtual channel structure, and extending through the semiconductor layer. This disclosure, by providing an isolation structure extending through the semiconductor layer between the memory channel structure and the virtual channel structure, prevents current from being conducted through the semiconductor layer between the virtual channel structure and the memory channel structure to the virtual channel structure when the memory channel structure is energized. Since no current flows through the virtual channel structure, leakage current in the virtual channel structure can be avoided, thus preventing it from affecting the performance of the memory channel structure, thereby improving product yield. Meanwhile, since this disclosure only requires setting up an isolation structure to avoid the leakage problem of the virtual channel structure from affecting the performance of the storage channel structure, it does not require spending a lot of time to determine the specific location of the virtual channel structure where the leakage problem occurs and to repair it. Therefore, the process requirements for the virtual channel structure can be reduced, thereby shortening the product development cycle. Attached Figure Description

[0030] Figure 1a A cross-sectional view of a semiconductor device provided in an embodiment of this disclosure;

[0031] Figure 1b A top view of a semiconductor device provided in an embodiment of this disclosure;

[0032] Figure 2a A cross-sectional view of a semiconductor device provided in an embodiment of this disclosure;

[0033] Figure 2b A top view of a semiconductor device provided in an embodiment of this disclosure;

[0034] Figure 2c for Figure 2b A cross-sectional view taken along line CC'.

[0035] Figure 2d A cross-sectional view of another semiconductor device provided in an embodiment of this disclosure;

[0036] Figure 3 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present disclosure;

[0037] Figure 4 A schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this disclosure;

[0038] Figures 5a-5j This is a schematic diagram of the structure of a semiconductor device during the fabrication process, provided as an embodiment of the present disclosure. Detailed Implementation

[0039] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0040] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0041] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0042] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “below” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0043] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0044] Figure 1a This is a cross-sectional view of a semiconductor device provided in an embodiment of the present disclosure. Figure 1b This is a top view of a semiconductor device provided in an embodiment of this disclosure. Figure 1a The part to the left of the middle dashed line is Figure 1b The cross-sectional view taken along line AA', the part to the right of the dashed line is... Figure 1b A cross-sectional view taken along line BB'. Combined with... Figure 1a and Figure 1b As shown, the semiconductor device includes a semiconductor layer 110, a stacked structure 120 located on the semiconductor layer 110, and a memory channel structure 130 and a virtual channel structure 140 extending through the stacked structure 120 and into the semiconductor layer 110. The virtual channel structure 140 is not used for memory functions. The virtual channel structure 140 typically suffers from leakage current, especially the first virtual channel structure 141 within the virtual channel structure 140, where the leakage problem is more pronounced. When the memory channel structure 130 is powered on, current flows through the semiconductor layer 110 to the virtual channel structure 140. Due to the leakage current in the virtual channel structure 140, current leaks from the virtual channel structure 140 to the gate layer 121 in the stacked structure 120, thereby affecting the performance of other memory channel structures 130 and reducing product yield.

[0045] Therefore, this disclosure provides a semiconductor device. Figure 2a This is a cross-sectional view of a semiconductor device provided in an embodiment of the present disclosure. Figure 2b This is a top view of a semiconductor device provided in an embodiment of this disclosure. Figure 2a The part to the left of the middle dashed line is Figure 2b The cross-sectional view taken along line AA', the part to the right of the dashed line is... Figure 2b A cross-sectional view taken along line BB'. Combined with... Figure 2a and Figure 2bAs shown, the semiconductor device includes a first semiconductor structure 100, which includes a core region 101. The core region 101 includes a semiconductor layer 110, a stacked structure 120 located on the semiconductor layer 110, and a memory channel structure 130 and a virtual channel structure 140 extending through the stacked structure 120 and into the semiconductor layer 110. The X and Y directions are parallel to the surface of the semiconductor layer 110, with the X direction perpendicular to the Y direction; the Z direction is perpendicular to the surface of the semiconductor layer 110. Figure 2b The number of storage channel structures 130 and virtual channel structures 140 is used merely as an example to illustrate embodiments of this disclosure and is not intended to limit the scope of this disclosure. It should be noted that... Figure 2a The portion to the left of the dashed line shows only one first virtual channel structure 141 in the first sub-region 107, one second virtual channel structure 142 in the second sub-region 108, two third virtual channel structures 143 in the third sub-region 109, and two storage channel structures 130 in the first region 102 as examples, and is not intended to limit the embodiments of this disclosure. Figure 2a The portion to the right of the dashed line only shows one memory channel structure 130 within the first region 102 as an example and is not intended to limit the embodiments of this disclosure. In some embodiments, the semiconductor layer 110 may be a doped semiconductor layer, specifically, the semiconductor layer 110 may be an N-type doped semiconductor layer. The N-type doped semiconductor layer may include a semiconductor material, such as silicon. In some embodiments, the N-type doped semiconductor layer includes polycrystalline silicon formed by a deposition process. The N-type doped semiconductor layer may be doped with any suitable N-type dopant (e.g., phosphorus (P), arsenic (Ar), or antimony (Sb)), which contributes free electrons and increases the conductivity of the intrinsic semiconductor. For example, the N-type doped semiconductor layer may be a polycrystalline silicon layer doped with an N-type dopant (e.g., P, Ar, or Sb).

[0046] The stacked structure 120 is formed by alternating stacked gate layers 121 and insulating layers 122. The gate layers 121 and insulating layers 122 may have the same thickness or different thicknesses. Each gate layer 121 may be adjacent to two insulating layers 122 on its upper and lower sides, and each insulating layer 122 may be adjacent to two gate layers 121 on its upper and lower sides. The gate layers 121 may extend laterally (along a direction parallel to the semiconductor layers) as word lines, terminating at one or more steps in the stacked structure 120. In some embodiments, each gate layer 121 may include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The material of the gate electrode includes, but is not limited to, W, Co, Cu, Al, polysilicon, silicides, or any combination thereof, and the material of the gate dielectric layer may include a high-k dielectric material, wherein the high-k dielectric material is a material with a dielectric constant greater than 3.9. The material of the insulating layer 122 includes, but is not limited to, silicon oxide.

[0047] Core region 101 includes adjacent first region 102 and second region 103. First region 102 includes a storage channel structure 130, and second region 103 includes a virtual channel structure 140. Virtual channel structure 140 includes a first virtual channel structure 141, a second virtual channel structure 142, and a third virtual channel structure 143. Second region 103 includes a first sub-region 107, a second sub-region 108 located on the side of first sub-region 107 closer to first region 102, and a third sub-region 109 located on the side of first sub-region 107 away from second sub-region 108. Specifically, first sub-region 107 includes the first virtual channel structure 141, second sub-region 108 includes the second virtual channel structure 142, and third sub-region 109 includes the third virtual channel structure 143. First sub-region 107 is located between second sub-region 108 and third sub-region 109.

[0048] In some embodiments, the isolation structure 180 is located between the storage channel structure 130 of the first region 102 and the second virtual channel structure 142 of the second sub-region 108.

[0049] In some embodiments, for the first sub-region 107, the distribution density of the first virtual channel structure 141 is less than the distribution density of the storage channel structure 130. In some embodiments, for the second sub-region 108, the distribution density of the second virtual channel structure 142 is equal to the distribution density of the storage channel structure 130. In some embodiments, for the third sub-region 109, the distribution density of the third virtual channel structure 143 is less than the distribution density of the first virtual channel structure 141. For example, the storage channel structure 130 is distributed with a first density in the first region 102, the first virtual channel structure 141 is distributed with a second density in the first sub-region 107 of the second region 103, the second virtual channel structure 142 is distributed with a first density in the second sub-region 108 of the second region 103, and the third virtual channel structure 143 is distributed with a third density in the third sub-region 109 of the second region 103, wherein the first density is greater than the second density, and the second density is greater than the third density. In some embodiments, the first virtual channel structure 141 and the second virtual channel structure 142 have the same internal structure and filling material as the storage channel structure 130, while the third virtual channel structure 143 has a different internal structure and filling material from the storage channel structure 130. For example, the third virtual channel structure 143 may be filled with insulating material to provide support and prevent the collapse of the stacked structure 120. In other embodiments, the third virtual channel structure 143 may also be located in the step region 104. In the embodiments of this application, the distribution density of the virtual channel structure and the storage channel structure gradually increases along the X direction, making the distribution of the channel structure in the core area more gradual and avoiding process problems caused by excessive differences in distribution density between adjacent areas.

[0050] In some embodiments, the critical dimension (CD) of the first virtual channel structure 141 is greater than the critical dimensions of the storage channel structure 130 and the second virtual channel structure 142. Here, the critical dimension of the first virtual channel structure 141 refers to the dimension of the first virtual channel structure 141 in a plane perpendicular to the Z direction. For example, when the orthographic projection of the first virtual channel structure 141 in the plane perpendicular to the Z direction is a circle, the critical dimension of the first virtual channel structure 141 refers to the diameter or radius of the orthographic projection of the first virtual channel structure 141 in the plane perpendicular to the Z direction.

[0051] To form the memory channel structure 130, a memory channel hole (CH) is first formed through the stacked structure 120 and extending into the semiconductor layer 110. This memory channel hole can be cylindrical. Then, a barrier layer, a memory layer, a tunneling layer, and a channel layer are sequentially formed within the memory channel hole, wherein the barrier layer, memory layer, and tunneling layer constitute the memory film of the memory channel structure 130. The fabrication process for forming the memory channel hole includes wet etching and / or dry etching. In some embodiments, the barrier layer and tunneling layer may comprise silicon oxide, silicon oxynitride, or any combination thereof; the memory layer may comprise silicon nitride, silicon oxynitride, silicon, or any combination thereof; and the channel layer 131 comprises silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. One or more thin-film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof, can be used to form the memory film and the channel layer 131. In one example, the memory film may comprise a composite layer of silicon oxide / silicon nitride / silicon oxide (ONO).

[0052] To form the virtual channel structure 140, a dummy channel hole (DCH) can be formed first. In some embodiments, the dummy channel hole and the memory channel hole are formed using the same mask. In other embodiments, the first dummy channel hole corresponding to the first dummy channel structure 141 and the second dummy channel hole corresponding to the second dummy channel structure 142 are formed using the same mask, while the third dummy channel hole corresponding to the third dummy channel structure 143 and the memory channel hole are formed using different masks. In some embodiments, the dummy channel hole can be cylindrical. It should be noted that as the number of stacked layers of the semiconductor device increases, the etching depth of the memory channel hole and the dummy channel hole also increases, resulting in different depths to which multiple dummy channel structures 140 and memory channel structures 130 extend into the semiconductor layer 110.

[0053] The storage channel structure 130 is electrically contacted with the semiconductor layer 110 through the channel layer 131. In some embodiments, the storage film of the storage channel structure 130 may terminate at the surface of the semiconductor layer 110 near the stacked structure 120, while the channel layer 131 may extend within the semiconductor layer 110, such that the storage channel structure 130 can be electrically contacted with the semiconductor layer 110 through the channel layer 131.

[0054] In some embodiments, etching is used to remove the memory film surrounding the channel layer 131 at the end of the memory channel structure 130 away from the stacked structure, thereby exposing the channel layer 131 at the end of the memory channel structure 130, allowing the memory channel structure 130 to make electrical contact with the subsequently formed first semiconductor layer 111 through the channel layer 131. A wet etching process can be used to remove the memory film surrounding the channel layer 131 at the end of the memory channel structure 130, thereby exposing the channel layer 131 at the end of the memory channel structure 130. As described above, the memory channel structure 130 includes a channel layer 131 and a memory film, the memory film comprising a barrier layer, a memory layer, and a tunneling layer sequentially inward along the radial direction of the memory channel structure 130. In some embodiments, a wet etching process can be used to selectively remove the barrier layer, memory layer, and tunneling layer at the end of the memory channel structure 130 without etching the channel layer 131. The etching of the memory film can also be controlled by controlling the etching time and / or etching rate, so that the etching does not further affect the remaining portion of the memory film surrounded by the stacked structure 120. In one example, the memory film is a composite layer comprising silicon oxide / silicon nitride / silicon oxide (ONO). A suitable etchant can be selected based on the etch selectivity ratio of silicon oxide and silicon nitride to sequentially remove the barrier layer, memory layer, and tunneling layer. Alternatively, an etchant capable of simultaneously removing both silicon oxide and silicon nitride can be used to simultaneously remove the memory film surrounding the channel layer. When etching using the etch selectivity ratio of silicon oxide and silicon nitride, for example, hydrofluoric acid can be used as an etchant to selectively remove silicon oxide, while an etchant such as phosphoric acid can be used to selectively remove silicon nitride.

[0055] In some embodiments, the channel layer 131 extending into the semiconductor layer 110 at the end of the storage channel structure 130 can be a doped channel layer. In some embodiments, an ion implantation process is performed on the channel layer 131 at the end of the storage channel structure 130 to form a doped channel layer at the end of the storage channel structure 130. In the ion implantation process, the implantation depth of the doped ions can be controlled by controlling the ion implantation energy. Here, the doped channel layer and the stacked structure 120 overlap in the extension direction (Z direction) of the storage channel structure 130. In other embodiments, different doping depths, doping concentrations, or doping profiles can be set according to the actual needs of the semiconductor device. The doping depth can be controlled by adjusting the acceleration energy of the ion beam; the doping concentration, i.e., the doping dose, can be controlled by monitoring the ion current during implantation; and the doping profile can be controlled by simultaneously adjusting the ion implantation energy and the ion implantation dose. Therefore, using an ion implantation process for doping allows for more accurate control of the doping concentration, doping depth, and doping profile, and provides repeatability.

[0056] In some embodiments, the doped channel layer is activated. This activation process may include thermal activation or laser activation. It should be noted that the laser activation temperature is lower than the high-temperature annealing activation temperature. In practical applications, the activation process can be selected according to actual needs to avoid the activation temperature affecting subsequent processes.

[0057] The doping type of the doped channel layer and the doped semiconductor layer can be the same. The doped channel layer and the stacked structure 120 overlap in the extension direction (Z direction) of the memory channel structure 130. At this time, the channel layer 131 of the memory channel structure 130 includes two parts: a doped channel layer and an undoped channel layer, with the undoped channel layer located on the side of the doped channel layer closer to the second semiconductor structure 200.

[0058] In some embodiments, the doped channel layer may be an N-type doped channel layer. ， This enables gate-induced drain leakage (GIDL) erasure. Specifically, the N-type doped channel layer can include, for example, polycrystalline silicon, monocrystalline silicon, or amorphous silicon. The N-type doped channel layer can include pentavalent impurity elements such as P, Ar, or Sb as N-type dopants. Since only four valence electrons in a pentavalent impurity atom can form covalent bonds with the valence electrons in the surrounding four semiconductor atoms, the extra valence electron easily becomes a free electron due to the lack of covalent bond binding. Therefore, the N-type doped channel layer can provide free electrons. In some embodiments, a channel contact 193 is provided at the end of each memory channel structure 130 away from the semiconductor layer 110. The channel contact 193 is used to electrically extract the signal in the memory channel structure 130.

[0059] In some embodiments, a portion of the virtual channel structure 140 (e.g., the second virtual channel structure 142) is etched to a deeper depth, allowing this portion of the virtual channel structure to extend into the substrate. During subsequent removal of the substrate using a chemical mechanical polishing (CMP) process, the channel layer of this portion of the virtual channel structure extending into the substrate is exposed, enabling this portion of the virtual channel structure to make electrical contact with the subsequently formed first semiconductor layer 111 through its channel layer. For example... Figure 2a As shown, the channel layer of the second virtual channel structure 142 is in electrical contact with the semiconductor layer 110.

[0060] The first semiconductor structure 100 further includes a gate isolation structure 160 extending through the stacked structure 120 and into the semiconductor layer 110. The gate isolation structure 160 extends in the X direction. The gate isolation structure 160 includes an electrical shielding layer 161 and a capping layer surrounding the electrical shielding layer 161. The gate isolation structure 160 can divide multiple memory strings into different memory blocks, or divide memory blocks into different memory fingers. In some embodiments, the capping layer may terminate at a surface of the semiconductor layer 110 near the stacked structure 120, while the electrical shielding layer 161 may extend within the semiconductor layer 110. The material of the electrical shielding layer 161 includes, but is not limited to, W, Co, Cu, Al, silicides, or any combination thereof, and the material of the capping layer includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. Here, the material of the capping layer can be the same as that of the storage film, so that when the storage film surrounding the channel layer 131 at the end of the storage channel structure 130 is removed, the capping layer surrounding the electrical shielding layer 161 at the end of the gate line isolation structure 160 is also removed, so as to expose the electrical shielding layer 161 at the end of the gate line isolation structure 160.

[0061] The first semiconductor structure 100 also includes a step region 104 and a peripheral region 105. The peripheral region 105 is used to form peripheral contact structures for electrical signal connections, and may be located around the core region 101 and the step region 104. The step region 104 includes multiple steps, with the top surface of each step exposing the gate layer 121. The step region 104 may be formed by performing multiple so-called "trim-etch" cycles on the stacked structure 120 toward the semiconductor layer 110. In some embodiments, the step region 104 includes multiple step contacts 191, which are in conductive contact with the gate layer 121 exposed on the corresponding step top surface. It should be noted that... Figure 2a The number of steps in the middle step region 104 and the number of stacked layers in the stacked structure 120 are used only as illustrative examples of embodiments of this disclosure and are not intended to limit the embodiments of this disclosure. The peripheral region 105 includes a plurality of peripheral contact structures 192. The peripheral contact structures 192 are used to bring out the portion of the peripheral circuit of the second semiconductor structure 200 to be electrically led out to the first semiconductor structure 100.

[0062] In some embodiments, the first semiconductor structure 100 further includes a first bonding layer 106. The first bonding layer 106 includes a plurality of first bonding contacts electrically connected to the stepped contact 191, the peripheral contact structure 192, and the channel contact 193. The first bonding layer 106 may also include an insulating material for electrically isolating the first bonding contacts. The material of the first bonding contacts may include, but is not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The insulating material used for electrically isolating the first bonding contacts may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0063] In some embodiments, the first semiconductor structure 100 further includes a first interconnect layer 190 located above the first bonding layer 106. The first interconnect layer 190 can be used to transmit electrical signals. The first interconnect layer 190 may include interconnects (metals) 194, contacts (vias) 195, and an interlayer dielectric layer. The interconnects 194 and contacts 195 can both be formed in the interlayer dielectric layer, that is, the first interconnect layer 190 may include a plurality of interconnects 194 and contacts 195 located in the interlayer dielectric layer. Stepped contacts 191, peripheral contact structures 192, and channel contacts 193 are connected to corresponding interconnects 194 in the first interconnect layer 190. Specifically, the materials of the interconnects 194 and contacts 195 in the first interconnect layer 190 may include, but are not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The materials of the interlayer dielectric layer include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. As an example, the interlayer dielectric layer includes a first silicon nitride layer 196 and silicon oxide material filling the gaps between the interconnects 194 and contacts 195.

[0064] In some embodiments, the isolation structure 180 penetrates the semiconductor layer 110 of the first region 102, or the isolation structure penetrates the semiconductor layer 110 of the second region 103.

[0065] Semiconductor layer 110 includes a first semiconductor layer 111 located in core region 101, step region 104, and peripheral region 105, and a second semiconductor layer 112 located in second region 103, step region 104, and peripheral region 105. The thickness of the first semiconductor layer 111 is greater than the thickness of the second semiconductor layer 112. Here, the thickness of the first semiconductor layer 111 or the second semiconductor layer 112 refers to its length in the Z direction. In some embodiments, the first semiconductor layer 111 and the second semiconductor layer 112 are made of the same material and are both doped semiconductor layers with the same doping type. The first semiconductor layer 111 and the second semiconductor layer 112 are formed in different processes. In some embodiments, a second semiconductor layer 112 is formed on a substrate, and a stacked structure 120 and a memory channel structure 130, a virtual channel structure 140, and a gate isolation structure 160 extending through the stacked structure 120 are formed on the second semiconductor layer 112. A portion of the virtual channel structure 140 (e.g., a first virtual channel structure 141 and a third virtual channel structure 143) extends into the second semiconductor layer 112, and a portion (e.g., the second virtual channel structure 142) penetrates the second semiconductor layer 112 and extends into the substrate; the memory channel structure 130 and the gate isolation structure 160 extend into the substrate. A second semiconductor layer 112 is formed; the substrate is removed to expose the channel layer of the second virtual channel structure 142 extending into the substrate; then the second semiconductor layer 112 on the first region 102 is etched away to expose the ends of the memory channel structure 130 and the gate isolation structure 160 within the first region 102; the memory film surrounding the channel layer 131 at the end of the memory channel structure 130 and the capping layer surrounding the electrical shielding layer 161 at the end of the gate isolation structure 160 are etched away to expose the channel layer 131 at the end of the memory channel structure 130 and the electrical shielding layer 161 at the end of the gate isolation structure 161. Then a first semiconductor layer 111 is formed, which covers the channel layer of the second virtual channel structure 142, the channel layer 131 at the end of the memory channel structure 130, and the end of the gate isolation structure 160.

[0066] In some embodiments, the first semiconductor structure 100 further includes a third semiconductor layer 113 located between the semiconductor layer 110 and the stacked structure 120. The third semiconductor layer 113 may serve as an etch stop layer. The material of the third semiconductor layer 113 includes, but is not limited to, silicon oxide, silicon nitride, and polysilicon. In some embodiments, the material of the third semiconductor layer 113 is the same as the material of the semiconductor layer 110.

[0067] In some embodiments, the first semiconductor structure 100 further includes a dielectric layer 114 located on the side of the semiconductor layer 110 away from the stacked structure 120. The material of the dielectric layer 114 includes, but is not limited to, silicon oxide, silicon nitride, and polysilicon.

[0068] The first semiconductor structure 100 also includes a peripheral contact 170 located in the peripheral region 105. In a specific example, the peripheral contact 170 may be a through silicon contact (TSC) structure. The peripheral contact 170 penetrates the dielectric layer 114, the second semiconductor layer 112, and the third semiconductor layer 113 to make electrical contact with the peripheral contact structure 192, and the peripheral contact 170 is electrically isolated from the second semiconductor layer 112 and the third semiconductor layer 113 by an isolation layer 171. The material of the peripheral contact 170 includes, but is not limited to, tungsten metal, and the material of the isolation layer 171 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. To form the peripheral contact 170, a peripheral contact opening penetrating the dielectric layer 114, the second semiconductor layer 112, and the third semiconductor layer 113 may be formed first, exposing the peripheral contact structure 192. An insulating material is filled into the peripheral contact opening to form an isolation layer 171 covering the sidewalls of the peripheral contact opening, and then a conductive material is filled into the peripheral contact opening to form the peripheral contact 170.

[0069] The core region 101 also includes a source contact 150 located in the first region 102 and in contact with the side of the semiconductor layer 110 away from the stacked structure 120. Specifically, the source contact 150 penetrates the dielectric layer 114 and makes electrical contact with the first semiconductor layer 111. In some embodiments, the source contact 150 may extend into the first semiconductor layer 111, in which case the lower surface of the source contact 150 is lower than the upper surface of the first semiconductor layer 111. The material of the source contact 150 includes, but is not limited to, tungsten. To form the source contact 150, a source contact opening penetrating the dielectric layer 114 and exposing the first semiconductor layer 114 may be formed first, and then a conductive material may be filled into the source contact opening to form the source contact 150. In some embodiments, conductive material may be filled into the source contact opening at the same time as described above, to simultaneously form the peripheral contact 170 and the source contact 150.

[0070] In some embodiments, the first semiconductor structure 100 may further include a wiring layer (not shown) located on the peripheral contact 170 and the source contact 150. This wiring layer is electrically connected to the peripheral contact 170 and the source contact 150 to enable pad take-out. For example, it facilitates the transmission of electrical signals between the first semiconductor structure 100 and the second semiconductor structure 200.

[0071] The core region 101 also includes an isolation structure 180 located between the memory channel structure 130 and the virtual channel structure 140, and between the source contact 150 and the virtual channel structure 140. The material of the isolation structure 180 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The isolation structure 180 penetrates the dielectric layer 114, the semiconductor layer 110, and the third semiconductor layer 113, electrically isolating the source contact 150 and the virtual channel structure 140. In some embodiments, the isolation structure 180 can be a backside deep trench isolation (BDTI) structure. In some embodiments, the isolation structure 180 penetrates the dielectric layer 114, the first semiconductor layer 111, the second semiconductor layer 112, and the third semiconductor layer 113 of the second region 103. The depth of the isolation structure 180 is substantially the same as the depth of the peripheral contact 170; therefore, the isolation structure 180 and the peripheral contact 170 can be formed using the same mask. To form the isolation structure 180, an isolation trench can first be formed penetrating the dielectric layer 114, the semiconductor layer 110, and the third semiconductor layer 113. This isolation trench and the aforementioned peripheral contact trench can be formed using the same mask. Then, an insulating material is filled into the isolation trench to form the isolation structure 180. In some embodiments, the isolation structure 180 can be formed simultaneously with the aforementioned filling of the peripheral contact trench with insulating material to form the isolation layer 171 covering the sidewalls of the peripheral contact trench. In other words, the isolation structure 180 includes the same insulating material (such as silicon oxide) as the isolation layer 171 of the peripheral contacts. Thus, the isolation structure is formed together with the peripheral contacts, eliminating the need for additional manufacturing processes and costs. Furthermore, the width of the isolation structure is smaller than the width of the peripheral contacts, thereby reducing the area occupied by the isolation structure.

[0072] In some embodiments, air gaps may be formed in the insulating material during the filling process of the isolation structure 180.

[0073] In some embodiments, the isolation structure 180 may further include a dielectric, which includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0074] In some embodiments, the width of the isolation structure 180 is smaller than the width of the peripheral contact 170.

[0075] In some embodiments, the width of the isolation structure 180 is smaller than the width of the gate isolation structure 160.

[0076] In some embodiments, the width of the isolation structure 180 is smaller than the aperture of the storage channel structure 130.

[0077] Combination Figure 2bAs shown, the isolation structure 180 passes through multiple grid isolation structures 160 in the Y direction. Figure 2c for Figure 2b A cross-sectional view taken along line CC', as shown below. Figure 2c As shown, the isolation structure 180 covers the gate isolation structure 160 in the Z direction. As previously described, the gate isolation structure 160 extends into the semiconductor layer 110, while the isolation structure 180 penetrates the semiconductor layer 110. Therefore, during the etching process described above... Figure 2a When the isolation structure 180 shown is etched, the portion of the gate isolation structure 160 that overlaps with the isolation structure 180 on a plane perpendicular to the Z direction and extends into the third semiconductor layer 113 and the second semiconductor layer 112 in the Z direction is removed.

[0078] Figure 2d A cross-sectional view of another semiconductor device provided in an embodiment of this disclosure. Figure 2d The semiconductor device shown is similar to Figure 2a The semiconductor devices shown differ in the location of the isolation structure 180. Specifically, Figure 2a In the semiconductor device shown, the isolation structure 180 is located in the second region 103 and penetrates the first semiconductor layer 111, the second semiconductor layer 112, and the third semiconductor layer 113. Figure 2d In the semiconductor device shown, the isolation structure 180 is located in the first region 102 and extends through the first semiconductor layer 111 and the third semiconductor layer 113. It should be understood that, for ease of description, no repetition is used. Figure 2d The semiconductor devices shown and Figure 2a Details of other identical structures in both of the semiconductor devices shown. (e.g.) Figure 2d As shown, the isolation structure 180 penetrates the dielectric layer 114, the first semiconductor layer 111 and the third semiconductor layer 113, thereby electrically isolating the memory channel structure 130 and the virtual channel structure 140.

[0079] Figure 3 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present disclosure, such as... Figure 3 As shown, the semiconductor device includes multiple memory planes 301, and each memory plane 301 may include multiple memory blocks 302. Here, Figure 2b It can be considered as Figure 3 A partially enlarged view. In some embodiments, the isolation structure 180 is a ring structure. Each isolation structure 180 surrounds all the memory channel structures of a memory surface 301. Enclosing a memory surface 301 with each isolation structure 180 reduces the area occupied by the isolation structure compared to each isolation structure 180 surrounding a memory block. It should be understood that the layout design of the isolation structure is not subject to... Figure 2bThe example of the isolation structure 180 is limited, and may include any other suitable ring structure, such as a circle, cross, annulus, triangle, etc.

[0080] In other embodiments, each isolation structure surrounds all the memory channel structures of at least one memory block.

[0081] This disclosure provides an isolation structure 180 that penetrates the semiconductor layer 110 between the memory channel structure 130 and the virtual channel structure 140. This prevents current from being conducted through the semiconductor layer 110 between the virtual channel structure 130 and the memory channel structure 130 when the memory channel structure 130 is powered on. Since no current flows through the virtual channel structure 140, leakage in the virtual channel structure 140 can be prevented from being conducted through the gate layer 121 to the memory channel structure 130, thus affecting the performance of the memory channel structure 130 and improving product yield. Furthermore, since this disclosure only requires the isolation structure 180 to prevent leakage in the virtual channel structure 140 from affecting the performance of the memory channel structure 130, it eliminates the need to spend considerable time identifying and repairing the specific location of the leakage problem in the virtual channel structure 140. This reduces the process requirements for the virtual channel structure 140, thereby shortening the product's learning cycle and accelerating mass production. Furthermore, in this disclosure, each isolation structure 180 surrounds all memory channel structures 130 of a memory surface, that is, each memory surface shares the same isolation structure 180. Therefore, the isolation structure 180 in this disclosure only needs to occupy a small area and will not affect the layout of other structures in the semiconductor device.

[0082] Return to reference Figure 2a In some embodiments, the semiconductor device further includes a second semiconductor structure 200 electrically connected to the first semiconductor structure 100. Exemplarily, the first semiconductor structure 100 may be bonded to the second semiconductor structure 200. The second semiconductor structure 200 includes a second substrate 201 and peripheral circuitry located on the second substrate 201. The second substrate 201 may include silicon (e.g., single-crystal silicon c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. The peripheral circuitry may be any suitable digital, analog, and / or mixed-signal control and sensing circuitry for the operation of the semiconductor device, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0083] The second semiconductor structure 200 further includes a second bonding layer 202, which may include a plurality of second bonding contacts and an insulating material for electrically isolating the second bonding contacts. The material of the second bonding contacts includes, but is not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The insulating material for electrically isolating the second bonding contacts may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0084] Similarly, the second semiconductor structure 200 also includes a second interconnect layer (not shown) above the peripheral circuit. The second interconnect layer is used to transmit electrical signals from the peripheral circuit, including inputting electrical signals into the peripheral circuit and outputting electrical signals from the peripheral circuit. The second interconnect layer may include peripheral interconnects, peripheral contacts, and an interlayer dielectric layer for the peripheral circuit. The peripheral interconnects and peripheral contacts can be formed within the interlayer dielectric layer; that is, the second interconnect layer may include multiple peripheral interconnects and peripheral contacts located within the interlayer dielectric layer. Specifically, the materials of the peripheral interconnects and peripheral contacts in the second interconnect layer may include, but are not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The materials of the interlayer dielectric layer include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. As an example, the interlayer dielectric layer includes a second silicon nitride layer 203 and silicon oxide material filling the gaps between the peripheral interconnects and peripheral contacts.

[0085] Figure 4 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present disclosure. Figures 5a-5j This is a schematic diagram illustrating the fabrication process of a semiconductor device according to an embodiment of this disclosure. Figure 4 As shown, in step 401, a first semiconductor structure is formed on the first substrate 500. (As illustrated...) Figure 5aAs shown, a second semiconductor layer 112 is formed on a first substrate 500, and a stacked structure 120 is formed on the second semiconductor layer 112. The stacked structure 120 is formed by alternately stacked gate layers 121 and insulating layers 122. In some embodiments, the second semiconductor layer 112 is doped using an ion implantation process before forming the stacked structure 120 to form a doped semiconductor layer. In practical applications, the stacked structure 120 can be formed by deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD). Here, the first substrate 500 can be a single-element semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a germanium-silicon (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. Since the first substrate 500 may be removed in subsequent steps, the material of the first substrate 500 can also be part of a dummy wafer (e.g., a carrier substrate) made of any suitable material to reduce the fabrication cost of the semiconductor device. For example, it can be glass, sapphire, plastic, silicon, and only a few examples are given here.

[0086] In some embodiments, the stacked structure 120 is formed on a second semiconductor layer, which can be removed from the back side to expose the ends of the memory channel structure 130. After removing the first substrate 500, a doped semiconductor layer can be deposited from the back side to electrically connect the sources of the plurality of memory channel structures, thereby increasing the conductivity of the array common source (ACS) of the memory channel structures. In some embodiments, one or more stop layers (e.g., a third semiconductor layer 113) are used to automatically stop the back side thinning process, allowing for complete substrate removal to avoid wafer thickness uniformity control issues and reduce the fabrication complexity of the back side process.

[0087] A memory channel structure 130 and a virtual channel structure 140 are formed through the stacked structure 120. A portion of the virtual channel structure 140 (e.g., the first virtual channel structure 141 and the third virtual channel structure 143) extends into the second semiconductor layer 112, and a portion (e.g., the second virtual channel structure 142) extends through the second semiconductor layer 112 and into the first substrate 500; the memory channel structure 130 extends into the second semiconductor layer 112. In some embodiments, memory channel vias and virtual channel vias that extend through the stacked structure 120 and into the second semiconductor layer 112 can be formed first using wet etching and / or dry etching. In some embodiments, the internal structure and filling material of the virtual channel structure 140 and the memory channel structure 130 are the same, and one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof can be used to form memory films and channel layers in the memory channel vias and virtual channel vias. In other embodiments, the internal structure and filling material of the virtual channel structure 140 and the storage channel structure 130 are different, and insulating material can be filled into the virtual channel holes.

[0088] A gate line isolation structure 160 is formed on the second semiconductor layer 112, penetrating the stacked structure 120 and extending into the second semiconductor layer 112. To form the gate line isolation structure 160, a gate line slit (GLS) can be formed first in the stacked structure 120, then a capping layer can be formed on the sidewalls of the gate line slit, and finally, conductive material can be filled to form an electrical shielding layer. The electrical shielding layer and the capping layer surrounding the electrical shielding layer constitute the gate line isolation structure 160. One or more thin film deposition processes, such as ALD, CVD, PVD, and any other suitable process or any combination thereof, can be used to form the capping layer and the electrical shielding layer.

[0089] The gate layer 121 in the stacked structure 120 can also be formed through the aforementioned gate line gaps. Specifically, an initial stacked structure is first formed, consisting of alternately stacked insulating and sacrificial layers. The initial stacked structure is etched to form gate line gaps. The sacrificial layer in the initial stacked structure is removed through the gate line gaps to form lateral recesses. Then, gate material is filled into the lateral recesses to form the gate layer 121. Gate materials include, but are not limited to, W, Co, Cu, Al, polysilicon, silicides, or any combination thereof.

[0090] In some embodiments, after forming the gate isolation structure 160, a step contact 192, a peripheral contact structure 191, and a channel contact 193 are formed. The step contact 192 makes a conductive contact with the gate layer 121 exposed on the corresponding step top surface. A mask layer can be formed on the stacked structure 120 by depositing a mask material (e.g., silicon oxide or silicon nitride) on top of the stacked structure 120 using one or more thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. Contact openings through the mask layer can be etched using wet etching and / or dry etching (e.g., reactive ion etching, RIE), followed by filling the contact openings with a conductive material using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof, to form the step contact 192, the peripheral contact structure 191, and the channel contact 193. In some embodiments, a first bonding layer 106 can also be formed on the stacked structure 120.

[0091] like Figure 5b As shown, Figure 5b Lieutenant General Figure 5a The first semiconductor structure 100 is flipped vertically and then bonded to the second semiconductor structure 200. In some embodiments, the first bonding layer 106 with the first semiconductor structure 100 facing downwards and the second bonding layer 202 with the second semiconductor structure 200 facing upwards are bonded face-to-face. In some embodiments, metal fusion bonding can be used to bond the first semiconductor structure 100 and the second semiconductor structure 200. Of course, in some embodiments, non-metallic bonding methods can also be used, including but not limited to using adhesives, to bond the first semiconductor structure 100 and the second semiconductor structure 200. In some embodiments, hybrid bonding, i.e., metal / non-metal hybrid bonding, can also be used to form a bonding layer between the first semiconductor structure 100 and the second semiconductor structure 200.

[0092] In some embodiments, processing techniques, such as plasma treatment, wet processing, and / or thermal treatment, may be applied to the surfaces of the first bonding layer 106 and the second bonding layer 202 prior to bonding. After bonding, the first bonding contacts in the first bonding layer 106 and the second bonding contacts in the second bonding layer 202 are aligned and made into contact, thereby electrically connecting the stacked structure 120 in the first semiconductor structure 100 and the memory channel structure 130 formed therethrough to the peripheral circuitry in the second semiconductor structure 200.

[0093] like Figure 5cAs shown, the first substrate 500 is removed to expose the channel layer of the second virtual channel structure 142 extending into the first substrate 500. The second semiconductor layer of the first region 102 is removed. The second semiconductor layer remains on the second region 103, the step region 104, and the peripheral region 105. The second semiconductor layer of the first region 102 is removed from the back side of the second semiconductor layer 112, wherein the back side of the second semiconductor layer 112 refers to the side of the second semiconductor layer 112 away from the stacked structure 120. The second semiconductor layer of the first region 102 is removed by a wet etching process to expose the ends of the memory channel structure 130 and the gate isolation structure 160. Because the wet etching process is selective, only the second semiconductor layer of the first region 102 can be etched and removed without etching the underlying structure, that is, the channel layer 131 and the memory film of the memory channel structure 130 remain intact.

[0094] The memory film surrounding the channel layer 131 at the end of the memory channel structure 130 is removed to expose the channel layer 131 of the memory channel structure 130. In some embodiments, the capping layer surrounding the electrical shielding layer 161 at the end of the gate isolation structure 160 is also removed simultaneously with the removal of the memory film surrounding the channel layer 131 at the end of the memory channel structure 130. In some embodiments, the barrier layer, memory layer, and tunneling layer at the end of the memory channel structure 130 can be selectively removed by a wet etching process without etching the channel layer 131. The etching of the memory film can also be controlled by controlling the etching time and / or etching rate so that the etching does not further affect the remaining portion of the memory film surrounded by the stacked structure 120.

[0095] like Figure 5d As shown, a first semiconductor layer 111 is formed, covering the remaining second semiconductor layer 112. The first semiconductor layer 111 covers the channel layer 131 at the end of the memory channel structure 130 and the channel layer of the second virtual channel structure 142. The thickness of the first semiconductor layer 111 is greater than the thickness of the second semiconductor layer 112, and the first semiconductor layer 111 and the second semiconductor layer 112 constitute semiconductor layer 110. In some embodiments, after forming the first semiconductor layer 111, the first semiconductor layer 111 is doped to form a doped semiconductor layer. The doping type of the doped semiconductor layer and the doped channel layer is the same. In some embodiments, the doped semiconductor layer may be an N-type doped semiconductor layer. In some embodiments, an ion implantation process is used to dope the first semiconductor layer 111 using an N-type dopant.

[0096] In step 402, an isolation structure penetrating the semiconductor layer is formed between the memory channel structure and the virtual channel structure. For example... Figure 5eAs shown, a dielectric layer 114 is formed on the side of the semiconductor layer 110 away from the stacked structure 120. The material of the dielectric layer 114 includes, but is not limited to, silicon oxide, silicon nitride, and polysilicon. Exemplarily, the dielectric layer 114 can be formed using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof.

[0097] In some embodiments, the isolation structure 180 extends through the dielectric layer 114, the second semiconductor layer 111, the second semiconductor layer 112, and the third semiconductor layer 113. For example... Figure 5f As shown, the dielectric layer 114 and the semiconductor layer 110 are etched using a first mask to form a peripheral contact trench 172 in the peripheral region 105, while simultaneously forming an isolation trench 181 between the memory channel structure 130 and the virtual channel structure 140. The peripheral contact trench 172 penetrates the dielectric layer 114, the second semiconductor layer 111, the second semiconductor layer 112, and the third semiconductor layer 113, exposing the peripheral contact structure 192. The isolation trench 181 also penetrates the dielectric layer 114, the second semiconductor layer 111, the second semiconductor layer 112, and the third semiconductor layer 113. First, a patterned mask layer (not shown) can be formed on the dielectric layer 114 using the first mask. The patterned mask layer has a first opening in the peripheral region 105 and a second opening in the core region 101, wherein the first and second openings expose the dielectric layer 114. Then, the dielectric layer 114, the second semiconductor layer 111, the second semiconductor layer 112 and the third semiconductor layer 113 are etched through a patterned mask layer to simultaneously form peripheral contact trenches 172 and isolation trenches 181 that penetrate the dielectric layer 114, the second semiconductor layer 111, the second semiconductor layer 112 and the third semiconductor layer 113.

[0098] like Figure 5gAs shown, the isolation trench 181 is filled to form an isolation structure 180. This filling step can be performed in the same step as filling the peripheral contact trench 172 with insulating material to form an isolation layer 171. One or more thin-film deposition processes, such as CVD, PVD, ALD, any other suitable process, or combinations thereof, can be used to form the isolation structure 180 within the isolation trench 181 while forming the isolation layer 171 covering the sidewalls of the peripheral contact trench 172. Specifically, insulating material can be filled into the peripheral contact trench 172 and the isolation trench 181 first, so as to form an insulating material layer covering the bottom and sidewalls of the peripheral contact trench 172, and an isolation structure 180 is formed in the isolation trench 181. Then, the insulating material layer in the peripheral contact trench 172 is subjected to anisotropic treatment so that the etching selectivity ratio of the insulating material at the bottom of the peripheral contact trench 172 and the insulating material at the sidewalls of the peripheral contact trench 172 is different. Therefore, the insulating material at the bottom of the peripheral contact trench 172 can be etched away, thereby obtaining the isolation layer 171 covering the sidewalls of the peripheral contact trench 172.

[0099] A source contact is formed on the first region, contacting the side of the semiconductor layer away from the stacked structure and located on the side of the isolation structure away from the virtual channel structure. For example... Figure 5h As shown, the dielectric layer 114 is etched to form a source contact trench 151 that penetrates the dielectric layer 114 and exposes the first semiconductor layer 111. In some embodiments, a dry etching process can be used to etch the dielectric layer 114 to form the source contact trench 151.

[0100] like Figure 5i As shown, conductive material is filled in the source contact trench 151 to form the source contact 150. In some embodiments, conductive material is filled in the peripheral contact trench 172 to form the peripheral contact 170, while conductive material is filled in the source contact trench 151 to form the source contact 150. Specifically, one or more thin film deposition processes, such as CVD, PVD, ALD, any other suitable process, or combinations thereof, can be used to deposit one or more conductive materials into the peripheral contact trench 172 and the source contact trench 151 to fill the peripheral contact trench 172 and the source contact trench 151 with binder and conductive material. Then, a planarization process, such as a chemical mechanical polishing (CMP) process, can be performed to remove excess conductive material so that the top surfaces of the peripheral contact 170 and the source contact 150 are flush with the top surface of the dielectric layer 114. In other embodiments, the source contact trench 151 and the peripheral contact trench 172 may be filled in different steps, which is not limited in this disclosure.

[0101] In other embodiments, the isolation structure 180 extends through the dielectric layer 114, the first semiconductor layer 111, and the third semiconductor layer 113, such as... Figure 5j As shown. It should be understood that, as formed... Figure 5j The method of the isolation structure shown is the same as that described above. Figures 5a-5i The preparation method is similar to that in the previous section, and will not be repeated here.

[0102] This disclosure utilizes the same mask to form a peripheral contact trench 172 in the peripheral region 105 and an isolation trench 181 in the core region 101. Simultaneously, insulating material is filled into the peripheral contact trench 172 to form an isolation layer 171 covering the sidewalls of the peripheral contact trench 172, while an isolation structure 180 is formed within the isolation trench 181. Therefore, this disclosure allows the isolation structure 180 to be formed within the existing fabrication process without requiring additional steps.

[0103] It should be noted that the description of the above semiconductor device fabrication method is similar to the description of the above semiconductor device embodiments and has similar beneficial effects, therefore it will not be repeated. For technical details not disclosed in the semiconductor device fabrication method of this disclosure embodiments, please refer to the description of the semiconductor device in this disclosure embodiments for understanding.

[0104] This disclosure also provides a storage system, which includes a controller and the semiconductor device described above in this disclosure; and a controller electrically connected to the semiconductor device.

[0105] In some embodiments, the semiconductor device may be a memory. Specifically, the semiconductor device may be a 3D memory, such as a 3D NAND memory.

[0106] In some implementations, the storage system may be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a Multimedia Card in the form of MMC, eMMC, RS-MMC, and Micro MMC, a Secure Digital Card in the form of SD, Mini SD, and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed ​​PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card, or a Memory Stick, etc.

[0107] Specifically, the aforementioned storage system can be used in terminal products such as computers, televisions, set-top boxes, and in-vehicle systems.

[0108] Accordingly, this disclosure also provides an electronic device, which includes the storage system provided in the above-mentioned embodiments of this disclosure. Specifically, the electronic device can be any device capable of storing data, such as a mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle device, wearable device, or power bank.

[0109] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0110] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0111] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: A first semiconductor structure, the first semiconductor structure including a core region; The core region includes a semiconductor layer, a stacked structure located on the semiconductor layer, and a memory channel structure and a virtual channel structure that penetrate the stacked structure and extend into the semiconductor layer; the core region includes an adjacent first region and a second region, the first region including the memory channel structure, and the second region including the virtual channel structure; The core region also includes an isolation structure located between the memory channel structure and the virtual channel structure, and extending through the semiconductor layer; The semiconductor device includes multiple memory surfaces, each memory surface including multiple memory blocks; the isolation structure is a ring structure, each isolation structure surrounding all memory channel structures of a memory surface.

2. The semiconductor device according to claim 1, characterized in that, The channel layer and the semiconductor layer in the virtual channel structure are electrically connected; the channel layer and the semiconductor layer at the end of the memory channel structure away from the stacked structure are electrically connected.

3. The semiconductor device according to claim 1, characterized in that, The isolation structure extends through the semiconductor layer of the first region, or the isolation structure extends through the semiconductor layer of the second region.

4. The semiconductor device according to claim 1, characterized in that, The core region also includes a source contact located in the first region and in contact with the side of the semiconductor layer away from the stacked structure; the isolation structure is located between the source contact and the virtual channel structure.

5. The semiconductor device according to claim 1, characterized in that, The virtual channel structure includes a first virtual channel structure and a second virtual channel structure; the second region includes a first sub-region and a second sub-region located on the side of the first sub-region closer to the first region, the first sub-region includes the first virtual channel structure, and the second sub-region includes the second virtual channel structure; the distribution density of the first virtual channel structure is less than the distribution density of the storage channel structure.

6. The semiconductor device according to claim 5, characterized in that, The isolation structure is located between the storage channel structure of the first region and the second virtual channel structure of the second sub-region.

7. The semiconductor device according to claim 5, characterized in that, The virtual channel structure further includes a third virtual channel structure; the second region further includes a third sub-region located on the side of the first sub-region away from the second sub-region, the third sub-region including the third virtual channel; the distribution density of the third virtual channel structure is less than the distribution density of the first virtual channel structure.

8. The semiconductor device according to any one of claims 1-7, characterized in that, It includes an isolation trench that extends through the semiconductor layer and an insulating material located within the isolation trench.

9. The semiconductor device according to any one of claims 1-7, characterized in that, The first semiconductor structure further includes a peripheral region; the peripheral region includes peripheral contacts that penetrate the semiconductor layer; the width of the isolation structure is smaller than the width of the peripheral contacts.

10. A method for fabricating a semiconductor device, characterized in that, The method includes: A first semiconductor structure is formed on a first substrate. The first semiconductor structure includes a core region. The core region includes a semiconductor layer, a stacked structure formed on the semiconductor layer, and a memory channel structure and a virtual channel structure extending through the stacked structure and into the semiconductor layer. The core region includes an adjacent first region and a second region, the first region including the memory channel structure, and the second region including the virtual channel structure. An isolation structure is formed between the memory channel structure and the virtual channel structure, extending through the semiconductor layer.

11. The method for fabricating a semiconductor device according to claim 10, characterized in that, The method further includes: A source contact is formed on the first region that contacts the side of the semiconductor layer away from the stacked structure and is located on the side of the isolation structure away from the virtual channel structure.

12. The method for fabricating a semiconductor device according to claim 10, characterized in that, The first semiconductor structure further includes a peripheral region; the isolation structure formed between the memory channel structure and the virtual channel structure, extending through the semiconductor layer, includes: A dielectric layer is formed on the side of the semiconductor layer away from the stacked structure; The dielectric layer and the semiconductor layer are etched using a first mask to form peripheral contact trenches in the peripheral region, while simultaneously forming isolation trenches between the memory channel structure and the virtual channel structure; the peripheral contact trenches and the isolation trenches penetrate the dielectric layer and the semiconductor layer; The peripheral contact groove and the isolation groove are filled to form the peripheral contact and the isolation structure, respectively.

13. The method for fabricating a semiconductor device according to claim 12, characterized in that, The step of etching the dielectric layer and the semiconductor layer through a first mask to form peripheral contact trenches in the peripheral region, while simultaneously forming isolation trenches between the memory channel structure and the virtual channel structure, includes: A patterned mask layer is formed on the dielectric layer by the first mask plate, the patterned mask layer having a first opening in the peripheral region and a second opening in the core region; the first opening and the second opening expose the dielectric layer; The dielectric layer and the semiconductor layer are etched using the patterned mask layer to simultaneously form peripheral contact trenches and isolation trenches that penetrate the dielectric layer and the semiconductor layer.

14. The method for fabricating a semiconductor device according to claim 10, characterized in that, The formation of the first semiconductor structure includes: A second semiconductor layer is formed on the first substrate, and the stacked structure, a memory channel structure, and a virtual channel structure are formed on the second semiconductor layer; a portion of the virtual channel structure extends into the second semiconductor layer, and a portion extends through the second semiconductor layer and into the first substrate; the memory channel structure extends into the second semiconductor layer. Remove the first substrate to expose the channel layer of the virtual channel structure extending into the first substrate; Remove the second semiconductor layer in the first region and the memory film surrounding the channel layer at the end of the memory channel structure to expose the channel layer of the memory channel structure; A first semiconductor layer is formed, which covers the channel layer at the end of the memory channel structure and the channel layer extending into the virtual channel structure of the first substrate; the first semiconductor layer and the second semiconductor layer in the second region constitute the semiconductor layer.

15. The method for fabricating a semiconductor device according to claim 14, characterized in that, The method of forming an isolation structure penetrating the semiconductor layer between the memory channel structure and the virtual channel structure includes: An isolation structure penetrating the first semiconductor layer is formed between the memory channel structure and the virtual channel structure; or... An isolation structure is formed between the memory channel structure and the virtual channel structure, extending through the first semiconductor layer and the second semiconductor layer.

16. A storage system, characterized in that, include: The semiconductor device as described in any one of claims 1-9; And a controller electrically connected to the semiconductor device.

17. An electronic device, characterized in that, include: The storage system of claim 16.

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