Semiconductor structure and method of manufacturing a semiconductor structure

Abstract

The present disclosure provides a semiconductor structure and a preparation method thereof. The semiconductor structure comprises: an active pillar, the active pillar is provided with an active region, the active pillar has opposite first and second ends, and the first and second ends are provided with source / drain electrodes of the active region; a capacitor, the capacitor is arranged on a side of the first end away from the second end, and the capacitor is electrically connected to the source / drain electrode on the first end; a bit line, the bit line is arranged on a side of the second end away from the first end, and the bit line is electrically connected to the source / drain electrode on the second end; and a logic circuit, the logic circuit is arranged on a side of the bit line away from the active pillar, and the logic circuit is electrically connected to the bit line. This structure can avoid the problem that the logic circuit and the active region are prepared on one substrate in the prior art, can increase the area available for preparing the active pillar in the semiconductor substrate, and thus improves the integration of the device.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the semiconductor structure. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used type of computer memory. It typically uses one transistor and one capacitor (1T1C) to represent one bit. In a typical DRAM structure, transistors, word lines, and bit lines are usually mounted on a substrate. In addition, logic circuitry needs to be placed on areas of the substrate other than where transistors are located. This significantly reduces the area on the substrate available for transistor fabrication, thus affecting the device's integration density. Summary of the Invention

[0003] Based on this, and in order to increase the area on the substrate available for manufacturing transistors and thereby improve the integration of the device, it is necessary to provide a semiconductor structure and its fabrication method.

[0004] According to some embodiments of this disclosure, a semiconductor structure is provided, comprising:

[0005] An active post is provided with an active region. The active post has a first end and a second end that are opposite each other. The first end and the second end are provided with the source / drain electrodes of the active region.

[0006] A capacitor is disposed on the side of the first end away from the second end, and the capacitor is electrically connected to the source / drain electrode located at the first end;

[0007] Bit lines, wherein the bit lines are disposed on the side of the second end away from the first end, and the bit lines are electrically connected to the source / drain located at the second end; and,

[0008] A logic circuit, wherein the logic circuit is disposed on the side of the bit line away from the active post.

[0009] In some embodiments of this disclosure, a second electrical contact layer is further included, which is disposed on the side of the second end of the active post away from the first end, and the second electrical contact layer is located between the active post and the bit line.

[0010] In some embodiments of this disclosure, a first electrical contact layer is further included, the first electrical contact layer being disposed on the side of the first end of the active post away from the second end, and the first electrical contact layer being located between the active post and the capacitor.

[0011] In some embodiments of this disclosure, the material of the first electrical contact layer comprises a conductive metal silicide.

[0012] In some embodiments of this disclosure, the material of the second electrical contact layer comprises a conductive metal silicide.

[0013] In some embodiments of this disclosure, the capacitor includes a lower electrode, a dielectric layer, and an upper electrode, the lower electrode being electrically connected to the source / drain electrode located at the first end, the dielectric layer covering the lower electrode, and the upper electrode covering the dielectric layer.

[0014] In some embodiments of this disclosure, there are multiple lower electrodes, with adjacent lower electrodes spaced apart, and the upper electrode also fills the space between adjacent lower electrodes.

[0015] In some embodiments of this disclosure, a support layer and a capacitor contact are further included. The capacitor contact is disposed in the support layer and located between the capacitor and the active post. The lower electrode is electrically connected to the active post through the capacitor contact.

[0016] In some embodiments of this disclosure, the capacitive contact includes a contact layer and a contact blocking layer, the contact blocking layer being disposed between the contact layer and the active post and between the contact layer and the support layer.

[0017] In some embodiments of this disclosure, the line connecting the first end and the second end of the active post is in a first direction, and there are a plurality of active posts arranged at intervals in a second direction intersecting the first direction, the bit line extending along the second direction.

[0018] In some embodiments of this disclosure, a plurality of active pillars are also arranged at intervals in a third direction that intersects the first direction and the second direction in pairs. The semiconductor structure also includes word lines disposed on the sidewalls of the active pillars and extending along the third direction.

[0019] In some embodiments of this disclosure, the word line includes a conductive layer and a gate dielectric layer, the conductive layer being disposed around the active pillar, and the gate dielectric layer being disposed between the conductive layer and the active layer.

[0020] In some embodiments of this disclosure, the logic circuit and the active pillar are respectively disposed on two substrates, and the bit line contacts the substrate on which the logic circuit is disposed and the substrate on which the active pillar is disposed.

[0021] This disclosure also provides a method for preparing the semiconductor structure in the above embodiments, which includes the following steps:

[0022] The capacitor and the bit line are respectively fabricated on opposite sides of the first substrate; and, between the steps of fabricating the capacitor and fabricating the bit line, the first substrate is etched to form the active pillar;

[0023] The logic circuit is disposed on the side of the bit line away from the active post.

[0024] In some embodiments of this disclosure, the step of etching the first substrate is performed after the capacitor is fabricated.

[0025] In some embodiments of this disclosure, prior to the step of fabricating the capacitor, the method further includes: fabricating a first electrical contact layer, a support layer, and capacitor contacts on the first substrate, wherein the capacitor contacts are formed between the support layers.

[0026] In some embodiments of this disclosure, the steps of fabricating a first electrical contact layer, a support layer, and a capacitor contact on the first substrate include:

[0027] A support layer is prepared on the first substrate;

[0028] The support layer is patterned to form contact vias that expose the first substrate.

[0029] The first electrical contact layer is prepared on the first substrate exposed by the contact through-hole;

[0030] The capacitor contacts are fabricated on the first electrical contact layer.

[0031] In some embodiments of this disclosure, the step of etching the first substrate includes: flipping the first substrate on which the capacitor is fabricated, using the side of the first substrate away from the capacitor as a processing surface, and etching the first substrate from the processing surface to form the active pillar.

[0032] In some embodiments of this disclosure, after forming the active post, a second electrical contact layer is further prepared on the end of the active post away from the capacitor.

[0033] In some embodiments of this disclosure, the step of setting the logic circuit includes: fabricating the logic circuit on a second substrate, wherein the second substrate on which the logic circuit is set is disposed on the side of the bit line away from the active pillar; or,

[0034] A second substrate is disposed on the side of the bit line away from the active pillar, and the logic circuit is then fabricated on the second substrate.

[0035] In conventional techniques, bit lines are typically embedded in a substrate with an active region, while logic circuits are placed in other areas of the substrate. In contrast to conventional techniques, the semiconductor structure fabrication method disclosed herein places the bit lines and capacitors on opposite sides of the active pillars, and places the logic circuits on the side of the bit lines furthest from the active pillars. This structure separates the logic circuits from the active region and relocates them to the side of the bit lines furthest from the active region, saving space on the substrate where the active pillars are located. This increases the area available for fabricating active pillars in the semiconductor substrate, thereby improving the device's integration density.

[0036] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, the preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0037] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of the semiconductor structure disclosed herein;

[0039] Figure 2 This is a schematic diagram illustrating the steps of the semiconductor structure fabrication method disclosed herein;

[0040] Figure 3 A schematic diagram of the structure of the first substrate with a support layer;

[0041] Figure 4 In order to be in Figure 3 Based on the structure shown, a schematic diagram of the structure after the support layer is patterned and the first electrical contact layer is formed;

[0042] Figure 5 In order to be in Figure 4 Based on the structure shown, a schematic diagram of the structure after the capacitor contacts are fabricated is presented.

[0043] Figure 6 In order to be in Figure 5 A schematic diagram of the structure after the sacrificial layer is formed based on the structure shown;

[0044] Figure 7 In order to be in Figure 6 Based on the structure shown, a schematic diagram of the structure after forming a capacitor hole in the sacrificial layer and forming a lower electrode in the capacitor hole is presented.

[0045] Figure 8 In order to be in Figure 7 A schematic diagram of the structure after removing the sacrificial layer, based on the structure shown.

[0046] Figure 9 In order to be in Figure 8 Based on the structure shown, a schematic diagram of the structure after the dielectric layer is fabricated is presented;

[0047] Figure 10 In order to be in Figure 9 Based on the structure shown, a schematic diagram of the structure after fabrication of the top electrode is presented;

[0048] Figure 11 In order to be in Figure 10 Based on the structure shown, a schematic diagram of the structure after the active column is formed;

[0049] Figure 12 In order to be in Figure 11 Based on the structure shown, a schematic diagram of the structure after fabricating the word lines and the second electrical contact layer is presented;

[0050] Figure 13 In order to be in Figure 12 Based on the structure shown, a schematic diagram of the structure after the bit lines are fabricated;

[0051] The reference numerals and their meanings in the attached figures are as follows:

[0052] 100, First substrate; 110, Active pillar; 120, First electrical contact layer; 130, Second electrical contact layer; 140, Word line; 211, Contact barrier layer; 212, Contact contact layer; 220, Support layer; 221, Sacrificial layer; 230, Capacitor via; 231, Lower electrode; 232, Dielectric layer; 233, Upper electrode; 300, Bit line; 400, Logic circuit. Detailed Implementation

[0053] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0055] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. The manner of electrical connection is used to indicate that current can be conducted between multiple electrically connected elements, specifically in the manner in which one element directly contacts another element, or one element is connected to another element through another conductive element. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer or part discussed below may be represented as the second element, component, region, layer or part.

[0056] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0057] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0058] One embodiment of this disclosure provides a semiconductor structure comprising:

[0059] An active column is provided with an active region. The active column has a first end and a second end, and the source / drain electrodes of the active region are provided in the first end and the second end.

[0060] A capacitor is disposed on the side of the first end away from the second end, and the capacitor is electrically connected to the source / drain of the first end.

[0061] Bit lines are located on the side of the second terminal away from the first terminal, and are electrically connected to the source / drain terminals located at the second terminal; and,

[0062] The logic circuit is located on the side of the bit line away from the active pillar.

[0063] In conventional techniques, bit lines are typically embedded in a substrate with an active region, while logic circuits are placed in other areas of the substrate. In contrast to conventional techniques, the semiconductor structure fabrication method disclosed herein places the bit lines and capacitors on opposite sides of the active pillars, and places the logic circuits on the side of the bit lines furthest from the active pillars. This structure separates the logic circuits from the active region and relocates them to the side of the bit lines furthest from the active region, saving space on the substrate where the active pillars are located. This increases the area available for fabricating active pillars in the semiconductor substrate, thereby improving the device's integration density.

[0064] To facilitate understanding of the semiconductor structure provided in this disclosure Figure 1 One embodiment of this semiconductor structure is shown.

[0065] Reference Figure 1As shown, the semiconductor structure includes an active pillar 110, a bit line 300, a logic circuit 400, and a capacitor. The active pillar 110 has an active region and two opposing ends. The active region contains source and drain electrodes, and the source and drain electrodes of the active region are located at the first and second ends of the active pillar 110. It can be understood that the "source / drain electrodes" can be either a source or a drain electrode, and their specific locations can be determined according to the actual functional requirements of the semiconductor structure. For example, a drain electrode may be located at the first end and a source electrode at the second end, or vice versa.

[0066] In this semiconductor structure, a capacitor is disposed on the side of the first terminal away from the second terminal, and the capacitor is electrically connected to the source / drain of the first terminal. A bit line 300 is disposed on the side of the second terminal away from the first terminal, and the bit line 300 is electrically connected to the source / drain of the second terminal. A logic circuit 400 is disposed on the side of the bit line 300 away from the active pillar 110. It can be understood that the logic circuit 400 is used to control the on / off state of the bit line 300. The active pillar 110 and the logic circuit 400 can be formed on different substrates to avoid the problem of fabricating the logic circuit 400 and the active region on the same substrate in conventional techniques.

[0067] In some examples of this embodiment, the active pillar 110 includes an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material may be selected from silicon or germanium, and the crystalline inorganic compound semiconductor material may be selected from silicon carbide, silicon germanide, gallium arsenide, or indium gallium phosphate. It is understood that the active region may be a specifically doped portion of the active pillar 110, or it may be located within the entire active pillar 110.

[0068] Reference Figure 1 As shown, in some examples of this embodiment, the extension direction of the active post 110 is a first direction, that is, the line connecting the first end and the second end of the active post 110 is in the first direction, and there are multiple active posts 110 arranged sequentially at intervals in a second direction intersecting the first direction, with the bit line 300 extending along the second direction. The first direction and the second direction may intersect at a certain angle. Optionally, the first direction and the second direction are perpendicular to each other. (Refer to...) Figure 1 As shown, for ease of description, the first direction is taken as the z-axis and the second direction as the y-axis. Multiple active columns 110 are arranged sequentially at intervals along the y-axis.

[0069] In some examples of this embodiment, a plurality of active pillars 110 are also arranged at intervals in a third direction that intersects the first and second directions in pairs. The semiconductor structure also includes word lines 140, which are disposed on the sidewalls of the active pillars 110 and extend along the third direction. Optionally, the third direction is perpendicular to the first direction, that is, the first direction is perpendicular to the plane defined by the second direction and the third direction.

[0070] In some examples of this embodiment, the word line 140 includes a conductive layer and a gate dielectric layer. The conductive layer surrounds the active pillar 110, and the gate dielectric layer is disposed between the conductive layer and the active layer. The conductive layer can serve as the gate of the corresponding active region, controlling the on / off state of charge carriers in the active region. Optionally, the material of the conductive layer can be a metal and / or a conductive metal compound. The metal can be selected from one or more of tungsten, aluminum, copper, silver, and gold. The conductive metal compound can be selected from one or more of titanium nitride and tantalum nitride.

[0071] Reference Figure 1 As shown, in some examples of this embodiment, the semiconductor structure further includes a second electrical contact layer 130, which is disposed on the side of the second end of the active pillar 110 away from the first end, and is located between the active pillar 110 and the bit line 300. The second electrical contact layer 130 is used to improve the conductivity between the bit line 300 and the active region of the active pillar 110. Since conventional semiconductor structures typically employ a buried bit line 300 design, this significantly increases the difficulty of additionally setting an electrical contact layer between the bit line 300 and the active region. The semiconductor structure of this embodiment, by placing the bit line 300 on the second end of the active pillar 110, avoids the buried bit line 300 design and facilitates the fabrication of the second electrical contact layer 130.

[0072] Optionally, the material of the second electrical contact layer 130 includes a conductive alloy formed with the material of the active pillar 110. For example, the material of the active pillar 110 includes silicon, and the material of the second electrical contact layer 130 may include a conductive metal silicide, such as cobalt silicide.

[0073] Reference Figure 1 As shown, in some examples of this embodiment, the semiconductor structure further includes a first electrical contact layer 120, which is disposed on the side of the first end of the active pillar 110 away from the second end, and is located between the capacitor and the active pillar 110. The first electrical contact layer 120 is used to improve the conductivity between the capacitor and the active region of the active pillar 110.

[0074] Optionally, the material of the first electrical contact layer 120 includes a conductive alloy formed with the material of the active pillar 110. For example, the material of the active pillar 110 includes silicon, and the material of the first electrical contact layer 120 may include a conductive metal silicide, such as cobalt silicide.

[0075] Reference Figure 1 As shown, bit line 300 is disposed on the side of the second electrical contact layer 130 away from the active pillar 110. In some examples of this embodiment, the material of bit line 300 includes a single metal, a conductive metal compound, or an alloy. The single metal can be selected from copper, aluminum, tungsten, gold, or silver. The conductive metal compound can be selected from tantalum nitride or titanium nitride. The alloy can be selected from an alloy material composed of at least two of copper, aluminum, tungsten, gold, and silver. By selecting a material with high conductivity to prepare bit line 300, it is beneficial to reduce the resistance of bit line 300, increase the transmission rate of electrical signals in bit line 300, reduce parasitic capacitance in bit line 300, and reduce power consumption and heat generation of bit line 300.

[0076] Reference Figure 1 As shown, the logic circuit 400 is disposed on the side of the bit line 300 away from the active pillar 110. In some examples of this embodiment, the logic circuit 400 and the active pillar 110 are disposed on two separate substrates, with the bit line 300 contacting both the substrate on which the logic circuit 400 is disposed and the substrate on which the active pillar 110 is disposed. The substrate may be a wafer containing semiconductor material.

[0077] Reference Figure 1 As shown, the capacitor includes a lower electrode 231, a dielectric layer 232, and an upper electrode 233. The lower electrode 231 is electrically connected to the source / drain electrode located at the first end. The dielectric layer 232 covers the lower electrode 231, and the upper electrode 233 covers the dielectric layer 232. Both the lower electrode 231 and the upper electrode 233 are made of conductive materials. Optionally, the lower electrode 231 and the upper electrode 233 each independently comprise a single metal, a conductive metal compound, or an alloy. The single metal can be selected from copper, aluminum, tungsten, gold, or silver. The conductive metal compound can be selected from tantalum nitride or titanium nitride. The alloy can be selected from an alloy material composed of at least two of copper, aluminum, tungsten, gold, and silver. The dielectric layer 232 is made of a high-k material, such as silicon dioxide, silicon nitride, or silicon oxynitride.

[0078] Reference Figure 1 As shown, there are multiple lower electrodes 231, with adjacent lower electrodes 231 spaced apart, and upper electrodes 233 filling the spaces between adjacent lower electrodes 231.

[0079] Reference Figure 1As shown, the semiconductor structure also includes a support layer 220 and capacitor contacts. The capacitor contacts are disposed in the support layer 220 and located between the capacitor and the active pillar 110. The lower electrode 231 is electrically connected to the active pillar 110 through the capacitor contacts. The capacitor contacts contact the lower electrode 231 of the capacitor for attachment of the lower electrode 231 and to improve the conductivity between the lower electrode 231 and the active pillar 110.

[0080] Optionally, the material of the support layer 220 is selected from insulating materials, such as one or both of silicon oxide and silicon nitride.

[0081] Reference Figure 1 As shown, in some examples of this embodiment, the capacitive contact includes a contact layer 212 and a contact blocking layer 211, with the contact blocking layer 211 disposed between the contact layer 212 and the active pillar 110, and between the contact layer 212 and the support layer 220. The contact blocking layer 211 is used to prevent atoms of the contact layer 212 from diffusing into the active pillar 110 or the support layer 220. Optionally, the contact blocking layer 211 is grooved, and the contact layer 212 is disposed within the groove of the contact blocking layer 211. Further, the upper surface of the contact layer 212 is flush with the upper surface of the contact blocking layer 211.

[0082] In some examples of this embodiment, the material of the contact layer 212 may be selected from one or more of metals and conductive metal silicides. The metal may be selected from one or more of tungsten, silver, copper, aluminum, titanium, and gold, and the conductive metal silicide may be selected from one or more of cobalt silicide, titanium silicide, and nickel silicide.

[0083] In some examples of this embodiment, the material of the contact blocking layer 211 may be selected from one or more conductive metal nitrides, such as titanium nitride and tantalum nitride.

[0084] An embodiment of this disclosure also provides a method for fabricating the semiconductor structure described in the above embodiments, which includes the following steps.

[0085] A capacitor and a bit line 300 are respectively fabricated on opposite sides of the first substrate 100; and, between the steps of fabricating the capacitor and fabricating the bit line 300, the first substrate 100 is etched to form an active pillar 110.

[0086] A logic circuit 400 is set on the side of bit line 300 away from the active post 110.

[0087] In the semiconductor structure fabrication method disclosed herein, the active pillar 110 serves as the main functional component of the transistor, and the active region is disposed within the active pillar 110. The source / drain of the active region is located at the first end and the second end of the active pillar 110. Alternatively, the drain may be located at the first end and the source at the second end, or the drain may be located at the second end and the source at the first end.

[0088] In traditional technologies, for transistors with a vertical gate ring structure, it is usually necessary to fabricate buried bit lines 300, which requires a complex fabrication process and is quite difficult to fabricate. In the fabrication method of this semiconductor structure, the bit lines 300 and capacitors are fabricated directly on opposite sides of the first substrate 100, avoiding the fabrication of buried bit lines 300. Therefore, the fabrication process of bit lines 300 can be effectively simplified and the fabrication difficulty is also reduced.

[0089] In the method for fabricating the semiconductor structure provided in this disclosure, the order of the steps is not particularly limited. The fabrication order can be changed based on the common understanding of those skilled in the art, as long as the fabrication process can be realized and the desired structure can be obtained. For example, the capacitor can be fabricated before or after the bit line 300.

[0090] In some embodiments of this disclosure, in order to facilitate the fabrication of other components such as the support layer 220, the capacitor can be fabricated first, and then the bit line 300 can be fabricated.

[0091] To facilitate understanding of the implementation process of the above semiconductor structure fabrication method, refer to... Figure 2 As shown, this disclosure also provides an embodiment of a method for fabricating the semiconductor structure, which includes steps S1 to S5.

[0092] Step S1: Provide a first substrate.

[0093] The first substrate 100 is used to fabricate the active pillar 110 in subsequent fabrication processes. (Refer to...) Figure 3 As shown, the first substrate 100 has opposing top and bottom surfaces. The top and bottom surfaces are used to distinguish two opposing sides on the semiconductor first substrate 100, but do not mean that the top surface is necessarily above the bottom surface during the fabrication process. Furthermore, the fabrication method involves flipping the first substrate 100, so in some subsequent fabrication steps, the top surface is below the bottom surface.

[0094] In some examples of this embodiment, the material of the first substrate 100 includes a semiconductor material, which may optionally be silicon, germanium, or a silicon-germanium alloy.

[0095] Figure 3 , Figure 4 and Figure 5This illustrates one method of forming a first electrical contact layer 120 on a first substrate 100, and forming a support layer 220 and capacitor contacts on the first substrate 100. (Refer to...) Figure 3 As shown, a support layer 220 covering the first substrate 100 is formed on the first end of the first substrate 100. Referring again... Figure 4 As shown, the support layer 220 is patterned to form contact vias that expose a portion of the first substrate 100 in the support layer 220, and then a first electrical contact layer 120 is fabricated on the portion of the first substrate 100 exposed by the vias. Referring again... Figure 5 As shown, a capacitor contact is fabricated on the first electrical contact layer 120.

[0096] In some examples of this embodiment, the material of the support layer 220 is selected from insulating materials, such as one or both of silicon oxide and silicon nitride.

[0097] In some examples of this embodiment, the first substrate 100 contains silicon, and the step of forming the first electrical contact layer 120 includes: forming a metal material on the region of the first substrate 100 for forming the first electrical contact layer 120, and performing heat treatment to alloy the metal material with the silicon in the first substrate 100 to form a conductive metal silicide on the first substrate 100.

[0098] In some examples of this embodiment, there are multiple first electrical contact layers 120, which are spaced apart along the second direction. It can be understood that the multiple first electrical contact layers 120 are respectively disposed on the first ends of the multiple active pillars 110 to be fabricated.

[0099] In some examples of this embodiment, the capacitor contact includes a contact layer 212 and a contact barrier layer 211, with the contact barrier layer 211 disposed between the contact layer 212 and the first substrate 100, and between the contact layer 212 and the support layer 220. The contact barrier layer 211 is used to prevent atoms from the contact layer 212 from diffusing into the support layer 220 or the first substrate 100. It is understood that the support layer 220 is used to support the subsequently fabricated capacitor.

[0100] In some examples of this embodiment, the steps of preparing the capacitor contact include: forming a contact blocking layer 211 with grooves in the through hole of the support layer 220, and then forming a contact contact layer 212 in the groove of the contact blocking layer 211.

[0101] In some examples of this embodiment, there are multiple capacitive contacts, each corresponding to a multiple first electrical contact layer 120.

[0102] Step S2: Fabricate a capacitor on the top surface of the first substrate.

[0103] The capacitor includes an upper electrode 233, a lower electrode 231, and a dielectric layer 232. The lower electrode 231 is electrically connected to the source / drain at the first end, the dielectric layer 232 covers the lower electrode 231, and the upper electrode 233 covers the dielectric layer 232.

[0104] In some examples of this embodiment, there are multiple lower electrodes 231, with adjacent lower electrodes 231 spaced apart, and upper electrodes 233 filling the space between adjacent lower electrodes 231. By placing the upper electrode 233 between adjacent lower electrodes 231, the capacitance of the capacitor can be increased.

[0105] Figures 6-9 This illustrates a method for manufacturing a capacitor. (Refer to...) Figure 6 As shown, in some examples of this embodiment, a sacrificial layer 221 is first formed on the support layer 220 and the capacitor contacts. Optionally, the material of the sacrificial layer 221 can be a different material from the material of the subsequently fabricated lower electrode 231. For example, the material of the sacrificial layer 221 can be one or both of silicon oxide and silicon nitride.

[0106] Reference Figure 7 As shown, a capacitor hole 230 exposing the contact connection portion is formed in the sacrificial layer 221, and a lower electrode 231 of the capacitor is formed in the capacitor hole 230. The lower electrode 231 covers the hole wall of the capacitor hole 230 and contacts the contact connection portion. Optionally, the material of the lower electrode 231 includes a single metal, a conductive metal compound, or an alloy. The single metal can be selected from copper, aluminum, tungsten, gold, or silver. The conductive metal compound can be selected from tantalum nitride or titanium nitride. The alloy can be selected from an alloy material composed of at least two of copper, aluminum, tungsten, gold, and silver.

[0107] Reference Figure 8 As shown, after the lower electrode 231 is formed, the sacrificial layer 221 is removed. This results in a gap between adjacent lower electrodes 231.

[0108] Reference Figure 9 As shown, a dielectric layer 232 is formed on the lower electrode 231, covering the lower electrode 231. The dielectric layer 232 covers the groove walls and the top of the groove formed by the lower electrode 231. Optionally, the dielectric layer 232 also covers the capacitor contacts and support layer 220 exposed between adjacent lower electrodes 231. The material of the dielectric layer 232 may include a high-k material, such as silicon dioxide, silicon nitride, or silicon oxynitride.

[0109] Reference Figure 10As shown, an upper electrode 233 is formed on the dielectric layer 232, covering the dielectric layer 232. The upper electrode 233 fills a groove formed in the dielectric layer 232. Optionally, the upper electrode 233 also covers the dielectric layer 232 located between adjacent lower electrodes 231 to increase the relative area between the upper electrode 233 and the lower electrode 231, thereby increasing the capacitance of the capacitor.

[0110] Step S3: Etch the first substrate to form an active pillar.

[0111] Reference Figure 11 As shown, when etching the first substrate 100, the first substrate 100 on which the capacitor is fabricated is first flipped upside down, so that the top surface of the first substrate 100 is facing downwards and the bottom surface of the first substrate 100 is facing upwards, using the bottom surface of the first substrate 100 as the processing surface. Etching of the first substrate 100 begins from the bottom surface of the first substrate 100. It can be understood that during the etching of the first substrate 100, annular vias extending from the bottom surface to the top surface of the first substrate 100 can be etched on the first substrate 100. The portion of the first substrate 100 located between the annular vias can be further fabricated to form an active pillar 110. The active pillar 110 has a first end and a second end in a first direction, wherein the first end is closer to the top surface of the first substrate 100, and the second end is closer to the bottom surface of the first substrate 100. The capacitor is disposed on the side of the active pillar 110 away from the second end, and the capacitor is electrically connected to the source / drain electrode located at the first end.

[0112] In some examples of this embodiment, the active pillar 110 may be doped to form an active region within the active pillar 110. In other examples, the provided first substrate 100 has already been doped in the corresponding region, and the active pillar 110 with the active region can be directly obtained by etching. It is understood that the active region has source / drain electrodes, which are disposed at the first and second ends of the active pillar 110.

[0113] In some examples of this embodiment, there are multiple active posts 110, which are arranged at intervals along the second direction. It can be understood that the multiple active posts 110 correspond to multiple capacitor contacts.

[0114] In some examples of this embodiment, when etching the first substrate 100, the etching is stopped when the support layer 220 and the capacitor contacts are reached, so as to avoid damaging the capacitors that have been fabricated on the top surface of the first substrate 100.

[0115] Reference Figure 12As shown, after etching the active pillars 110, the method further includes the step of fabricating word lines 140 on the sidewalls of the active pillars 110. Multiple active pillars 110 (not shown in the figure) can also be arranged at intervals in the third direction, with the word lines 140 extending along the third direction.

[0116] In some examples of this embodiment, word line 140 includes a conductive layer and a gate dielectric layer, the conductive layer surrounding the active pillar 110, and the gate dielectric layer disposed between the conductive layer and the active pillar 110. It can be understood that the active region in the active pillar 110 can be distributed in the region of the active pillar 110 near the sidewall surface to facilitate gate control of its on or off.

[0117] Optionally, the conductive layer can be made of a metal and / or a conductive metal compound. The metal can be selected from one or more of tungsten, aluminum, copper, silver, and gold. The conductive metal compound can be selected from one or more of titanium nitride and tantalum nitride.

[0118] Reference Figure 12 As shown, the method further includes the step of forming a second electrical contact layer 130 on the second end of the active pillar 110. Optionally, the material of the second electrical contact layer 130 includes a conductive alloy formed with the material of the active pillar 110. For example, the material of the active pillar 110 includes silicon, and the material of the second electrical contact layer 130 may include a conductive metal silicide, such as cobalt silicide. The step of forming the second electrical contact layer 130 includes: forming a metal material on the second end of the active pillar 110, and performing a heat treatment to alloy the metal material with the semiconductor material in the active pillar 110 to form the second electrical contact layer 130 on the second end of the active pillar 110.

[0119] Step S4: Prepare a bit line on the second end of the active pillar.

[0120] Reference Figure 13 As shown, bit line 300 is disposed on the side of the second electrical contact layer 130 away from the active post 110. Bit line 300 extends along the second direction and is electrically connected to a plurality of active posts 110 arranged along the second direction.

[0121] In some examples of this embodiment, the material of the bit line 300 includes a single metal, a conductive metal compound, or an alloy. The single metal may be selected from copper, aluminum, tungsten, gold, or silver. The conductive metal compound may be selected from tantalum nitride or titanium nitride. The alloy may be selected from an alloy material composed of at least two of copper, aluminum, tungsten, gold, and silver. The bit line 300 may be prepared by deposition, such as physical vapor deposition or chemical vapor deposition.

[0122] Step S5: Set up the logic circuit on the side of the bit line away from the active pillar.

[0123] It is understandable that logic circuit 400 is used to read and write capacitors via bit line 300 and active post 110.

[0124] In some examples of this embodiment, the logic circuit 400 and the active pillar 110 are fabricated on different substrates. The logic circuit 400 may be pre-fabricated on a second substrate, and then in this step, the second substrate is positioned on the side of the bit line 300 away from the active pillar 110. Alternatively, the second substrate for fabricating the logic circuit 400 may first be positioned on the side of the bit line 300 away from the active pillar 110, and then the logic circuit 400 is fabricated on this second substrate. In conventional techniques, the logic circuit 400 and the active layer are typically fabricated on the same substrate. In this embodiment, the logic circuit 400 and the active pillar 110 are located on two separate substrates, and the logic circuit 400 and the active pillar 110 are stacked, so that the substrate for fabricating the active pillar 110 does not need to reserve additional area for fabricating the logic circuit 400, thus increasing the density of the active pillar 110 and consequently increasing the integration density.

[0125] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0126] It should be understood that, unless otherwise expressly stated herein, there is no strict order in which the steps are executed, and these steps may be executed in other orders. Moreover, at least some of the steps may include multiple sub-steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0127] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0128] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide a first substrate; A capacitor is fabricated on the top surface of the first substrate; The first substrate on which the capacitor is fabricated is etched to form an active pillar, the active pillar having a first end and a second end opposite to each other, the first end being close to the capacitor and the second end being away from the capacitor; Word lines are fabricated on the sidewall of the active column; A bit line is fabricated on the second end of the active pillar; A logic circuit is disposed on the side of the bit line away from the active post.

2. The preparation method according to claim 1, characterized in that, Before manufacturing the capacitor, the following steps are also included: A support layer is prepared on the top surface of the first substrate; The support layer is patterned to form contact vias that expose the first substrate. A first electrical contact layer is prepared on the first substrate exposed by the contact via; A capacitor contact is prepared on the first electrical contact layer, and the capacitor contact fills the contact through-hole; The first electrical contact layer and the capacitor contact are disposed on the side of the first end of the active post away from the second end, and the first electrical contact layer and the capacitor contact are located between the active post and the capacitor.

3. The preparation method according to claim 2, characterized in that, The capacitor contact includes a contact layer and a contact blocking layer, wherein the contact blocking layer is disposed between the contact layer and the active post and between the contact layer and the support layer.

4. The preparation method according to claim 2, characterized in that, The material of the first electrical contact layer includes a conductive metal silicide.

5. The preparation method according to any one of claims 1 to 4, characterized in that, The capacitor includes a lower electrode, a dielectric layer, and an upper electrode. The lower electrode is electrically connected to the source / drain electrode located at the first end. The dielectric layer covers the lower electrode, and the upper electrode covers the dielectric layer.

6. The preparation method according to claim 5, characterized in that, There are multiple lower electrodes, with adjacent lower electrodes spaced apart, and the upper electrode also fills the space between adjacent lower electrodes.

7. The preparation method according to any one of claims 1 to 4, characterized in that, Etching the first substrate includes: flipping the first substrate on which the capacitor is fabricated, using the bottom surface of the first substrate as the processing surface, and etching the first substrate from the processing surface to form the active pillar.

8. The preparation method according to any one of claims 1 to 4, characterized in that, The line connecting the first end and the second end of the active column is in a first direction, and there are multiple active columns arranged at intervals in a second direction that intersects the first direction, and the bit line extends along the second direction.

9. The preparation method according to claim 8, characterized in that, The active columns are also arranged at intervals in a third direction that intersects the first direction and the second direction in pairs, and the word lines extend along the third direction.

10. The preparation method according to claim 9, characterized in that, The word line includes a conductive layer and a gate dielectric layer. The conductive layer is disposed around the active post, and the gate dielectric layer is disposed between the conductive layer and the active post.

11. The preparation method according to any one of claims 1 to 4, characterized in that, After forming the active pillar, the method further includes: preparing a second electrical contact layer on the second end of the active pillar; The second electrical contact layer is located between the active post and the bit line.

12. The preparation method according to claim 11, characterized in that, The material of the second electrical contact layer includes a conductive metal silicide.

13. The preparation method according to any one of claims 1 to 4, characterized in that, The configuration of the logic circuit includes: fabricating the logic circuit on a second substrate, and positioning the second substrate on which the logic circuit is disposed on the side of the bit line away from the active pillar; or, A second substrate is disposed on the side of the bit line away from the active pillar, and the logic circuit is then fabricated on the second substrate.

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