Graphical processor device management method, system, computer device and medium

Abstract

The application discloses a kind of graphic processor equipment management method, system, computer equipment and medium, graphic manager equipment at least includes graphic processor chip and remote management chip, graphic processor chip is also connected with PCIe;Method includes: based on PCIe obtains the firmware information of graphic processor chip;Based on remote management chip obtains the state information of graphic processor chip;Based on the firmware information of graphic processor chip and the state information of graphic processor chip and preset management rule match target management strategy and execute;Through increasing remote management chip in graphic manager equipment, the management instruction operation of graphic manager equipment is realized;Through remote management chip scheme processing, the convenient out-of-band management to graphic processor is realized.

Description

Technical Field

[0001] This invention relates to the field of graphics processors, and more specifically to a graphics processor device management method, system, computer device, and medium. Background Technology

[0002] With the development of big data and artificial intelligence, data services are constantly expanding, and the performance requirements for servers are also increasing. As a result, various heterogeneous acceleration technologies and PCIe interfaces with graphics rendering, model inference, and model training functions have been developed. GPU cards, inserted into the server's PCIe slot via the PCIe bus interface, have become the mainstream way for server manufacturers to enhance server performance.

[0003] As AI servers increasingly utilize GPUs, higher demands are being placed on the out-of-band management of these GPUs. While existing GPUs on the market offer some out-of-band management, the increasing power consumption and complexity of power supply design, coupled with the deeper application of AI servers, necessitate greater management requirements for GPU usage. Summary of the Invention

[0004] The purpose of this invention is to provide a method, system, computer device, and medium for managing graphics processor devices.

[0005] The technical solution of the present invention is as follows: Firstly, the present invention provides a method for managing a graphics processing unit (GPU) device, wherein the GPU device includes at least a GPU chip and a remote management chip, and the GPU chip is further connected to a PCIe network; the method includes:

[0006] Firmware information of the graphics processor chip is obtained based on the PCIe;

[0007] The status information of the graphics processor chip is obtained based on the remote management chip;

[0008] The target management strategy is matched and executed based on the firmware information of the graphics processor chip, the status information of the graphics processor chip, and preset management rules.

[0009] In a preferred embodiment, the PCIe establishes a connection with the main server via a gold finger, the gold finger being equipped with a system management bus;

[0010] The graphics processing chip includes at least a field-replaceable unit, an electrically erasable programmable read-only memory, and a temperature chip.

[0011] The process of obtaining the firmware information of the graphics processor chip based on the PCIe includes:

[0012] The information of the field replaceable unit, the information of the electrically erasable programmable read-only memory, and the information of the temperature chip are read based on the PCIe and the system management bus.

[0013] In a preferred embodiment, the method further includes:

[0014] Based on the PCIe, the PCIe x16 signal sent by the main server is transmitted to the graphics processor chip via the gold fingers;

[0015] The data calculated by the graphics processor chip based on the PCIe x16 signal is obtained and transmitted to the main server.

[0016] In a preferred embodiment, the graphics processor chip is connected to a power connector via the gold fingers for power supply; the method further includes:

[0017] The remote management chip status information and the graphics processor chip voltage status information are read based on the PCIe and the system management bus.

[0018] In a preferred embodiment, obtaining the status information of the graphics processor chip based on the remote management chip includes:

[0019] The power information and out-of-band information of the graphics processor chip are obtained based on the remote management chip.

[0020] In a preferred embodiment, the remote management chip includes a microcontroller unit; the acquisition of power information and out-of-band information of the graphics processor chip based on the remote management chip includes:

[0021] Based on the remote management chip, power data and power status signal data are monitored and obtained. The power data includes at least peak power data and power data of each component in the graphics processor device.

[0022] Based on the microcontroller unit and the bidirectional two-wire synchronous serial bus, the following data are acquired: internal temperature data of the graphics processor chip, total card power data, memory temperature data, clock frequency, memory error check and correction data, power supply data, power status signals, graphics processor status signals, and firmware version number of the remote management chip.

[0023] In a preferred embodiment, the step of obtaining the power information and out-of-band information of the graphics processor chip based on the remote management chip further includes:

[0024] The fault information and PCIe interface information of the graphics processor chip are obtained based on the GPIO resource detection of the remote management chip.

[0025] In a second aspect, the present invention also provides a graphics processor device management system, wherein the graphics manager device includes at least a graphics processor chip and a remote management chip, and the graphics processor chip is further connected to a PCIe; the system includes:

[0026] The first acquisition module is used to acquire the firmware information of the graphics processor chip based on the PCIe;

[0027] The second acquisition module is used to acquire the status information of the graphics processor chip based on the remote management chip;

[0028] The matching execution module is used to match the target management strategy with the firmware information of the graphics processor chip and the status information and preset management rules of the graphics processor chip, and then execute it.

[0029] Thirdly, the present invention also provides a computer device, the device comprising:

[0030] One or more processors; and

[0031] A memory associated with the one or more processors, the memory being used to store program instructions that, when read and executed by the one or more processors, perform the graphics processor device management method as described in any one of the first aspects.

[0032] Fourthly, the present invention also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of any of the methods described in the first aspect.

[0033] The advantages of this invention are: it provides a graphics processor device management method, system, computer device, and medium, wherein the graphics manager device includes at least a graphics processor chip and a remote management chip, and the graphics processor chip is also connected to a PCIe; the method includes: obtaining firmware information of the graphics processor chip based on the PCIe; obtaining status information of the graphics processor chip based on the remote management chip; matching the firmware information of the graphics processor chip with the status information of the graphics processor chip and preset management rules to a target management strategy and executing it; realizing command-based operation for managing the graphics manager device by adding a remote management chip to the graphics manager device; and realizing convenient out-of-band management of the graphics processor through the remote management chip solution. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of the architecture for managing graphics processor devices provided in this application;

[0036] Figure 2 A schematic diagram of the I2C topology for the architecture used in the application to manage graphics processor devices;

[0037] Figure 3 The flowchart of the graphics processor device management method provided in this application;

[0038] Figure 4 The diagram of the graphics processor device management system provided in this application;

[0039] Figure 5 The computer device architecture diagram provided for this application. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0041] As described in the background section, with the increasing use of GPU cards in AI servers, higher requirements are being placed on the out-of-band management of the GPU cards themselves. Existing GPU cards on the market have achieved some out-of-band management, but with the deepening application of AI servers, power consumption is increasing and power supply design complexity is rising. Consequently, servers are placing more management demands on the use of GPU cards, and existing out-of-band management methods are gradually failing to meet the GPU management requirements.

[0042] To address the aforementioned issues, this application creatively proposes a graphics processor device management method, system, computer device, and computer-readable storage medium. By adding a remote management chip to the graphics manager device, instruction-based operation is achieved for managing the graphics manager device. The remote management chip solution enables convenient out-of-band management of the graphics processor, meeting the out-of-band management requirements of existing GPUs.

[0043] The solution of this application will now be described in detail with reference to the accompanying drawings and various embodiments.

[0044] Example 1: This example describes the architecture for managing graphics processor devices in this application.

[0045] Reference Figure 1 As shown, the architecture includes: a main control chip, which in one example is an AMD GPU main control chip;

[0046] In one example, the video memory uses 16 x 16Gb GDDR (Graphics Double Data Rate) chips, for a total of 32GB of video memory.

[0047] In one example, two PCIe 8-pin power connectors are used for power supply, and the maximum power consumption of the overall graphics processor device is 300W.

[0048] In one example, the GPU PCIe interface is PCIe X16 GEN4.

[0049] The remote management chip, specifically the RM (Remote Management) chip, mainly functions to aggregate a large number of I2C and sideband signals and communicate with the motherboard BMC (Baseboard Management Controller) via the gold finger I2C, thereby improving the manageability of the GPU.

[0050] Power management chips, in one example, include the IR35217M / INA3221 / XDPE132G5D power management chip;

[0051] The power management chip connects to the PCA9555 I2C and Sideband I / O expansion, and the Temperature Sensor.

[0052] The main control chip connects to the main server via a gold finger;

[0053] The PCIe signal receives the PCIe x16 signal from the host server, connects to the GPU card via the gold fingers, and then sends the data back to the host server after the chip's calculations. The graphics processing unit is powered through the gold fingers and two +12V power connectors, and a remote management chip controls the activation of each power conversion chip and receives the status of each power conversion chip after power conversion. The chips communicate with each other via I2C for easy firmware updates. The host server can read information from the FRU (Field Replaceable Unit), EEPROM (Electrically Erasable Programmable Read-Only Memory), and temperature chip on the board through the SMBus (System Management Bus) on the gold fingers. It can also read the status of the remote management chip through this SMBus, thus knowing the current voltage status on the board and the status of the GPU card.

[0054] The remote management chip collects GPU and memory-related information via the SMBUS bus, and the BMC accesses the remote management chip via SMBUS to manage the GPU card. The GPU card adds an EMC1413 to monitor inlet and outlet temperatures; adds a PCA9555 (I / O extension) to obtain Board ID, PCB Revision ID, and BOM ID; and adds FRU storage information for the FRU card.

[0055] Figure 2 This diagram illustrates the I2C topology of the architecture for managing this graphics processor device.

[0056] Example 2: Based on the architecture for managing graphics processor devices described in Example 1 above, this example combines... Figure 3 This application describes the process of managing graphics processor devices.

[0057] Specifically, this embodiment provides a graphics processor device management method, wherein the graphics manager device includes at least a graphics processor chip and a remote management chip, and the graphics processor chip is further connected to a PCIe; the method includes:

[0058] S310: Obtain firmware information of graphics processor chip based on PCIe.

[0059] In one embodiment, the PCIe establishes a connection with the main server via a gold finger, and the gold finger is provided with a system management bus; the graphics processing chip is provided with at least a field-replaceable unit, a electrically erasable programmable read-only memory and a temperature chip.

[0060] This step includes:

[0061] S311. Read the field replaceable unit information, the electrically erasable programmable read-only memory information, and the temperature chip information based on the PCIe and the system management bus.

[0062] Specifically, the main server reads information from the field-replaceable unit, electrically erasable programmable read-only memory, and temperature chip on the graphics processing chip via the system management bus on the gold finger.

[0063] Preferably, the method further includes:

[0064] S312. Based on the PCIe, transmit the PCIe x16 signal sent by the main server to the graphics processor chip via the gold finger.

[0065] S313. Obtain the data calculated by the graphics processor chip based on the PCIe x16 signal and transmit the data to the main server.

[0066] Specifically, the PCIe signal receives the PCIe x16 signal from the main server, connects to the graphics processor chip via the gold fingers, and then transmits the calculated data back to the main server via the gold fingers after the graphics processor chip has processed the data.

[0067] Preferably, the graphics processor chip is connected to a power connector via the gold fingers for power supply; the method further includes:

[0068] S314. Read the status information of the remote management chip and the voltage status information of the graphics processor chip based on the PCIe and the system management bus.

[0069] Specifically, the graphics processing unit (GPU) chip is powered via a gold finger and two +12V power connectors. A remote management chip controls the activation of each power conversion chip and receives the status of each chip after power conversion. The chips communicate with each other via I2C for easy firmware updates. The main server reads the status of the remote management chip through the system management bus on the gold finger, thus obtaining information about the current voltage status of the GPU device and the status of the GPU chip.

[0070] S320: Obtains status information of graphics processor chip based on remote management chip.

[0071] Specifically, the power information and out-of-band information of the graphics processor chip are obtained based on the remote management chip.

[0072] Specifically, the analog-to-digital converter and GPIO (General-purpose input / output) based on the remote management chip monitor power information, and the MCU (Microcontroller Unit) based on the remote management chip obtains out-of-band information of the graphics processor chip.

[0073] In one embodiment, the remote management chip includes a microcontroller unit; the acquisition of power information and out-of-band information of the graphics processor chip based on the remote management chip includes:

[0074] S321. Based on the monitoring of the remote management chip, power data and power status signal data are obtained, wherein the power data includes at least peak power data and power data of each component in the graphics processor device.

[0075] Specifically, the ADC (Analog-to-Digital Converter) of the remote management chip is used to monitor the following 7 power supplies to obtain power data: P0V75, VDDCR_GFX, VPP, VDDCR_SOC, VDD_MEM, VDDCI_MEM, and P1V8.

[0076] Use the GPIO of the remote management chip to monitor the power status signal and acquire power status signal data by monitoring the following 5 power status signals: +0.75V_PWRGD, VPP_PWRGD, +1.8V_PWRGD, GFX_SOC_PWRGD, and MVDD_VDDCI_PWRGD.

[0077] S322. Based on the microcontroller unit and the bidirectional two-wire synchronous serial bus, acquire the graphics processor chip's internal temperature data, total card power data, video memory temperature data, clock frequency, memory error check and correction data, power supply data, power status signal, graphics processor status signal, and remote management chip firmware version number.

[0078] Specifically, (1) the master server BMC and the microcontroller unit of the remote management chip obtain the internal temperature data of the graphics processor chip through I2C (Inter-Integrated Circuit bidirectional two-wire synchronous serial bus) communication. The graphics processor chip has an internal temperature sensor, and the graphics processor chip has completed writing the temperature value of the temperature sensor into the corresponding register. The microcontroller unit acts as an I2C slave device, and the master server BMC acts as an I2C master device. The microcontroller unit will provide an out-of-band I2C call interface to the master server BMC, and the master server BMC completes the acquisition of the internal temperature data of the graphics processor chip by calling this interface. The internal temperature of the graphics processor chip can be read normally before and after the graphics processor device driver is loaded. The only difference is that before the driver is loaded, the temperature is read from an external sensor, and after the driver is loaded, it is read from the graphics processor chip. There is no difference for the remote management chip, as it reads the same register.

[0079] (2) The main server BMC and the microcontroller unit of the remote management chip obtain the total power data of the graphics processor chip through I2C communication:

[0080] The graphics processing unit (GPU) chip writes the GPU power data to the corresponding registers. The microcontroller unit (MCU) acts as an I2C slave, and the master server block designator (BMC) acts as an I2C master. The MCU provides an out-of-band I2C interface to the BMC, which then uses this interface to acquire the GPU power data. Reading the GPU power data depends on the GPU driver. Before the driver is loaded, reading the data will return a fixed register value, indicating that the data is known to be unreadable. After the driver is loaded, the actual power can be read normally.

[0081] (3) The main server BMC and the microcontroller unit obtain memory temperature data through I2C communication:

[0082] The graphics processing unit (GPU) chip provides registers corresponding to the GDDR (Graphics Double Data Rate) temperature value. The microcontroller unit (MCU) acts as an I2C slave device, and the master server BMC acts as an I2C master device. The MCU provides an out-of-band I2C call interface to the master server BMC, which then uses this interface to obtain the GDDR temperature. The actual GDDR temperature value can only be read after the GPU driver is loaded. Before the GPU driver is loaded, the value cannot be read. At this time, when the BMC reads the GDDR temperature, the MCU will return a fixed value (known to be unreadable).

[0083] (4) The main server BMC and the microcontroller unit obtain the graphics processor clock frequency through I2C communication:

[0084] The graphics processor (GPU) provides a register corresponding to the GPU clock frequency. The microcontroller unit (MCU) acts as an I2C slave device, and the master server (BMC) acts as an I2C master device. The MCU provides an out-of-band I2C call interface to the master server (BMC), and the master server (BMC) obtains the GPU clock frequency by calling this interface.

[0085] (5) The master server BMC obtains memory error checking and correction data via out-of-band I2C: The master server BMC obtains the total number of memory ECC (Error Checking and Correcting) records and the channels where ECC occurred via out-of-band I2C. The specific number of ECC records for each memory chip is not required by the out-of-band read function. The graphics processor provides the total number of memory ECC records and the registers corresponding to the channels where ECC occurred. The microcontroller unit acts as the I2C slave device, and the master server BMC acts as the I2C master device. The microcontroller unit provides an out-of-band I2C call interface to the master server BMC, and the master server BMC obtains the total number of memory ECC records and the channels where ECC occurred by calling this interface.

[0086] (6) Remote management chip compatible with monitoring and acquisition of power data:

[0087] The control unit monitors the power supply signal through the internal ADC, including P0V75, VDDCR_GFX, VPP, VDDCR_SOC, VDD_MEM, VDDCI_MEM, and P1V8.

[0088] The microcontroller unit has a built-in 12-bit ADC. The data collected by the ADC is converted to obtain the power data. The main server BMC communicates with the microcontroller unit through I2C to obtain the power data.

[0089] The default voltage value for each channel is set to 0xffff. If the ADC fails to acquire data for a certain channel, the microcontroller unit will return 0xFE (data acquired but not acquired) when the BMC acquires data for that channel.

[0090] By configuring the ADC component in the integrated development environment, the microcontroller unit can automatically generate ADC-related application programming interfaces (APIs) and call different APIs to meet power monitoring requirements.

[0091] (7) The microcontroller monitors the power status signals via GPIO: +0.75V_PWRGD, VPP_PWRGD, +1.8V_PWRGD, GFX_SOC_PWRGD, VDD_VDDCI_PWRGD.

[0092] During the operation of the graphics processing unit (GPU), the power status signal is monitored by detecting the GPIO level of the microcontroller unit (MCU). A high GPIO level indicates a normal power status signal, while a low GPIO level indicates an abnormal power status signal. The main server (BMC) communicates with the MCU via SMBUS to obtain the power status signal.

[0093] (8) The remote management chip is compatible with monitoring graphics processor status signals:

[0094] The microcontroller unit monitors the graphics processor status signals via GPIO, including four signals: GPU Fault, PCIe GEN4, SENSE_P12V_CONN_1, and SENSE_P12V_CONN_2.

[0095] The status signals of the graphics processing unit (GPU) are monitored by detecting the GPIO levels of the microcontroller unit. The main server (BMC) obtains the GPU status signals from the microcontroller unit via I2C.

[0096] (9) The master server BMC obtains the firmware version number of the remote management chip:

[0097] The main server BMC and the microcontroller unit obtain the firmware version number of the remote management chip through I2C communication.

[0098] A register corresponding to the firmware version number of the remote management chip is added to the graphics processor chip area mapped by the register. The microcontroller unit acts as an I2C slave device, and the master server BMC acts as an I2C master device. The microcontroller unit will provide an out-of-band I2C call interface to the master server BMC, and the master server BMC will obtain the firmware version number of the remote management chip by calling this interface.

[0099] Preferably, this step also includes:

[0100] S323. Obtain the fault information and PCIe interface information of the graphics processor chip based on the GPIO resource detection of the remote management chip.

[0101] By using the GPIO resources of the remote management chip, the following two graphics processor chip status signals are monitored: GPUFault and PCIe GEN4, in order to obtain the fault information and PCIe interface information of the graphics processor chip.

[0102] S330 matches the firmware information of the graphics processor chip with the status information and preset management rules of the graphics processor chip to the target management strategy and executes it.

[0103] Example 3: Corresponding to Examples 1 and 2 above, the following will be combined with... Figure 4This application describes the graphics processor device management system provided. This system can be implemented in hardware or software, or a combination of both; this application does not limit its implementation.

[0104] In one example, this application provides a graphics processor device management system, wherein the graphics management device includes at least a graphics processor chip and a remote management chip, and the graphics processor chip is further connected to a PCIe; the graphics processor device management system includes:

[0105] The first acquisition module 410 is used to acquire the firmware information of the graphics processor chip based on the PCIe;

[0106] The second acquisition module 420 is used to acquire the status information of the graphics processor chip based on the remote management chip;

[0107] The matching execution module 430 is used to match the target management strategy with the firmware information of the graphics processor chip and the status information and preset management rules of the graphics processor chip, and then execute it.

[0108] In one embodiment, the PCIe establishes a connection with the main server via a gold finger, and the gold finger is provided with a system management bus; the graphics processing chip is provided with at least a field-replaceable unit, a electrically erasable programmable read-only memory and a temperature chip.

[0109] The first acquisition module 410 includes:

[0110] The first reading unit 411 is used to read the field replaceable unit information, the electrically erasable programmable read-only memory information, and the temperature chip information based on the PCIe and the system management bus.

[0111] Preferably, the first acquisition module 410 further includes:

[0112] The transmission unit 412 is used to transmit the PCIe x16 signal sent by the host server to the graphics processor chip via the gold finger based on the PCIe;

[0113] The first acquisition unit 413 is used to acquire the data calculated by the graphics processor chip based on the PCIe x16 signal and transmit the data to the main server.

[0114] More preferably, the graphics processor chip is connected to a power connector via the gold finger for power supply; the first acquisition module 410 further includes:

[0115] The second reading unit 414 is used to read the status information of the remote management chip and the voltage status information of the graphics processor chip based on the PCIe and the system management bus.

[0116] In one embodiment, the second acquisition module 420 is specifically used for:

[0117] The power information and out-of-band information of the graphics processor chip are obtained based on the remote management chip.

[0118] Preferably, the remote management chip includes a microcontroller unit; the second acquisition module 420 includes:

[0119] The second acquisition unit 421 is used to acquire power data and power status signal data based on the monitoring of the remote management chip. The power data includes at least peak power data and power data of each component in the graphics processor device.

[0120] The third acquisition unit 422 is used to acquire, based on the microcontroller unit and the bidirectional two-wire synchronous serial bus, the internal temperature data of the graphics processor chip, the total power data of the card, the memory temperature data, the clock frequency, the memory error check and correction data, the power data, the power status signal, the graphics processor status signal, and the firmware version number of the remote management chip.

[0121] More preferably, the second acquisition module 420 further includes:

[0122] The fourth acquisition unit 423 is used to acquire fault information and PCIe interface information of the graphics processor chip based on the GPIO resource detection of the remote management chip.

[0123] Example 4: Corresponding to Examples 1 to 3 above, the following will be combined with... Figure 5 This application provides a description of the computer equipment provided. In one example, for instance... Figure 5 As shown, this application provides a computer device, which includes:

[0124] One or more processors;

[0125] and a memory associated with the one or more processors, the memory being used to store program instructions that, when read and executed by the one or more processors, perform the following operations:

[0126] Firmware information of the graphics processor chip is obtained based on the PCIe;

[0127] The status information of the graphics processor chip is obtained based on the remote management chip;

[0128] The target management strategy is matched and executed based on the firmware information of the graphics processor chip, the status information of the graphics processor chip, and preset management rules.

[0129] In one implementation, when the program instructions are read and executed by the one or more processors, the following operations are also performed:

[0130] The information of the field replaceable unit, the information of the electrically erasable programmable read-only memory, and the information of the temperature chip are read based on the PCIe and the system management bus.

[0131] When the program instructions are read and executed by the one or more processors, the following operations are also performed:

[0132] Based on the PCIe, the PCIe x16 signal sent by the main server is transmitted to the graphics processor chip via the gold fingers;

[0133] The data calculated by the graphics processor chip based on the PCIe x16 signal is obtained and transmitted to the main server.

[0134] When the program instructions are read and executed by the one or more processors, the following operations are also performed:

[0135] The remote management chip status information and the graphics processor chip voltage status information are read based on the PCIe and the system management bus.

[0136] When the program instructions are read and executed by the one or more processors, the following operations are also performed:

[0137] The power information and out-of-band information of the graphics processor chip are obtained based on the remote management chip.

[0138] When the program instructions are read and executed by the one or more processors, the following operations are also performed:

[0139] Based on the remote management chip, power data and power status signal data are monitored and obtained. The power data includes at least peak power data and power data of each component in the graphics processor device.

[0140] Based on the microcontroller unit and the bidirectional two-wire synchronous serial bus, the following data are acquired: internal temperature data of the graphics processor chip, total card power data, memory temperature data, clock frequency, memory error check and correction data, power supply data, power status signals, graphics processor status signals, and firmware version number of the remote management chip.

[0141] When the program instructions are read and executed by the one or more processors, the following operations are also performed:

[0142] The fault information and PCIe interface information of the graphics processor chip are obtained based on the GPIO resource detection of the remote management chip.

[0143] When the program instructions are read and executed by the one or more processors, they can also perform operations corresponding to the steps in the above method embodiments, as described above, and will not be repeated here. (Reference) Figure 5 This exemplifies the architecture of a computer device, which may include a processor 510, a video display adapter 511, a disk drive 512, an input / output interface 513, a network interface 514, and a memory 520. The processor 510, video display adapter 511, disk drive 512, input / output interface 513, network interface 514, and memory 520 can communicate with each other via a communication bus 530.

[0144] The processor 510 can be implemented using a general-purpose central processing unit (CPU), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solution provided in this application.

[0145] The memory 520 can be implemented as a read-only memory (ROM), random access memory (RAM), static storage device, dynamic storage device, etc. The memory 520 can store the operating system 521 for controlling the operation of the computer device 500, and the basic input / output system (BIOS) 522 for controlling the low-level operations of the computer device 500. Additionally, it can store a web browser 523, data storage management 524, and an icon font processing system 525, etc. The aforementioned icon font processing system 525 can be the application program that specifically implements the aforementioned steps in this embodiment. In summary, when the technical solution provided in this application is implemented through software or firmware, the relevant program code is stored in the memory 520 and is called and executed by the processor 510.

[0146] Input / output interface 513 is used to connect input / output modules to realize information input and output. Input / output modules can be configured as components in the device (not shown in the figure) or externally connected to the device to provide corresponding functions. Input devices may include keyboards, mice, touch screens, microphones, various sensors, etc., and output devices may include displays, speakers, vibrators, indicator lights, etc.

[0147] Network interface 514 is used to connect a communication module (not shown in the figure) to enable communication between this device and other devices. The communication module can communicate via wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0148] Bus 530 includes a pathway for transmitting information between various components of the device, such as processor 510, video display adapter 511, disk drive 512, input / output interface 513, network interface 514, and memory 520.

[0149] In addition, the computer device 500 can also obtain information on specific acquisition conditions from the virtual resource object acquisition condition information database 541 for condition judgment, etc.

[0150] It should be noted that although the computer device 500 described above only shows a processor 510, a video display adapter 511, a disk drive 512, an input / output interface 513, a network interface 514, a memory 520, and a bus 530, in specific implementations, the computer device may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above device may only include the components necessary for implementing the solution of this application, and does not necessarily include all the components shown in the figures.

[0151] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, cloud server, or network device, etc.) to execute the methods described in various embodiments or some parts of the embodiments of this application.

[0152] Example 5: Corresponding to Examples 1 to 4 above, the computer-readable storage medium provided in this application will be described below. In one example, this application provides a computer-readable storage medium storing a computer program thereon, wherein the computer program, when executed by a processor, performs the following steps:

[0153] Firmware information of the graphics processor chip is obtained based on the PCIe;

[0154] The status information of the graphics processor chip is obtained based on the remote management chip;

[0155] The target management strategy is matched and executed based on the firmware information of the graphics processor chip, the status information of the graphics processor chip, and preset management rules.

[0156] In one implementation, the computer program, when executed by a processor, further performs the following steps:

[0157] The information of the field replaceable unit, the information of the electrically erasable programmable read-only memory, and the information of the temperature chip are read based on the PCIe and the system management bus.

[0158] When the computer program is executed by the processor, it also performs the following steps:

[0159] Based on the PCIe, the PCIe x16 signal sent by the main server is transmitted to the graphics processor chip via the gold fingers;

[0160] The data calculated by the graphics processor chip based on the PCIe x16 signal is obtained and transmitted to the main server.

[0161] When the computer program is executed by the processor, it also performs the following steps:

[0162] The remote management chip status information and the graphics processor chip voltage status information are read based on the PCIe and the system management bus.

[0163] When the computer program is executed by the processor, it also performs the following steps:

[0164] The power information and out-of-band information of the graphics processor chip are obtained based on the remote management chip.

[0165] When the computer program is executed by the processor, it also performs the following steps:

[0166] Based on the remote management chip, power data and power status signal data are monitored and obtained. The power data includes at least peak power data and power data of each component in the graphics processor device.

[0167] Based on the microcontroller unit and the bidirectional two-wire synchronous serial bus, the following data are acquired: internal temperature data of the graphics processor chip, total card power data, memory temperature data, clock frequency, memory error check and correction data, power supply data, power status signals, graphics processor status signals, and firmware version number of the remote management chip.

[0168] When the computer program is executed by the processor, it also performs the following steps:

[0169] The fault information and PCIe interface information of the graphics processor chip are obtained based on the GPIO resource detection of the remote management chip.

[0170] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments. The system embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0171] Furthermore, it should be understood that the terms "first," "second," "third," and "fourth" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," "third," or "fourth" may explicitly or implicitly include one or more of that feature.

[0172] Of course, the above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be used to limit the scope of protection of the present invention. All modifications made according to the spirit and essence of the main technical solution of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A graphics processor device management method, applied to a graphics manager device, characterized in that, The graphics management device includes at least a graphics processor chip and a remote management chip, and the graphics processor chip is further connected to a PCIe; the method includes: Firmware information of the graphics processor chip is obtained based on the PCIe; The status information of the graphics processor chip is obtained based on the remote management chip; The target management strategy is matched and executed based on the firmware information of the graphics processor chip, the status information of the graphics processor chip, and preset management rules. The step of obtaining the status information of the graphics processor chip based on the remote management chip includes: The power information and out-of-band information of the graphics processor chip are obtained based on the remote management chip; The remote management chip contains a microcontroller unit, and the acquisition of power information and out-of-band information of the graphics processor chip based on the remote management chip includes: Based on the remote management chip, power data and power status signal data are monitored and obtained. The power data includes at least peak power data and power data of each component in the graphics processor device. Based on the microcontroller unit and the bidirectional two-wire synchronous serial bus, the following data are acquired: internal temperature data of the graphics processor chip, total card power data, graphics memory temperature data, clock frequency, memory error checking and correction data, power supply data, power status signals, graphics processor status signals, and firmware version number of the remote management chip. Among them, the microcontroller unit acts as a slave device of the bidirectional two-wire synchronous serial bus, and the main server baseboard management controller acts as a master device of the bidirectional two-wire synchronous serial bus. The microcontroller unit will provide the main server baseboard management controller with an out-of-band bidirectional two-wire synchronous serial bus call interface. The main server baseboard management controller completes the acquisition of graphics processor chip internal temperature data, card power data, video memory temperature data, clock frequency, memory error check and correction data, and remote management chip firmware version number by calling the out-of-band bidirectional two-wire synchronous serial bus call interface.

2. The graphics processor device management method according to claim 1, characterized in that, The PCIe establishes a connection with the main server via a gold finger, and the gold finger is equipped with a system management bus. The graphics processor chip is equipped with at least a field-replaceable unit, an electrically erasable programmable read-only memory, and a temperature chip. The process of obtaining the firmware information of the graphics processor chip based on the PCIe includes: The information of the field replaceable unit, the information of the electrically erasable programmable read-only memory, and the information of the temperature chip are read based on the PCIe and the system management bus.

3. The graphics processor device management method according to claim 2, characterized in that, The method further includes: Based on the PCIe, the PCIe x16 signal sent by the main server is transmitted to the graphics processor chip via the gold fingers; The data calculated by the graphics processor chip based on the PCIe x16 signal is obtained and transmitted to the main server.

4. The graphics processor device management method according to claim 2, characterized in that, The graphics processor chip is connected to a power connector via the gold fingers for power supply; the method further includes: The remote management chip status information and the graphics processor chip voltage status information are read based on the PCIe and the system management bus.

5. The graphics processor device management method according to claim 1, characterized in that, The process of obtaining the power information and out-of-band information of the graphics processor chip based on the remote management chip also includes: The fault information and PCIe interface information of the graphics processor chip are obtained based on the GPIO resource detection of the remote management chip.

6. A graphics manager device for implementing the method of claim 1, characterized in that, The graphics management device includes at least a graphics processor chip and a remote management chip, and the graphics processor chip is also connected to a PCIe; the graphics management device further includes: The first acquisition module is used to acquire the firmware information of the graphics processor chip based on the PCIe; The second acquisition module is used to acquire the status information of the graphics processor chip based on the remote management chip; The matching execution module is used to match the target management strategy with the firmware information of the graphics processor chip and the status information and preset management rules of the graphics processor chip, and then execute it.

7. A computer device, characterized in that, The device includes: One or more processors; and A memory associated with the one or more processors, the memory being used to store program instructions that, when read and executed by the one or more processors, perform the graphics processor device management method as described in any one of claims 1-5.

8. A computer-readable storage medium having a computer program stored thereon, wherein, When the computer program is executed by the processor, it implements the steps of the graphics processor device management method as described in any one of claims 1-5.

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