A security test circuit and method for MCU chips
By reusing the pin switching debugging protocol and key authentication mechanism, efficient and secure testing of MCU chips is achieved, solving the problems of high testing costs and insufficient security. Parallel testing of storage units and programmable memories is realized, reducing testing costs and preventing unauthorized modifications.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 3PEAK INC
- Filing Date
- 2022-10-11
- Publication Date
- 2026-07-31
AI Technical Summary
The testing process for MCU chips suffers from high testing costs, long testing times, and insufficient security, especially during the CP testing phase. Comprehensive testing needs to be carried out under limited equipment resources and complex circuits, while preventing unauthorized personnel from entering the testing mode and modifying the circuit.
Multiplexed pins are used to switch between SWD and non-SWD debugging protocols. Combined with a key authentication mechanism, the multiplexed pins are used to simultaneously perform tests on the storage unit and the programmable memory. The core test module and the programmable memory test module are executed in parallel to ensure test security.
This approach achieves the goal of saving test pins and time, reducing costs, and improving test security while preventing external modifications, all while ensuring test coverage.
Smart Images
Figure CN115576814B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip testing technology, and in particular to a security testing circuit and method for MCU chips. Background Technology
[0002] The process of an MCU chip being used in a final product typically involves several stages, including chip design, chip verification, chip testing, wafer manufacturing, and subsequent testing, packaging, final product testing, and board-level testing. Throughout the entire production chain, chip testing is integral to the design and mass production process. With continuous innovation in chip manufacturing processes, chip sizes are increasing, and the failure modes that occur during production are becoming more complex, making chip testing increasingly challenging.
[0003] Generally, MCU chip testing is divided into Circuit Probe (CP) testing and Final Test (FT) testing. CP testing is a direct test of the bare die before packaging, while FT testing is performed in the laboratory after chip packaging. The earlier failures are detected during chip testing, the less unnecessary resource waste can be reduced. Therefore, chip design manufacturers typically need to perform as comprehensive a test as possible during the CP testing phase. CP testing needs to be performed on test equipment, which is usually expensive and has a limited number of probes. MCU chips contain various external interfaces and complex analog circuits, such as I2C, UART, SPI, SWD, ADC, DAC, and touchscreens. Therefore, complex testing is required during MCU chip testing to ensure that all chip functions correctly.
[0004] On the one hand, during the testing process, it is required to ensure the completion of test coverage while saving test pins and time as much as possible. Therefore, from a cost perspective, more efficient and time-saving testing methods can better reduce testing costs.
[0005] On the other hand, during the design of MCU chips, design manufacturers will embed some circuits that are not exposed to customers. However, if downstream customers can freely enter the test mode and modify the embedded circuit design, the security of the chip cannot be guaranteed, and it will also cause incalculable losses to the chip design manufacturer. Therefore, ensuring the security of MCU chips when entering the test mode is also very important. Summary of the Invention
[0006] The purpose of this invention is to provide a secure testing circuit and method for MCU chips, which enables efficient and time-saving testing while reducing testing costs, and ensures testing security by preventing external personnel from entering the testing mode and modifying the chip's circuitry.
[0007] To achieve the above-mentioned objectives, the embodiments of the present invention provide the following technical solutions:
[0008] A security test circuit for an MCU chip includes an MCU chip, wherein the MCU chip includes multiplexed pins, a storage unit, and a programmable memory, characterized in that: the MCU chip further includes a core test module and a programmable memory test module; wherein...
[0009] The multiplexed pin has both SWD debugging protocol and non-SWD debugging protocol; when writing a test program to the memory cell, the multiplexed pin uses the SWD debugging protocol; when writing a test sequence to the programmable memory, the multiplexed pin uses the non-SWD debugging protocol.
[0010] The core test module is used to perform tests on the memory unit according to the test program written by the multiplexed pins;
[0011] The programmable memory test module is used to perform tests on the programmable memory according to the test sequence written by the multiplexed pins; and the time periods for the core test module and the programmable memory test module to perform tests partially or completely overlap.
[0012] In the above scheme, the multiplexed pin has two interface protocols: SWD debugging protocol and non-SWD debugging protocol. When it is necessary to write test programs to the memory unit, the SWD debugging protocol is used; when it is necessary to access on-chip resources, the non-SWD debugging protocol is used. The protocol can be switched in real time to realize both testing and non-testing processes, saving test pins. Furthermore, during the test execution process, the core test module and the programmable memory test module can perform tests simultaneously, which not only saves the machine probes required for testing but also saves test time, reducing the overall test cost and solving the first technical problem of this invention.
[0013] Furthermore, the core testing module includes a CPU core unit and registers;
[0014] When the multiplexed pin writes a test program to the memory unit using the SWD debugging protocol, the register is set to a high level, and the CPU core unit does not enter the instruction fetch execution state.
[0015] When the multiplexed pin writes the test program to the memory unit using the SWD debugging protocol, the register remains high and responds to the multiplexed pin, and the CPU core unit does not enter the instruction fetch execution state.
[0016] Once the multiplexed pin writes a test sequence to the programmable memory using a non-SWD debugging protocol, the register is set to low, the CPU core unit enters the instruction fetch execution state, executes the test program in the memory unit, and returns the test result to the multiplexed pin.
[0017] Furthermore, the programmable storage test module includes a test unit and a test control unit;
[0018] When the multiplexed pin writes a test sequence to the programmable memory using a non-SWD debugging protocol, the test control unit determines the test mode to be entered based on the test sequence and responds to the multiplexed pin.
[0019] After receiving a response, the multiplexed pin polls and reads the test unit, causing the test unit to execute the test sequence in the programmable memory and return the test result to the multiplexed pin.
[0020] Furthermore, the multiplexing pin is also used to write a key into the programmable memory using a non-SWD debugging protocol after receiving a response from the test control unit; after the test control unit determines that the key written by the multiplexing pin matches the existing key in the programmable memory, it replies with an authentication response to the multiplexing pin.
[0021] In the above scheme, based on the security requirements of the MCU chip test mode, a key authentication method is adopted. During production, the key is injected into the test unit, and different keys can be set for different batches of MCU chips. Before the test is executed, the written key is matched with the existing key in the test unit. If the match is successful, the next test is executed, which greatly improves the security of the test and prevents external personnel from entering the test mode and modifying the circuit of the MCU chip. This solves the second technical problem of the present invention.
[0022] Furthermore, the MCU chip also includes a circuit under test and a data test module. The data test module includes a test bus and test pins. The test pins input detection voltage and detection current to the circuit under test through the test bus, and the circuit under test returns the test results to the test pins through the test bus. The data test module performs tests simultaneously with the core test module and the programmable memory test module.
[0023] In the above scheme, not only can the core test module and the programmable memory test module perform tests simultaneously, but the data test module can also perform tests on the circuit under test at the same time, realizing simultaneous testing of the storage unit, programmable memory, and test circuit, further saving test pins and time.
[0024] Furthermore, the MCU chip also includes a reset pin;
[0025] When the multiplexed pin is used to write a test program to the memory cell using the SWD debugging protocol, the reset pin is set to a high level.
[0026] When the multiplexed pin is used to write a test sequence to the programmable memory using a non-SWD debug protocol, the reset pin is set to low.
[0027] When the core test module and programmable memory test module perform tests, the reset pin is set to a high level;
[0028] After the core test module and programmable memory test module have completed the test, when returning the test results to the multiplexing pin, the reset pin is set to a low level.
[0029] A security testing method for MCU chips includes the following steps:
[0030] Step S1: Power on the MCU chip, set the reset pin to high level, and use the SWD debugging protocol to write the test program to the memory unit using the multiplexed pin;
[0031] Step S2: Set the reset pin to low level, and use the multiplexed pin to write a test sequence to the programmable memory using a non-SWD debug protocol;
[0032] Step S3: Set the reset pin to high level. The core test module executes the test program in the memory unit, and at the same time, the programmable memory test module executes the test sequence in the programmable memory.
[0033] Step S4: Set the reset pin to low level, and the core test module and programmable memory test module return the test results to the multiplexed pin.
[0034] Furthermore, step S1 specifically includes the following steps:
[0035] When the MCU chip is powered on, the reset pin is set to high level, the multiplexed pin uses the SWD debugging protocol to write the test program to the memory unit, the register is set to high level, and the CPU core unit does not enter the instruction fetch execution state.
[0036] After the test program is written, the register remains at a high level and sends a response to the multiplexed pin, while the CPU core unit still does not enter the instruction fetch execution state.
[0037] Furthermore, step S2 specifically includes the following steps:
[0038] When the multiplexed pin receives a response from the register, it sets the reset pin to a low level and writes a test sequence to the programmable memory using a non-SWD debugging protocol. The test control unit determines the test mode to be entered based on the test sequence and responds to the multiplexed pin.
[0039] After receiving the response from the test control unit, the multiplexed pin writes a key to the programmable memory using a non-SWD debugging protocol. The test control unit then sends an authentication response back to the multiplexed pin after determining that the key written by the multiplexed pin matches the key already in the programmable memory.
[0040] Furthermore, step S3 specifically includes the following steps:
[0041] When the multiplexing pin receives the reply authentication response from the test control unit, the reset pin is set to high level, the register is set to low level, the CPU core unit enters the instruction fetch execution state, and executes the test program in the memory unit;
[0042] Simultaneously, the pins are used to poll and read the test unit, enabling the test unit to execute the test sequence in the programmable memory.
[0043] Furthermore, it also includes step P:
[0044] The test pin inputs the detection voltage and detection current to the circuit under test through the test bus, and the circuit under test returns the test results to the test pin; the time period of step P and steps S1-S4 partially or completely overlaps.
[0045] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0046] (1) This invention performs tests on storage units, programmable memory and test circuits simultaneously while ensuring test coverage, thereby saving test pins and time and reducing test costs.
[0047] (2) The present invention performs key authentication, which improves the security of the test and prevents external personnel from entering the test mode and modifying the circuit of the MCU chip. Attached Figure Description
[0048] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0049] Figure 1 This is a schematic diagram of the test circuit for Embodiment 1 of the present invention;
[0050] Figure 2 This is a schematic diagram of the test circuit for Embodiment 2 of the present invention. Detailed Implementation
[0051] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.
[0052] It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, the terms "first," "second," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance, or suggesting any such actual relationship or order between these entities or operations.
[0053] Example 1:
[0054] This invention is achieved through the following technical solutions, such as... Figure 1 As shown, a security test circuit for an MCU chip includes an MCU chip, which includes multiplexing pins, a reset pin, a storage unit, a core test module, a programmable memory, and a programmable storage test module.
[0055] The multiplexed pin supports both SWD (The Serial Wire Debug Port) and non-SWD (The Serial Wire Debug Port) debugging protocols. SWD is a serial debug port, one of the two debug ports currently supported by ARM, based on the ARM CoreSight debug architecture. SWD can read and write chip registers by transmitting data packets. The non-SWD debugging protocol is a protocol that does not use SWD debugging and can be customized according to the needs of technical personnel. When writing test programs to memory units through the multiplexed pin, the multiplexed pin uses the SWD debugging protocol; when writing test sequences to programmable memory through the multiplexed pin, the multiplexed pin uses the non-SWD debugging protocol. In addition to writing test programs and test sequences, the multiplexed pin also writes keys to programmable memory.
[0056] The core test module is used to execute tests on the memory unit according to the test program written to the multiplexed pin and return the test results to the multiplexed pin. Specifically, the core test module includes a CPU core unit and registers. When the multiplexed pin writes a test program to the memory unit using the SWD debugging protocol, the reset pin is set to high level, the register is set to high level, and the CPU core unit does not enter the instruction fetch execution state. Then, after the multiplexed pin writes a test program to the memory unit using the SWD debugging protocol, the register remains high level and responds to the multiplexed pin, and the CPU core unit does not enter the instruction fetch execution state. Until the multiplexed pin writes a test sequence to the programmable memory using a non-SWD debugging protocol, the reset pin is set to high level, the register is set to low level, the CPU core unit enters the instruction fetch execution state, executes the test program in the memory unit, and returns the test results to the multiplexed pin. When the CPU core unit returns the test results to the multiplexed pin, the reset pin is set to low level, and while the CPU core unit executes the test program, the programmable memory test module also simultaneously executes the test sequence in the programmable memory. Therefore, the time periods for the core test module and the programmable memory test module to execute tests partially or completely overlap.
[0057] The programmable memory test module is used to perform tests on the programmable memory according to the test sequence written by the multiplexed pin, and return the test results to the multiplexed pin. Specifically, the programmable memory test module includes a test unit and a test control unit. When the multiplexed pin writes a test sequence to the programmable memory using a non-SWD debugging protocol, the reset pin is set to a low level. Then, after the multiplexed pin writes a test sequence to the programmable memory using a non-SWD debugging protocol, the test control unit determines the required test mode based on the test sequence and sends a response to the multiplexed pin. After receiving the response, the multiplexed pin sets the reset pin to a high level, polls the test unit, causing the test unit to execute the test sequence in the programmable memory and return the test results to the multiplexed pin; when the test unit returns the test results to the multiplexed pin, the reset pin is set to a low level.
[0058] In a further embodiment, after receiving a response from the test control unit, the multiplexed pin writes a key to the programmable memory using a non-SWD debugging protocol. The test control unit then determines whether the key written by the multiplexed pin matches an existing key in the programmable memory and sends an authentication response back to the multiplexed pin. Only after the multiplexed pin receives the authentication response from the test control unit does the reset pin go high, and then the CPU core unit and test unit begin executing the test.
[0059] In a further embodiment, in addition to the programmable memory test module performing tests on the programmable memory and the core test module performing tests on the memory cells, a data test module is also included to perform tests on some circuits under test in the MCU chip. Specifically, the data test module includes a test bus and test pins, wherein the test pins input detection voltage and detection current to the circuit under test through the test bus, and the circuit under test returns the test results to the test pins through the test bus.
[0060] Furthermore, the data testing module can perform tests simultaneously with the core testing module and the programmable memory testing module. Therefore, this solution includes three parts: the storage unit to be tested, the programmable memory, and the circuit under test. Test programs and test sequences are written to the storage unit and the programmable memory respectively via multiplexed pins. Then, the core testing module and the programmable memory testing module can simultaneously perform tests on the storage unit and the programmable memory. When the test program or test sequence is written via the multiplexed pins, the data testing module can begin executing the test. Therefore, this solution can achieve partial or complete overlap in the testing timelines of the storage unit, programmable memory, and test circuit.
[0061] Based on the above circuit, this solution also proposes a security testing method for MCU chips, including the following steps:
[0062] Step S1: Power on the MCU chip, set the reset pin to high level, and use the SWD debugging protocol to write the test program to the memory unit using the multiplexed pin.
[0063] The MCU powers on normally, and the reset pin is set to a high level. At this time, the control permission of the multiplexed pin is SWD debug protocol, and the test program is written to the memory unit through the multiplexed pin. During the writing of the test program, the register is set to a high level, and the CPU core unit does not enter the instruction fetch execution state. After the test program is written, the register remains at a high level and sends an acknowledgment to the multiplexed pin, indicating that the test program has been successfully written. At this time, the CPU core unit still does not enter the instruction fetch execution state, and proceeds to step S2.
[0064] The test program for writing to the memory cell is a test of the internal circuits of the MCU chip, such as ADC, DAC, power management, touch screen, etc. However, this solution does not limit the specific test process and test results. Instead, it proposes to save test pins and time as much as possible and reduce test costs while ensuring the completion of test coverage.
[0065] Step S2: Set the reset pin to low level and use the multiplexed pin to write a test sequence to the programmable memory using a non-SWD debugging protocol.
[0066] When the reset pin receives a response from the register, it goes low. At this point, the multiplexed pin is controlled under a non-SWD debug protocol. Test sequences are written to the programmable memory via the multiplexed pin. The test control unit uses these test sequences to determine the required test mode. For example, test sequences might be binary codes like "100" or "111," with different binary codes representing different test modes. After determining the test mode, the test unit sends a response to the multiplexed pin, indicating that the test sequence has been successfully written and the test mode has been determined.
[0067] At this point, we can proceed to step S3, where the core test module executes the test program in the storage unit, and the programmable storage test module executes the test sequence in the programmable memory. That is, the test execution time periods partially or completely overlap. While ensuring the completion of test coverage, the simultaneous execution of tests saves test pins and time, reduces test costs, and solves the first technical problem of this invention.
[0068] To further address the second technical problem of this invention, after the multiplexed pin receives the response from the test control unit in step S2, the reset pin remains at a low level, and the multiplexed pin writes a key to the programmable memory using a non-SWD debugging protocol. The test control unit determines whether the key written by the multiplexed pin matches an existing key in the programmable memory. The existing key in the programmable memory is embedded during the manufacturing process of the MCU chip, and different batches of MCU chips can have different keys. Verifying key compatibility before executing the test sequence in the programmable memory ensures test security and prevents external personnel from entering the test mode and modifying the MCU chip's circuitry, thus preventing resource leakage. Furthermore, the ability to embed different keys into batches of MCU chips further prevents losses caused by key leakage.
[0069] Once the test control unit determines that the key written to the multiplexing pin matches an existing key in the programmable memory, it sends an authentication response to the multiplexing pin. After receiving the authentication response, the multiplexing pin proceeds to step S3.
[0070] Step S3: Set the reset pin to high level. The core test module executes the test program in the storage unit, and at the same time, the programmable storage test module executes the test sequence in the programmable memory.
[0071] After completing the test program and test writing, and receiving the response acknowledgment and authentication acknowledgment on the multiplexed pin, the reset pin is set to high. At this point, the multiplexed pin's control permission is set to non-SWD debug protocol, and the test execution process begins. The register is set to low, releasing the CPU core unit to enter the instruction fetch execution state, retrieving the test program from the memory unit and executing it. Simultaneously, the multiplexed pin polls and reads the test unit, causing the test unit to execute the test sequence in the programmable memory.
[0072] As can be seen, by using multiplexed pins to write test programs and test sequences to the memory cell and programmable memory respectively, the core test module and the programmable memory test module can simultaneously perform tests on the memory cell and programmable memory. Parallel testing can save test pins and time, and reduce test costs.
[0073] Step S4: Set the reset pin to low level, and the core test module and programmable memory test module return the test results to the multiplexed pin.
[0074] After the CPU core unit finishes executing the test program in the memory unit and the test unit finishes executing the test sequence in the programmable memory, the reset pin is automatically set to low. At this time, the CPU core unit returns the test results of the memory unit to the multiplexed pin, and the test unit returns the test results of the programmable memory to the multiplexed pin. Alternatively, the control permission of the multiplexed pin can be set to the SWD debug protocol, and the multiplexed pin reads back the test results of the memory unit and the programmable memory.
[0075] Step P: The test pin inputs the detection voltage and detection current to the circuit under test through the test bus, and the circuit under test returns the test results to the test pin; Step P and Steps S1-S4 partially or completely overlap in time.
[0076] Steps S1-S4 involve writing and executing the test program and test sequence, which performs tests on the storage unit and programmable memory. Simultaneously, step P can be performed concurrently, enabling simultaneous testing of the storage unit, programmable memory, and test circuitry, meaning that the testing time periods partially or completely overlap, further reducing testing costs.
[0077] Example 2:
[0078] This embodiment is a further optimization based on Embodiment 1 described above, such as... Figure 2As shown, in the actual production of MCU chips, the test unit is a programmable test unit, the programmable memory is a non-volatile programmable memory, such as FLASH or ROM, the CPU core unit is CPU CORE, the register is CPU_WAIT, the storage unit is SRAM or DRAM, and the remaining unit devices are the same as in Embodiment 1, and the test methods are also the same.
[0079] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. An MCU chip security test circuit, comprising an MCU chip, the MCU chip comprising a multiplexing pin, a storage unit, a programmable memory, characterized in that: The MCU chip also includes a core testing module and a programmable memory testing module; wherein... The multiplexed pin has both SWD debugging protocol and non-SWD debugging protocol; when writing a test program to the memory cell, the multiplexed pin uses the SWD debugging protocol; when writing a test sequence to the programmable memory, the multiplexed pin uses the non-SWD debugging protocol. The core testing module is used to perform tests on the memory unit according to the test program written by the multiplexed pins; the core testing module includes a CPU core unit and registers; When the multiplexed pin writes a test program to the memory unit using the SWD debugging protocol, the register is set to a high level, and the CPU core unit does not enter the instruction fetch execution state. When the multiplexed pin writes the test program to the memory unit using the SWD debugging protocol, the register remains high and responds to the multiplexed pin, and the CPU core unit does not enter the instruction fetch execution state. Once the multiplexed pin writes a test sequence to the programmable memory using a non-SWD debugging protocol, the register is set to low, the CPU core unit enters the instruction fetch execution state, executes the test program in the memory unit, and returns the test result to the multiplexed pin. The programmable memory test module is used to perform tests on the programmable memory according to the test sequence written by the multiplexed pins; and the time periods for the core test module and the programmable memory test module to perform tests partially or completely overlap.
2. The MCU chip security test circuit of claim 1, wherein: The programmable storage test module includes a test unit and a test control unit; When the multiplexed pin writes a test sequence to the programmable memory using a non-SWD debugging protocol, the test control unit determines the test mode to be entered based on the test sequence and responds to the multiplexed pin. After receiving a response, the multiplexed pin polls and reads the test unit, causing the test unit to execute the test sequence in the programmable memory and return the test result to the multiplexed pin.
3. The MCU chip security test circuit of claim 2, wherein: The multiplexing pin is also used to write a key into the programmable memory using a non-SWD debugging protocol after receiving a response from the test control unit; after the test control unit determines that the key written by the multiplexing pin matches the existing key in the programmable memory, it replies with an authentication response to the multiplexing pin.
4. The MCU chip security test circuit of claim 1, wherein: The MCU chip also includes a circuit under test and a data test module. The data test module includes a test bus and test pins. The test pins input detection voltage and detection current to the circuit under test through the test bus. The circuit under test returns the test results to the test pins through the test bus. The data test module performs tests simultaneously with the core test module and the programmable memory test module.
5. The MCU chip security test circuit according to claim 1, characterized in that: The MCU chip also includes a reset pin; When the multiplexed pin is used to write a test program to the memory cell using the SWD debugging protocol, the reset pin is set to a high level. When the multiplexed pin is used to write a test sequence to the programmable memory using a non-SWD debug protocol, the reset pin is set to low. When the core test module and programmable memory test module perform tests, the reset pin is set to a high level; After the core test module and programmable memory test module have completed the test, when returning the test results to the multiplexing pin, the reset pin is set to a low level.
6. A security testing method for an MCU chip, characterized in that: Includes the following steps: Step S1: Power on the MCU chip, set the reset pin to high level, and use the SWD debugging protocol to write the test program to the memory unit using the multiplexed pin; Step S1 specifically includes the following steps: When the MCU chip is powered on, the reset pin is set to high level, the multiplexed pin uses the SWD debugging protocol to write the test program to the memory unit, the register is set to high level, and the CPU core unit does not enter the instruction fetch execution state. After the test program is written, the register remains at a high level and sends a response to the multiplexed pin, while the CPU core unit still does not enter the instruction fetch execution state; Step S2: Set the reset pin to low level, and use the multiplexed pin to write a test sequence to the programmable memory using a non-SWD debug protocol; Step S3: Set the reset pin to high level. The core test module executes the test program in the memory unit, and at the same time, the programmable memory test module executes the test sequence in the programmable memory. Step S4: Set the reset pin to low level, and the core test module and programmable memory test module return the test results to the multiplexed pin.
7. The MCU chip security testing method according to claim 6, characterized in that: Step S2 specifically includes the following steps: When the multiplexed pin receives a response from the register, it sets the reset pin to a low level and writes a test sequence to the programmable memory using a non-SWD debugging protocol. The test control unit determines the test mode to be entered based on the test sequence and responds to the multiplexed pin. After receiving the response from the test control unit, the multiplexed pin writes a key to the programmable memory using a non-SWD debugging protocol. The test control unit then sends an authentication response back to the multiplexed pin after determining that the key written by the multiplexed pin matches the key already in the programmable memory.
8. The MCU chip security testing method according to claim 7, characterized in that: Step S3 specifically includes the following steps: When the multiplexing pin receives the reply authentication response from the test control unit, the reset pin is set to high level, the register is set to low level, the CPU core unit enters the instruction fetch execution state, and executes the test program in the memory unit; Simultaneously, the pins are used to poll and read the test unit, enabling the test unit to execute the test sequence in the programmable memory.
9. A security testing method for an MCU chip according to claim 6, characterized in that: It also includes step P: The test pin inputs the detection voltage and detection current to the circuit under test through the test bus, and the circuit under test returns the test results to the test pin. The time periods of step P and steps S1-S4 may partially or completely overlap.