Storage device and method of operating the same

Abstract

The disclosure provides a storage device and an operating method thereof. The storage device can include a memory device, a cache memory device including a first cache memory and a second cache memory, the first cache memory caching first data among data stored in a plurality of pages, the second cache memory caching second data among the data stored in the plurality of pages, and a memory controller counting a number of times each of the plurality of pages is read and a number of times each of the plurality of pages is written based on a read request or a write request received from a host, and moving the first data from the first cache memory to the second cache memory when the first data is stored in a first page and the number of times the first page is read and the number of times the first page is written satisfy a predetermined condition.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0080281, filed on June 21, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure generally relates to an electronic device, and more specifically, to a storage device and a method of operating the same. Background Technology

[0004] A storage device is a means of storing data under the control of a host device such as a computer or smartphone. A storage device may include a memory device for storing data and a memory controller for controlling the memory device. Memory devices are classified as volatile memory devices and non-volatile memory devices.

[0005] Volatile memory devices are memory devices that store data only while power is supplied and lose the stored data when the power supply is interrupted. Volatile memory devices can include static random access memory (SRAM), dynamic random access memory (DRAM), etc.

[0006] Non-volatile memory devices are memory devices that do not lose data even when the power supply is interrupted. Non-volatile memory devices can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEROM), flash memory, etc. Summary of the Invention

[0007] Embodiments of this disclosure provide a storage device for managing an improved multi-level cache memory and a method for operating the storage device.

[0008] According to one aspect of this disclosure, a storage device is provided, the storage device comprising: a memory device including a plurality of pages; a cache memory device including a first cache memory and a second cache memory, the first cache memory caches first data among data stored in the plurality of pages, and the second cache memory caches second data among data stored in the plurality of pages; and a memory controller configured to count the number of times each of the plurality of pages is read and the number of times each of the plurality of pages is written based on a read request or a write request received from a host, and to move the first data from the first cache memory to the second cache memory when the first data is stored in the first page among the plurality of pages and the number of times the first page is read and the number of times the first page is written meets the predetermined conditions.

[0009] According to another aspect of this disclosure, a method for operating a storage device is provided, the storage device including a first cache memory and a second cache memory, the method comprising: storing first data of data stored in a plurality of pages included in the storage device in the first cache memory, and storing second data of data stored in a plurality of pages included in the storage device in the second cache memory; counting the number of times a page corresponding to a read request or a write request is received from a host; and moving the first data from the first cache memory to the second cache memory when the first data is stored in the first page of the plurality of pages and the number of times the first page is read and the number of times the first page is written meets predetermined conditions.

[0010] According to another aspect of this disclosure, a method of operating a controller is provided, the method comprising: caching page data into a first cache in response to a first request for accessing page data stored or to be stored in a page within a memory device; moving the portion of cached data to a second cache when the number of accesses to at least a portion of the cached data is greater than the sum of a predetermined number of read accesses to the portion and a single write access to the portion; and providing the cached data from one of the first cache and the second cache in response to a second request for accessing the page data. Attached Figure Description

[0011] Various embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings. However, embodiments may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the embodiments to those skilled in the art.

[0012] In the accompanying drawings, dimensions may be enlarged for clarity. It will be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or there may be one or more intermediate elements. The same reference numerals always refer to the same elements.

[0013] Figure 1 This is a block diagram illustrating a storage device according to an embodiment of the present disclosure.

[0014] Figure 2 This is a diagram illustrating the configuration of a memory controller according to an embodiment of the present disclosure.

[0015] Figure 3 This is a diagram illustrating a data caching method according to an embodiment of the present disclosure.

[0016] Figure 4 This is a diagram illustrating the operation of a storage device according to an embodiment of the present disclosure.

[0017] Figure 5 This is a diagram illustrating the operation of a cache memory during a read operation according to an embodiment of the present disclosure.

[0018] Figure 6 This is a diagram illustrating a method of operating a storage device according to an embodiment of the present disclosure.

[0019] Figure 7 This is a diagram illustrating a memory controller according to another embodiment of the present disclosure.

[0020] Figure 8 This is a diagram illustrating a memory card system according to an embodiment of the present disclosure.

[0021] Figure 9 This is a diagram illustrating a solid-state drive (SSD) system according to an embodiment of the present disclosure.

[0022] Figure 10 This is a diagram illustrating a user system according to an embodiment of the present disclosure. Detailed Implementation

[0023] The specific structural or functional descriptions disclosed herein are merely illustrative and are intended to describe embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein.

[0024] Figure 1 This is a block diagram illustrating a storage device according to an embodiment of the present disclosure.

[0025] Reference Figure 1 The storage device 1000 may include a memory device 100, a memory controller 200, and a cache memory device 300.

[0026] Storage device 1000 can be a device for storing data under the control of host 2000 such as: mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, display device, tablet PC or in-vehicle infotainment device.

[0027] Depending on the host interface, which serves as the communication scheme with the host 2000, the storage device 1000 can be manufactured as any of various types of storage devices. For example, the storage device 1000 can be implemented using any of the following types of storage devices: solid-state drive (SSD), multimedia card (MMC), embedded MMC (eMMC), reduced-size MMC (RS-MMC), micro MMC (micro-MMC), secure digital card (SD), mini SD card, micro SD card, universal serial bus (USB) storage device, universal flash memory (UFS) device, compact flash memory (CF) card, smart media card (SMC), memory stick, etc.

[0028] The storage device 1000 can be implemented as any of a variety of package types. For example, the storage device 1000 can be implemented as any of the following package types: Point-of-Package (POP), System-in-Package (SIP), System-on-Chip (SOC), Multi-Chip Package (MCP), Chip-on-Board (COB), Wafer-Level Fabrication Package (WFP), and Wafer-Level Stacked Package (WSP).

[0029] The memory device 100 can store data or use the stored data. The memory device 100 operates under the control of the memory controller 200. Moreover, the memory device 100 may include a plurality of memory dies, and each of the plurality of memory dies may include a memory cell array, the memory cell array including a plurality of memory cells for storing data.

[0030] Each memory cell can be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits.

[0031] The memory cell array may include multiple memory blocks. Each memory block may include multiple memory cells, and a memory block may include multiple pages. A page may be a unit for storing data in the memory device 100 or retrieving data stored in the memory device 100.

[0032] The memory device 100 can be implemented as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Generation 4 Low Power Double Data Rate (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND Flash Memory, Vertical NAND Flash Memory, NOR Flash Memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Spin-Torque Random Access Memory (STT-RAM), etc. In this specification, for ease of description, the case where the memory device 100 is NAND Flash Memory is described.

[0033] Memory device 100 can receive commands and addresses from memory controller 200. Memory device 100 can access a region in the memory cell array selected by the received address. Memory device 100 accessing the selected region can indicate that memory device 100 performs an operation corresponding to the received command on the selected region. For example, memory device 100 can perform a write operation (programming operation), a read operation, and an erase operation. A programming operation can be an operation in which memory device 100 records data in the region selected by the address. A read operation can be an operation in which memory device 100 reads data from the region selected by the address. An erase operation can be an operation in which memory device 100 erases the data stored in the region selected by the address.

[0034] The memory controller 200 can control all operations of the storage device 1000.

[0035] When power is applied to the storage device 1000, the memory controller 200 can run firmware (FW). The FW may include a host interface layer (HIL), a flash translation layer (FTL), and a flash interface layer (FIL). The host interface layer (HIL) receives requests from the host 2000 or outputs responses to the host 2000. The flash translation layer (FTL) manages the operation between the interface of the host 2000 and the interface of the storage device 100. The flash interface layer (FIL) provides commands to the storage device 100 or receives responses from the storage device 100.

[0036] The memory controller 200 can receive data and logical addresses (LA) from the host 2000 and translate the LA into physical addresses (PA). The physical address (PA) represents the address of a memory cell included in the memory device 100 where data will be stored. The LA can be a logical block address (LBA), and the PA can be a physical block address (PBA).

[0037] The memory controller 200 can control the memory device 100 to perform programming operations, read operations, erase operations, etc., in response to requests from the host 2000. During a programming operation, the memory controller 200 can provide programming commands, PBAs, and data to the memory device 100. During a read operation, the memory controller 200 can provide read commands and PBAs to the memory device 100. During an erase operation, the memory controller 200 can provide erase commands and PBAs to the memory device 100.

[0038] The memory controller 200 can control the memory device 100 to autonomously perform programming, reading, or erasing operations, regardless of any requests from the host 2000. For example, the memory controller 200 can control the memory device 100 to perform programming, reading, or erasing operations for background operations, such as wear leveling, garbage collection, or read recycling.

[0039] The cache memory device 300 may include a first cache memory 310 and a second cache memory 320. The cache memory device 300 can cache data stored in the memory device 100. Specifically, under the control of the memory controller 200, the cache memory device 300 can cache data stored in the memory device 100 in the first cache memory 310 or the second cache memory 320. Cache can be an operation that temporarily stores or uses frequently referenced data in memory operating at high speed to reduce the time required to access the stored data. By using the cache memory device 300, the memory device 1000 can reduce the number of times it accesses the memory device 100 at low speed.

[0040] The cache memory device 300 includes a first cache memory 310 and a second cache memory 320, which can cache data stored in the memory device 100. Specifically, the second cache memory 320 can cache data evicted from the first cache memory 310. That is, the first cache memory 310 can be a cache memory at a higher level than the second cache memory 320. The first cache memory 310 can be a memory with an operating speed higher than the operating speed of the second cache memory 320. In an embodiment, the first cache memory 310 can operate at a first speed, and the second cache memory 320 can operate at a second speed, which is slower than the first speed.

[0041] Furthermore, the capacity of the first cache memory 310 can be smaller than the capacity of the second cache memory 320. That is, the first cache memory 310 can be a memory with a higher operating speed than the second cache memory 320 but a smaller capacity. In embodiments, the first cache memory 310 and the second cache memory 320 can correspond to exclusive caches in which no data shared by the first cache memory 310 and the second cache memory 320 exists. In embodiments, the first cache memory 310 can be dynamic random access memory (DRAM), and the second cache memory 320 can be persistent memory (PM).

[0042] In this embodiment, because the cache memory device 300 constitutes a multi-layer memory including a first cache memory 310 and a second cache memory 320, hot data in the cache is stored in the first cache memory 310 and cold data in the cache is stored in the second cache memory 320, thereby improving cache efficiency. Furthermore, the cache memory device 300 prevents frequent wipes and loads, thereby improving the operational efficiency of the multi-layer memory.

[0043] The host 2000 can communicate with the storage device 1000 using at least one of the following communication standards or interfaces: Universal Serial Bus (USB), Serial AT Accessory (SATA), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), FireWire, Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), High Speed ​​Non-Volatile Memory (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Low Load DIMM (LRDIMM).

[0044] Figure 2 This is a diagram illustrating the configuration of a memory controller according to an embodiment of the present disclosure.

[0045] Reference Figure 2The memory controller 200 may include a counter 210, a register 220, and a cache table 230. The counter 210 can count the number of times a page is read and the number of times a page is written based on read and write requests received from the host 2000. A page can represent a memory cell connected to the same word line among memory cells included in a memory block. A page can be a unit for storing data in the memory device 100 or retrieving data stored in the memory device 100. Specifically, when the counter 210 receives a read request from the host 2000, the counter 210 can count the number of times a page is read based on the read request. Furthermore, when the counter 210 receives a write request from the host 2000, the counter 210 can count the number of times a page is written based on the write request. That is, the counter 210 can count the number of read or write operations performed based on read or write requests. The number of times each page is read and each page is written, counted by the counter 210, can be stored in the register 220.

[0046] While counter 210 counts the number of times a page is read and the number of times a page is written, register 220 can store information corresponding to the corresponding read or write request. For example, the number of times data corresponding to a read or write request is read and the number of times data corresponding to a read or write request is written can be accumulated and stored in register 220. Memory controller 200 can manage cached data in the first cache memory 310 and the second cache memory 320 based on the number of times data is read and data is written, i.e., the amount stored in register 220. Specifically, memory controller 200 can move data stored in the first cache memory 310 to the second cache memory 320 based on the number of times data is read and data is written, i.e., the amount stored in register 220. Moreover, memory controller 200 can move data stored in the second cache memory 320 to the first cache memory 310 based on the number of times data is read and data is written, i.e., the amount stored in register 220. According to embodiments of this disclosure, the memory controller 200 can move first data that meets predetermined conditions from the data stored in the first cache memory 310 to the second cache memory 320. The predetermined conditions may represent a condition where the number of times the data is read is equal to or greater than a threshold and the number of times the data is written is once. Furthermore, according to embodiments, the memory controller 200 can initialize the number of times the data corresponding to the first cache memory 310 is read and the number of times the data corresponding to the first cache memory 310 is written in the register 220 according to a constant period. That is, the memory controller 200 can control the cache memory device 300 to store hot data in the first cache memory 310 and cold data in the second cache memory 320 based on the information stored in the register 220.

[0047] Cache table 230 may store mapping information about cached data in cache memory device 300. In an embodiment, cache table 230 may store mapping information about cached data in first cache memory 310 and second cache memory 320. The mapping information may be information related to the address (e.g., the logical and physical address of memory device 100) indicating the location where cached data in cache memory device 300 is stored. When memory controller 200 receives a write request or read request from host 2000, memory controller 200 may refer to the mapping information stored in cache table 230 to determine a cache miss or cache hit. A cache miss may indicate that the corresponding data is not cached in cache memory device 300, and a cache hit may indicate that the corresponding data is cached in cache memory device 300.

[0048] Figure 3 This is a diagram illustrating a data caching method according to an embodiment of the present disclosure.

[0049] Reference Figure 3 This paper illustrates a method for transferring cached data A to host 2000 after caching data A stored in memory device 100 in cache memory device 300.

[0050] Specifically, the memory device 100 may include a plurality of memory cells, and the plurality of memory cells may store data. For example, data A may be stored in at least one of the plurality of memory cells included in the memory device 100.

[0051] Additionally, the cache memory device 300 can receive a read request from the host 2000 for requesting specific data (e.g., data A) stored in the memory device 100. The cache memory device 300 can load the specific data corresponding to the read request in response to the read request received from the host 2000.

[0052] According to embodiments of this disclosure, when storage device 1000 receives a read request for "data A" from host 2000, storage device 1000 can determine whether "data A" has already been cached in cache memory device 300. Furthermore, if it is determined that there is no cache miss for "data A" in cache memory device 300, storage device 1000 can load "data A" from storage device 100 into cache memory device 300. Moreover, storage device 1000 can transmit "data A" loaded into cache memory device 300 to host 2000.

[0053] Before "Data A" is loaded into cache memory device 300, storage device 1000 can ensure the space in cache memory device 300 where "Data A" is to be loaded. When the remaining storage capacity is less than the storage capacity required to load "Data A" into cache memory device 300, storage device 1000 can delete the least recently used "Data X" from the cached data in cache memory device 300. After storage device 1000 ensures the space for "Data A" to be loaded by deleting "Data X", storage device 1000 can transfer "Data A" from storage device 100.

[0054] Figure 4 This is a diagram illustrating the operation of a storage device according to an embodiment of the present disclosure.

[0055] Reference Figure 4 The storage device 1000 may include a memory device 100, a memory controller 200, and a cache memory device 300.

[0056] The memory device 100 may include multiple pages. Additionally, the cache memory device 300 may include a first cache memory 310 and a second cache memory 320, whereby the first cache memory 310 caches first data among the data stored in the multiple pages, and the second cache memory 320 caches second data among the data stored in the multiple pages.

[0057] The memory controller 200 can count the number of times each of the multiple pages is read and the number of times each of the multiple pages is written based on read requests and write requests received from the host 2000. Furthermore, when any page (e.g., page k) among the multiple pages has a read count and a write count that satisfy a predetermined condition, the memory controller 200 can move the first data (e.g., data k) stored in that page (e.g., page k) from the first cache memory 310 to the second cache memory 320. The predetermined condition can represent a condition where the number of times any page is read is equal to or greater than a threshold and the number of times any page is written is once. For example, the number of times page k is read can be equal to or greater than the threshold, and the number of times page k is written can be once.

[0058] In this embodiment, the memory controller 200 can initialize the number of times the first data is read and the number of times the first data is written according to a constant period. The memory controller 200 also initializes the number of times cached data in the first cache memory 310 is read and the number of times cached data in the first cache memory 310 is written according to a constant period, so that the cached data is not concentratedly cached in either the first cache memory 310 or the second cache memory 320.

[0059] When a write request is received from the host 2000, if data that has been written twice or more appears in the second data cached in the second cache memory 320, the storage device 1000 can move the data that has been written twice or more from the second cache memory 320 to the first cache memory 310, and initialize the number of times the moved data has been read and the number of times the moved data has been written.

[0060] Figure 5 This is a diagram illustrating the operation of a cache memory during a read operation according to an embodiment of the present disclosure.

[0061] Reference Figure 5 , Figure 5 This diagram illustrates a scenario where storage device 1000 receives a read request for "Data B" or "Data C" from host 2000. When storage device 1000 receives a read request for "Data B" or "Data C" from host 2000, storage device 1000 can determine whether "Data B" or "Data C" has already been cached in the first cache memory 310 or the second cache memory 320. Because the first cache memory 310 is a cache memory at a higher level than the second cache memory 320, storage device 1000 can determine whether "Data B" or "Data C" has already been cached in the first cache memory 310, and then determine whether "Data B" or "Data C" has already been cached in the second cache memory 320.

[0062] Because "Data B" is cached in the first cache memory 310, "Data B" can be cache-hung in the first cache memory 310. Additionally, the storage device 1000 can transfer "Data B" from the first cache memory 310 to the host 2000.

[0063] When it is determined that there is no cache miss for "data C" in the first cache memory 310, the storage device 1000 can determine whether "data C" has already been cached in the second cache memory 320. Because "data C" is cached in the second cache memory 320, "data C" can be cache hit in the second cache memory 320. In an embodiment, the storage device 1000 can transfer "data C" from the second cache memory 320 to the host 2000 in response to a read request corresponding to "data C" received from the host 2000. That is, the storage device 1000 does not transfer "data C" from the second cache memory 320 to the first cache memory 310, which is a cache memory at a higher level than the second cache memory 320, but can directly transfer "data C" from the second cache memory 320 to the host 2000.

[0064] Figure 6 This is a diagram illustrating a method of operating a storage device according to an embodiment of the present disclosure.

[0065] Reference Figure 6 The storage device 1000 can store the first data and the second data in the first cache memory 310 and the second cache memory 320, respectively (S810). Specifically, when the storage device 1000 receives a read request or a write request from the host 2000, the storage device 1000 can store the data corresponding to the read request or write request in the first cache memory 310 or the second cache memory 320.

[0066] Furthermore, the storage device 1000 can count the number of times a page corresponding to a read request or write request received from the host 2000 is read and the number of times a page corresponding to a read request or write request is written (S820). In an embodiment, the number of times each of the plurality of pages is read or the number of times each of the plurality of pages is written can be accumulated and stored in the register 220.

[0067] Furthermore, the storage device 1000 can move the first data stored in the first cache memory 310 that meets predetermined conditions to the second cache memory 320 based on the number of times each of the multiple pages is read and the number of times each of the multiple pages is written, that is, the number of times it is stored in the register 220 (S830). Specifically, the storage device 1000 can determine whether the number of times any page in the pages corresponding to the first data is read and the number of times that page in the pages corresponding to the first data is written meet predetermined conditions. The predetermined conditions may indicate that the number of times a page is read is equal to or greater than a threshold and the number of times a specific page is written is once. Moreover, the storage device 1000 can move the first data stored in the first cache memory 310 that meets predetermined conditions to the second cache memory 320.

[0068] In an embodiment, the storage device 1000 can initialize the number of times the page corresponding to the first data is read and the number of times the page corresponding to the first data is written according to a constant period.

[0069] In this embodiment, when the storage device 1000 receives from the host 2000 third data that replaces the second data stored in the second cache memory 320 and a write request for the third data, the storage device 1000 can remove the second data from the second cache memory 320. Furthermore, the storage device 1000 can store the third data in the first cache memory 310. The third data can be the same as the second data, or it can be a newer version of the second data.

[0070] Figure 7 This is a diagram illustrating a memory controller according to another embodiment of the present disclosure.

[0071] Reference Figure 7 The memory controller 1300 may include a processor 1310, RAM 1320, error correction code (ECC) circuitry 1330, ROM 1360, host interface 1370, and memory interface 1380. Figure 7 The memory controller 1300 shown can be Figure 1 An embodiment of the memory controller 200 is shown.

[0072] Processor 1310 can communicate with host 2000 via host interface 1370 and perform logical operations to control the operation of memory controller 1300. For example, processor 1310 can load program commands, data files, data structures, etc., based on requests received from host 2000 or external devices, and perform various operations or generate commands and addresses. For example, processor 1310 can generate various commands required for programming operations, read operations, erase operations, pause operations, and parameter setting operations.

[0073] Furthermore, the processor 1310 can perform the functions of a Flash Translation Layer (FTL). The processor 1310 can use the FTL to translate logical block addresses (LBAs) provided by the host 2000 into physical block addresses (PBAs). The FTL can receive input LBAs and translate them into PBAs using a mapping table. Depending on the mapping unit, there are several address mapping methods for the FTL. Representative address mapping methods include page mapping, block mapping, and hybrid mapping.

[0074] Furthermore, the processor 1310 can generate commands without any request from the host 2000. For example, the processor 1310 can generate commands for background operations such as wear leveling operations for the memory device 100 and garbage collection operations for the memory device 100.

[0075] RAM 1320 can be used as a buffer memory, working memory, or cache memory for processor 1310. Furthermore, RAM 1320 can store code and commands executed by processor 1310. RAM 1320 can store data processed by processor 1310. Moreover, RAM 1320 can include static RAM (SRAM) or dynamic RAM (DRAM).

[0076] The ECC circuit 1330 can detect and correct errors during programming or reading operations. Specifically, the ECC circuit 1330 can perform error correction operations based on an error correction code (ECC). Furthermore, the ECC circuit 1330 can perform ECC encoding based on data to be written to the memory device 100. The ECC-encoded data can be transmitted to the memory device 100 via the memory interface 1380. Moreover, the ECC circuit 1330 can perform ECC decoding on data received from the memory device 100 via the memory interface 1380.

[0077] ROM 1360 can be used as a storage unit to store various information required for the operation of memory controller 1300. Specifically, ROM 1360 may include a mapping table, and physical-to-logical address information and logical-to-physical address information can be stored in the mapping table. Moreover, ROM 1360 can be controlled by processor 1310.

[0078] The host interface 1370 may include protocols for exchanging data between the host 2000 and the memory controller 1300. Specifically, the host interface 1370 may communicate with the host 2000 through at least one of a variety of communication interfaces or protocols, such as: Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, High Speed ​​PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Electronic Integrated Drive (IDE) protocol, and proprietary protocols.

[0079] The memory interface 1380 can communicate with the memory device 100 under the control of the processor 1310 using a communication protocol. Specifically, the memory interface 1380 can communicate commands, addresses, and data with the memory device 100 through channels. For example, the memory interface 1380 may include a NAND interface.

[0080] Figure 8 This is a diagram illustrating a memory card system according to an embodiment of the present disclosure.

[0081] Reference Figure 8 The memory card system 3000 includes a memory controller 3100, a memory device 3200, and a connector 3300.

[0082] The memory controller 3100 can be connected to the memory device 3200. The memory controller 3100 can access the memory device 3200. For example, the memory controller 3100 can control read operations, write operations, erase operations, and background operations on the memory device 3200. The memory controller 3100 can provide an interface between the memory device 3200 and the host computer. Furthermore, the memory controller 3100 can drive the firmware used to control the memory device 3200.

[0083] For example, memory controller 3100 may include components such as random access memory (RAM), processing unit, host interface, memory interface, and error corrector.

[0084] The memory controller 3100 can communicate with external devices via connector 3300. The memory controller 3100 can communicate with external devices (e.g., a host) according to a specific communication protocol. The memory controller 3100 can communicate with external devices via at least one of a variety of communication standards or interfaces, such as: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), WiFi, Bluetooth, and NVMe.

[0085] The memory device 3200 can be implemented using various non-volatile memory devices such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-transfer torque magnetic RAM (STT-MRAM).

[0086] The memory controller 3100 and memory device 3200 can be integrated into a single semiconductor device to form a memory card. For example, the memory controller 3100 and memory device 3200 can form memory cards such as PC cards (Personal Computer Memory Card International Association (PCMCIA)), compact flash memory (CF) cards, smart media cards (SM and SMC), memory sticks, multimedia cards (MMC, RS-MMC, micro MMC and eMMC), SD cards (SD, mini SD, micro SD and SDHC) and universal flash memory (UFS).

[0087] Figure 9 This is a diagram illustrating a solid-state drive (SSD) system according to an embodiment of the present disclosure.

[0088] Reference Figure 9 The SSD system 4000 includes a host 4100 and an SSD 4200. The SSD 4200 exchanges signals SIG with the host 4100 through a signal connector 4001 and receives power PWR through a power connector 4002. The SSD 4200 includes an SSD controller 4210, multiple flash memory or non-volatile memory (NVM) 4221 to 422n, an auxiliary power supply 4230, and a cache memory 4240.

[0089] In this embodiment, the SSD controller 4210 can be used as a reference. Figure 1The memory controller 200 is described. The SSD controller 4210 can control multiple flash memories 4221 to 422n in response to a signal SIG received from the host 4100. The signal SIG can be a signal based on the interface between the host 4100 and the SSD 4200. For example, the signal SIG can be a signal defined by at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe.

[0090] Auxiliary power supply 4230 can be connected to host 4100 via power connector 4002. Auxiliary power supply 4230 can receive power PWR from host 4100 and can use the power PWR for charging. When the power supply from host 4100 is unstable, auxiliary power supply 4230 can provide power to SSD 4200. Auxiliary power supply 4230 can be located inside or outside SSD 4200. For example, auxiliary power supply 4230 can be located on the motherboard and provide auxiliary power to SSD 4200.

[0091] Buffer memory 4240 can operate as a buffer memory for SSD 4200. For example, buffer memory 4240 can temporarily store data received from host 4100 or data received from multiple flash memories 4221 to 422n, or temporarily store metadata (e.g., mapping tables) of flash memories 4221 to 422n. Buffer memory 4240 can include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0092] Figure 10 This is a diagram illustrating a user system according to an embodiment of the present disclosure.

[0093] Reference Figure 10 The user system 5000 includes an application processor 5100, a memory module 5200, a network module 5300, a storage module 5400, and a user interface 5500.

[0094] Application processor 5100 can drive components, operating system (OS), user programs, etc., included in user system 5000. Application processor 5100 may include controllers, interfaces, graphics engines, etc., for controlling components included in user system 5000. Application processor 5100 can be configured as a system-on-a-chip (SoC).

[0095] Memory module 5200 can operate as main memory, working memory, buffer memory, or cache memory of user system 5000. Memory module 5200 may include volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. Application processor 5100 and memory module 5200 can be configured as a single semiconductor package via a PoP-based package.

[0096] Network module 5300 can communicate with external devices. Network module 5300 can support wireless communications such as: Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi. Network module 5300 can be included in application processor 5100.

[0097] Storage module 5400 can store data. For example, storage module 5400 can store data received from application processor 5100. Optionally, storage module 5400 can transfer data stored in storage module 5400 to application processor 5100. Storage module 5400 can be implemented using non-volatile semiconductor memory devices such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, or NAND flash memory with a three-dimensional structure. Storage module 5400 can be configured as a memory card of user system 5000 or a removable drive of an external drive.

[0098] The storage module 5400 may include multiple non-volatile memory devices, and the multiple non-volatile memory devices may be used in conjunction with a reference. Figure 1 The memory device 100 described operates in the same manner. The memory module 4400 can be compared with the referenced... Figure 1 The storage device 1000 described operates in the same manner.

[0099] User interface 5500 may include interfaces for inputting data or commands to application processor 5100 or outputting data to external devices. User interface 5500 may include user input interfaces such as: keyboard, keypad, buttons, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric element. User interface 5500 may include user output interfaces such as: liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active-matrix OLED (AMOLED) display device, LED, speaker, and monitor.

[0100] According to this disclosure, a storage device for managing an improved multi-level cache memory and a method of operating the storage device can be provided.

[0101] While this disclosure has been shown and described with reference to specific embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the embodiments described above, but rather should be defined not only by the appended claims but also by their equivalents.

[0102] In the above embodiments, all operations may be selectively performed or some operations may be omitted. In each embodiment, the operations are not necessarily performed in the described order and may be rearranged. The embodiments disclosed in this specification and drawings are merely examples to facilitate understanding of this disclosure, and this disclosure is not limited thereto. That is, it will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure.

[0103] Embodiments of this disclosure have been described in the accompanying drawings and specification. While specific terminology is used herein, it is for the purpose of describing embodiments of this disclosure only. Therefore, this disclosure is not limited to the embodiments described above, and many variations can exist within the spirit and scope of this disclosure. It will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure in addition to the embodiments disclosed herein and the appended claims. Furthermore, embodiments can be combined to form additional embodiments.

Claims

1. A storage device, comprising: A memory device comprising multiple pages; A cache memory device includes a first cache memory and a second cache memory, wherein the first cache memory caches first data among the data stored in the plurality of pages, and the second cache memory caches second data among the data stored in the plurality of pages; as well as Memory controller: The number of times each of the plurality of pages is read and the number of times each of the plurality of pages is written are counted based on the read or write requests received from the host. When the first data is stored in the first page among the plurality of pages and the number of times the first page is read and the number of times the first page is written meet predetermined conditions, the first data is moved from the first cache memory to the second cache memory. The predetermined conditions are that the number of times the first page is read is equal to or greater than a threshold and the number of times the first page is written is once.

2. The storage device according to claim 1, wherein the memory controller comprises: A counter is used to count the number of times each of the plurality of pages is read and the number of times each of the plurality of pages is written, based on the read request or the write request received from the host. as well as The register stores the number of times each of the plurality of pages has been read and the number of times each of the plurality of pages has been written.

3. The storage device of claim 2, wherein the memory controller further periodically initializes the number of times the first page is read and the number of times the first page is written.

4. The storage device of claim 2, wherein the memory controller further moves the first data from the second cache memory back to the first cache memory when the first page is written two or more times.

5. The storage device of claim 4, wherein the memory controller further initializes the number of times the first page was read and the number of times the first page was written after moving the first data from the second cache memory back to the first cache memory.

6. The storage device of claim 1, wherein when a write request is provided for third data replacing the second data, the memory controller further removes the second data from the second cache memory and caches the third data in the first cache memory.

7. The storage device of claim 1, wherein upon receiving a read request for the second data from the host, the memory controller further controls the second cache memory to transfer the second data from the second cache memory to the host.

8. The storage device of claim 1, wherein the first cache memory and the second cache memory correspond to exclusive caches in which no data shared by the first cache memory and the second cache memory exists.

9. The storage device of claim 1, wherein the first cache memory operates at a first speed, and the second cache memory operates at a second speed slower than the first speed.

10. The storage device according to claim 1, wherein the first cache memory is dynamic random access memory (DRAM) and the second cache memory is persistent memory (PM).

11. A method of operating a storage device, the storage device comprising a first cache memory and a second cache memory, the method comprising: The first data among the data stored in the plurality of pages included in the memory device is stored in the first cache memory, and the second data among the data stored in the plurality of pages included in the memory device is stored in the second cache memory; When a read request or write request is received from the host, the number of times the page corresponding to the read request or the write request is read or the number of times the page is written is counted. and When the first data is stored in the first page among the plurality of pages and the number of times the first page is read and the number of times the first page is written meet predetermined conditions, the first data is moved from the first cache memory to the second cache memory. The predetermined conditions are that the number of times the first page is read is equal to or greater than a threshold and the number of times the first page is written is once.

12. The method of claim 11, further comprising: The system stores the number of times each of the plurality of pages was read and the number of times each of the plurality of pages was written.

13. The method of claim 11, further comprising: The number of times the first page is read and the number of times the first page is written are periodically initialized.

14. The method of claim 11, further comprising: When a write request is made for third data that replaces the second data: The second data is moved out of the second cache memory, and The third data is stored in the first cache memory.

15. The method of claim 11, further comprising: When a read request for the second data is received from the host, the second data is transferred from the second cache memory to the host.

16. The method of claim 11, wherein the first cache memory and the second cache memory correspond to exclusive caches in which no data shared by the first cache memory and the second cache memory exists.

17. The method of claim 11, wherein the first cache memory operates at a first speed, and the second cache memory operates at a second speed slower than the first speed.

18. A method of operating a controller, the method comprising: In response to a first request for accessing page data stored or to be stored in a page within a memory device, the page data is cached in a first cache; When at least a portion of the cached data is read an equal number of times equal to or greater than a threshold and said portion is written an only number of times, said portion is moved to the second cache. as well as In response to a second request for accessing the page data, the cached data is provided from one of the first cache and the second cache.

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