Memory system and control method

Abstract

An embodiment of the present invention addresses the problem of providing a memory system and a control method capable of efficiently utilizing each block included in a nonvolatile memory. A controller configures a plurality of block groups. The plurality of block groups includes at least a first block group configured using a first type block group and a second block group configured using a second type block group. The first type block group includes a plurality of non-defective blocks obtained by selecting the same number of non-defective blocks more than one from a plurality of dies or planes, respectively. The second type block group includes the same number of non-defective blocks as those included in the first type block group. The number of non-defective blocks included in each die or each plane of the second type block group differs among the plurality of dies or planes.

Description

[0001] Related applications

[0002] This application is based on and claims priority to Japanese Patent Application No. 2021-102382 (filed on June 21, 2021). The entire contents of the basic application are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to a memory system having non-volatile memory and techniques for controlling non-volatile memory. Background Technology

[0004] In recent years, memory systems with non-volatile memory have become widely used. As one type of such memory system, solid-state drives (SSDs) with NAND flash memory are known.

[0005] In memory systems such as SSDs, multiple blocks (multiple physical blocks) selected from different dies are used as access units for writing or reading data. In this case, when there is a large discrepancy in the number of defective blocks among the dies in the memory system, the number of blocks that are not actually defective, even if they are not defective, can increase.

[0006] Therefore, in memory systems, there is a need for new technologies that can efficiently utilize the individual blocks contained in non-volatile memory. Summary of the Invention

[0007] One embodiment of the present invention aims to provide a memory system and control method that can efficiently utilize the individual blocks contained in a non-volatile memory.

[0008] According to one embodiment, a memory system capable of connecting to a host includes: a non-volatile memory comprising a plurality of dies or a plurality of planes capable of operating in parallel; and a controller configured to be electrically connected to the non-volatile memory and to control the non-volatile memory. Each of the plurality of dies or the plurality of planes comprises a plurality of blocks. Each of the plurality of blocks is a unit for data deletion operations. The controller constructs a plurality of block groups, each comprising a plurality of blocks, from the plurality of dies or the plurality of planes. In response to a write instruction received from the host for writing data to one of the block groups, the controller writes data associated with the received write instruction to the one block group. The plurality of block groups at least includes a first block group constructed using a first type of block group and a second block group constructed using a second type of block group. The first type of block group includes a plurality of non-defective blocks obtained by selecting one or more equal numbers of non-defective blocks from each of the plurality of dies or the plurality of planes. The second type of block group includes a plurality of non-defective blocks selected from the plurality of dies or the plurality of planes, the same number as the plurality of non-defective blocks included in the first type of block group, and the number of non-defective blocks for each die or each plane included in the second type of block group is different among the plurality of dies or the plurality of planes. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating an example configuration of an information processing system including a memory system and a host in relation to an implementation method.

[0010] Figure 2 This is a block diagram illustrating an example of the relationship between multiple channels and multiple NAND flash memory dies used in a memory system according to a relevant implementation.

[0011] Figure 3 This is a block diagram illustrating another example of the relationship between multiple channels and multiple NAND flash memory dies used in a memory system according to an embodiment.

[0012] Figure 4 This is a diagram illustrating an example of the structure of a partition namespace as defined by the NVMe standard.

[0013] Figure 5 This is a diagram illustrating the update operation of the write indicator performed in a memory system according to a relevant implementation.

[0014] Figure 6 This is a diagram illustrating a first configuration example of multiple block groups managed in a memory system according to a relevant implementation.

[0015] Figure 7 This is a diagram illustrating a second configuration example of multiple block groups managed in a memory system according to a relevant implementation.

[0016] Figure 8 This is a diagram illustrating a third configuration example of multiple block groups managed in a memory system according to a relevant implementation.

[0017] Figure 9 This is a diagram illustrating a fourth configuration example of multiple block groups managed in a memory system according to a relevant implementation.

[0018] Figure 10 This is a diagram illustrating a fifth configuration example of multiple block groups managed in a memory system according to a relevant implementation.

[0019] Figure 11 This diagram illustrates an example of multiple block groups constructed in a memory system according to a relevant embodiment when the difference in the number of defective blocks between the plane with the fewest defective blocks and the plane with the most defective blocks is less than 1, and an example of multiple block groups constructed in a memory system according to a relevant embodiment when the difference in the number of defective blocks is 2 or more.

[0020] Figure 12 This is a block diagram illustrating an example of the order of write operations and the order of read operations performed in a memory system according to a relevant implementation.

[0021] Figure 13 It is a flowchart showing the sequence of block group construction operations performed in a memory system of a relevant implementation.

[0022] Figure 14 It is a flowchart showing the sequence of block group allocation operations performed in the memory system of the relevant implementation.

[0023] Figure 15 This is a flowchart illustrating the sequence of access speed notification actions performed in a memory system according to a relevant implementation.

[0024] Figure 16 It is a flowchart showing the sequence of data write operations performed in a memory system according to a relevant implementation.

[0025] Figure 17 This is a flowchart illustrating the sequence of data readout operations performed in a memory system according to a relevant implementation.

[0026] Label Explanation

[0027] 2…Host; 3…SSD; 4…Controller; 5…NAND flash memory; 21…Flash memory management unit; SB0~SB7…Superblock (block group). Detailed Implementation

[0028] The embodiments will now be described with reference to the accompanying drawings.

[0029] First, an example of the configuration of an information processing system including a memory system in the relevant implementation will be described. Figure 1 This is a block diagram illustrating an example configuration of an information processing system 1, which includes a memory system and a host, according to an embodiment. Hereinafter, we assume the memory system is implemented as a solid-state drive (SSD) 3 containing NAND flash memory.

[0030] Information processing system 1 includes a host (host device) 2 and an SSD 3. The SSD 3 is a semiconductor memory device configured to write data to and read data from non-volatile memory. The SSD 3 is connected to the host 2 via a cable or network. Alternatively, the SSD 3 may be integrated into the host 2. A standard for the logical interface connecting the host 2 and the SSD 3 can be, for example, NVM Express. TM (NVMe TM standard).

[0031] The host 2 includes a processor 101 and a memory 102. The processor 101 is a CPU (Central Processing Unit) configured to control the operation of various parts within the host 2.

[0032] Processor 101 executes software (host software) installed in memory 102 from SSD 3 or other storage devices within host 2. The host software includes an operating system, file system, device drivers, application programs, etc.

[0033] Memory 102 is the main memory located in host 2. Memory 102 is implemented, for example, by random access memory such as DRAM (Dynamic Random Access Memory).

[0034] A portion of the storage area of ​​memory 102 is used to store one or more subtask queue / completion queue pairs (SQ / CQ pairs). Each SQ / CQ pair contains one or more subtask queues (SQ) and a completion queue (CQ) associated with those subtask queues (SQ).

[0035] The Subtask Queue (SQ) is used to issue instructions to the SSD3. The Completion Queue (CQ) is used to receive responses from the SSD3 indicating that instructions have been completed.

[0036] Host 2 sends various instructions to SSD3 via one or more subtask queues (SQs) contained in each SQ / CQ pair.

[0037] The SSD3 features a controller 4 and non-volatile memory (such as NAND flash memory 5). The SSD3 may also feature random access memory, such as DRAM 6.

[0038] NAND flash memory 5 includes a memory cell array, which contains multiple memory cells arranged in a matrix. NAND flash memory 5 can be either two-dimensional or three-dimensional.

[0039] The storage cell array comprises multiple blocks BLK0 to BLKx-1. Each block BLK0 to BLKx-1 contains multiple pages (here, pages P0 to Py-1). Each page contains multiple storage cells connected to the same word line. Blocks BLK0 to BLKx-1 are the units for data deletion operations. Blocks BLK0 to BLKx-1 are also referred to as physical blocks or flash memory blocks. Pages P0 to Py-1 are the units for data write operations and data read operations, respectively.

[0040] NAND flash memory 5 Figure 2 The diagram shows multiple dies (NAND flash memory dies, or NAND flash memory chips). Each die, or NAND flash memory die, can operate independently. Therefore, multiple NAND flash memory dies are used as units capable of operating in parallel.

[0041] exist Figure 2 The example illustrates a scenario where sixteen channels Ch.1 to Ch.16 are connected to NAND interface 13, and one NAND flash memory die is connected to each of the sixteen channels Ch.1 to Ch.16. In this case, data write / read operations can be performed in parallel on the sixteen NAND flash memory dies #0 to #15 connected to channels Ch.1 to Ch.16.

[0042] Alternatively, NAND flash memory dies #0 to #15 may each have a multi-plane structure containing multiple planes capable of parallel operation. Each plane contains multiple blocks (physical blocks). For example, NAND flash memory dies #0 to #15 may each have the following... Figure 3 The diagram shows a multiplanar structure containing two planes (PLANE0, PLANE1). Figure 3 Among the NAND flash memory dies #0 to #15 shown, data write / read operations for the first plane (PLANE0) and data write / read operations for the second plane (PLANE1) can be performed in parallel. Figure 3 The structure shown can perform data write / read operations on the thirty-two planes contained in the NAND flash memory 5 in parallel.

[0043] Figure 1The controller 4 shown is implemented using circuitry similar to that of a System-on-a-chip (SoC).

[0044] The controller 4 is electrically connected to the NAND flash memory 5 (i.e., NAND flash memory #0 to #15) via the NAND interface 13, which is based on the Toggle NAND flash memory interface or the Open NAND flash memory interface (ONFI). The controller 4 operates as a memory controller configured to control the NAND flash memory 5.

[0045] The controller 4 controls the NAND flash memory 5 (i.e., NAND flash memory #0 to #15) to perform data writing operations that write data received from the host 2 into the NAND flash memory 5, and data reading operations that read data requested by the host 2 from the NAND flash memory 5.

[0046] The controller 4 constructs multiple block groups, each containing multiple blocks (multiple physical blocks), from multiple dies or multiple planes within the NAND flash memory 5 that can operate in parallel. The controller 4 manages these multiple block groups as multiple physical storage areas accessible to the host 2.

[0047] Multiple block groups (i.e. multiple physical storage areas) are used so that host 2 and controller 4 can jointly manage the data configuration on NAND flash memory 5.

[0048] For example, when the controller 4 receives a write instruction from the host 2 to write data to a certain block group, it designates that block group as the write location block group and writes the data associated with the received write instruction to that write location block group. Similarly, when the controller 4 receives a write instruction from the host 2 to write data to another block group, it designates that other block group as the write location block group and writes the data associated with the received write instruction to that write location block group.

[0049] As a write instruction for writing data to any block group, a write instruction containing parameters that specify an identifier for the block group to be written to can be used. In this case, the controller 4 will determine the block group to be written to based on the block group specified by the received write instruction.

[0050] Alternatively, as a write command for writing data to any block group, it is also possible to use write commands that are used in Zoned Namespaces (ZNS) as defined by the NVMe standard.

[0051] When controller 4 supports ZNS, controller 4 enables SSD3 to operate as a zoned device. In a zoned device, multiple regions, each consisting of a logical address range divided by the logical address space used to access SSD3, are allocated and used as logical storage areas.

[0052] The logical address space used to access SSD3 is a contiguous logical address space used by host 2 to access SSD3. Logical block addresses (LBAs) are used as logical addresses.

[0053] The multiple block groups managed by controller 4 are used as multiple physical storage areas that can be allocated to these multiple areas respectively.

[0054] The following mainly explains the controller 4's support for ZNS as a write command for writing data to any block group, using the write commands used in ZNS as specified in the NVMe standard, i.e., the write commands for a specified area.

[0055] Figure 4 This is a diagram illustrating an example of the structure of a partition namespace as defined by the NVMe standard.

[0056] The logical block address range of each partition namespace starts from LBA 0. For example, Figure 4 The logical block address range of the partition namespace comprises z consecutive LBAs from LBA 0 to LBA z-1. This partition namespace is divided into k+1 regions from region #0 to region #k. These k+1 regions contain consecutive, non-repeating logical block addresses.

[0057] More specifically, the partition namespace is assigned regions #0, #1, ..., #k. LBA 0 represents the smallest LBA in region #0. LBA z-1 represents the largest LBA in region #k. Region #1 contains LBA m, LBA m+1, ..., LBAn-2, LBA n-1. LBA m represents the smallest LBA in region #1. LBA n-1 represents the largest LBA in region #1.

[0058] Controller 4 allocates one block group from multiple block groups as a physical storage area to multiple regions, thereby managing the mapping between each block group in the multiple block groups and each region in the multiple regions.

[0059] Upon receiving a write command specifying a certain area from host 2, controller 4 determines the block group allocated to the area specified by the received write command as the write location block group. Furthermore, controller 4 writes the data associated with the received write command to the block group determined as the write location block group.

[0060] The next writable LBA value in each region is managed by the write indicator corresponding to each region. Figure 5 This is a diagram showing the update action of the write indicator performed in SSD3.

[0061] Controller 4 manages multiple write indicators corresponding to multiple regions. Each write indicator indicates the next writable LBA within its corresponding region. When continuously writing data to a region, controller 4 increments the value of the write indicator corresponding to that region by the number of logical blocks of data written.

[0062] Here, taking region #1 as an example, the update operation of the write indicator is explained. Region #1 contains a logical block address range from LBA m to LBA n-1. LBA m is the smallest logical block address of region #1, that is, the region start logical block address (ZSLBA) of region #1.

[0063] When region #1 is in a free state without valid data, the write indicator for region #1 shows the starting logical block address of region #1, i.e., LBAm. Upon receiving a command from host 2 to open region #1, controller 4 puts region #1 into an open state where data can be written. In this case, controller 4 performs a deletion operation on a block group (free block group) in the free state without valid data, and allocates this block group as a physical storage area associated with the open state of region #1. Thus, writing to region #1 becomes possible.

[0064] If the write location (starting LBA) specified by the write instruction of designated region #1 is the same as the write indicator (here, LBAm) of region #1, the controller 4 writes data to the range of LBAs starting from the specified starting LBA, such as LBAm and LBA m+1.

[0065] Controller 4 updates the write indicator for region #1 by incrementing the value of the write indicator for region #1 by the number of logical blocks on which data has been written. For example, if data has been written to LBA m and LBA m+1, controller 4 updates the write indicator value to LBA m+2. LBA m+2 represents the smallest unwritten LBA in region #1, i.e., the next writable LBA in region #1.

[0066] If data is written again within an LBA range in region #1 where data has already been written, region #1 needs to be reset so that the write indicator value returns to LBA m, and region #1 needs to be reopened.

[0067] When region #1 is reset, controller 4 can treat the block group allocated to the physical storage area used as region #1 as a free block group that does not contain valid data. Therefore, by simply deleting the block group, it can be reused for writing data.

[0068] Return to Figure 1 The controller 4 functions as a flash translation layer (FTL) that performs data management and block management of the NAND flash memory 5. The data management performed by this FTL includes (1) the management of mapping information that represents the correspondence between each logical address and each physical address of the NAND flash memory 5, and (2) the processing of hiding the limitations of the NAND flash memory 5 (such as page unit read / write operations and block unit delete operations).

[0069] In this embodiment, writes are performed continuously within each region, so the controller 4 can also use the region / block group allocation management table 31 to manage only the correspondence between the starting LBA of each region and the block group allocated to each region.

[0070] Block management includes the management of bad blocks. A bad block is a block that cannot be read or written normally.

[0071] During the manufacturing process of NAND flash memory dies #0 to #15, defective blocks may occur in each NAND flash memory die. The controller 4 uses a defective block management table 32 to manage the defective blocks contained in each NAND flash memory die (or each plane of each NAND flash memory die). Furthermore, the controller 4 considers the defective blocks contained in NAND flash memory dies #0 to #15 and constructs multiple block groups. The defective block management table 32 stores defect information representing the defective blocks contained in each NAND flash memory die (or each plane).

[0072] Furthermore, the defective blocks managed in the defective block management table 32 can include only defective blocks generated during the manufacturing process of NAND flash memory dies #0 to #15 (initial defective blocks), or they can include both initial defective blocks and defective blocks generated after the SSD3 begins use (fragmented defective blocks). Information on each defective block generated during the manufacturing process of NAND flash memory dies #0 to #15 can also be installed in the defective block management table 32 from the NAND flash memory 5.

[0073] In addition to the NAND interface 13 mentioned above, controller 4 also includes a host interface 11, a CPU 12, a DRAM interface 14, a direct memory access controller (DMAC) 15, static RAM (SRAM) 16, and an ECC (Error Correction Code) encoder / decoder 17. These host interface 11, CPU 12, NAND interface 13, DRAM interface 14, DMAC 15, SRAM 16, and ECC encoder / decoder 17 are interconnected via bus 10.

[0074] Host interface 11 is a host interface circuit configured to perform communication with host 2. Host interface 11 is, for example, a PCIe controller. Alternatively, if SSD 3 has a built-in network interface controller, host interface 11 can also be implemented as part of the network interface controller.

[0075] Host interface 11 can communicate with host 2 according to the NVMe standard. Host interface 11 receives (acquires) various commands from host 2. These commands include write commands, read commands, open region commands, close region commands, reset region commands, etc.

[0076] A write instruction is an instruction (write request) that writes the data to be written (write data) to the NAND flash memory 5. A write instruction may include, for example, the logical address (start LBA) of the initial sector to which the write data should be written, the size of the write data, and a data indicator (buffer address) indicating the location within the write buffer of the host 2 where the write data is stored. The write buffer of the host 2 refers to a storage area set up within the memory 102 of the host 2.

[0077] For example, the high-order bits of the logical address (start LBA) contained in the write instruction are used as an identifier, i.e., the ZSLBA of the region where the write data associated with the write instruction should be written. Conversely, the low-order bits of the logical address (start LBA) contained in the write instruction are used as the write location LBA (offset) within the region where the write data should be written.

[0078] Therefore, the logical address specified by the write instruction indicates one of multiple regions and the offset within that region where the write data should be written. Alternatively, a region append instruction specifying only the ZSLBA can also be used as a write instruction. In this case, the write location LBA (offset) within the region is determined by controller 4 in such a manner that writes within that region are executed sequentially.

[0079] The size of the data to be written can also be specified using the number of sectors (logical blocks). One sector corresponds to the minimum size of data that can be written via host 2. That is, the size of the data to be written is expressed as a multiple of the number of sectors.

[0080] A read instruction is an instruction (read request) to read data from NAND flash memory 5. The read instruction includes the logical address (start LBA) of the initial sector from which the data (read target data) should be read, the data size of the read target data, and a data indicator (buffer address) indicating the position of the read target data within the read buffer of host 2. The read buffer of host 2 refers to the storage area set up within the memory 102 of host 2.

[0081] The high-order bits of the logical address contained in the read instruction are used as an identifier to specify the region where the data to be read is stored. Conversely, the low-order bits of the logical address contained in the read instruction specify the offset within the region where the data to be read is stored.

[0082] An open region command is an instruction (open request) used to bring one of several regions in an idle state into an open state that can be used for data writing. In other words, an open region command is used to bring a specific block group in an idle state that does not contain valid data into an open state that can be used for data writing.

[0083] The open region instruction contains the logical address of the region that should be opened. For example, the high-order bits of the logical address specified by the open region instruction are used as an identifier for the region that should be opened.

[0084] A close region instruction is used to bring a region in an open state into a closed state (close request) after a write interruption. The close region instruction contains the logical address of the region that should be brought into the closed state. For example, the high-order bits of the logical address specified by the close region instruction are used as an identifier for the region that should be brought into the closed state.

[0085] A reset region instruction is used to reset a region that should be overwritten to an idle state (reset request). For example, a reset region instruction is used to move a full region that is filled with data into an idle state that does not contain valid data. Valid data refers to data associated with a logical address. The reset region instruction contains the logical address of the region that should enter the idle state. For example, the high-order bits of the logical address specified by the reset region instruction are used as an identifier for the region that should enter the idle state. The write indicator value corresponding to the region that has entered the idle state according to the reset region instruction is set to the ZSLBA value representing that region.

[0086] CPU12 is a processor configured with a host control interface 11, a NAND interface 13, a DRAM interface 14, a DMAC 15, an SRAM 16, and an ECC encoding / decoding unit 17.

[0087] In response to the power-on of the SSD3, the CPU12 installs the control program (firmware) from the NAND flash memory 5 or a ROM (not shown) onto the DRAM6, and executes the firmware to perform various processes. Alternatively, the firmware can also be installed on the SRAM16.

[0088] CPU 12 is capable of performing instruction processing and other tasks to handle various instructions from host 2. The operation of CPU 12 is controlled by the aforementioned firmware. Alternatively, some or all of the instruction processing can be performed by dedicated hardware within controller 4.

[0089] CPU12 can function as the flash memory management unit 21. Alternatively, part or all of the flash memory management unit 21 can be implemented using dedicated hardware within the controller 4.

[0090] The flash memory management unit 21 constructs multiple block groups from multiple dies or planes contained in the NAND flash memory 5, each containing multiple non-defective blocks, and manages these multiple block groups as multiple physical storage areas accessible to the host 2. Here, a non-defective block refers to a block that is not faulty. The number of dies or planes used to construct each block group is two or more.

[0091] In this embodiment, two types of block groups can be used to construct multiple block groups: a first type of block group and a second type of block group. That is, the multiple block groups managed by the flash memory management unit 21 include at least a first block group composed of the first type of block group and a second block group composed of the second type of block group.

[0092] The first type of block group includes multiple non-defective blocks obtained by selecting one or more non-defective blocks of the same number from multiple dies or multiple planes contained in the NAND flash memory 5.

[0093] The second type of block group contains the same number of non-defective blocks selected from multiple dies or planes contained in the NAND flash memory 5, as the number of non-defective blocks contained in the first type of block group. The number of non-defective blocks in each die or plane contained in the second type of block group is not the same, and varies among multiple dies or planes.

[0094] The difference between the maximum number of non-defective blocks per die or plane in the second type block group and the minimum number of non-defective blocks per die or plane in the second type block group is greater than 2. For example, the second type block group contains two or more non-defective blocks selected from the die or plane with the fewest number of defective blocks among multiple dies or planes, and does not include non-defective blocks from the die or plane with the most defective blocks among multiple dies or planes.

[0095] Here, several examples of the construction of the first type of block group and the second type of block group are explained.

[0096] In this embodiment, in order to ensure that the capacity of the multiple physical storage regions that the host 2 can access is the same, the number of non-bad blocks contained in each of the multiple block groups is set to be the same.

[0097] Multiple block groups can, for example, consist of multiple first-type block groups and one or more second-type block groups. The number of non-bad blocks contained in each of the multiple second-type block groups is the same as the number of non-bad blocks contained in each of the multiple first-type block groups.

[0098] Multiple first-type block groups are formed, for example, by using two or more non-volatile memory dies from NAND flash memory dies #0 to #15 in the SSD3.

[0099] In this case, the flash memory management unit 21 constructs multiple first-type block groups, each containing multiple non-defective blocks obtained by selecting one or more non-defective blocks from two or more non-volatile memory dies. For example, if each first-type block group consists of two blocks, each first-type block group contains a total of two non-defective blocks selected from each of the two non-volatile memory dies. Alternatively, if each first-type block group consists of four blocks, each first-type block group contains a total of four non-defective blocks selected from each of the four non-volatile memory dies.

[0100] Alternatively, each of the multiple first-type block groups may consist of a set of two non-defective blocks selected from two or more non-volatile memory dies (#0 to #15) of the NAND flash memory dies mounted on the SSD3. For example, if each first-type block group consists of four blocks, each first-type block group contains a total of four non-defective blocks selected from two non-volatile memory dies.

[0101] Thus, multiple groups of first-type blocks each contain one or more identical non-bad blocks selected from two or more non-volatile memory dies.

[0102] One or more second-type block groups are also constructed using two or more non-volatile memory dies used in the construction of multiple first-type block groups. The flash memory management unit 21 constructs one or more second-type block groups, each containing multiple non-defective blocks obtained by selecting different numbers of non-defective blocks from two or more non-volatile memory dies.

[0103] In this case, one or more second-type block groups each contain two or more non-defective blocks selected from the non-volatile memory die with the fewest number of defective blocks among these two or more non-volatile memory dies, and do not contain non-defective blocks from the non-volatile memory die with the most defective blocks among these two or more non-volatile memory dies.

[0104] For example, when each second type block group consists of two blocks, each second type block group contains only two non-defective blocks selected from the non-volatile memory die of the party with fewer defective blocks, and does not contain non-defective blocks from the non-volatile memory die of the party with more defective blocks.

[0105] If multiple block groups are constructed using only the first type of block group, then given a significant variation in the number of defective blocks between non-volatile memory dies, the maximum number of block groups that can be constructed will be limited to the number of non-defective blocks contained in the non-volatile memory die with the most defective blocks. This results in an increase in the number of non-defective blocks, even those on non-volatile memory dies with fewer defective blocks, that are not actually used for block group construction. This could be a significant factor limiting the number of usable areas.

[0106] In this embodiment, not only is a first type of block group comprising multiple non-defective blocks obtained by selecting the same number of blocks from multiple non-volatile memory dies, but a second type of block group having the same capacity as the first type of block group and comprising multiple non-defective blocks obtained by selecting a different number of blocks from multiple non-volatile memory dies is also used in the construction of multiple block groups.

[0107] That is, multiple block groups are constructed using first-type block groups and second-type block groups.

[0108] In the construction of the second type of block group, more non-bad blocks are selected from the non-volatile memory die with fewer bad blocks.

[0109] Therefore, it is possible to maintain the same capacity for all block groups and efficiently utilize almost all non-defective blocks in the construction of multiple block groups. Thus, even when there is a large discrepancy in the number of defective blocks between non-volatile memory dies, almost all non-defective blocks contained in these non-volatile memory dies can be used for block group construction. As a result, the number of usable regions can be increased, and the capacity of these regions (region capacity) can be made the same. This reduces the burden associated with host 2's management of each region, maximizing the capacity of SSD 3.

[0110] Furthermore, when the NAND flash memory 5 in the SSD3 contains multiple planes, multiple first-type block groups can be constructed using two or more of these planes. Similarly, one or more second-type block groups can be constructed using two or more of these planes.

[0111] Furthermore, when multiple non-volatile memory dies (or planes) with a low number of defective blocks exist, in the construction of a certain second type of block group, the flash memory management unit 21 selects more non-defective blocks from the first non-volatile memory die (or the first plane with a low number of defective blocks). Similarly, in the construction of another second type of block group, the flash memory management unit 21 selects more non-defective blocks from the second non-volatile memory die (or the second plane with a low number of defective blocks). Thus, almost all the non-defective blocks contained in each of these non-volatile memory dies (or planes) with a low number of defective blocks can be used for the construction of the block group.

[0112] For example, consider a case where each block group consists of three or more non-defective blocks. Additionally, consider a case where the number of defective blocks in the first non-volatile memory die is two or more fewer than the number of defective blocks in the second non-volatile memory die, and the number of defective blocks in the third non-volatile memory die is two or more fewer than the number of defective blocks in the second non-volatile memory die.

[0113] In this case, multiple first-type block groups each contain one or more identical non-defective blocks selected from the first to third non-volatile memory dies.

[0114] One or more second-type block groups include block groups that select more blocks from a first non-volatile memory die and block groups that select more blocks from a third non-volatile memory die.

[0115] A block group that selects more blocks from the first non-volatile memory die includes two or more non-defective blocks selected from the first non-volatile memory die and one or more non-defective blocks selected from the third non-volatile memory die, but does not include non-defective blocks selected from the second non-volatile memory die.

[0116] A block group selected from a third non-volatile memory die includes one or more non-defective blocks selected from a first non-volatile memory die and two or more non-defective blocks selected from a third non-volatile memory die, but does not include non-defective blocks selected from a second non-volatile memory die.

[0117] Based on this configuration, almost all the defective blocks contained in the first to third non-volatile memory dies can be used for the construction of block groups.

[0118] In addition, when the difference between the number of defective blocks in the die or plane with the fewest defective blocks among the multiple dies or planes used to construct multiple block groups is 2 or more, the flash memory management unit 21 constructs multiple block groups using the first type block group and the second type block group.

[0119] When the difference between the number of defective blocks in the die or plane with the fewest defective blocks and the number of defective blocks in the die or plane with the most defective blocks is less than 1, the flash memory management unit 21 constructs multiple block groups using only the first type of block group.

[0120] In the following explanation, each block group is also referred to as a superblock.

[0121] NAND interface 13 is a memory control circuit configured to control NAND flash memory 5 under the control of CPU 12.

[0122] DRAM interface 14 is a DRAM control circuit configured to control DRAM 6 under the control of CPU 12. A portion of the storage area of ​​DRAM 6 can also be used as a storage area for storage area / block group allocation management table 31 and bad block management table 32.

[0123] Under the control of CPU 12, DMAC 15 performs data transfers between the host 2's memory 102 and internal buffer 161. A portion of the SRAM 15's storage area is used as the internal buffer 161. Additionally, a portion of the DRAM 5's storage area can also be used as the internal buffer 161. When write data needs to be transferred from the write buffer in the host 2's memory 102 to the internal buffer 161, CPU 12 specifies to DMAC 15 the source address indicating the location within the host 2's write buffer, the size of the write data to be transferred, and the location address indicating the location within the internal buffer 161.

[0124] When data should be written to the NAND flash memory 5, the ECC encoding / decoding unit 17 encodes the data (the data to be written) and adds error correction codes (ECC) to the data as redundant codes. When data is read from the NAND flash memory 5, the ECC encoding / decoding unit 17 uses the ECC attached to the read data to perform error correction (ECC decoding) on ​​the data.

[0125] Next, we will explain an example of the configuration of each block group that is allocated as a physical storage area in the region. Figure 6 This is a diagram illustrating a first configuration example of multiple block groups managed in an SSD3 according to a relevant implementation.

[0126] First, refer to Figure 6 The upper part explains the composition example of the block group for the comparative example. Here, we imagine a case where a block group allocated to a region contains two blocks. For example... Figure 6 As shown at the top, NAND flash memory die #0 and NAND flash memory die #1 each contain ten blocks BLK0 to BLK9. In NAND flash memory die #0, four of the ten blocks BLK0 to BLK9, BLK2 and BLK7 to BLK9, are defective blocks. On the other hand, in NAND flash memory die #1, there are no defective blocks, and all ten blocks BLK0 to BLK9 are non-defective blocks.

[0127] In the comparative example, multiple block groups (multiple superblocks SB) are always constructed using only the first type of block group. Therefore, the maximum number of superblocks SB that can be constructed is limited to the number of non-bad blocks contained in NAND flash memory die #0 (here, 6).

[0128] That is, superblocks SB0 to SB5 are each composed of two non-defective blocks selected from two NAND flash memory dies #0 to #1.

[0129] For example, super block SB0 consists of non-bad block BLK0 selected from NAND flash memory die #0 and non-bad block BLK0 selected from NAND flash memory die #1.

[0130] Superblock SB1 consists of non-defective block BLK1 selected from NAND flash memory die #0 and non-defective block BLK1 selected from NAND flash memory die #1.

[0131] Superblock SB2 consists of non-defective block BLK3 selected from NAND flash memory die #0 and non-defective block BLK3 selected from NAND flash memory die #1.

[0132] Superblock SB3 consists of non-defective block BLK4 selected from NAND flash memory die #0 and non-defective block BLK4 selected from NAND flash memory die #1.

[0133] Superblock SB4 consists of non-defective block BLK5 selected from NAND flash memory die #0 and non-defective block BLK5 selected from NAND flash memory die #1.

[0134] Superblock SB5 consists of non-defective block BLK6 selected from NAND flash memory die #0 and non-defective block BLK6 selected from NAND flash memory die #1.

[0135] When six superblocks SB0 to SB5 are built, the number of remaining non-defective blocks in NAND flash memory die #0 becomes zero. Therefore, four of the ten non-defective blocks (BLK0 to BLK9) in NAND flash memory die #1 (here, BLK2, BLK7 to BLK9) are not used for building superblocks SB. As a result, a capacity equivalent to four blocks is wasted.

[0136] It is also possible to construct four superblocks SB using four non-bad blocks (BLK2, BLK7~BLK9 in this case).

[0137] However, in this case, the capacity of each of the four superblocks (SB) is half the capacity of the other superblocks (SB). As a result, the capacities of multiple regions are inconsistent, making it difficult for host 2 to process multiple regions.

[0138] Next, refer to Figure 6 The following section describes an example of the block group configuration in this embodiment. In this embodiment, not only multiple first-type block groups are used, but also one or more second-type block groups are used to construct eight block groups (superblocks SB0 to SB7).

[0139] Superblocks SB0 to SB5 are the first type of block groups. Superblocks SB0 to SB5 are each composed of two non-defective blocks selected from each of the two NAND flash memory dies #0 to #1.

[0140] For example, super block SB0 consists of non-bad block BLK0 selected from NAND flash memory die #0 and non-bad block BLK0 selected from NAND flash memory die #1.

[0141] Superblock SB1 consists of non-defective block BLK1 selected from NAND flash memory die #0 and non-defective block BLK1 selected from NAND flash memory die #1.

[0142] Superblock SB2 consists of non-defective block BLK3 selected from NAND flash memory die #0 and non-defective block BLK2 selected from NAND flash memory die #1.

[0143] Superblock SB3 consists of non-defective block BLK4 selected from NAND flash memory die #0 and non-defective block BLK3 selected from NAND flash memory die #1.

[0144] Superblock SB4 consists of non-defective block BLK5 selected from NAND flash memory die #0 and non-defective block BLK4 selected from NAND flash memory die #1.

[0145] Superblock SB5 consists of non-defective block BLK6 selected from NAND flash memory die #0 and non-defective block BLK5 selected from NAND flash memory die #1.

[0146] Superblocks SB6 to SB7 are type II block groups. Each superblock SB6 to SB7 consists of two non-defective blocks selected from NAND flash memory die #1, which has a smaller number of defective blocks. None of the superblocks SB6 to SB7 contain non-defective blocks from NAND flash memory die #0, which has a larger number of defective blocks.

[0147] Within each superblock SB0 to SB5, the two blocks contained in each superblock SB belong to different NAND flash memory dies. Therefore, write or read operations on these two blocks can be performed in parallel.

[0148] On the other hand, within each superblock SB6 to SB7, the two blocks contained in each superblock SB belong to the same NAND flash memory die. Therefore, write or read operations on these two blocks cannot be performed in parallel.

[0149] Therefore, the time required to write data to a region allocated with superblock SB6 or SB7 is twice the time required to write data to a region allocated with any of the superblocks SB0 to SB5.

[0150] Similarly, the time required to read data from a region assigned to superblock SB6 or SB7 is twice the time required to read data from a region assigned to any of the superblocks SB0 to SB5.

[0151] Thus, the access speed of the second type of block group is half that of the first type of block group.

[0152] However, by using the second type of block group, even if there is a discrepancy in the number of defective blocks between NAND flash memory die #0 and NAND flash memory die #1, all (or almost all) of the non-defective blocks contained in NAND flash memory die #1 with fewer defective blocks can be used to construct the super block SB.

[0153] Hereinafter, the region assigned to the first type of block group will be called the full-speed region, and the region assigned to the second type of block group will be called the half-speed region. Furthermore, the first type of block group will be called the full-speed block group, and the second type of block group will be called the half-speed block group.

[0154] Figure 7 This is a diagram illustrating a second configuration example of multiple block groups managed in an SSD3 according to a relevant implementation.

[0155] First, refer to Figure 7 The upper part describes the configuration example of the block group for the comparative example. Here, we assume that the NAND flash memory die #0 contains two planes, and a block group allocated to a region contains two blocks. For example... Figure 7 As shown at the top, the first plane (PLANE0) and the second plane (PLANE1) within the NAND flash memory die #0 each contain ten blocks BLK0 to BLK9. In the first plane (PLANE0), four of the ten blocks BLK0 to BLK9, BLK2 and BLK7 to BLK9, are defective blocks. On the other hand, in the second plane (PLANE1), there are no defective blocks, and all ten blocks BLK0 to BLK9 are non-defective blocks.

[0156] In the comparative example, multiple block groups (multiple superblocks SB) are constructed using only the first type of block group. Therefore, the maximum number of superblocks SB that can be constructed is limited to the number of non-bad blocks contained in the first plane (PLANE0) (here, 6).

[0157] That is, superblocks SB0 to SB5 are each composed of two non-defective blocks selected from each of the two planes (PLANE0 to PLANE1). For example, superblock SB0 is composed of non-defective block BLK0 selected from the first plane (PLANE0) and non-defective block BLK0 selected from the second plane (PLANE1). Superblock SB1 is composed of non-defective block BLK1 selected from the first plane (PLANE0) and non-defective block BLK1 selected from the second plane (PLANE1). Superblock SB2 is composed of non-defective block BLK3 selected from the first plane (PLANE0) and non-defective block BLK3 selected from the second plane (PLANE1). Superblock SB3 is composed of non-defective block BLK4 selected from the first plane (PLANE0) and non-defective block BLK4 selected from the second plane (PLANE1). Superblock SB4 is composed of non-defective block BLK5 selected from the first plane (PLANE0) and non-defective block BLK5 selected from the second plane (PLANE1). Superblock SB5 is composed of non-bad block BLK6 selected from the first plane (PLANE0) and non-bad block BLK6 selected from the second plane (PLANE1).

[0158] When the six superblocks SB0–SB5 are constructed, the number of remaining non-bad blocks in the first plane (PLANE0) becomes zero. Therefore, four of the ten non-bad blocks (BLK0–BLK9) in the second plane (PLANE1) (here, BLK2, BLK7–BLK9) are not used in the construction of superblock SB. As a result, a capacity equivalent to four blocks is wasted.

[0159] Next, refer to Figure 7 The following section describes an example of the block group configuration in this embodiment. In this embodiment, not only multiple first-type block groups are used, but also one or more second-type block groups are used to construct eight block groups (superblocks SB0 to SB7).

[0160] Superblocks SB0 to SB5 are the first type of block groups. Superblocks SB0 to SB5 are each composed of two non-defective blocks selected from the first plane (PLANE0) and the second plane (PLANE1).

[0161] For example, superblock SB0 is composed of non-defective block BLK0 selected from the first plane (PLANE0) and non-defective block BLK0 selected from the second plane (PLANE1). Superblock SB1 is composed of non-defective block BLK1 selected from the first plane (PLANE0) and non-defective block BLK1 selected from the second plane (PLANE1). Superblock SB2 is composed of non-defective block BLK3 selected from the first plane (PLANE0) and non-defective block BLK2 selected from the second plane (PLANE1). Superblock SB3 is composed of non-defective block BLK4 selected from the first plane (PLANE0) and non-defective block BLK3 selected from the second plane (PLANE1). Superblock SB4 is composed of non-defective block BLK5 selected from the first plane (PLANE0) and non-defective block BLK4 selected from the second plane (PLANE1). Superblock SB5 is composed of non-bad block BLK6 selected from the first plane (PLANE0) and non-bad block BLK5 selected from the second plane (PLANE1).

[0162] Superblocks SB6 to SB7 are type II block groups. Each superblock SB6 to SB7 consists of two non-defective blocks selected from the second plane (PLANE1) with fewer defective blocks. Each superblock SB6 to SB7 does not contain any non-defective blocks from the first plane (PLANE0) with more defective blocks.

[0163] Within each superblock SB0 to SB5, the two blocks contained in each superblock SB belong to different planes. Therefore, write or read operations on these two blocks can be performed in parallel.

[0164] On the other hand, within each superblock SB6 to SB7, the two blocks contained in each superblock SB belong to the same plane. Therefore, write or read operations on these two blocks cannot be performed concurrently.

[0165] Thus, by using not only multiple first-type block groups but also more than one second-type block group, even if there is a large deviation in the number of bad blocks between the first plane (PLANE0) and the second plane (PLANE1), all (or almost all) of the non-bad blocks contained in the second plane (PLANE1) with fewer bad blocks can be used for the construction of the superblock SB.

[0166] Figure 8 This is a diagram illustrating a third configuration example of multiple block groups managed in an SSD3 according to a relevant implementation.

[0167] First, refer to Figure 8 The upper part explains the composition example of the block group for the comparative example. Here, we imagine a case where a block group allocated to a region contains four blocks. For example... Figure 8 As shown at the top, NAND flash memory dies #0 to #3 each contain ten blocks BLK0 to BLK9. NAND flash memory die #0 contains zero defective blocks. NAND flash memory die #1 also contains zero defective blocks. NAND flash memory die #2 contains 2 defective blocks. NAND flash memory die #3 contains 5 defective blocks.

[0168] In the comparative example, multiple block groups (multiple superblocks SB) are constructed using only the first type of block group. Therefore, the maximum number of superblocks SB that can be constructed is limited to the number of non-bad blocks contained in the NAND flash memory die #3, which has the most bad blocks (here, 5).

[0169] Five of the ten non-bad blocks (BLK0 to BLK9) within the NAND flash memory die #0 (BLK1 to BLK2 and BLK6 to BLK8 in this case) are not used to build the superblock SB. As a result, a capacity equivalent to five blocks is wasted.

[0170] In NAND flash memory die #1, the five non-bad blocks (BLK1~BLK2, BLK6~BLK8) are not used to build the superblock SB. As a result, a capacity equivalent to five blocks is wasted.

[0171] In NAND flash memory die #2, three non-bad blocks (BLK1, BLK6-BLK7) are not used to build the superblock SB. As a result, a capacity equivalent to three blocks is wasted.

[0172] Next, refer to Figure 8 The following section describes an example of the block group configuration in this embodiment. In this embodiment, not only multiple first-type block groups are used, but also one or more second-type block groups are used to construct eight block groups (superblocks SB0 to SB7).

[0173] Superblocks SB0, SB2-SB4, and SB7 are the first type of block groups. Superblocks SB0, SB2-SB4, and SB7 each consist of four non-defective blocks selected from each of the four NAND flash memory dies #0 to #3.

[0174] Superblocks SB1 and SB5-SB6 are the second type of block groups. Superblock SB1 contains two non-defective blocks BLK1-BLK2 selected from NAND flash memory die #0, one non-defective block BLK1 selected from NAND flash memory die #1, and one non-defective block BLK1 selected from NAND flash memory die #2. Superblock SB1 does not contain any non-defective blocks within NAND flash memory die #3.

[0175] In superblock SB1, write or read operations on one of the two non-defective blocks BLK1 to BLK2 within NAND flash memory die #0 can be performed concurrently with write or read operations on the other of the two non-defective blocks BLK1 within NAND flash memory dies #1 to #2. However, write or read operations on the other of the two non-defective blocks BLK1 to BLK2 within NAND flash memory die #0 cannot be performed concurrently. Therefore, the time required to write data to the area allocated to superblock SB1 is twice the time required to write data to the area allocated to any one of superblocks SB0, SB2 to SB4, or SB7. Consequently, the area allocated to superblock SB1 operates as a half-speed area.

[0176] Superblock SB5 contains two non-defective blocks BLK6-BLK7 selected from NAND flash memory die #0, one non-defective block BLK6 selected from NAND flash memory die #1, and one non-defective block BLK6 selected from NAND flash memory die #2. Superblock SB5 does not contain any non-defective blocks within NAND flash memory die #3. The area allocated to Superblock SB5 also operates as a half-speed area.

[0177] Superblock SB6 contains one non-defective block BLK8 selected from NAND flash memory die #0, two non-defective blocks BLK7 to BLK8 selected from NAND flash memory die #1, and one non-defective block BLK7 selected from NAND flash memory die #2. Superblock SB6 does not contain any non-defective blocks within NAND flash memory die #3.

[0178] In superblock SB6, write or read operations on one of the two non-defective blocks BLK7-BLK8 within NAND flash memory die #1 can be performed concurrently with write or read operations on non-defective blocks BLK8 within NAND flash memory die #0 and BLK7 within NAND flash memory die #2. However, write or read operations on the other of the two non-defective blocks BLK7-BLK8 within NAND flash memory die #1 cannot be performed concurrently. Therefore, the time required to write data to the area allocated to superblock SB6 is twice the time required to write data to the area allocated to any one of superblocks SB0, SB2-SB4, or SB7. Consequently, the area allocated to superblock SB6 also operates as a half-speed area.

[0179] Figure 9 This is a diagram illustrating a fourth configuration example of multiple block groups managed in an SSD3 according to a relevant implementation.

[0180] First, refer to Figure 9The upper part describes the configuration example of the block group for the comparative example. Here, we assume that the NAND flash memory die #0 contains four planes, and a block group allocated to a region contains four blocks. For example... Figure 9 As shown in the upper part, the first to fourth planes (PLANE0 to PLANE3) each contain ten blocks BLK0 to BLK9. The first plane (PLANE0) contains zero defective blocks. The second plane (PLANE1) also contains zero defective blocks. The third plane (PLANE2) contains two defective blocks. The fourth plane (PLANE3) contains five defective blocks.

[0181] In the comparative example, multiple block groups (multiple superblocks SB) are constructed using only the first type of block groups. Therefore, the maximum number of superblocks SB that can be constructed is limited to the number of non-bad blocks contained in the fourth plane (PLANE3) with the most bad blocks (here, 5).

[0182] Five of the ten non-bad blocks (BLK0 to BLK9) in the first plane (PLANE0) (BLK1 to BLK2 and BLK6 to BLK8 in this case) are not used in the construction of the superblock SB. As a result, a capacity equivalent to five blocks is wasted.

[0183] In the second plane (PLANE1), the five non-bad blocks (BLK1~BLK2, BLK6~BLK8) are also not used in the construction of the superblock SB. As a result, a capacity equivalent to five blocks is wasted.

[0184] In the third plane (PLANE2), three non-bad blocks (BLK1, BLK6-BLK7) are not used in the construction of the superblock SB. As a result, a capacity equivalent to three blocks is wasted.

[0185] Next, refer to Figure 9 The following section describes an example of the block group configuration in this embodiment. In this embodiment, not only multiple first-type block groups are used, but also one or more second-type block groups are used to construct eight block groups (superblocks SB0 to SB7).

[0186] Superblocks SB0, SB2-SB4, and SB7 are all first-type block groups. Superblocks SB0, SB2-SB4, and SB7 are each composed of four non-defective blocks selected from each of the four planes (PLANE0-PLANE3).

[0187] Superblocks SB1 and SB5-SB6 are the second type of block groups. Superblock SB1 contains two non-defective blocks BLK1-BLK2 selected from the first plane (PLANE0), one non-defective block BLK1 selected from the second plane (PLANE1), and one non-defective block BLK1 selected from the third plane (PLANE2). Superblock SB1 does not contain any non-defective blocks in the fourth plane (PLANE3). The area allocated to superblock SB1 is used as a half-speed region for operation.

[0188] Superblock SB5 includes two non-defective blocks BLK6-BLK7 selected from the first plane (PLANE0), one non-defective block BLK6 selected from the second plane (PLANE1), and one non-defective block BLK6 selected from the third plane (PLANE2). Superblock SB5 does not include non-defective blocks within the fourth plane (PLANE3). The area assigned to Superblock SB5 also operates as a half-speed area.

[0189] Superblock SB6 includes one non-defective block BLK8 selected from the first plane (PLANE0), two non-defective blocks BLK7-BLK8 selected from the second plane (PLANE1), and one non-defective block BLK7 selected from the third plane (PLANE2). Superblock SB6 does not include non-defective blocks in the fourth plane (PLANE3). The area assigned to Superblock SB6 also operates as a half-speed area.

[0190] Figure 10 This is a diagram illustrating a fifth configuration example of multiple block groups managed in an SSD3 according to a relevant implementation.

[0191] First, refer to Figure 10 The upper part describes the configuration example of the block group for the comparative example. Here, we assume that two NAND flash memory dies #0 to #1 each contain two planes, and a block group allocated to a region contains four blocks. For example... Figure 10 As shown at the top, the first plane (PLANE0) and the second plane (PLANE1) within NAND flash memory die #0 each contain ten blocks BLK0 to BLK9. The first plane (PLANE0) and the second plane (PLANE1) within NAND flash memory die #1 also each contain ten blocks BLK0 to BLK9.

[0192] The number of defective blocks in the first plane (PLANE0) of NAND flash memory die #0 is zero. The number of defective blocks in the second plane (PLANE1) of NAND flash memory die #0 is also zero. The number of defective blocks in the first plane (PLANE0) of NAND flash memory die #1 is 2. The number of defective blocks in the second plane (PLANE1) of NAND flash memory die #1 is 5.

[0193] In the comparative example, multiple block groups (multiple superblocks SB) are constructed using only the first type of block group. Therefore, the maximum number of superblocks SB that can be constructed is limited to the number of non-bad blocks contained in the second plane (PLANE1) of the NAND flash memory die #1 with the most bad blocks (here, 5).

[0194] Five of the ten non-bad blocks (BLK0 to BLK9) within the first plane (PLANE0) of the NAND flash memory die #0 (BLK1 to BLK2 and BLK6 to BLK8 in this case) are not used for the construction of the superblock SB. As a result, a capacity equivalent to five blocks is wasted.

[0195] In the second plane (PLANE1) of NAND flash memory die #0, the five non-bad blocks (BLK1~BLK2, BLK6~BLK8) are not used for the construction of the superblock SB. As a result, a capacity equivalent to five blocks is wasted.

[0196] In the first plane (PLANE0) of NAND flash memory die #1, three non-bad blocks (BLK1, BLK6-BLK7) are not used for the construction of the superblock SB. As a result, a capacity equivalent to three blocks is wasted.

[0197] Next, refer to Figure 10 The following section describes an example of the block group configuration in this embodiment. In this embodiment, not only multiple first-type block groups are used, but also one or more second-type block groups are used to construct eight block groups (superblocks SB0 to SB7).

[0198] Superblocks SB0, SB2-SB4, and SB7 are the first type of block groups. Superblocks SB0, SB2-SB4, and SB7 are each composed of four non-defective blocks selected from each of the four planes (the first plane (PLANE0) and the second plane (PLANE1) of NAND flash memory die #0, and the first plane (PLANE0) and the second plane (PLANE1) of NAND flash memory die #1).

[0199] Superblocks SB1 and SB5-SB6 are the second type of block groups. Superblock SB1 contains two non-defective blocks BLK1-BLK2 selected from the first plane (PLANE0) of NAND flash memory die #0, one non-defective block BLK1 selected from the second plane (PLANE1) of NAND flash memory die #0, and one non-defective block BLK1 selected from the first plane (PLANE0) of NAND flash memory die #1. Superblock SB1 does not contain any non-defective blocks within the second plane (PLANE1) of NAND flash memory die #1. The area allocated to Superblock SB1 operates as a half-speed area.

[0200] Superblock SB5 contains two non-defective blocks BLK6-BLK7 selected from the first plane (PLANE0) of NAND flash memory die #0, one non-defective block BLK6 selected from the second plane (PLANE1) of NAND flash memory die #0, and one non-defective block BLK6 selected from the first plane (PLANE0) of NAND flash memory die #1. Superblock SB5 does not contain any non-defective blocks within the second plane (PLANE1) of NAND flash memory die #1. The area allocated to Superblock SB5 also operates as a half-speed area.

[0201] Superblock SB6 contains one non-defective block BLK8 selected from the first plane (PLANE0) of NAND flash memory die #0, two non-defective blocks BLK7 to BLK8 selected from the second plane (PLANE1) of NAND flash memory die #0, and one non-defective block BLK7 selected from the first plane (PLANE0) of NAND flash memory die #1. Superblock SB6 does not contain any non-defective blocks within the second plane (PLANE1) of NAND flash memory die #1. The area allocated to Superblock SB6 also operates as a half-speed area.

[0202] Next, we will explain the process of switching between using the second type of block group based on the difference in the number of defective blocks between the plane with the fewest defective blocks and the plane with the most defective blocks.

[0203] Figure 11 The diagram illustrates an example of multiple block groups constructed in the SSD3 of the relevant implementation when the difference in the number of defective blocks between the plane with the fewest defective blocks and the plane with the most defective blocks is less than 1, and an example of multiple block groups constructed in the SSD3 of the relevant implementation when the difference in the number of defective blocks is 2 or more.

[0204] exist Figure 11 In this context, we envision a NAND flash memory die #0 containing two planes, and a block group allocated to a region containing two blocks. Figure 11 The upper part indicates cases where the difference in the number of defective blocks is less than 1. Additionally, Figure 11 The lower part indicates cases where the difference in the number of defective blocks is 2 or more.

[0205] like Figure 11 As shown at the top, the first plane (PLANE0) and the second plane (PLANE1) within the NAND flash memory die #0 each contain ten blocks BLK0 to BLK9. In the first plane (PLANE0), three of the ten blocks BLK0 to BLK9, BLK2 to BLK3 and BLK6, are defective blocks. In the second plane (PLANE1), two of the ten blocks BLK0 to BLK9, BLK2 and BLK5, are defective blocks.

[0206] In this case, in this embodiment, multiple block groups (multiple superblocks SB) are constructed using only the first type of block groups. That is, each superblock SB consists of a total of two non-defective blocks selected from the first plane (PLANE0) and the second plane (PLANE1). Therefore, the number of second type block groups contained in the multiple block groups is zero.

[0207] For example, superblock SB0 is composed of non-defective block BLK0 selected from the first plane (PLANE0) and non-defective block BLK0 selected from the second plane (PLANE1). Superblock SB1 is composed of non-defective block BLK1 selected from the first plane (PLANE0) and non-defective block BLK1 selected from the second plane (PLANE1). Superblock SB2 is composed of non-defective block BLK4 selected from the first plane (PLANE0) and non-defective block BLK3 selected from the second plane (PLANE1). Superblock SB3 is composed of non-defective block BLK5 selected from the first plane (PLANE0) and non-defective block BLK4 selected from the second plane (PLANE1). Superblock SB4 is composed of non-defective block BLK7 selected from the first plane (PLANE0) and non-defective block BLK6 selected from the second plane (PLANE1). Superblock SB5 is composed of non-defective block BLK8 selected from the first plane (PLANE0) and non-defective block BLK7 selected from the second plane (PLANE1). Superblock SB6 is composed of non-defective block BLK9 selected from the first plane (PLANE0) and non-defective block BLK8 selected from the second plane (PLANE1).

[0208] The non-bad block that is not used in the construction of any superblock is only block BLK9 in the second plane (PLANE1).

[0209] Next, we will explain the cases where the difference in the number of defective blocks is more than 2. For example... Figure 11As shown in the lower part, in the first plane (PLANE0), three of the ten blocks BLK0 to BLK9, namely blocks BLK2 to BLK3 and BLK6, are defective blocks. In the second plane (PLANE1), one of the ten blocks BLK0 to BLK9, namely block BLK2, is a defective block.

[0210] In this case, in this embodiment, not only are multiple first-type block groups used, but also more than one second-type block group is used to construct eight block groups (superblocks SB0 to SB7). The number of second-type block groups contained in the eight block groups is one or more.

[0211] Superblocks SB0 to SB6 are the first type of block groups. Superblocks SB0 to SB6 are each composed of two non-defective blocks selected from the first plane (PLANE0) and the second plane (PLANE1).

[0212] For example, superblock SB0 is composed of non-defective block BLK0 selected from the first plane (PLANE0) and non-defective block BLK0 selected from the second plane (PLANE1). Superblock SB1 is composed of non-defective block BLK1 selected from the first plane (PLANE0) and non-defective block BLK1 selected from the second plane (PLANE1). Superblock SB2 is composed of non-defective block BLK4 selected from the first plane (PLANE0) and non-defective block BLK3 selected from the second plane (PLANE1). Superblock SB3 is composed of non-defective block BLK5 selected from the first plane (PLANE0) and non-defective block BLK4 selected from the second plane (PLANE1). Superblock SB4 is composed of non-defective block BLK6 selected from the first plane (PLANE0) and non-defective block BLK5 selected from the second plane (PLANE1). Superblock SB5 is composed of non-defective block BLK7 selected from the first plane (PLANE0) and non-defective block BLK6 selected from the second plane (PLANE1). Superblock SB6 is composed of non-defective block BLK8 selected from the first plane (PLANE0) and non-defective block BLK7 selected from the second plane (PLANE1).

[0213] Superblock SB7 is a type 2 block group. Each superblock SB7 consists of two non-bad blocks BLK8 to BLK9 selected from the second plane (PLANE1) with fewer bad blocks. Each superblock SB7 does not contain any non-bad blocks from the first plane (PLANE0) with more bad blocks.

[0214] Next, we will explain the write and read operations performed in the SSD3. Figure 12 It is a block diagram showing the order of write operations and the order of read operations performed in an SSD3.

[0215] The SSD3 controller 4 is configured to manage the mapping between multiple block groups (i.e., multiple superblocks SB) and multiple regions, and can allocate any superblock SB as a physical storage region.

[0216] A superblock (SB) corresponding to a region is accessed using contiguous logical addresses within the LBA range allocated to that region. Writes within a region are performed essentially sequentially.

[0217] The status of each area can be roughly divided into open state (open area), closed state (closed area), full state (full area), and idle state (idle area).

[0218] An open region is a region allocated as a write location where data can be written. When a region is opened, the superblock SB corresponding to that region is allocated as an open physical storage region that can be used for data writing. The flash memory management unit 21 uses the open region list 111 to manage each open region, that is, the superblock SB corresponding to each open region.

[0219] The regions in the off state are regions where write operations have been interrupted. The superblock SB corresponding to the region where write operations were interrupted is a superblock SB in which only a portion of the superblock SB has been written, i.e., a superblock SB that has been partially written. Within the superblock SB corresponding to the region in the off state, there are still a few pages that can be used for writing data. The flash memory management unit 21 uses the off region list 112 to manage each region in the off state, i.e., the superblock SB corresponding to each region in the off state.

[0220] A full region is a region that is completely filled with data. The superblock SB corresponding to a full region is a block in which all pages within the superblock SB have been written. The flash memory management unit 21 uses the full region list 113 to manage each full region, i.e., the superblock SB corresponding to each full region.

[0221] The idle region is the region that has been reset. The superblock SB corresponding to the idle region is a free superblock SB that has not yet stored valid data. The flash memory management unit 21 uses the free region list 114 to manage each idle region, that is, the superblock SB corresponding to each idle region.

[0222] When host 2 is expected to write data to a free region, host 2 sends an open region instruction, specifically an open region instruction specifying the free region's ZSLBA, to SSD 3, containing parameters for that free region. The open region instruction is used to allocate one of the superblocks (SBs) as an open physical storage region capable of being used for data writing. In response to receiving the open region instruction from host 2, flash memory management unit 21 selects a superblock (SB) from the free superblocks (SBs) managed by free region list 114. Furthermore, flash memory management unit 21 performs a deletion operation on the selected superblock (SB), thereby allocating it as an open physical storage region. As a result, the region specified by the open region instruction changes from a free state to an open state.

[0223] Host 2 can set multiple regions to open status by repeatedly executing the process of sending open region commands to SSD3.

[0224] For example, when the host 2 receives a write command containing parameters for a region with a specified open state, i.e., a write command for the ZSLBA of a region with a specified open state, the flash memory management unit 21 uses the DMAC 15 to transfer the write data associated with the received write command from the host 2's write buffer 51 to the internal buffer 161. Furthermore, the flash memory management unit 21 writes the write data transferred to the internal buffer 161 into the superblock SB allocated to region #1. Finally, the flash memory management unit 21 replies to the host 2 with a write completion response indicating the completion of each write command.

[0225] When no data is written to a region that is open for a short period of time, host 2 sends a close region command to SSD 3 to put that region into a closed state, so as to release the region in host 2's write buffer 51 that was secured for that region.

[0226] For example, when the host 2 receives a region-close instruction containing parameters for the specified region #1, i.e., a region-close instruction for the ZSLBA of the specified region #1, the flash memory management unit 21 puts region #1 into a closed state. In this case, the flash memory management unit 21 removes region #1, i.e., the superblock SB allocated to region #1, from the open region list 111 and adds it to the closed region list 112.

[0227] Upon receiving a write command from host 2 containing parameters for a region that is specified to be in a closed state, flash memory management unit 21 reallocates (reopens) the superblock SB allocated to that region as an open physical storage region.

[0228] When a certain area is completely filled with data, the flash memory management unit 21 changes the state of that area from open or closed to full. The superblock SB corresponding to that area is managed as a full superblock SB.

[0229] Upon receiving a read command from host 2 requesting the read of object data, flash memory management unit 21 determines the object region to be read based on the starting LBA contained in the read command, and reads the object data from the superblock allocated to that object region. Furthermore, flash memory management unit 21 sends the read object data as read success data to host 2 using DMAC 15.

[0230] When all data stored in a full region becomes unnecessary and unused, host 2 can send a reset region command to SSD 3, specifying the logical address representing that region. In response to receiving the reset region command from host 2, flash memory management unit 21 removes the superblock SB allocated to that region from the full region list 113 and adds it to the free region list 114. Thus, the region's state changes from full to free.

[0231] Next, the block group construction action used to build multiple superblocks (SB) will be explained. Figure 13 This is a flowchart showing the sequence of block group construction actions performed in the SSD3 of the relevant implementation.

[0232] The controller 4 determines whether the difference in the number of defective blocks among the multiple NAND flash memory dies (or multiple planes capable of parallel operation) used in the construction of the multiple superblocks SB is greater than or equal to 2 (step S11). The number of NAND flash memory dies (or planes) used in the construction of the superblocks SB only needs to be greater than or equal to 2.

[0233] In step S11, the controller 4 calculates the difference between the number of defective blocks contained in the NAND flash memory die (or plane) with the most defective blocks among the two or more NAND flash memory dies (or two or more planes) used to construct the multiple super blocks SB, based on the defective information stored in the defective block management table 32, and the number of defective blocks contained in the NAND flash memory die (or plane) with the fewest defective blocks among these two or more NAND flash memory dies (or two or more planes).

[0234] If the difference is less than 1 (step S11: No), the controller 4 constructs multiple first-type block groups, each containing multiple non-defective blocks obtained by selecting one or more non-defective blocks of the same number from two or more non-volatile memory dies (or two or more planes), as multiple super blocks SB (step S12). All of the first-type block groups constructed in step S12 are used as full-speed block groups.

[0235] If the difference is greater than 2 (step S11: yes), the controller 4 constructs multiple first-type block groups and one or more second-type block groups based on the bad information.

[0236] In this case, controller 4 first constructs multiple first-type block groups, each containing multiple non-defective blocks obtained by selecting one or more identical non-defective blocks from two or more non-volatile memory dies (or two or more planes), as multiple super blocks SB (step S13). In step S13, for example, all non-defective blocks contained in the NAND flash memory die (or plane) with the most defective blocks are used to construct the multiple first-type block groups. All of the first-type block groups constructed in step S13 are used as full-speed block groups.

[0237] When there are no remaining non-defective blocks in the NAND flash memory die (or plane) with the most defective blocks, the controller 4 constructs one or more second-type block groups, each containing multiple non-defective blocks obtained by selecting different numbers of non-defective blocks from two or more non-volatile memory dies (or two or more planes), as one or more super blocks SB (step S14).

[0238] In the construction of each second-type block group, non-defective blocks are not selected from the NAND flash memory die (or plane) with the most defective blocks. Two or more non-defective blocks are selected from the NAND flash memory die (or plane) with the fewest defective blocks. Furthermore, when constructing each superblock using three or more NAND flash memory dies (or planes), one or more identical numbers of non-defective blocks are selected from all NAND flash memory dies (or planes) except for the one with the most and fewest defective blocks. All of the second-type block groups constructed in step S14 are used as half-speed block groups.

[0239] Next, the process of allocating one of multiple block groups as an open physical storage area that can be used for data writing will be explained. Figure 14 This is a flowchart showing the sequence of block group allocation operations performed in the SSD3 according to the relevant implementation.

[0240] In this embodiment, there are two types of block groups: full-speed block groups and half-speed block groups. Therefore, in this embodiment, the instruction for allocating one of the multiple block groups as an open physical storage area that can be used for data writing uses an instruction containing a first parameter, which indicates whether the allocation of a block group with a second access speed that is slower than the first access speed is allowed.

[0241] Instructions for allocating one of multiple block groups as an open physical storage area capable of being used for data writing are implemented, for example, via open area instructions (open requests). Typical open area instructions do not include parameters indicating whether allocation of block groups with a second access speed slower than a first access speed is permitted. This embodiment uses a new open area instruction (open request) that includes parameters indicating whether allocation of block groups with a second access speed is permitted.

[0242] The first access speed is comparable to the access speed of a full-speed region (full-speed block group). The second access speed is comparable to the access speed of a half-speed region (half-speed block group). In this embodiment, the parameters contained in the open request indicate whether the allocation of a half-speed region is allowed.

[0243] When a request to open a specified area is received from host 2 (step S101: Yes), controller 4 determines whether the parameters contained in the received request indicate that the allocation of a half-speed area is allowed (step S102).

[0244] If the parameters contained in the received open request allow for the allocation of a half-speed region (step S102: Yes), the controller 4 selects a half-speed block group (second type block group) from the idle block group (free superblock SB) (step S103).

[0245] Next, controller 4 performs a deletion operation on the selected second type block group, allocating the physical storage area of ​​the selected second type block group as an open block group, i.e., the specified region (step S104). As a result, the specified region is opened.

[0246] Furthermore, controller 4 replies to host 2 with a response indicating the completion of the open request, thereby informing host 2 whether the opened area is a half-speed area or a full-speed area (step S105). That is, the response contains a parameter indicating whether the opened area is a half-speed area or a full-speed area. In step S104, the second type block group, i.e., the half-speed area, is opened. In step S105, host 2 is notified that the opened area is a half-speed area.

[0247] If the parameters contained in the received open request do not allow the allocation of a half-speed region (step S102: No), the controller 4 selects a full half-speed block group (first type block group) from the idle block group (free superblock SB) (step S106).

[0248] Next, controller 4 performs a deletion operation on the selected first type block group, allocating the physical storage area of ​​the selected first type block group as an open block group, i.e., the specified region (step S104). As a result, the specified region is opened.

[0249] Furthermore, the controller 4 replies to the host 2 with a response indicating that the opening request has been completed, thereby notifying the host 2 that the area that has been opened is the full-speed area (step S105).

[0250] Host 2 can identify which areas among the open regions are full-speed areas and which are half-speed areas. Thus, host 2 can, for example, control the data configuration for each region by writing data that requires high-speed access to the full-speed region and data that does not require high-speed access to the half-speed region.

[0251] Next, the process of notifying host 2 of the access speed of each of the multiple block groups based on the request from host 2 will be explained. Figure 15 This is a flowchart illustrating the sequence of access speed notification actions performed in the SSD3 according to the relevant implementation. Host 2 can obtain the region data structures representing the characteristics of each of the multiple regions managed in the SSD3 by requesting region data structures representing the characteristics of each of the multiple regions from the SSD3.

[0252] Upon receiving a request from host 2 to obtain region data construction (step S201: Yes), controller 4 constructs region data together with access speed information indicating whether each region is a full-speed or half-speed region, region capacity, region status (open / closed / full / idle, etc.), re-instruction notification corresponding to each region, write indicator of each region, ZSLBA of each region, etc., and notifies SSD 3 (step S202).

[0253] In step S202, for regions allocated with the first type of block group, information indicating the first access speed (full-speed region) is notified to host 2. Additionally, for regions allocated with the second type of block group, information indicating the second access speed (half-speed region) is notified to host 2.

[0254] Next, the process of writing data to one of multiple block groups will be explained. Figure 16 This is a flowchart showing the sequence of data write operations performed in an SSD3 according to a relevant implementation.

[0255] Upon receiving a write command containing parameters specifying a certain region from host 2 (step S301), controller 4 selects the block group (superblock SB) corresponding to the region specified by the received write command (step S302). Next, controller 4 writes the write data associated with the received write command to the selected block group (step S303).

[0256] Furthermore, the controller 4 will notify the host 2 of the completion of the received write instruction (step S304).

[0257] Next, the process of reading data from one of multiple block groups will be explained. Figure 17 This is a flowchart showing the sequence of data readout operations performed in an SSD3 according to a relevant implementation.

[0258] When a read instruction containing parameters for a specified region is received from the host 2 (step S401: Yes), the controller 4 selects the block group (superblock SB) corresponding to the region specified by the read instruction received in step S401 (step S402).

[0259] Next, the controller 4 reads the data of the read object specified by the received read instruction from the block group selected in step S402, and sends the read data to the host 2 (step S403).

[0260] Furthermore, the controller 4 will notify the host 2 of the completion of the received read instruction (step S404).

[0261] As explained above, according to this embodiment, the plurality of block groups at least include a first block group composed of a first type of block group and a second block group composed of a second type of block group. The first type of block group includes a plurality of non-defective blocks obtained by selecting one or more identical non-defective blocks from a plurality of dies or planes contained in the non-volatile memory 5. The second type of block group includes a plurality of non-defective blocks selected from a plurality of dies or planes, the same number as the plurality of non-defective blocks contained in the first type of block group. The number of non-defective blocks in each die or plane of the second type of block group varies among the dies or planes.

[0262] Thus, by using a second type of block group—where the number of non-defective blocks varies between dies or planes and includes the same number of non-defective blocks as the first block group—although the number of defective blocks varies significantly between dies or planes in the NAND flash memory 5, almost all non-defective blocks can be used to construct the block group. As a result, the number of usable areas can be increased, and the block groups can have the same capacity. This reduces the burden on the host 2 regarding the management of each block group (e.g., area), maximizing the capacity of the SSD 3.

[0263] While several embodiments of the invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as set forth in the claims and its equivalents.

Claims

1. A memory system capable of being connected to a host computer, characterized in that, have: A non-volatile memory includes multiple dies or multiple planes that can operate in parallel, each of the dies or planes containing multiple blocks, each block being a unit for data deletion operations; as well as The controller is configured to be electrically connected to the non-volatile memory and to control the non-volatile memory. The controller is constructed from the plurality of bare dies or the plurality of planes, each comprising a plurality of blocks. The controller is configured to respond to a write instruction received from the host for writing data to one of the plurality of block groups, by writing data associated with the received write instruction to the one block group. The plurality of block groups includes at least a first block group composed of a first type of block group and a second block group composed of a second type of block group. The first type of block group comprises a plurality of non-defective blocks obtained by selecting one or more equal numbers of non-defective blocks from the plurality of dies or the plurality of planes. The second type of block group includes a plurality of non-defective blocks selected from the plurality of dies or the plurality of planes, the same number as the plurality of non-defective blocks included in the first type of block group, and the number of non-defective blocks for each die or each plane included in the second type of block group differs between at least two dies or two planes among the plurality of dies or the plurality of planes.

2. The memory system according to claim 1, characterized in that, The difference between the maximum number of non-defective blocks in each die or plane of the second type of block group and the minimum number of non-defective blocks in each die or plane of the second type of block group is greater than 2.

3. The memory system according to claim 1, characterized in that, The second type of block group includes two or more non-defective blocks selected from the first die or the first plane with the fewest defective blocks among the plurality of dies or the plurality of planes, and does not include non-defective blocks in the second die or the second plane with the most defective blocks among the plurality of dies or the plurality of planes.

4. The memory system according to claim 1, characterized in that, The controller is configured as follows: If the difference between the number of defective blocks in the first die or first plane with the fewest defective blocks among the plurality of dies or planes and the number of defective blocks in the second die or second plane with the most defective blocks among the plurality of dies or planes is greater than 2, then the plurality of block groups are constructed using the first type block group and the second type block group. If the difference between the number of defective blocks contained in the first die or the first plane and the number of defective blocks contained in the second die or the second plane is less than 1, the plurality of block groups are constructed using only the first type of block group.

5. The memory system according to claim 1, characterized in that, The controller is configured as follows: For each of the multiple regions that have been allocated multiple logical address ranges, one of the multiple block groups is allocated as a physical storage region. The multiple logical address ranges are obtained by dividing the logical address space used to access the memory system. In response to receiving a first write instruction from the host containing parameters for a first region of the plurality of regions, data associated with the first write instruction is written to the block group allocated to the first region.

6. The memory system according to claim 1, characterized in that, The controller is configured as follows: The host receives a first instruction for allocating one of the plurality of block groups as an open physical storage area capable of being used for data writing, and the first instruction includes a first parameter indicating whether the allocation of a block group with a second access speed slower than the first access speed is allowed. If the first parameter of the received first instruction indicates that the allocation of block groups with the second access speed is permitted, then a block group consisting of block groups of the second type will be allocated as the physical storage area in the open state. If the first parameter of the first instruction indicates that the allocation of block groups with the second access speed is not allowed, a block group consisting of the first type of block groups will be allocated as the physical storage area in the open state.

7. The memory system according to claim 1, characterized in that, The controller is configured to notify the host of the access speed of each of the plurality of block groups based on a request from the host. For each block group consisting of the first type of block groups among the plurality of block groups, information indicating the first access speed is notified to the host. For each block group consisting of the second type of block groups among the plurality of block groups, the host is notified of information indicating a second access speed that is slower than the first access speed.

8. A memory system capable of being connected to a host computer, characterized in that, have: A non-volatile memory includes multiple dies or multiple planes that can operate in parallel, each of the dies or planes containing multiple blocks, each block being a unit for data deletion operations; as well as The controller is configured to be electrically connected to the non-volatile memory and to control the non-volatile memory. The controller is configured as follows: If the difference between the number of defective blocks in the first die or first plane with the fewest defective blocks among the plurality of dies or planes and the number of defective blocks in the second die or second plane with the most defective blocks among the plurality of dies or planes is greater than 2, then a first type block group and a second type block group are used to construct multiple block groups, each containing multiple blocks, from the plurality of dies or planes. If the difference between the number of defective blocks contained in the first die or the first plane and the number of defective blocks contained in the second die or the second plane is less than 1, then only the first type of block group is used to construct the plurality of block groups from the plurality of dies or the plurality of planes. In response to receiving a write instruction from the host for writing data to one of the plurality of block groups, the system writes the data associated with the received write instruction to the one block group. The first type of block group comprises a plurality of non-defective blocks obtained by selecting one or more equal numbers of non-defective blocks from the plurality of dies or the plurality of planes. The second type of block group includes a plurality of non-defective blocks selected from the plurality of dies or the plurality of planes, the same number as the plurality of non-defective blocks included in the first type of block group, and the number of non-defective blocks for each die or each plane included in the second type of block group differs between at least two dies or two planes among the plurality of dies or the plurality of planes.

9. The memory system according to claim 8, characterized in that, The difference between the maximum number of non-defective blocks in each die or plane of the second type of block group and the minimum number of non-defective blocks in each die or plane of the second type of block group is greater than 2.

10. The memory system according to claim 8, characterized in that, The second type of block group includes two or more non-defective blocks selected from the first die or the first plane with the fewest defective blocks among the plurality of dies or the plurality of planes, and does not include non-defective blocks in the second die or the second plane with the most defective blocks among the plurality of dies or the plurality of planes.

11. A control method for controlling a non-volatile memory, the non-volatile memory comprising a plurality of dies or a plurality of planes capable of parallel operation, each of the dies or planes comprising a plurality of blocks, the plurality of blocks being units of data deletion operations, characterized in that, The control method includes: Multiple block groups, each containing multiple blocks, are constructed from the multiple bare dies or the multiple planes; In response to receiving a write instruction from the host for writing data to one of the plurality of block groups, the system writes the data associated with the received write instruction to the one block group. The plurality of block groups includes at least a first block group composed of a first type of block group and a second block group composed of a second type of block group. The first type of block group comprises a plurality of non-defective blocks obtained by selecting one or more equal numbers of non-defective blocks from the plurality of dies or the plurality of planes. The second type of block group includes a plurality of non-defective blocks selected from the plurality of dies or the plurality of planes, the same number as the plurality of non-defective blocks included in the first type of block group, and the number of non-defective blocks for each die or each plane included in the second type of block group differs between at least two dies or two planes among the plurality of dies or the plurality of planes.

12. The control method according to claim 11, characterized in that, The difference between the maximum number of non-defective blocks in each die or plane of the second type of block group and the minimum number of non-defective blocks in each die or plane of the second type of block group is greater than 2.

13. The control method according to claim 11, characterized in that, The number of the plurality of bare wafers or the plurality of planes is two or more. The second type of block group includes two or more non-defective blocks selected from the first die or the first plane with the fewest defective blocks among the plurality of dies or the plurality of planes, and does not include non-defective blocks in the second die or the second plane with the most defective blocks among the plurality of dies or the plurality of planes.

14. The control method according to claim 11, characterized in that, If the difference between the number of defective blocks in the first die or first plane with the fewest defective blocks among the plurality of dies or planes and the number of defective blocks in the second die or second plane with the most defective blocks among the plurality of dies or planes is greater than 2, the plurality of block groups are constructed using the first type of block group and the second type of block group. If the difference between the number of defective blocks contained in the first die or the first plane and the number of defective blocks contained in the second die or the second plane is less than 1, the plurality of block groups are constructed using only the first type of block group.

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