A DMA allocation and management method for NVMe SSDs

Abstract

The application discloses a DMA distribution and management method applied to an NVMe SSD. The method estimates the work of each DMA and allocates appropriate data for next DMA transmission. First, the data volume of data transmission is calculated. When the data volume is less than a minimum data volume threshold, continuous work of a certain DMA is emphasized instead of small data volume transmission of all DMAs after frequent transmission. When the data volume is greater than the minimum data volume threshold, continuous work of all DMAs is emphasized instead of work accumulation in a certain DMA. The method fully considers factors reflecting DMA load during DMA operation, can obtain accurate DMA state statistical information, selects the most suitable DMA to be started for next data transmission, improves the utilization rate of the DMA in the controller, and improves the IO processing speed of the front end of the controller.

Description

Technical Field

[0001] This invention relates to the field of NVMe storage, specifically a DMA allocation and management method applied to NVMe SSDs. Background Technology

[0002] NVMe SSDs are solid-state drives that conform to the Non-Volatile Memoryexpress (NVEX) host controller interface specification. An SSD consists of a controller and memory. A high-quality NVMe SSD controller can fully utilize the low latency and parallelism of the PCIe channel, significantly improving the read and write performance of the SSD while reducing the high latency caused by the AHCI interface, thus fully unleashing the ultimate performance potential of SATA-era SSDs.

[0003] As a crucial component of NVMe SSDs, the controller plays a vital role in establishing the data path between the host and the storage, handling I / O requests from the host, admin commands, and optimizing storage usage. In the data interaction between the host and the storage, DMA is a typical function that improves data transfer efficiency.

[0004] In a typical NVMe SSD controller configuration, multiple front-end DMAs are generally present to achieve data parallelism and fully utilize bus bandwidth. The front-end DMAs are responsible for transferring data from host memory to the controller's buffer, or vice versa. Therefore, the allocation and management of front-end DMAs is particularly important. Most mainstream controllers today use a fixed-weight allocation method, assigning a fixed workload to each DMA. This can lead to unbalanced DMA transfers; some DMAs are working at full capacity, while others, due to their low weight, do not perform any DMA transfers, resulting in wasted DMA resources. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a DMA allocation and management method for NVMe SSDs, offering a flexible and efficient scheduling approach during data transmission between the host and controller. Front-end firmware designed based on this method can significantly improve data transmission efficiency, increase NVMe SSD IOPS and bandwidth, and reduce firmware interference and impact on DMA transfers.

[0006] To solve the aforementioned technical problem, the technical solution adopted by the present invention is: a DMA allocation and management method applied to NVMe SSDs, comprising the following steps: S01) After receiving the IO / Admin command from the host, the firmware parses it and initiates a DMA request; S02) The firmware determines whether the DMA is in an idle state by the number of bytes transferred in the DMA status information, i.e., the DMA load statistics. If the load statistics are 0, the DMA is in an idle state. S03) If all DMAs are idle, then the highest priority DMA will be started for transmission according to the DMA weight priority. S04) If there is a DMA in a non-idle state, compare the load statistics of the DMA in the non-idle state. S05) If the amount of data to be transferred in the non-idle DMA is less than the minimum data amount threshold M, and the number of bytes to be transferred is less than the threshold S, then the DMA is started for transfer. S06) If there is no DMA in the above state, then all DMAs are transmitting and the amount of data m transmitted is not less than the threshold M, and the number of bytes s transmitted is not less than the threshold. S07) Select the DMA transfer with the shortest current transfer time to start the transfer; S08) Firmware detects DMA completion of this data transfer; S09), Update the DMA status information structure.

[0007] Furthermore, let the startup time of a single DMA be T. s The number of DMA activations is k, and the time taken from activation to the completion of a unit byte transfer is the unit byte transfer time T. b The amount of data being processed by a single DMA is n, and the number of bytes to be transferred per descriptor is m. i Therefore, the time taken from the start of DMA data transfer to the completion of the transfer should be... In step S07), the transmission time of each DMA is determined according to the formula.

[0008] Furthermore, steps S01) to S07) are run through thread 1, and steps S08) to S09) are run through thread 2. When data is continuously transmitted, thread 1 and thread 2 run in parallel.

[0009] Furthermore, the updated DMA status information structure in step S09) includes DMA load statistics, namely the number of bytes transferred s and the amount of data transferred by DMA.

[0010] The beneficial effects of this invention are as follows: This method fully considers factors that reflect DMA load, such as the number of bytes transferred and the number of descriptors during DMA operation, and can obtain accurate DMA status statistics to select the most suitable DMA for the next data transfer. It effectively utilizes the DMA in the NVMe SSD controller for data transfer, improving the DMA utilization rate in the controller and increasing the front-end I / O processing speed of the controller. Attached Figure Description

[0011] Figure 1 This is a flowchart of the present invention. Detailed Implementation

[0012] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0013] Example 1 In multi-DMA data transfer, maintaining the continuity of each DMA transfer can enhance data transfer capabilities. When a DMA transfer completes a data transfer, it pauses to await the configuration of the next DMA data transfer. The series of DMA restart operations are controlled and allocated by firmware in NVMe SSDs, which undoubtedly adds unnecessary startup time.

[0014] Each data transfer is configured with a DMA Descriptor. The DMA determines the amount of data to be transferred by reading the Descriptor. When there are multiple data transfers to be serially transferred using DMA, the DMA can automatically start the next data transfer after completing the current data transfer, based on the read Descriptor. Therefore, the firmware layer can prepare multiple data transfers for a specific DMA, or prepare the Descriptor for the next data transfer and move it after the Descriptor of the current DMA data transfer before the current DMA data transfer is completed.

[0015] To estimate the workload of each DMA and allocate an appropriate amount of data for the next DMA transfer, this embodiment adopts the following measures. First, the data volume of a data transfer is calculated. When the data volume is less than a certain minimum data volume threshold, the focus is on maintaining the continuous operation of a specific DMA rather than having all DMAs frequently complete and then start small data transfers again. That is, if the data volume is less than a certain minimum data volume threshold, the same DMA is used for each small data volume transfer instead of allocating each small data volume transfer to all DMAs. At the same time, this data volume is recorded in the load statistics of that DMA. When the data volume is greater than a certain minimum data volume threshold, it is considered a large data volume transfer. The focus is on maintaining the continuous operation of all DMAs rather than accumulating work on a single DMA. That is, according to the data volume and DMA weight priority, this data is allocated to the DMA with the lowest load and the highest weight. At the same time, this data volume is recorded in the load statistics of that DMA. Therefore, this method uses DMA weight priority, DMA load, and the number of descriptors currently running in the DMA as three elements in the DMA allocation and management method. This enables the acquisition of accurate DMA status statistics to select the most suitable DMA for the next data transfer.

[0016] like Figure 1 As shown, the specific steps of the method described in this embodiment are as follows: S01) After receiving the IO / Admin command from the host, the firmware parses it and initiates a DMA request; S02) The firmware determines whether the DMA is in an idle state by the number of bytes transferred in the DMA status information, i.e., the DMA load statistics. If the load statistics are 0, the DMA is in an idle state. S03) If all DMAs are idle, then the highest priority DMA will be started for transmission according to the DMA weight priority. S04) If there is a DMA in a non-idle state, compare the load statistics of the DMA in the non-idle state. S05) If the amount of data to be transferred in the non-idle DMA is less than the minimum data amount threshold M, and the number of bytes to be transferred is less than the threshold S, then the DMA is started for transfer. S06) If there is no DMA in the above state, then all DMAs are transmitting and the amount of data m transmitted is not less than the threshold M, and the number of bytes s transmitted is not less than the threshold. S07) Select the DMA transfer with the shortest current transfer time to start the transfer; S08) Firmware detects DMA completion of this data transfer; S09) Update the DMA status information structure, including DMA load statistics, i.e., the number of bytes transferred s and the amount of data transferred by DMA.

[0017] Assume the startup time of a single DMA is T. s The number of DMA activations is k, and the time taken from activation to the completion of a unit byte transfer is the unit byte transfer time T. b The amount of data being processed by a single DMA is n, and the number of bytes to be transferred per descriptor is m. i Therefore, the time taken from the start of DMA data transfer to the completion of the transfer should be... In step S07), the transfer time for each DMA is determined according to the formula. In this formula, the DMA startup time T... s and unit byte transmission time T b The constants are: DMA activation count k, data transfer count n, and the number of bytes to be transferred for each data transfer. i These are the key factors affecting DMA transfer. The DMA transfer time can be estimated using these three factors.

[0018] In this embodiment, steps S01) to S07) are run by thread 1, and steps S08) to S09) are run by thread 2. When data is transmitted continuously, thread 1 and thread 2 run in parallel.

[0019] The above description only illustrates the basic principles and preferred embodiments of the present invention. Modifications and substitutions made by those skilled in the art based on the present invention are within the scope of protection of the present invention.

Claims

1. A DMA allocation and management method applied to NVMe SSDs, characterized in that: Includes the following steps: S01) After receiving the IO / Admin command from the host, the firmware parses it and initiates a DMA request; S02) The firmware determines whether the DMA is in an idle state by the number of bytes transferred in the DMA status information, i.e., the DMA load statistics. If the load statistics are 0, the DMA is in an idle state. S03) If all DMAs are idle, then the highest priority DMA will be started for transmission according to the DMA weight priority. S04) If there is a DMA in a non-idle state, compare the load statistics of the DMA in the non-idle state. S05) If the amount of data to be transferred in the non-idle DMA is less than the minimum data amount threshold M, and the number of bytes to be transferred is less than the threshold S, then the DMA is started for transfer. S06) If there is no DMA in the above state, then all DMAs are transmitting and the amount of data m transmitted is not less than the threshold M, and the number of bytes s transmitted is not less than the threshold. S07) Select the DMA transfer with the shortest current transfer time to start the transfer; S08) Firmware detects DMA completion of this data transfer; S09), Update the DMA status information structure.

2. The DMA allocation and management method for NVMe SSDs according to claim 1, characterized in that: Let the startup time of a single DMA be T. s The number of DMA activations is k, and the time taken from activation to the completion of a unit byte transfer is the unit byte transfer time T. b The amount of data being processed by a single DMA is n, and the number of bytes to be transferred per descriptor is m. i Therefore, the time taken from the start of DMA data transfer to the completion of the transfer should be... In step S07), the transmission time of each DMA is determined according to the formula.

3. The DMA allocation and management method for NVMe SSDs according to claim 1, characterized in that: Steps S01) to S07) are run through thread 1, and steps S08) to S09) are run through thread 2. When data is continuously transmitted, thread 1 and thread 2 run in parallel.

4. The DMA allocation and management method for NVMe SSDs according to claim 1, characterized in that: Step S09) The updated DMA status information structure includes DMA load statistics, namely the number of bytes transferred s and the amount of data transferred by DMA.

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