Sense amplifier, method of operating the same, memory, and memory system

Abstract

The embodiment of the present disclosure provides a sense amplifier, comprising: a pre-charge unit, a readout unit, a first switch unit and a second switch unit; the pre-charge unit is coupled to a first bit line of a storage unit and a second bit line of the storage unit; the readout unit comprises a first node, a second node, a third node and a fourth node; the first bit line is coupled to the first node, the second bit line is coupled to the third node, the first switch unit is coupled to the first bit line and the second node, and the second switch unit is coupled to the second bit line and the fourth node; wherein the second node and the fourth node in the sense amplifier are discharged to different potentials in a discharge stage, so that the discharge rates of the first node and the third node are different in a read stage.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a sense amplifier and its operating method, a memory and a memory system. Background Technology

[0002] With the advancement of integrated circuit process technology, the requirements for chip power consumption, area, and performance are becoming increasingly stringent. For example, feature size and area are constantly decreasing, power supply voltage and power consumption are constantly decreasing, and performance requirements such as speed and accuracy are constantly increasing.

[0003] The readout circuit is one of the key unit modules in memory design. Its response speed and accuracy directly determine the time required to read data from the memory. Therefore, designing a readout circuit that meets the requirements of the application is crucial. Existing memory readout circuit designs are insufficient to meet the requirements for accuracy and high performance. Summary of the Invention

[0004] According to a first aspect of the present disclosure, a readout amplifier is provided, comprising: a precharge unit, a readout unit, a first switching unit, and a second switching unit; wherein...

[0005] The pre-charge unit is coupled to the first bit line of the memory cell and the second bit line of the memory cell;

[0006] The readout unit includes a first node, a second node, a third node, and a fourth node, wherein the first bit line is coupled to the first node, and the second bit line is coupled to the third node;

[0007] The first switching unit is coupled to the first bit line and the second node;

[0008] The second switching unit is coupled to the second bit line and the fourth node;

[0009] In the sense amplifier, the second node and the fourth node discharge to different potentials during the discharge phase, which causes the first node and the third node to have different discharge rates during the read phase.

[0010] In some embodiments, the sense amplifier further includes an enable signal line;

[0011] The enable signal line is configured to transmit an enable signal;

[0012] The first switching unit and the second switching unit are also respectively coupled to the enable signal line and are configured to be turned on when the enable signal is low and turned off when the enable signal is high.

[0013] In some embodiments, the first switching unit includes: a first transistor; wherein...

[0014] The gate of the first transistor is coupled to the enable signal line, the second end of the first transistor is coupled to the second node, and the first end of the first transistor is coupled to the first bit line.

[0015] The first transistor is configured to be turned on when the enable signal transmitted by the received enable signal line is at a logic low level, so as to connect the first bit line to the second node.

[0016] In some embodiments, the second switching unit includes: a second transistor; wherein...

[0017] The gate of the second transistor is coupled to the enable signal line, the second terminal of the second transistor is coupled to the fourth node, and the first terminal of the second transistor is coupled to the second bit line.

[0018] The second transistor is configured to be turned on when the enable signal transmitted by the received enable signal line is at a logic low level, so as to connect the second bit line to the fourth node.

[0019] In some embodiments, both the first switching unit and the second switching unit include a P-type transistor.

[0020] In some embodiments, the readout unit includes: a third transistor and a fourth transistor; wherein,

[0021] The gates of the third transistor and the fourth transistor are both coupled to the enable signal line. The first terminal of the third transistor is coupled to the first bit line, and the second terminal of the third transistor is coupled to the first node. The first terminal of the fourth transistor is coupled to the second bit line, and the second terminal of the fourth transistor is coupled to the third node.

[0022] The third transistor is configured to be turned on when the received enable signal is at a logic low level, so that the first bit line is coupled to the first node;

[0023] The fourth transistor is configured to be turned on when the received enable signal is at a logic low level, so that the second bit line is coupled to the third node.

[0024] In some embodiments, the first switching unit includes: a fifth transistor; wherein...

[0025] The gate of the fifth transistor is coupled to the enable signal line, the second terminal of the fifth transistor is coupled to the second node, and the first terminal of the fifth transistor is coupled to the first node.

[0026] The fifth transistor is configured to be turned on when the enable signal transmitted by the received enable signal line is at a logic low level, so as to connect the first bit line to the second node.

[0027] In some embodiments, the second switching unit includes: a sixth transistor; wherein...

[0028] The gate of the sixth transistor is coupled to the enable signal line, the second terminal of the sixth transistor is coupled to the fourth node, and the first terminal of the sixth transistor is coupled to the third node.

[0029] The sixth transistor is configured to be turned on when the enable signal transmitted by the received enable signal line is at a logic low level, so as to connect the second bit line to the fourth node.

[0030] In some embodiments, the readout unit includes: a first inverter, a second inverter, and a bypass transistor unit; wherein,

[0031] The input terminal of the first inverter is coupled to the output terminal of the second inverter, and the output terminal of the first inverter is coupled to the input terminal of the second inverter.

[0032] The output terminals of the first inverter and the second inverter are respectively coupled to the input terminal of the bypass transistor unit, and the output terminal of the bypass transistor unit is grounded.

[0033] In some embodiments, the first inverter includes a seventh transistor and an eighth transistor, and the second inverter includes a ninth transistor and a tenth transistor; wherein...

[0034] The gates of the seventh transistor and the eighth transistor are coupled to the output terminal of the second inverter. The first terminal of the seventh transistor is coupled to the first voltage terminal. The second terminals of the seventh transistor and the eighth transistor are coupled to the first node. The first terminal of the eighth transistor is coupled to the second node.

[0035] The gates of the ninth transistor and the tenth transistor are coupled to the output terminal of the first inverter. The first terminal of the ninth transistor is coupled to the first voltage terminal. The second terminals of the ninth transistor and the tenth transistor are coupled to the third node. The first terminal of the tenth transistor is coupled to the fourth node.

[0036] In some embodiments, the seventh and ninth transistors comprise P-type transistors, and the eighth and tenth transistors comprise N-type transistors.

[0037] In some embodiments, the bypass transistor unit includes a first bypass transistor, a second bypass transistor, and a third bypass transistor; wherein,

[0038] The gate of the first bypass transistor is coupled to the first bit line, and the second terminal of the first bypass transistor is coupled to the output terminal of the first inverter.

[0039] The gate of the second bypass transistor is coupled to the second bit line, and the second terminal of the second bypass transistor is coupled to the output terminal of the second inverter.

[0040] The first terminal of the first bypass transistor and the first terminal of the second bypass transistor are coupled to the second terminal of the third bypass transistor. The first terminal of the third bypass transistor is grounded, and the gate of the third bypass transistor is coupled to the enable signal line.

[0041] In some embodiments, the first bypass transistor, the second bypass transistor, and the third bypass transistor all include N-type transistors.

[0042] According to a second aspect of the present disclosure, a memory is provided, comprising: a plurality of memory cells and a readout amplifier as described in the above embodiments; wherein...

[0043] The storage unit, coupled to the sense amplifier, is configured to store data;

[0044] The readout amplifier is configured to read data stored in the storage unit and amplify the data.

[0045] In some embodiments, the memory includes static random access memory, and the storage unit includes a static random access memory unit.

[0046] In some embodiments, the static random access memory cell includes a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; wherein,

[0047] The gate of the first PMOS transistor is coupled to the gate of the first NMOS transistor, the first terminal of the first PMOS transistor is coupled to the first voltage terminal, the second terminal of the first PMOS transistor is coupled to the second terminal of the first NMOS transistor, and the first terminal of the first NMOS transistor is grounded.

[0048] The gate of the second PMOS transistor is coupled to the gate of the second NMOS transistor, the first end of the second PMOS transistor is coupled to the first voltage terminal, the second end of the second PMOS transistor is coupled to the second end of the second NMOS transistor, and the first end of the second NMOS transistor is grounded.

[0049] The gate of the third NMOS transistor is coupled to the select word line, the first end of the third NMOS transistor is coupled to the first bit line, the second end of the third NMOS transistor is coupled to the second end of the first PMOS transistor, the gate of the fourth NMOS transistor is coupled to the select word line, the first end of the fourth NMOS transistor is coupled to the second bit line, and the second end of the fourth NMOS transistor is coupled to the second end of the second PMOS transistor.

[0050] According to a third aspect of the present disclosure, a memory system is provided, including a memory as described in the above embodiments, and a memory controller; wherein,

[0051] The memory;

[0052] The memory controller, coupled to the memory, is configured to control the memory.

[0053] According to a fourth aspect of the present disclosure, a method for operating a readout amplifier is provided, the method comprising:

[0054] During the pre-charging phase, the first bit line and the second bit line are pre-charged to the first voltage;

[0055] During the discharge phase, when the first switching unit and the second switching unit are turned on, the first bit line is coupled to the second node and the second bit line is coupled to the fourth node, so that the second node and the fourth node discharge to different potentials;

[0056] During the reading phase, when the first and second switching units are turned off, the first node and the third node discharge at different discharge rates.

[0057] In the readout amplifier of this embodiment, the readout unit includes a first node, a second node, a third node, and a fourth node. The first node is coupled to a first bit line, the second node is coupled to the first bit line via a first switching unit, the third node is coupled to a second bit line, and the fourth node is coupled to the second bit line via a second switching unit. Instead of the second and fourth nodes discharging to the same potential during the discharge phase, which could lead to readout errors due to manufacturing defects in the readout amplifier, this embodiment addresses this issue by having the first and second switching units conduct during the discharge phase, with the first bit line coupled to the second node and the second bit line coupled to the fourth node, causing the second and fourth nodes to discharge to different potentials. During the readout phase, the different potentials of the second and fourth nodes result in different discharge rates for the first and third nodes, reducing the probability of readout errors and improving the accuracy of the readout data. Attached Figure Description

[0058] Figure 1This is a schematic diagram of the circuit structure of a readout amplifier according to an exemplary embodiment;

[0059] Figure 2 for Figure 1 The diagram shows the timing sequence of the readout amplifier during the read operation.

[0060] Figure 3 This is a schematic diagram illustrating a storage unit according to an exemplary embodiment;

[0061] Figure 4 for Figure 1 Another timing diagram of the readout amplifier during the read operation is shown below;

[0062] Figure 5a This is a schematic diagram of a first circuit structure of another readout amplifier according to an exemplary embodiment;

[0063] Figure 5b This is a schematic diagram of a second circuit structure for another readout amplifier according to an exemplary embodiment;

[0064] Figure 6 for Figure 5a or Figure 5b The diagram shows the timing sequence of another readout amplifier during the readout operation.

[0065] Figure 7 This is a schematic diagram illustrating a memory according to an exemplary embodiment;

[0066] Figure 8 This is a schematic diagram illustrating a memory system according to an exemplary embodiment;

[0067] Figure 9a This is a schematic diagram illustrating a memory card according to an exemplary embodiment;

[0068] Figure 9b This is a schematic diagram illustrating a solid-state drive (SSD) according to an exemplary embodiment;

[0069] Figure 10 This is a flowchart illustrating an operation method of a readout amplifier according to an exemplary embodiment. Detailed Implementation

[0070] The technical solution of this disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0071] In this embodiment of the disclosure, the terms "first," "second," etc., are used to distinguish similar objects, and not to describe a specific order or sequence.

[0072] In this embodiment of the disclosure, the term "A in contact with B" includes the case where A and B are in direct contact, or the case where there are other components between A and B and A is indirectly in contact with B.

[0073] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of a continuous structure. Layers may extend horizontally, vertically, and / or along inclined surfaces. Furthermore, a layer may comprise multiple sublayers.

[0074] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0075] Static Random Access Memory (SRAM) is commonly used in computer devices for temporary data storage. As long as a continuous power supply is provided, the stored data can be continuously stored without any update operations. To prevent the loss of internally stored data, compared to Dynamic Random Access Memory (DRAM) circuits, SRAM does not require periodic refresh and charging. Therefore, SRAM circuits have higher performance and lower power consumption.

[0076] The sense amplifier is a crucial component of Static Random Access Memory (SRAM). Since reading data from an SRAM typically takes longer than writing data, the speed of an SRAM is primarily determined by the read time. During data read operations, the numerous memory cells connected to the bit lines result in significant capacitance on those lines. This slows down the charging and discharging processes of the bit lines, impacting the data read speed. The sense amplifier amplifies the minute voltage swings on the SRAM bit lines to the level of digital signals, thus accelerating the read speed and reducing voltage swings on the bit lines, significantly minimizing power consumption related to charging and discharging.

[0077] There are two main types of readout amplifiers: voltage-mode amplifiers and current-mode amplifiers. The main characteristic of a voltage-mode amplifier is that it detects and amplifies the voltage difference on the bit line. The main characteristic of a current-mode amplifier is that it detects and amplifies the current difference on the bit line. Current-mode amplifiers are not affected by capacitance or load on the bit line, but their circuit structure is more complex, their reliability is lower, and their power consumption is higher. Although voltage-mode amplifiers are affected by capacitance and load on the bit line, they have a simpler structure, higher stability, and lower power consumption. Here, we will use voltage-mode amplifiers as an example for explanation.

[0078] Voltage-source amplifiers mainly include operational amplifiers, cross-coupled amplifiers, and latching amplifiers. Here, we will take the latching amplifier, which has a fast readout speed, as an example for explanation.

[0079] When reading data from SRAM, it is necessary to use, such as Figure 1 Similar amplifiers, see reference Figure 1 , Figure 2 and Figure 3 The specific operation instructions for reading data from SRAM are as follows:

[0080] according to Figure 2 As shown, during the first time period T1, the select word line SEL is set to logic low (e.g., "0"). The precharge signal pre_n is then set to logic low, precharging the first bit line BT and the second bit line BB to voltage VDD. Next, the precharge signal pre_n is set to logic high (e.g., "1"), maintaining voltage VDD for the first bit line BT and the second bit line BB. During the second time period T2, the precharge signal pre_n remains logic high. During this time, the select word line SEL is set to logic high. (Refer to...) Figure 3 If the data stored in the storage cell is represented with voltage d = 1 and voltage d_n = 0, then the first bit line BT will maintain voltage VDD, and the second bit line BB will gradually discharge to voltage VP (for example, if the discharge is controlled to be 200mV, then voltage VP is VDD-200mV).

[0081] according to Figure 1 As shown, node dp is coupled to the voltage VDD terminal through transistors MN2 and MP0, and node dp_n is coupled to the voltage VDD terminal through transistors MN3 and MP1. Figure 2 As shown, nodes dp and dp_n maintain voltage VDD-V before the third time period T3. THN , where V THN This is the threshold voltage of transistor MN3 or transistor MN2.

[0082] exist Figure 1In the first time period, when the enable signal line EN is set to low, transistors MP2 and MP3 are turned on. The voltage of node sou follows the voltage of the second bit line BB, and the voltage of node sou_n follows the voltage of the first bit line BT. After the second time period T2 ends, the second bit line BB discharges to voltage VP (approximately VDD-200mV), while the first bit line BT maintains voltage VDD. At this time, the voltage of node sou also becomes voltage VP, and the voltage of node sou_n is voltage VDD. During the third time period T3, the enable signal line EN is set to logic high, transistors MP2 and MP3 are turned off, and transistors MN0, MN1, and M_EN form a discharge path. At this time, nodes dp, sou, dp_n, and sou_n discharge.

[0083] During the discharge phase, since the voltage of node sou is lower than that of node sou_n, and the voltages of nodes dp and dp_n are the same, the voltage difference between nodes dp and sou is less than the voltage difference between nodes dp_n and sou_n. Therefore, nodes dp and sou discharge faster than nodes dp_n and sou_n. (Reference) Figure 2 Finally, the voltage of the sout node is 0 and the voltage of the sout_n node is 1. The differential signal output by the read amplifier (the voltage of the sout node is 0 and the voltage of the sout_n node is 1) is converted into a single-ended voltage signal output by the output circuit (not shown) to complete the read operation.

[0084] but, Figure 1 The SRAM readout circuit shown has a read error problem, which affects the readout reliability of the SRAM.

[0085] Specifically, both node dp and node dp_n originate from the voltage VDD-V THN Discharge, reference Figure 1 and Figure 4 Due to manufacturing errors in transistor production, such as transistors MN0 and MN2 being smaller than their design dimensions, their discharge capabilities are weaker than those of transistors MN1 and MN3. If the discharge charge at voltage VP on the second bit line BB is insufficient (i.e., VP is not low enough relative to VDD – for example, the voltage difference between VP and VDD is less than or equal to 100mV), nodes dp and sou may discharge more slowly than nodes dp_n and sou_n. (Refer to...) Figure 4 Finally, the voltage of the sout node is 1, and the voltage of the sout_n node is 0. Here, the discharge capacity of the second bit line BB when it discharges to voltage VP is related to the specific manufacturing process.

[0086] Based on the above analysis, a correct read operation should output a voltage of 0 for the sout node and a voltage of 1 for the sout_n node. Figure 4 The voltage of the sout node is 1, and the voltage of the sout_n node is 0, indicating a read error.

[0087] In view of this, embodiments of the present disclosure provide another readout amplifier.

[0088] Figure 5a This is a schematic diagram of a first circuit structure for another sense amplifier according to an exemplary embodiment. (Refer to...) Figure 5a As shown, the readout amplifier 100 includes: a precharge unit 101, a readout unit 102, a first switching unit 103, and a second switching unit 104; wherein,

[0089] The precharge unit 101 is coupled to the first bit line BT of the memory cell and the second bit line BB of the memory cell;

[0090] The readout unit 102 includes a first node sou_n, a second node dp_n, a third node sou, and a fourth node dp; wherein, the first bit line BT is coupled to the first node sou_n, and the second bit line BB is coupled to the third node sou;

[0091] The first switching unit 103 is coupled to the first bit line BT and the second node dp_n;

[0092] The second switching unit 104 is coupled to the second bit line BB and the fourth node dp;

[0093] In the readout amplifier, the second node dp_n and the fourth node dp discharge to different potentials during the discharge phase, which affects the discharge rate of the first node sou_n and the third node sou during the readout phase.

[0094] Here, in response to... Figure 3 The operation of the readout amplifier 100 is illustrated by performing a read operation on the storage unit shown. Figure 3 The basic structure of the memory cell shown includes six transistors (e.g., Figure 3 Transistors P1 to P6 are used to select word line SEL, first bit line BT, and second bit line BB. Data is stored in the memory cell by two cross-coupled inverters (e.g.,...). Figure 3 (It consists of transistors P1 to P4). Figure 3 The storage cell shown has two stable states (e.g., logical states "1" or "0") to indicate the stored data information. Specifically, the logical state is represented by the voltage of node d and the voltage of node d_n. Figure 3The storage unit shown also includes transistors P5 and P6, which are used to control read and write operations on the storage unit.

[0095] When using a read amplifier to read and amplify data stored in a memory cell, the process can include a pre-charge phase, a discharge phase, and a read phase. Specifically, the pre-charge phase (e.g., ...) Figure 6 During the first time period T1, the first bit line BT and the second bit line BB are pre-charged to a first voltage. For example, the first bit line BT and the second bit line BB can be pre-charged to a stable voltage VDD by the pre-charge unit 101. During the discharge phase (e.g. Figure 6 During the second time period (T2), either the first bit line BT or the second bit line BB discharges. Specifically, the pre-charge signal terminal pre_n remains at a logic high level, the select word line SEL is set to a logic high level, and either the first bit line BT or the second bit line BB discharges according to the data stored in the memory cell. During the discharge phase (e.g. Figure 6 During the second time period T2), when the first switching unit 103 and the second switching unit 104 are turned on, the first bit line BT is coupled to the second node dp_n and the second bit line BB is coupled to the fourth node dp, so that the second node dp_n and the fourth node dp follow the bit line voltages of the first bit line BT and the second bit line BB respectively during the discharge phase, thereby discharging to different potentials. During the reading phase (e.g. Figure 6 During the third time period (T3), when the first switching unit 103 and the second switching unit 104 are turned off, the different potentials of the second node dp_n and the fourth node dp will cause the first node sou_n and the third node sou to have different discharge rates during the reading phase. For example, if the potential of the second node dp_n is higher than that of the fourth node dp, the discharge rate of the first node sou_n during the reading phase will be slower than that of the third node sou; if the potential of the second node dp_n is lower than that of the fourth node dp, the discharge rate of the first node sou_n during the reading phase will be faster than that of the third node sou. Thus, by causing the second node dp_n and the fourth node dp to discharge to different potentials during the discharge phase, the difference in discharge rates between the first node sou_n and the third node sou during the reading phase can be increased.

[0096] For example, the illustration will be given with node d having a high voltage level ("1") and node d_n having a low voltage level ("0"). (See reference...) Figure 5a and Figure 6The process of reading from the storage unit may include a first time period T1, a second time period T2, and a third time period T3. The first time period T1 is the pre-charging stage of the first bit line BT and the second bit line BB. The second time period T2 is the discharge stage of the first switching unit 103 and the second switching unit 104 being turned on and the first bit line BT or the second bit line BB being discharged. The third time period T3 is the discharge stage of the first switching unit 103 and the second switching unit 104 being turned off and the nodes (first node sou_n, second node dp_n, third node sou, and fourth node dp) in the read unit 102 being discharged.

[0097] Specifically, pre-charging is performed during the first time period T1, and the first bit line BT and the second bit line BB are pre-charged to a stable voltage by the pre-charging unit 101. See reference [link to relevant documentation]. Figure 3 and Figure 6 During the first time period T1, the first voltage terminal VDD and the first bit line BT, the first voltage terminal VDD and the second bit line BB are respectively turned on by the pre-charge signal terminal pre_n, so that the first bit line BT and the second bit line BB are pre-charged to the first voltage VDD.

[0098] After precharging is complete, refer to Figure 3 and Figure 6 During the second time period T2, either the first bit line BT or the second bit line BB discharges. Specifically, the precharge signal terminal pre_n remains at a logic high level, and the select word line SEL is set to a logic high level at this time. (Refer to...) Figure 3 Since the voltage of node d is high ("1") and the voltage of node d_n is low ("0"), at this time, the first bit line BT will maintain the first voltage VDD, and the second bit line BB will gradually discharge to the second voltage VP (for example, if the discharge is controlled to be 200mV, then the voltage VP is VDD-200mV).

[0099] For example, the first voltage VDD includes 3.3V. In other embodiments, those skilled in the art can adjust the parameters of the first voltage VDD according to the actual application environment and circuit parameters.

[0100] The first switching unit 103 is gradually turned on during the first time period T1 of the read operation and remains on during the second time period T2, so that the second node dp_n is coupled to the first bit line BT, and the voltage of the second node dp_n is the first voltage VDD. The second switching unit 104 is gradually turned on during the first time period T1 of the read operation and remains on during the second time period T2, so that the fourth node dp is coupled to the second bit line BB, and the voltage of the fourth node dp is the second voltage VP. Then, during the third time period T3, the first switching unit 103 and the second switching unit 104 are in the off state, and the first node sou_n, the second node dp_n, the third node sou, and the fourth node dp in the read unit 102 are discharged.

[0101] Specifically, the first node sou_n and the second node dp_n discharge from the first voltage VDD, while the third node sou and the fourth node dp discharge from the second voltage VP. Based on the above analysis, the first voltage VDD is greater than the second voltage VP; therefore, the third node sou and the fourth node dp discharge faster than the first node sou_n and the second node dp_n. Figure 6 The voltages of the third node sout and the fourth node dp drop to 0 first. Therefore, the reading unit 102 collects the voltages of the first node sout_n and the third node sout based on the fact that the voltage of the second node dp_n drops to 0 first compared to the voltage of the fourth node dp. Finally, the voltage of the sout node is 0 and the voltage of the sout_n node is 1, so the reading is correct.

[0102] like Figure 6 As shown, between the second time period T2 and the third time period T3, there may also be an interval time period in which the first node sou_n and the second node dp_n maintain the first voltage VDD, and the voltages of the third node sou and the fourth node dp continue to decrease, so that at the beginning of the third time period T3, the voltages of the third node sou and the fourth node dp are the second voltage VP.

[0103] It is understood that, similar to the reading process where the voltage of node d is high ("1") and the voltage of node d_n is low ("0"), if the voltage of node d in the memory cell is low ("0") and the voltage of node d_n is high ("1"), the specific process of performing the read operation through the read amplifier proposed in this embodiment can be analyzed and derived in conjunction with the reading process where the voltage of node d is high ("1") and the voltage of node d_n is low ("0"), and will not be repeated here.

[0104] In the sense amplifier proposed in this embodiment, during the discharge process, the third node sou and the fourth node dp both discharge from the second voltage VP, while the first node sou_n and the second node dp_n both discharge from the first voltage VDD. Even if the actual manufacturing error of the sense amplifier causes the third node sou and the fourth node dp to discharge slower than the first node sou_n and the second node dp_n, since the second voltage VP is less than the first voltage VDD, even if the voltage VP is not low enough compared to the voltage VDD (e.g., VDD-VP is less than or equal to 100mV), the difference between the sum of the voltages of the third node sou and the fourth node dp and the sum of the voltages of the first node sou_n and the second node dp_n is 2*(VDD-VP), which is much larger than the difference between the first voltage VDD and the second voltage VP. Therefore, the third node sou and the fourth node dp discharge faster than the first node sou_n and the second node dp_n, which can achieve correct data readout and improve the readout accuracy of the sense amplifier.

[0105] In some embodiments, reference Figure 5a or Figure 5b The readout amplifier also includes the enable signal line EN;

[0106] The enable signal line EN is configured to transmit an enable signal;

[0107] The first switching unit 103 and the second switching unit 104 are also coupled to the enable signal line EN, and are configured to be turned on when the enable signal is low and turned off when the enable signal is high.

[0108] Here, the first switching unit 103 and the second switching unit 104 can be turned on or off via the enable signal line EN. When the enable signal is low, the first switching unit 103 is turned on, coupling the second node dp_n to the first bit line BT, and the second switching unit 104 is turned on, coupling the fourth node dp to the second bit line BB, so that the voltage of the fourth node dp is less than the voltage of the second node dp_n, further increasing the voltage difference between the third node sou and the fourth node dp and the first node sou_n and the second node dp_n.

[0109] In some embodiments, the acquisition process of the first bit line BT voltage and the second bit line BB voltage by the readout unit 102 can also be controlled by the enable signal line EN. Specifically, when the enable signal transmitted by the enable signal line EN is at a low level, the readout unit 102 is controlled by the enable signal to acquire the voltage of the first bit line BT and the voltage of the second bit line BB. The readout amplifier 100 can acquire the voltage of the first bit line BT and the voltage of the second bit line BB, and amplify the voltage difference between the first bit line BT and the second bit line BB, thereby reading the data information stored in the storage unit.

[0110] The readout amplifier proposed in this embodiment synchronously controls the on / off state of the first switching unit 103 and the second switching unit 104 through the enable signal transmitted by the enable signal line EN. When the first switching unit 103 and the second switching unit 104 are synchronously turned on, the voltage of the fourth node dp and the voltage of the second node dp_n are synchronously adjusted. Compared with adding multiple enable signal lines to control the first switching unit 103 and the second switching unit 104 respectively, in this embodiment, the first switching unit 103 and the second switching unit 104 are coupled to the same enable signal line, which reduces the impact of time delay on the voltage changes of the fourth node dp and the second node dp_n, thereby improving the accuracy of the readout operation. In addition, the method of coupling different switching units to the same enable signal line helps to reduce the occupied area of ​​the readout amplifier and reduce the power consumption of the readout amplifier. When the enable signal is low, the first switching unit 103 and the second switching unit 104 are turned on to regulate the voltage of the fourth node dp and the second node dp_n. This makes the voltage of the third node sou and the fourth node dp smaller than the voltage of the first node sou_n and the second node dp_n. Therefore, the third node sou and the fourth node dp discharge faster than the first node sou_n and the second node dp_n, which can achieve correct data reading and improve the readout accuracy of the readout amplifier.

[0111] In some embodiments, reference Figure 5a The first switching unit 103 includes: a first transistor Q1; wherein,

[0112] The gate of the first transistor Q1 is coupled to the enable signal line EN, the second terminal of the first transistor Q1 is coupled to the second node dp_n, and the first terminal of the first transistor Q1 is coupled to the first bit line BT.

[0113] The first transistor Q1 is configured to be turned on when the enable signal transmitted by the received enable signal line EN is at a logic low level, so as to connect the first bit line BT with the second node dp_n.

[0114] It should be noted that the first terminal and the second terminal are the source and drain of the transistor, respectively. In one example, the first terminal is the source of the transistor, and the second terminal is the drain. In another example, the first terminal is the drain of the transistor, and the second terminal is the source. The gate of the first transistor Q1 can be coupled to the enable signal line EN, which is the read enable signal line in the sense amplifier, or the gate of the first transistor Q1 can be coupled to other signal lines, controlling the turn-off or turn-on of the first switching unit 103 according to the high or low level output of other signal lines. Here, the example of the first transistor Q1 being coupled to the enable signal line EN is used for explanation.

[0115] refer to Figure 1 and Figure 2 As shown, nodes dp and dp_n maintain voltage VDD-V before the third time period T3. THN The voltage of node dp is the same as the voltage of node dp_n. In this embodiment, the first transistor Q1 is turned on when the enable signal is low, so that the first bit line BT is connected to the second node dp_n, and the voltage of the second node dp_n becomes the voltage VDD of the first bit line BT. Furthermore, the second switching unit 104 is turned on, so that the fourth node dp is coupled to the second bit line BB, and the voltage of the fourth node dp becomes the voltage VP of the second bit line BB.

[0116] Therefore, the first transistor Q1 is turned on when the enable signal is low, thereby regulating the voltage of the second node dp_n so that the voltage of the fourth node dp is different from the voltage of the second node dp_n, and the voltage of the fourth node dp is less than the voltage of the second node dp_n. This results in the voltage of the third node sou and the voltage of the fourth node dp being smaller than the voltage of the first node sou_n and the voltage of the second node dp_n.

[0117] It should be noted that the reference Figure 5a The size of the first transistor Q1 is related to the size of the eighth transistor Q8 and the size of the second bypass transistor M2.

[0118] Specifically, in one embodiment, the gate length of the first transistor Q1, the gate length of the eighth transistor Q8, and the gate length of the second bypass transistor M2 are the same, and the gate width of the first transistor Q1 is one-third or one-quarter of the sum of the gate widths of the eighth transistor Q8 and the second bypass transistor M2. In another embodiment, the gate length of the first transistor Q1 is one-third or one-quarter of the sum of the gate lengths of the eighth transistor Q8 and the second bypass transistor M2, and the gate width of the first transistor Q1 is one-third or one-quarter of the sum of the gate widths of the eighth transistor Q8 and the second bypass transistor M2.

[0119] It is understood that the dimensions of the first transistor Q1 are illustrated herein by way of example, and the dimensions of the first transistor Q1 may be adjusted according to actual design requirements to meet the requirements for completing the required discharge or charge within a specified time.

[0120] The sense amplifier proposed in this embodiment uses a first transistor Q1 that conducts when the enable signal is low, thereby regulating the voltage of the second node dp_n. This ensures that the voltages of the third node sou and the fourth node dp are lower than the voltages of the first node sou_n and the second node dp_n. Therefore, the third node sou and the fourth node dp discharge faster than the first node sou_n and the second node dp_n, enabling accurate data readout and improving the readout accuracy of the sense amplifier. Furthermore, compared to adding multiple transistors to achieve this function, adding only one first transistor Q1 reduces the size of the sense amplifier and lowers its power consumption.

[0121] In some embodiments, reference Figure 5a The second switching unit includes: a second transistor Q2; wherein,

[0122] The gate of the second transistor Q2 is coupled to the enable signal line EN, the second terminal of the second transistor Q2 is coupled to the fourth node dp, and the first terminal of the second transistor Q2 is coupled to the second bit line BB.

[0123] The second transistor Q2 is configured to be turned on when the enable signal transmitted by the received enable signal line EN is at a logic low level, so as to connect the second bit line BB with the fourth node dp.

[0124] It should be noted that the gate of the second transistor Q2 is coupled to the enable signal line EN, which is the read enable signal line in the sense amplifier. Alternatively, the gate of the second transistor Q2 can be coupled to other signal lines, and the high or low level output of other signal lines controls the turn-off or turn-on of the second switching unit 104. Here, the example of the second transistor Q2 being coupled to the enable signal line EN is used for explanation.

[0125] Here, the second transistor Q2 is turned on when the enable signal is low, so that the second bit line BB is connected to the fourth node dp, and the voltage of the fourth node dp becomes the voltage VP of the second bit line BB. In one embodiment, the first switching unit 103 is also controlled to be turned on, so that the voltage of the second node dp_n becomes the voltage VDD of the first bit line BT.

[0126] Therefore, the second transistor Q2 is turned on when the enable signal is low, thereby regulating the voltage of the fourth node dp so that the voltage of the fourth node dp is different from the voltage of the second node dp_n, and the voltage of the fourth node dp is less than the voltage of the second node dp_n. This results in the voltage of the third node sou and the voltage of the fourth node dp being smaller than the voltage of the first node sou_n and the voltage of the second node dp_n.

[0127] It should be noted that the reference Figure 5aThe size of the second transistor Q2 is related to the size of the tenth transistor Q10 and the size of the first bypass transistor M1.

[0128] Specifically, in one embodiment, the gate lengths of the second transistor Q2, the tenth transistor Q10, and the first bypass transistor M1 are the same, and the gate width of the second transistor Q2 is one-third or one-quarter of the sum of the gate widths of the tenth transistor Q10 and the first bypass transistor M1. In another embodiment, the gate length of the second transistor Q2 is one-third or one-quarter of the sum of the gate lengths of the tenth transistor Q10 and the first bypass transistor M1, and the gate width of the second transistor Q2 is one-third or one-quarter of the sum of the gate widths of the tenth transistor Q10 and the first bypass transistor M1.

[0129] It is understood that the dimensions of the second transistor Q2 are illustrated herein by way of example, and the dimensions of the second transistor Q2 can be adjusted according to actual design requirements to meet the requirements for completing the required discharge or charge within a specified time.

[0130] In the sense amplifier proposed in this embodiment, the second transistor Q2 is turned on when the enable signal is low, thereby regulating the voltage of the fourth node dp. This ensures that the voltages of the third node sou and the fourth node dp are lower than the voltages of the first node sou_n and the second node dp_n. Therefore, the third node sou and the fourth node dp discharge faster than the first node sou_n and the second node dp_n, enabling accurate data readout and improving the readout accuracy of the sense amplifier. Furthermore, compared to adding multiple transistors to achieve this function, adding only one second transistor Q2 reduces the footprint and power consumption of the sense amplifier.

[0131] In some embodiments, reference Figure 5a Both the first switching unit 103 and the second switching unit 104 include P-type transistors.

[0132] It should be noted that before the first node sou_n, the second node dp_n, the third node sou, and the fourth node dp discharge, the enable signal transmitted by the enable signal line EN is set to a low level ("0"). In order to enable the first switching unit 103 to be turned on when the enable signal is at a logic low level ("0"), the first switching unit 103 preferably includes a P-type transistor.

[0133] Understandably, the first switching unit 103 may also include multiple transistors to enable conduction when the enable signal is at a logic low level (“0”).

[0134] The specific configuration of the second switching unit 104 is the same as that of the first switching unit 103 described above, and will not be repeated here.

[0135] In this embodiment, the first switching unit 103 preferably includes a P-type transistor. This preferred method not only enables the transistor to be turned on when the enable signal is low, so that the first bit line BT is connected to the second node dp_n, but also reduces the area occupied by the sense amplifier and the power consumption of the sense amplifier compared to adding multiple transistors to achieve this function.

[0136] In some embodiments, reference Figure 5a or Figure 5b The readout unit 102 includes: a third transistor Q3 and a fourth transistor Q4; wherein,

[0137] The gates of the third transistor Q3 and the fourth transistor Q4 are both coupled to the enable signal line EN. The first terminal of the third transistor Q3 is coupled to the first bit line BT, and the second terminal of the third transistor Q3 is coupled to the first node sou_n. The first terminal of the fourth transistor Q4 is coupled to the second bit line BB, and the second terminal of the fourth transistor Q4 is coupled to the third node sou.

[0138] The third transistor Q3 is configured to be turned on when the received enable signal is logic low, so that the first bit line BT is coupled to the first node sout_n;

[0139] The fourth transistor Q4 is configured to be turned on when the received enable signal is logic low, so that the second bit line BB is coupled to the third node sout.

[0140] Here, we will take the voltage-type sense amplifier 100 as an example for explanation.

[0141] For example, the sense amplifier 100 acquires the voltage value transmitted on the first bit line BT through the third transistor Q3 and acquires the voltage value on the second bit line BB through the fourth transistor Q4. Therefore, the voltage difference between the first bit line BT and the second bit line BB can be acquired and amplified by the sense unit 102 of the sense amplifier 100.

[0142] Specifically, before the first node sou_n, the second node dp_n, the third node sou, and the fourth node dp discharge, the enable signal transmitted by the enable signal line EN is set to a low level ("0"). The third transistor Q3 is then turned on during the read operation via the enable signal line EN, so that the first node sou_n is coupled to the first bit line BT, and the voltage of the first node sou_n is the first voltage VDD. The fourth transistor Q4 is then turned on during the read operation via the enable signal line EN, so that the third node sou is coupled to the second bit line BB, and the voltage of the third node sou is the second voltage VP.

[0143] Set the enable signal transmitted by the enable signal line EN to a high level ("1"), and discharge the first node sou_n, the second node dp_n, the third node sou, and the fourth node dp in the readout unit 102.

[0144] Specifically, the first node sou_n and the second node dp_n discharge from the first voltage VDD, and the third node sou and the fourth node dp discharge from the second voltage VP.

[0145] In this embodiment, a voltage-type sense amplifier 100 is preferably used to read stored data information. The third transistor Q3 in the sense unit 102 acquires the voltage value transmitted on the first bit line BT, and the fourth transistor Q4 acquires the voltage value on the second bit line BB. The voltage-type sense amplifier 100 can acquire and amplify the voltage difference between the first bit line BT and the second bit line BB, and has the advantages of simple structure, high stability, and low power consumption.

[0146] In some embodiments, reference Figure 5b The first switching unit 103 includes: a fifth transistor Q5; wherein,

[0147] The gate of the fifth transistor Q5 is coupled to the enable signal line EN, the second terminal of the fifth transistor Q5 is coupled to the second node dp_n, and the first terminal of the fifth transistor Q5 is coupled to the first node sou_n.

[0148] The fifth transistor Q5 is configured to be turned on when the enable signal transmitted by the received enable signal line EN is at a logic low level, so as to connect the first bit line BT with the second node dp_n.

[0149] Here, for reference Figure 5b The first line BT is coupled to the first node sou_n through the third transistor Q3, and the first line BT is coupled to the second node dp_n through the third transistor Q3 and the fifth transistor Q5.

[0150] In this embodiment, the fifth transistor Q5 and the third transistor Q3 are turned on when the enable signal is low, so that the first bit line BT is connected to the second node dp_n, and the voltage of the second node dp_n becomes the voltage VDD of the first bit line BT. Furthermore, the second switching unit 104 is turned on, so that the fourth node dp is coupled to the second bit line BB through the fourth transistor Q4, and the voltage of the fourth node dp becomes the voltage VP of the second bit line BB.

[0151] Therefore, the fifth transistor Q5 is turned on when the enable signal is low, thereby regulating the voltage of the second node dp_n. This makes the voltage of the fourth node dp different from the voltage of the second node dp_n, and the voltage of the fourth node dp is less than the voltage of the second node dp_n. At this time, the difference between the sum of the voltages of the third node sou and the fourth node dp and the sum of the voltages of the first node sou_n and the second node dp_n is 2*(VDD-VP), which is much larger than the difference between the first voltage VDD and the second voltage VP. Therefore, the third node sou and the fourth node dp discharge faster than the first node sou_n and the second node dp_n.

[0152] It should be noted that the dimensions of the fifth transistor Q5 can be referenced above. Figure 5a The relevant descriptions of the first transistor Q1 are not repeated here.

[0153] In the sense amplifier proposed in this embodiment, the fifth transistor Q5 is turned on when the enable signal is low. Through the third transistor Q3 and the fifth transistor Q5, the voltage of the second node dp_n is regulated so that the voltages of the third node sou and the fourth node dp are lower than the voltages of the first node sou_n and the second node dp_n. Therefore, the third node sou and the fourth node dp discharge faster than the first node sou_n and the second node dp_n, enabling accurate data readout and improving the readout accuracy of the sense amplifier. Furthermore, compared to adding multiple transistors to achieve this function, adding only one fifth transistor Q5 reduces the area occupied by the sense amplifier and lowers its power consumption.

[0154] In some embodiments, reference Figure 5b The second switching unit 104 includes: a sixth transistor Q6; wherein,

[0155] The gate of the sixth transistor Q6 is coupled to the enable signal line EN, the second terminal of the sixth transistor Q6 is coupled to the fourth node dp, and the first terminal of the sixth transistor Q6 is coupled to the third node sou.

[0156] The sixth transistor Q6 is configured to be turned on when the enable signal transmitted by the received enable signal line EN is at a logic low level, so as to connect the second bit line BB to the fourth node dp.

[0157] Here, for reference Figure 5b The second bit line BB is coupled to the third node sout through the fourth transistor Q4, and the second bit line BB is coupled to the fourth node dp through the fourth transistor Q4 and the sixth transistor Q6.

[0158] In this embodiment, the fourth transistor Q4 and the sixth transistor Q6 are turned on when the enable signal is low, so that the second bit line BB is connected to the fourth node dp, and the voltage of the fourth node dp becomes the voltage VP of the second bit line BB. In one embodiment, the first switching unit 103 is also controlled to be turned on, so that the voltage of the second node dp_n becomes the voltage VDD of the first bit line BT.

[0159] Therefore, the sixth transistor Q6 is turned on when the enable signal is low, thereby regulating the voltage of the fourth node dp. This makes the voltage of the fourth node dp different from the voltage of the second node dp_n, and the voltage of the fourth node dp is less than the voltage of the second node dp_n. At this time, the difference between the sum of the voltages of the third node sou and the fourth node dp and the sum of the voltages of the first node sou_n and the second node dp_n is 2*(VDD-VP), which is much larger than the difference between the first voltage VDD and the second voltage VP. Therefore, the third node sou and the fourth node dp discharge faster than the first node sou_n and the second node dp_n.

[0160] It should be noted that the dimensions of the sixth transistor Q6 can be referenced above. Figure 5a The details regarding the second transistor Q2 are not repeated here.

[0161] In the sense amplifier proposed in this embodiment, the sixth transistor Q6 is turned on when the enable signal is low, thereby regulating the voltage of the fourth node dp. This ensures that the voltages of the third node sou and the fourth node dp are lower than the voltages of the first node sou_n and the second node dp_n. Therefore, the third node sou and the fourth node dp discharge faster than the first node sou_n and the second node dp_n, enabling accurate data readout and improving the readout accuracy of the sense amplifier. Furthermore, compared to adding multiple transistors to achieve this function, adding only a sixth transistor Q6 reduces the footprint and power consumption of the sense amplifier.

[0162] In some embodiments, reference Figure 5a or Figure 5b The readout unit 102 includes: a first inverter 1021, a second inverter 1022, and a bypass transistor unit 1023; wherein,

[0163] The input terminal of the first inverter 1021 is coupled to the output terminal of the second inverter 1022, and the output terminal of the first inverter 1021 is coupled to the input terminal of the second inverter 1022.

[0164] The output terminals of the first inverter 1021 and the second inverter 1022 are respectively coupled to the input terminal of the bypass transistor unit 1023, and the output terminal of the bypass transistor unit 1023 is grounded.

[0165] Here, we will take the voltage latch-type readout amplifier 100 as an example for explanation.

[0166] The voltage latch-type readout amplifier 100 can be constructed by interconnecting two CMOS inverters (e.g., the first inverter 1021 and the second inverter 1022) to form a latch, such as... Figure 5a or Figure 5b Transistors Q5 to Q8 are shown in the diagram. The output voltage signals of the first inverter 1021 and the second inverter 1022 can achieve a full swing. Since the larger the voltage signal swing, the more obvious the voltage signal fluctuation, and the easier it is to generate an effective output voltage signal, a voltage latching type sense amplifier 100 with an output voltage signal that can achieve a full swing is preferred.

[0167] In this embodiment, a voltage latching type readout amplifier 100 is preferred for reading out stored data information. The voltage difference between the first bit line BT and the second bit line BB is amplified by the first inverter 1021, the second inverter 1022 and the bypass transistor unit 1023. It has the advantages of fast readout speed and more effective output voltage signal.

[0168] In some embodiments, reference Figure 5a or Figure 5b The first inverter 1021 includes a seventh transistor Q7 and an eighth transistor Q8, and the second inverter 1022 includes a ninth transistor Q9 and a tenth transistor Q10; wherein,

[0169] The gates of the seventh transistor Q7 and the eighth transistor Q8 are coupled to the output of the second inverter 1022. The first terminal of the seventh transistor Q7 is coupled to the first voltage terminal. The second terminals of the seventh transistor Q7 and the eighth transistor Q8 are coupled to the first node sout_n. The first terminal of the eighth transistor Q8 is coupled to the second node dp_n.

[0170] The gates of the ninth transistor Q9 and the tenth transistor Q10 are coupled to the output of the first inverter 1021. The first terminal of the ninth transistor Q9 is coupled to the first voltage terminal. The second terminals of the ninth transistor Q9 and the tenth transistor Q10 are coupled to the third node sout. The first terminal of the tenth transistor Q10 is coupled to the fourth node dp.

[0171] Here, the seventh transistor Q7 and the eighth transistor Q8 in the first inverter 1021 are cross-coupled with the ninth transistor Q9 and the tenth transistor Q10 in the second inverter 1022 to latch the voltages provided by the first node sout_n and the third node sout, respectively, during the latching mode; wherein the latching mode includes the period during which the enable signal transmitted by the enable signal line EN is set to a low level (“0”).

[0172] After entering the latch mode, the read mode is entered. The enable signal transmitted by the enable signal line EN is set to a high level ("1"), and the first node sou_n, the second node dp_n, the third node sou, and the fourth node dp in the read unit 102 are discharged.

[0173] In this embodiment, to improve readout accuracy and enhance the performance of the readout amplifier 100, the transistor parameters in the first inverter 1021 and the second inverter 1022 can be adjusted. Specifically, the seventh transistor Q7 in the first inverter 1021 and the ninth transistor Q9 in the second inverter 1022 are set to have equal or substantially equal drive strengths. Similarly, the eighth transistor Q8 in the first inverter 1021 and the tenth transistor Q10 in the second inverter 1022 are set to have equal or substantially equal drive strengths.

[0174] In this embodiment, a voltage latching type readout amplifier 100 is preferred for reading out stored data information. The voltage difference between the first bit line BT and the second bit line BB is amplified by the first inverter 1021, the second inverter 1022 and the bypass transistor unit 1023. It has the advantages of fast readout speed and more effective output voltage signal.

[0175] In some embodiments, reference Figure 5a or Figure 5b The seventh transistor Q7 and the ninth transistor Q9 are P-type transistors, and the eighth transistor Q8 and the tenth transistor Q10 are N-type transistors.

[0176] For example, the seventh transistor Q7 and the ninth transistor Q9 are P-type transistors. When the gate voltage of these P-type transistors is below the threshold voltage, these P-type transistors will turn on and supply the positive voltage of the voltage terminal labeled "VDD" to the corresponding node (the first node sout_n and the third node sout), thereby achieving "pull-up drive" at that node. Since the seventh transistor Q7 and the ninth transistor Q9 are PMOS pull-up drives, the discharge of the first node sout_n and the third node sout will be very fast, thereby achieving the effect of speeding up the readout speed.

[0177] For example, the eighth transistor Q8 and the tenth transistor Q10 are N-type transistors. When the gate voltage of these N-type transistors exceeds the threshold voltage, these N-type transistors will turn on and discharge the corresponding nodes (the first node sout_n and the third node sout) to the ground terminal or a voltage terminal that provides a negative voltage.

[0178] In this embodiment, the seventh transistor Q7 and the ninth transistor Q9 are P-type transistors, and the eighth transistor Q8 and the tenth transistor Q10 are N-type transistors. By rapidly discharging the seventh transistor Q7, the ninth transistor Q9, the eighth transistor Q8, and the tenth transistor Q10, the reading speed is accelerated.

[0179] In some embodiments, reference Figure 5a or Figure 5b The bypass transistor unit 1023 includes a first bypass transistor M1, a second bypass transistor M2, and a third bypass transistor M3; wherein,

[0180] The gate of the first bypass transistor M1 is coupled to the first bit line BT, and the second terminal of the first bypass transistor M1 is coupled to the output terminal of the first inverter 1021.

[0181] The gate of the second bypass transistor M2 is coupled to the second bit line BB, and the second terminal of the second bypass transistor M2 is coupled to the output terminal of the second inverter 1022.

[0182] The first terminal of the first bypass transistor M1 and the first terminal of the second bypass transistor M2 are coupled to the second terminal of the third bypass transistor M3. The first terminal of the third bypass transistor M3 is grounded, and the gate of the third bypass transistor M3 is coupled to the enable signal line EN.

[0183] For example, the first bypass transistor M1, the second bypass transistor M2, and the third bypass transistor M3 are turned on when the enable signal transmitted on the enable signal line EN is set to a high level, and the corresponding nodes (such as...) are turned on. Figure 5a or Figure 5b The second node dp_n and the fourth node dp are connected to the ground terminal or the voltage terminal that provides a negative voltage for discharge.

[0184] In another embodiment, the first terminal of the third bypass transistor M3 is grounded to reduce power consumption of the third bypass transistor M3 in response to an enable signal of a logic "low" state received by the gate when the sense amplifier 100 is not operating.

[0185] In this embodiment, the voltage difference between the first bit line BT and the second bit line BB is amplified by the first inverter 1021, the second inverter 1022, and the bypass transistor unit 1023, which has the advantages of fast readout speed and more effective output voltage signal. Furthermore, the bypass transistor unit 1023 has a simple structure, requires fewer control signals to achieve discharge, is easy to manufacture, and minimizes production costs.

[0186] In some embodiments, reference Figure 5a or Figure 5bThe first bypass transistor M1, the second bypass transistor M2, and the third bypass transistor M3 all include N-type transistors.

[0187] For example, the first bypass transistor M1, the second bypass transistor M2, and the third bypass transistor M3 are N-type transistors, which will turn on when the gate voltage of these N-type transistors exceeds the threshold voltage.

[0188] In this embodiment, the first bypass transistor M1, the second bypass transistor M2, and the third bypass transistor M3 preferably include N-type transistors, so that they can be turned on when the enable signal transmitted by the enable signal line EN is set to a high level, thereby reducing the required control signals to achieve discharge and facilitating the reduction of production costs.

[0189] Figure 7 This is a schematic diagram of a memory according to an exemplary embodiment. Based on the above-described readout amplifier structure, embodiments of this disclosure provide a memory, such as... Figure 7 As shown, the memory 700 includes: a plurality of memory cells and a readout amplifier according to the above embodiment; wherein,

[0190] A storage cell, coupled to a sense amplifier, is configured to store either first data or second data; wherein the first data includes a logic high level and the second data includes a logic low level.

[0191] The readout amplifier is configured to read data stored in the memory cell and amplify the data.

[0192] It should be noted that the reference Figure 7 The storage cell is coupled to a sense amplifier via a first bit line BT and a second bit line BB. The sense amplifier reads the data stored in the storage cell. Specifically, the sense amplifier acquires and amplifies the voltage difference between the first bit line BT and the second bit line BB, and finally outputs an amplified signal, which represents the data stored in the storage cell.

[0193] In some embodiments, the memory includes static random access memory, and the storage unit includes static random access memory.

[0194] For example, if the memory includes static random access memory (SRAM), then Figure 7 The storage units shown may include static random access memory (SRAM cells).

[0195] In some embodiments, reference Figure 3 The static random access memory (SRAM) cell includes a first PMOS transistor P1, a first NMOS transistor P2, a second PMOS transistor P3, a second NMOS transistor P4, a third NMOS transistor P5, and a fourth NMOS transistor P6; wherein,

[0196] The gate of the first PMOS transistor P1 is coupled to the gate of the first NMOS transistor P2. The first terminal of the first PMOS transistor P1 is coupled to the first voltage terminal VDD. The second terminal of the first PMOS transistor P1 is coupled to the second terminal of the first NMOS transistor P2. The first terminal of the first NMOS transistor P2 is grounded.

[0197] The gate of the second PMOS transistor P3 is coupled to the gate of the second NMOS transistor P4. The first terminal of the second PMOS transistor P3 is coupled to the first voltage terminal VDD. The second terminal of the second PMOS transistor P3 is coupled to the second terminal of the second NMOS transistor P4. The first terminal of the second NMOS transistor P4 is grounded.

[0198] The gate of the third NMOS transistor P5 is coupled to the select word line SEL. The first terminal of the third NMOS transistor P5 is coupled to the first bit line BT. The second terminal of the third NMOS transistor P5 is coupled to the second terminal of the first PMOS transistor P1. The gate of the fourth NMOS transistor P6 is coupled to the select word line SEL. The first terminal of the fourth NMOS transistor P6 is coupled to the second bit line BB. The second terminal of the fourth NMOS transistor P6 is coupled to the second terminal of the second PMOS transistor P3.

[0199] For example, refer to Figure 3 , Figure 3 This illustrates a specific structure of a static random access memory unit. Figure 3 The basic structure of the memory cell shown includes six transistors (e.g., Figure 3 Transistors P1 to P6 are used to select word line SEL to store data information in two cross-coupled inverters (e.g., transistors P1 to P6). Figure 3 (It consists of transistors P1 to P4). Figure 3 The storage cell shown has two stable states (e.g., logical states "1" or "0") to indicate the stored data information. Specifically, the logical state is represented by the voltage of node d and the voltage of node d_n. Figure 3 The storage unit shown also includes transistors P5 and P6, which are used to control read and write operations on the storage unit.

[0200] In another embodiment, the static random access memory unit may further include other memory units that are read in a differential-signal manner.

[0201] Figure 8 This is a schematic diagram illustrating a memory system according to an exemplary embodiment. Based on the above memory structure, embodiments of this disclosure provide a memory system, such as... Figure 8 As shown, it includes the memory as described in the above embodiments, and a memory controller; wherein,

[0202] Memory 700;

[0203] The memory controller 706 is coupled to the memory 700 and is configured to control the memory 700.

[0204] The memory system 800 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0205] like Figure 8 As shown, the memory system 800 may include a host 708 and a memory subsystem 702, the memory subsystem 702 having one or more memories 700, and the memory subsystem also including a memory controller 706. The host 708 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 708 may be configured to send data to the memory 700. Alternatively, the host 708 may be configured to receive data from the memory 700.

[0206] The memory 700 can be any memory disclosed in this disclosure.

[0207] According to some implementations, the memory controller 706 is also coupled to the host 708. The memory controller 706 can manage data stored in the memory 700 and communicate with the host 708.

[0208] In some implementations, the memory controller 706 is designed to operate in low duty cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0209] In some implementations, the memory controller 706 is designed to operate in a high duty cycle environment solid-state drive (SSD) or embedded multimedia card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0210] The memory controller 706 can be configured to control the operation of the memory 700, such as read and write operations. The memory controller 706 can also be configured to manage various functions relating to data stored or to be stored in the memory 700, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 706 is also configured to process error correction codes (ECC) relating to data read from or written to the memory 700.

[0211] The memory controller 706 can also perform any other suitable function, such as formatting the memory 700. The memory controller 706 can communicate with external devices (e.g., the host 708) according to a specific communication protocol. For example, the memory controller 706 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0212] The memory controller 706 and one or more memories 700 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 800 can be implemented and packaged into different types of end electronic products.

[0213] In such Figure 9a In one example shown, the memory controller 706 and a single memory 700 can be integrated into a memory card 802. The memory card 802 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 802 may also include a connection between the memory card 802 and a host computer (e.g., Figure 8 The memory card connector 804 is coupled to the host 708 in the memory card connector.

[0214] In such Figure 9b In another example shown, the memory controller 706 and multiple memories 700 may be integrated into a solid-state drive (SSD) 806. The solid-state drive 806 may also include a connection between the solid-state drive 806 and a host (e.g., ...). Figure 8The solid-state drive connector 808 is coupled to the host 708 in the memory card 802. In some embodiments, the storage capacity and / or operating speed of the solid-state drive 806 is greater than the storage capacity and / or operating speed of the memory card 802.

[0215] It is understood that the memory controller 706 can perform the read method as provided in any embodiment of this disclosure.

[0216] Figure 10 This is a flowchart illustrating an operation method of a sense amplifier according to an exemplary embodiment. Based on the above-described sense amplifier structure, this disclosure provides an operation method of a sense amplifier, the method comprising:

[0217] S10: During the pre-charging phase, the first bit line and the second bit line are pre-charged to the first voltage;

[0218] S20: During the discharge phase, when the first switching unit and the second switching unit are turned on, the first bit line is coupled to the second node and the second bit line is coupled to the fourth node, so that the second node and the fourth node discharge to different potentials;

[0219] S30: During the reading phase, when the first and second switching units are turned off, the first node and the third node discharge at different discharge rates.

[0220] It should be noted that the specific implementation process of the readout amplifier operation method provided in this disclosure embodiment can be referred to the above-described readout amplifier embodiment, and will not be repeated here.

[0221] It is understood that the pre-charge unit 101, readout unit 102, first bit line BT, second bit line BB, first switch unit 103 and second switch unit 104 in the embodiments of this disclosure can all be manufactured using conventional integrated circuit processing technology. There are no special requirements for the process conditions, and they are compatible with conventional MOS transistor processing technology.

[0222] Here, it is preferable that the pre-charge unit 101, readout unit 102, first bit line BT, second bit line BB, first switch unit 103 and second switch unit 104 are fabricated in the same MOS transistor processing flow, which facilitates the simplification of the process and saves manufacturing costs.

[0223] It should be understood that the phrase "some embodiments" mentioned throughout the specification means that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "in some embodiments" or "in other embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0224] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A readout amplifier, characterized in that, include: The pre-charge unit, the readout unit, the first switching unit, and the second switching unit; wherein, The pre-charge unit is coupled to the first bit line of the memory cell and the second bit line of the memory cell; The readout unit includes a first inverter, a second inverter, a first node, a second node, a third node, a fourth node, a third transistor, and a fourth transistor. The first inverter includes a seventh transistor and an eighth transistor, and the second inverter includes a ninth transistor and a tenth transistor. The first terminal of the seventh transistor is coupled to a first voltage terminal. The second terminals of the seventh transistor and the eighth transistor are coupled to the first node. The first terminal of the eighth transistor is coupled to the second node. The first terminal of the ninth transistor is coupled to the first voltage terminal. The second terminals of the ninth transistor and the tenth transistor are coupled to the third node. The first terminal of the tenth transistor is coupled to the fourth node. The first bit line is coupled to the first node via the third transistor, and the second bit line is coupled to the third node via the fourth transistor. The first switching unit is coupled to the first bit line and the second node; The second switching unit is coupled to the second bit line and the fourth node; In the sense amplifier, the second node and the fourth node discharge to different potentials during the discharge phase, which causes the first node and the third node to have different discharge rates during the read phase.

2. The readout amplifier according to claim 1, characterized in that, The sense amplifier also includes an enable signal line; The enable signal line is configured to transmit an enable signal; The first switching unit and the second switching unit are also respectively coupled to the enable signal line and are configured to be turned on when the enable signal is low and turned off when the enable signal is high.

3. The readout amplifier according to claim 1, characterized in that, The first switching unit includes: a first transistor; wherein, The gate of the first transistor is coupled to the enable signal line, the second end of the first transistor is coupled to the second node, and the first end of the first transistor is coupled to the first bit line. The first transistor is configured to be turned on when the enable signal transmitted by the received enable signal line is at a logic low level, so as to connect the first bit line to the second node.

4. The readout amplifier according to claim 1, characterized in that, The second switching unit includes: a second transistor; wherein, The gate of the second transistor is coupled to the enable signal line, the second terminal of the second transistor is coupled to the fourth node, and the first terminal of the second transistor is coupled to the second bit line. The second transistor is configured to be turned on when the enable signal transmitted by the received enable signal line is at a logic low level, so as to connect the second bit line to the fourth node.

5. The readout amplifier according to claim 1, characterized in that, Both the first switching unit and the second switching unit include P-type transistors.

6. The readout amplifier according to claim 2, characterized in that, The gates of the third transistor and the fourth transistor are both coupled to the enable signal line. The first terminal of the third transistor is coupled to the first bit line, and the second terminal of the third transistor is coupled to the first node. The first terminal of the fourth transistor is coupled to the second bit line, and the second terminal of the fourth transistor is coupled to the third node. The third transistor is configured to be turned on when the received enable signal is at a logic low level, so that the first bit line is coupled to the first node; The fourth transistor is configured to be turned on when the received enable signal is at a logic low level, so that the second bit line is coupled to the third node.

7. The readout amplifier according to claim 1, characterized in that, The first switching unit includes: a fifth transistor; wherein, The gate of the fifth transistor is coupled to the enable signal line, the second terminal of the fifth transistor is coupled to the second node, and the first terminal of the fifth transistor is coupled to the first node. The fifth transistor is configured to be turned on when the enable signal transmitted by the received enable signal line is at a logic low level, so as to connect the first bit line to the second node.

8. The readout amplifier according to claim 1, characterized in that, The second switching unit includes: a sixth transistor; wherein, The gate of the sixth transistor is coupled to the enable signal line, the second terminal of the sixth transistor is coupled to the fourth node, and the first terminal of the sixth transistor is coupled to the third node. The sixth transistor is configured to be turned on when the enable signal transmitted by the received enable signal line is at a logic low level, so as to connect the second bit line to the fourth node.

9. The readout amplifier according to claim 2, characterized in that, The readout unit further includes: a bypass transistor unit; wherein... The input terminal of the first inverter is coupled to the output terminal of the second inverter, and the output terminal of the first inverter is coupled to the input terminal of the second inverter. The output terminals of the first inverter and the second inverter are respectively coupled to the input terminal of the bypass transistor unit, and the output terminal of the bypass transistor unit is grounded.

10. The readout amplifier according to claim 9, characterized in that, The gates of the seventh transistor and the eighth transistor are coupled to the output of the second inverter. The gates of the ninth transistor and the tenth transistor are coupled to the output of the first inverter.

11. The readout amplifier according to claim 10, characterized in that, The seventh and ninth transistors are P-type transistors, and the eighth and tenth transistors are N-type transistors.

12. The readout amplifier according to claim 9, characterized in that, The bypass transistor unit includes a first bypass transistor, a second bypass transistor, and a third bypass transistor; wherein, The gate of the first bypass transistor is coupled to the first bit line, and the second terminal of the first bypass transistor is coupled to the output terminal of the first inverter. The gate of the second bypass transistor is coupled to the second bit line, and the second terminal of the second bypass transistor is coupled to the output terminal of the second inverter. The first terminal of the first bypass transistor and the first terminal of the second bypass transistor are coupled to the second terminal of the third bypass transistor. The first terminal of the third bypass transistor is grounded, and the gate of the third bypass transistor is coupled to the enable signal line.

13. The readout amplifier according to claim 12, characterized in that, The first bypass transistor, the second bypass transistor, and the third bypass transistor all include N-type transistors.

14. A memory, characterized in that, include: Multiple storage cells and a readout amplifier according to any one of claims 1 to 13; wherein, The storage unit, coupled to the sense amplifier, is configured to store data; The readout amplifier is configured to read data stored in the storage unit and amplify the data.

15. The memory according to claim 14, characterized in that, The memory includes static random access memory, and the storage unit includes static random access memory.

16. The memory according to claim 15, characterized in that, The static random access memory cell includes a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; wherein, The gate of the first PMOS transistor is coupled to the gate of the first NMOS transistor, the first terminal of the first PMOS transistor is coupled to the first voltage terminal, the second terminal of the first PMOS transistor is coupled to the second terminal of the first NMOS transistor, and the first terminal of the first NMOS transistor is grounded. The gate of the second PMOS transistor is coupled to the gate of the second NMOS transistor, the first end of the second PMOS transistor is coupled to the first voltage terminal, the second end of the second PMOS transistor is coupled to the second end of the second NMOS transistor, and the first end of the second NMOS transistor is grounded. The gate of the third NMOS transistor is coupled to the select word line, the first end of the third NMOS transistor is coupled to the first bit line, the second end of the third NMOS transistor is coupled to the second end of the first PMOS transistor, the gate of the fourth NMOS transistor is coupled to the select word line, the first end of the fourth NMOS transistor is coupled to the second bit line, and the second end of the fourth NMOS transistor is coupled to the second end of the second PMOS transistor.

17. A memory system, characterized in that, Includes the memory as described in any one of claims 14 to 16, and a memory controller; wherein, The memory; The memory controller, coupled to the memory, is configured to control the memory.

18. A method for operating a readout amplifier, characterized in that, Applied to a readout amplifier as described in any one of claims 1 to 13, the method comprises: During the pre-charging phase, the first bit line and the second bit line are pre-charged to the first voltage; During the discharge phase, the third transistor is turned on to couple the first bit line to the first node, and the fourth transistor is turned on to couple the second bit line to the third node; the first switching unit and the second switching unit are turned on, the first bit line is coupled to the second node and the second bit line is coupled to the fourth node, so that the second node and the fourth node discharge to different potentials; During the reading phase, when the third transistor, the fourth transistor, the first switching unit, and the second switching unit are turned off, the first node and the third node discharge at different discharge rates.

Images