Semiconductor memory device

Abstract

The semiconductor storage device of the present application includes a plurality of first conductive layers, a plurality of second conductive layers, a first semiconductor layer provided between the plurality of first conductive layers and the plurality of second conductive layers, a charge storage layer, and a first wiring electrically connected to the first semiconductor layer, wherein the charge storage layer has a first portion provided between the plurality of first conductive layers and the first semiconductor layer, and a second portion provided between the plurality of second conductive layers and the first semiconductor layer; and the semiconductor storage device is configured to perform a deletion operation including a first deletion cycle and a second deletion cycle. In the first deletion cycle, a first voltage is supplied to at least a portion of the plurality of first conductive layers and at least a portion of the plurality of second conductive layers, and a deletion voltage greater than the first voltage is supplied to the first wiring. In the second deletion cycle, the first voltage is supplied to at least a portion of the plurality of first conductive layers, a second voltage greater than the first voltage is supplied to at least a portion of the plurality of second conductive layers, and the deletion voltage is supplied to the first wiring.

Description

[0001] [Citation of relevant applications]

[0002] This application is based on and claims the priority interest held by prior Japanese Patent Application No. 2021-102805, filed on June 21, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor memory device. Background Technology

[0004] A known semiconductor memory device includes: a semiconductor substrate; a plurality of conductive layers arranged along a direction intersecting the surface of the semiconductor substrate; a semiconductor layer facing the plurality of conductive layers; and a gate insulating layer disposed between the conductive layers and the semiconductor layer. The gate insulating layer may have, for example, a data storage section such as an insulating charge storage layer (e.g., silicon nitride (Si3N4)) or a conductive charge storage layer (e.g., a floating gate). Summary of the Invention

[0005] One embodiment provides a semiconductor memory device that operates well.

[0006] One embodiment of a semiconductor memory device includes: a plurality of first conductive layers arranged along a first direction; a plurality of second conductive layers disposed spaced apart from the plurality of first conductive layers in a second direction intersecting the first direction and arranged along the first direction; a first semiconductor layer disposed between the plurality of first conductive layers and the plurality of second conductive layers, extending along the first direction and facing the plurality of first conductive layers and the plurality of second conductive layers; a charge storage layer having a first portion disposed between the plurality of first conductive layers and the first semiconductor layer, and a second portion disposed between the plurality of second conductive layers and the first semiconductor layer; and a first wiring electrically connected to the first semiconductor layer. Furthermore, the semiconductor memory device is configured to perform a deletion operation including a first deletion cycle and a second deletion cycle. In the first deletion cycle, the semiconductor memory device supplies a first voltage to at least a portion of the plurality of first conductive layers, supplies a first voltage to at least a portion of the plurality of second conductive layers, and supplies a deletion voltage greater than the first voltage to the first wiring. Furthermore, in the second deletion cycle, the semiconductor memory device supplies a first voltage to at least a portion of the plurality of first conductive layers, supplies a second voltage greater than the first voltage to at least a portion of the plurality of second conductive layers, and supplies a deletion voltage to the first wiring. Based on this configuration, a semiconductor memory device capable of relatively good operation can be provided. Attached Figure Description

[0007] Figure 1 This is a schematic block diagram showing a portion of the semiconductor memory device according to the first embodiment.

[0008] Figure 2 This is a schematic equivalent circuit diagram representing a portion of the semiconductor memory device.

[0009] Figure 3 This is a schematic equivalent circuit diagram representing a portion of the semiconductor memory device.

[0010] Figure 4 This is a schematic top view showing a portion of the structure of the semiconductor memory device.

[0011] Figure 5 This is a schematic perspective view showing a portion of the structure of the semiconductor memory device.

[0012] Figure 6 This is a schematic top view showing a portion of the structure of the semiconductor memory device.

[0013] Figure 7 This is a schematic histogram used to illustrate the threshold voltage of the storage cell MCI, MCO that records multi-bit data.

[0014] Figure 8 This is a schematic cross-sectional view used to illustrate the readout operation of the semiconductor memory device according to the first embodiment.

[0015] Figure 9 This is a schematic flowchart used to illustrate the deletion operation of the semiconductor memory device.

[0016] Figure 10 It is a schematic cross-sectional view used to illustrate the double-sided voltage supply operation.

[0017] Figure 11 It is a schematic waveform diagram used to illustrate the double-sided voltage supply operation.

[0018] Figure 12 It is a schematic cross-sectional view used to illustrate the odd-number verification action.

[0019] Figure 13 It is a schematic cross-sectional view used to illustrate the even-number verification action.

[0020] Figure 14 It is a schematic waveform diagram used to illustrate the odd-number verification action and the even-number verification action.

[0021] Figure 15 It is a schematic cross-sectional view used to illustrate the single-sided voltage supply deletion operation.

[0022] Figure 16 It is a schematic waveform diagram used to illustrate the single-sided voltage supply deletion operation.

[0023] Figure 17 This is a schematic flowchart used to illustrate the deletion action of the comparative example.

[0024] Figure 18 It is a schematic histogram used to illustrate the threshold voltage changes of storage cells MCI and MCO caused by deletion actions.

[0025] Figure 19 It is a schematic histogram used to illustrate the threshold voltage changes of storage cells MCI and MCO caused by deletion actions.

[0026] Figure 20 It is a schematic histogram used to illustrate the threshold voltage changes of storage cells MCI and MCO caused by deletion actions.

[0027] Figure 21 This is a schematic cross-sectional view used to illustrate the single-sided deletion voltage supply operation of the second embodiment.

[0028] Figure 22 This is a schematic waveform diagram used to illustrate the single-sided deletion voltage supply operation of the second embodiment.

[0029] Figure 23 This is a schematic flowchart used to illustrate the deletion operation in the third embodiment.

[0030] Figure 24 This is a schematic flowchart used to illustrate the deletion operation in the third embodiment.

[0031] Figure 25 This is a schematic cross-sectional view used to illustrate the deletion verification operation in the third embodiment.

[0032] Figure 26 This is a schematic cross-sectional view used to illustrate the deletion verification operation in the third embodiment.

[0033] Figure 27 This is a schematic cross-sectional view used to illustrate the single-sided deletion voltage supply operation of the third embodiment.

[0034] Figure 28 This is a schematic cross-sectional view used to illustrate the single-sided deletion voltage supply operation of the third embodiment. Detailed Implementation

[0035] Next, the semiconductor memory device according to the embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the scope of the invention. Additionally, the following drawings are schematic diagrams, and sometimes certain components may be omitted for ease of explanation. Furthermore, common parts in multiple embodiments are labeled with the same symbols, and sometimes descriptions are omitted.

[0036] Furthermore, when referred to as a "semiconductor memory device" in this specification, it sometimes refers to a memory die, and sometimes to a storage system that includes a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). Moreover, it sometimes refers to a device including a host computer, such as a smartphone, tablet, or personal computer.

[0037] Furthermore, when this specification describes the first component as being "electrically connected to" the second component, it can mean that the first component is directly connected to the second component, or that the first component is connected to the second component via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the off state, the first transistor is "electrically connected to" the third transistor.

[0038] Additionally, when described in this specification as the first component being "connected" "between" the second and third components, it sometimes means that the first, second, and third components are connected in series, and the second component is connected to the third component via the first component.

[0039] In addition, when the description in this specification refers to a circuit or the like as "conducting" two wirings, it sometimes means, for example, that the circuit or the like includes a transistor or the like, which is disposed in the current path between the two wirings, and that the transistor or the like is in an on state.

[0040] In addition, in this specification, the specified direction parallel to the upper surface of the substrate is called the X direction, the direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and the direction perpendicular to the upper surface of the substrate is called the Z direction.

[0041] In addition, in this specification, the direction along a specified surface is sometimes referred to as the first direction, the direction along the specified surface and intersecting the first direction is referred to as the second direction, and the direction intersecting the specified surface is referred to as the third direction. The first, second, and third directions may correspond to any one of the X, Y, and Z directions, or they may not correspond to any of them.

[0042] Furthermore, in this specification, expressions such as "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "upper," and the direction closer to the substrate along the Z direction is called "lower." Additionally, when a configuration is described as a lower surface or lower end, it refers to the surface or end of that configuration on the substrate side; when described as an upper surface or upper end, it refers to the surface or end of that configuration on the opposite side of the substrate. Furthermore, surfaces intersecting the X or Y direction are called side surfaces, etc.

[0043] [First Implementation]

[0044] [constitute]

[0045] Figure 1 This is a schematic block diagram showing a portion of the semiconductor memory device according to the first embodiment. Figure 2 and Figure 3 This is a schematic equivalent circuit diagram representing a portion of the semiconductor memory device.

[0046] like Figure 1 As shown, the semiconductor memory device of this embodiment includes a memory cell array (MCA) and peripheral circuitry (PC) for controlling the memory cell array (MCA).

[0047] The memory cell array (MCA) has multiple memory blocks (BLK). Each memory block (BLK) has multiple serial units (SU). For example, as... Figure 2 As shown, the string unit SU has multiple memory units MU. Each of the multiple memory units MU has two memory strings MSI and MSO. One end of each memory string MSI and MSO is connected to the drain-side selection transistors STD and STDT, respectively, and is connected to a common bit line BL via them. The other end of each memory string MSI and MSO is connected to the common source-side selection transistors STS and STSb, and is connected to a common source line SL via them.

[0048] The memory string MSI has m+1 memory cells MCI connected in series (m is an integer greater than or equal to 1). The memory string MSO has m+1 memory cells MCO connected in series. Each memory cell MCI and MCO is a field-effect transistor with a semiconductor layer, a gate insulating layer, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating layer has a charge storage layer for storing data. The threshold voltage of each memory cell MCI and MCO varies depending on the amount of charge in the charge storage layer. The gate electrodes of the m+1 memory cells MCI are connected to word lines WLI_0 to WLI_m. Similarly, the gate electrodes of the m+1 memory cells MCO are connected to word lines WLO_0 to WLO_m. Word lines WLI_0 to WLI_m and WLO_0 to WLO_m are connected to all memory cells MU in the memory block BLK.

[0049] Additionally, the memory strings MSI and MSO each have one or more dummy memory cells MCDD connected between multiple memory cells MCI and MCO and drain-side select transistor STD. Furthermore, the memory strings MSI and MSO each have one or more dummy memory cells MCDS connected between multiple memory cells MCI and MCO and source-side select transistor STS. The dummy memory cells MCDD and MCDS have the same configuration as the memory cells MCI and MCO, but they are not used for data storage. The gate electrode of the dummy memory cell MCDD is connected to the dummy word line WLDD. The gate electrode of the dummy memory cell MCDS is connected to the dummy word line WLDS. The dummy word lines WLDD and WLDS are respectively connected to all memory cells MU in the memory block BLK.

[0050] Select transistors (STD, STDT, STS, STSb) are field-effect transistors with a semiconductor layer, a gate insulating layer, and a gate electrode. The semiconductor layer functions as a channel region. The gate electrode of the drain-side select transistor STDT is connected to the drain-side select gate line SGDT. The drain-side select gate line SGDT is connected to all memory cells MU in the memory block BLK. The gate electrode of the drain-side select transistor STD is connected to the drain-side select gate line SGD. The drain-side select gate line SGD is connected to all memory cells MU in the serial cell SU. The gate electrodes of the source-side select transistors STS and STSb are connected to the source-side select gate lines SGS and SGSb, respectively. The source-side select gate lines SGS and SGSb are connected to all memory cells MU in the memory block BLK.

[0051] For example, such as Figure 1 As shown, the peripheral circuit PC includes a row decoder RD connected to the memory cell array MCA, a sense amplifier module SAM connected to the memory cell array MCA, and a voltage generation circuit VG connected to the row decoder RD and the sense amplifier module SAM. Additionally, the peripheral circuit PC includes a sequencer, an address register, a status register, etc. (not shown).

[0052] For example, such as Figure 3 As shown, the line decoder RD includes a block decoder BLKD, a word line decoder WLD, and a driver circuit DRV.

[0053] The block decoder BLKD has multiple block decoding units blkd corresponding to multiple memory blocks BLK in the memory cell array MCA. Each block decoding unit blkd has multiple transistors T corresponding to multiple word lines WLI, WLO in the memory block BLK. BLK Transistor T BLKFor example, an NMOS (N-Channel Metal Oxide Semiconductor) transistor exhibits the field-effect transistor characteristic. Transistor T BLK The drain electrode of transistor T is connected to word lines WLI and WLO. BLK The source electrode is connected to wiring CG. Wiring CG is connected to all block decoding units (blkd) in the block decoder BLKD. Transistor T BLK The gate electrode is connected to the signal supply line BLKSEL. Multiple signal supply lines BLKSEL are provided, corresponding to all block decoding units (blkd). Additionally, the signal supply lines BLKSEL are connected to all transistors T in the block decoding unit (blkd). BLK .

[0054] In read, write, and delete operations, for example, one signal supply line BLKSEL corresponding to a block address in an address register (not shown) becomes "H", while other signal supply lines BLKSEL become "L". For example, a specified drive voltage with a positive value is supplied to one signal supply line BLKSEL, while ground voltage V is supplied to the other signal supply lines BLKSEL. SS Therefore, all word lines WLI, WLO in a memory block BLK corresponding to this block address are connected to all wiring CG. Additionally, all word lines WLI, WLO in other memory blocks BLK become floating.

[0055] The word line decoder (WLD) has multiple word line decoding units (wld) corresponding to multiple memory cells (MCI, MCO) in the memory strings (MSI, MSO). In the illustrated example, the word line decoding unit wld has two transistors T. WL Transistor T WL For example, an NMOS transistor with electric field effect. Transistor T WL The drain electrode of transistor T is connected to wiring CG. WL The source electrode is connected to the wiring CG. S Or wired CG U Transistor T WL The gate electrode is connected to the signal supply line WLSEL. S Or signal supply line WLSEL U Signal supply line WLSEL S With a transistor T contained in all word line decoding units wld WL There are multiple corresponding signal supply lines (WLSEL). U Another transistor T contained in all word line decoding units wld WL There are multiple corresponding settings.

[0056] In read and write operations, for example, the signal supply line WLSEL corresponds to a word line decoding unit wld that corresponds to a page address in an address register (not shown). S Becoming in the "H" state, and its corresponding WLSEL U It enters the "L" state. Additionally, the signal supply line WLSEL, corresponding to the other word line decoding units wld, is also connected. S It becomes the "L" state, and its corresponding WLSEL U It becomes the "H" state. Additionally, it connects to the wiring CG. S Supply the voltage corresponding to the select word lines WLI and WLO. Additionally, supply the voltage to the wiring CG. U The voltages corresponding to the non-select word lines WLI and WLO are supplied. Thus, the voltages corresponding to the select word lines WLI and WLO are supplied to one word line WLI and WLO corresponding to the page address. Additionally, the voltages corresponding to the non-select word lines WLI and WLO are supplied to the other word lines WLI and WLO. Furthermore, when a page address in an address register (not shown) corresponds to a word line WLI, the voltages corresponding to the non-select word lines WLI and WLO are supplied to all word lines WLO. Similarly, when a page address in an address register (not shown) corresponds to a word line WLO, the voltages corresponding to the non-select word lines WLI and WLO are supplied to all word lines WLI.

[0057] The drive circuit DRV, for example, has a connection with the wiring CG. S and wiring CG U Two corresponding drive units (drv) are provided. Each drive unit (drv) has multiple transistors (T). DRV Transistor T DRV For example, an NMOS transistor with electric field effect. Transistor T DRV The drain electrode is connected to the wiring CG. S Or wired CG U Transistor T DRV The source electrode is connected to the voltage supply line L. VG Or voltage supply line L P Voltage supply line L VG Connected to one of the multiple output terminals of the voltage generation circuit VG. Voltage supply line L P Connected to the supplied ground voltage V SS The bonding pad electrode P. Transistor T. DRV The gate electrode is connected to the signal supply line VSEL.

[0058] In read, write, and delete operations, for example, any one of the multiple signal supply lines VSEL corresponding to a drive unit drv becomes the "H" state, while the other signal supply lines VSEL become the "L" state.

[0059] For example, such as Figure 3 As shown, the voltage generation circuit VG has multiple voltage generation units vg. During read operations, write operations, etc., the voltage generation units vg generate a voltage of a specified magnitude and transmit it via the voltage supply line L. VG Output. The voltage generation unit vg can be a boost circuit such as a charge pump circuit, or a buck circuit such as a regulator.

[0060] Sensing Amplification Module (SAM) Figure 1 It has the ability to work with multiple bit lines (BL). Figure 2 A plurality of sensing amplification units (not shown) are provided accordingly. Each sensing amplification unit includes: a sensing transistor having a gate electrode electrically connected to the bit line BL; a plurality of data latch circuits connected to the drain electrode of the sensing transistor; and a voltage adjustment circuit that adjusts the voltage of the bit line BL according to data from one of the plurality of data latch circuits.

[0061] Next, refer to Figures 4-6 Here, an example of the configuration of the semiconductor memory device of this embodiment will be described. Figure 4 This is a schematic top view showing a portion of the configuration of the semiconductor memory device according to this embodiment. Figure 5 This is a schematic perspective view showing a portion of the configuration of the semiconductor memory device according to this embodiment. Figure 6 This is a schematic top view showing a portion of the configuration of the semiconductor memory device according to this embodiment.

[0062] like Figure 4 As shown, the semiconductor memory device of this embodiment includes a semiconductor substrate 100. In the illustrated example, two memory cell array regions R arranged along the X direction are provided on the semiconductor substrate 100. MCA Along the X direction and the storage cell array region R MCA A row decoder area R is set up side by side. RD Additionally, a peripheral circuit region R is provided at the end of the semiconductor substrate 100 in the Y direction. PC .

[0063] The semiconductor substrate 100 is, for example, a single-crystal silicon (Si) semiconductor substrate containing p-type impurities. An n-type well containing n-type impurities and a p-type well containing p-type impurities are provided on the upper surface of the semiconductor substrate. Furthermore, peripheral circuitry PCs (PCs) are provided on the surface of the semiconductor substrate 100, for example. Figure 1 At least a portion of the transistors and wiring, etc.

[0064] In the storage cell array region R MCA It contains multiple memory blocks (BLKs) arranged along the Y direction. The memory blocks (BLKs) are as shown in the reference... Figure 1As explained above, it has multiple serial units (SU). For example, such as... Figure 5 As shown, the string unit SU includes multiple stacked bulk structures LSI, LSO arranged alternately along the Y direction, and a trench structure AT disposed between the multiple stacked bulk structures LSI, LSO. The stacked bulk structure LSI, for example, includes m+7 conductive layers 110I stacked along the Z direction. The stacked bulk structure LSO, for example, includes m+7 conductive layers 110O stacked along the Z direction (see reference). Figure 5 and Figure 6 The trench structure AT includes multiple memory string structures (MSS) arranged along the X-direction. Each memory string structure (MSS) includes a generally bottom-cylindrical semiconductor layer 120 extending along the Z-direction, a gate insulating layer 130 disposed between the multilayer structure LSI, LSO and the semiconductor layer 120, and an insulating layer 140 such as silicon oxide (SiO2) disposed in the central portion of the semiconductor layer 120. Furthermore, an insulating layer 150 such as silicon oxide (SiO2) is disposed between the multiple memory string structures (MSS) arranged along the X-direction.

[0065] The conductive layers 110I and 110O are generally plate-shaped conductive layers extending along the X direction, such as a multilayer film of titanium nitride (TiN) and tungsten (W), or a conductive layer of polycrystalline silicon (Si) implanted with impurities. An insulating layer 101, such as silicon oxide (SiO2), is disposed between the multiple conductive layers 110I and 110O arranged along the Z direction.

[0066] Among the multiple conductive layers 110I, 110O, the conductive layer ranked first from the bottom functions as the gate electrode of the source-side selection transistor STSb and the source-side selection gate line SGSb.

[0067] Among the multiple conductive layers 110I and 110O, the second conductive layer from the bottom functions as the gate electrode of the source-side select transistor STS and the source-side select gate line SGS.

[0068] Among the multiple conductive layers 110I and 110O, the third conductive layer from the bottom functions as the gate electrode of the dummy memory cell MCDS and the dummy word line WLDS.

[0069] Among the multiple conductive layers 110I, the conductive layers 110I located from the bottom, from the 4th to the (m+4th)th, function as the gate electrode of the memory cell MCI and the word lines WLI_0 to WLI_m.

[0070] Among the multiple conductive layers 110O, the conductive layers 110O arranged from the bottom 4th to the (m+4th)th position function as the gate electrode of the memory cell MCO and the word lines WLO_0 to WLO_m.

[0071] Among the multiple conductive layers 110I and 110O, the conductive layer at position m+5 from the bottom functions as the gate electrode of the dummy memory cell MCDD and the dummy word line WLDD.

[0072] Among the multiple conductive layers 110I and 110O, the conductive layer at position m+6 from the bottom functions as the gate electrode of the drain-side select transistor STD and the drain-side select gate line SGD.

[0073] Among the multiple conductive layers 110I, 110O, the conductive layer at position m+7 from the bottom functions as the gate electrode of the drain-side select transistor STDT and the drain-side select gate line SGDT.

[0074] Semiconductor layer 120 ( Figure 5 For example, it is a semiconductor layer such as undoped polycrystalline silicon (Si). As described above, semiconductor layer 120 has a generally bottomed cylindrical shape. Semiconductor layer 120 serves as a component in memory modules such as MSI and MSO. Figure 2 The corresponding multiple memory cells MCI, MCO, dummy memory cells MCDD, MCDS, and the channel regions of the selection transistors (STSb, STS, STD, STDT) function.

[0075] The lower end of semiconductor layer 120 is connected to semiconductor layer 121. Figure 5 Semiconductor layer 121 is, for example, a semiconductor layer containing n-type impurities such as phosphorus (P) or polycrystalline silicon (Si). Semiconductor layer 121 serves as the source line SL. Figure 2 To fulfill its function.

[0076] Furthermore, although the illustration is omitted, an impurity layer containing n-type impurities such as phosphorus (P) is actually formed on the upper end of the semiconductor layer 120. The semiconductor layer 120 is electrically connected to the bit line BL via this impurity layer. Figure 2 ).

[0077] The gate insulating layer 130 has a generally cylindrical shape and extends in the Z direction along the outer peripheral surface of the semiconductor layer 120. The gate insulating layer 130 includes a tunnel insulating layer 131 such as silicon oxide (SiO2), a charge storage layer 132 such as silicon nitride (SiN), and a barrier insulating layer 133 such as silicon oxide (SiO2) disposed from the semiconductor layer 120 side toward the conductive layers 110I, 110O side.

[0078] [Threshold voltage of storage cell MCI, MCO]

[0079] Next, refer to Figure 7 The threshold voltages of storage cells MCI and MCO are explained.

[0080] As described above, the memory cell array MCA has multiple memory cells MCI and MCO. When a write operation is performed on the multiple memory cells MCI and MCO, the threshold voltage of the memory cells MCI and MCO can be controlled to various states.

[0081] Figure 7 This is a schematic histogram illustrating the threshold voltages of the storage cells MCI and MCO that record multi-bit data. The horizontal axis represents the voltages of the word lines WLI and WLO, and the vertical axis represents the number of storage cells MCI and MCO.

[0082] Figure 7 The diagram illustrates three distributions of the threshold voltage for storage cells MCI,MCO. For example, the threshold voltage of the storage cell MCI,MCO controlled in the Er state is greater than the readout blocking voltage V. BB Less than the readout voltage V CGAR Furthermore, the largest threshold voltage contained in the threshold distribution of the Er state is the deletion verification voltage V. VFYEr The magnitude of the magnitude. Additionally, the threshold voltage of the storage cell MCI,MCO controlled in state A is greater than the readout voltage V. CGAR Less than the readout voltage V CGBR Furthermore, the smallest threshold voltage contained in the threshold distribution of state A is the verification voltage V. VFYA The magnitude of the magnitude. Additionally, the threshold voltage of the storage cell MCI,MCO controlled in state B is greater than the readout voltage V. CGBR Furthermore, the smallest threshold voltage contained in the threshold distribution of state B is the verification voltage V. VFYB The magnitude of the reading. Additionally, the threshold voltages of all storage cells MCI and MCO are less than the readout voltage V. READ .

[0083] The threshold distribution is assigned 1 bit or more bits of data respectively.

[0084] For example, when 3 bits of data are allocated to storage cells MCI and MCO, the threshold voltage of storage cells MCI and MCO is set to a value belonging to 2. 3 =Controlled by any one of 8 threshold distributions. In addition, any one of the following 8 threshold distributions is assigned: "0,0,0", "0,0,1", "0,1,0", "0,1,1", "1,0,0", "1,0,1", "1,1,0", and "1,1,1".

[0085] Additionally, for example, when allocating 1 bit of data to the storage cell MCI,MCO, the threshold voltage of the storage cell MCI,MCO is set to a value belonging to 2. 1The threshold can be controlled using either of two threshold distributions. Furthermore, either "0" or "1" can be assigned to either of these two threshold distributions.

[0086] [Read the action]

[0087] Next, refer to Figure 8 The read operation of the semiconductor memory device in this embodiment will be explained. Figure 8 It is a schematic cross-sectional view used to illustrate the readout action.

[0088] Furthermore, the read operation in this embodiment is uniformly performed on all memory cells MCI,MCO that are contained in a specified string unit SU within a specified memory block BLK and connected to a specified word line WLI or word line WLO. Hereinafter, this configuration containing multiple memory cells MCI,MCO will sometimes be referred to as a page.

[0089] Additionally, the following description explains the relationship between memory string MSI ( Figure 2 Examples of reading operations performed on the page corresponding to the word line WLI_n. Additionally, in the following descriptions, the selected memory string MSI ( Figure 2 The drain-side select gate line SGD corresponding to the unselected memory string MSO is called the drain-side select gate line SGD_SEL, and the drain-side select gate line SGD corresponding to the unselected memory string MSO is called the drain-side select gate line SGD_USEL.

[0090] For example, such as Figure 8 As shown, when performing the read operation, a voltage V is supplied to the bit line BL. SRC +V BL Additionally, a voltage V is supplied to the source line SL. SRC Voltage V SRC Greater than the ground voltage V SS Voltage V SRC +V BL Greater than voltage V SRC .

[0091] Additionally, a voltage V is supplied to the gate line SGDT,SGD_SEL on the drain side. SG Voltage V SG Greater than voltage V SRC +V BL Additionally, voltage V SG With voltage V SRC +V BL The difference is greater than the threshold voltage at which the drain-side selection transistor STDT,STD operates as an NMOS transistor. Therefore, an electron channel is formed in the channel region of the drain-side selection transistor STDT,STD corresponding to the selected memory string MSI.

[0092] Additionally, a voltage V is supplied to the gate line SGD_USEL on the drain side. DD Voltage V DD Greater than voltage V SRC Additionally, voltage V DD With voltage V SRC +V BL The difference is less than the threshold voltage at which the drain-side selection transistor STD operates as an NMOS transistor. Therefore, no channel will be formed in the channel region of the drain-side selection transistor STD corresponding to the unselected memory string MSO.

[0093] Additionally, voltage V is supplied to the dummy word lines WLDD and WLDS. READ_DMT Voltage V READ_DMT Greater than voltage V DD Less than the readout voltage V READ Additionally, voltage V READ_DMT With voltage V SRC +V BL The difference is greater than the threshold voltage required for the dummy storage cells MCDD and MCDS to operate as NMOS transistors. Therefore, electron channels are formed in the channel regions of the dummy storage cells MCDD and MCDS.

[0094] In addition, the read-through voltage V is supplied to the word lines WLI_0~WLI_n-2, WLI_n+2~WLI_m. READ Additionally, the read-through voltage V is supplied to word lines WLI_n-1 and WLI_n+1. READk Read the voltage V. READk Greater than the readout voltage V READ Therefore, electron channels will be formed in the channel regions of multiple non-selective storage cells (MCIs).

[0095] Additionally, a read voltage V is supplied to the select word line WLI_n. CGRV Read the voltage V CGRV For example, as a reference Figure 7 The readout voltage V described CGAR V CGBR Any one of ... Therefore, depending on the data recorded in the selected storage cell MCI, a channel may or may not form in the channel region of the selected storage cell MCI.

[0096] In addition, the read-through voltage V is supplied to the word lines WLO_0~WLO_n-3, WLO_n+3~WLO_m. READ Therefore, electron channels will be formed in the channel regions of multiple non-selective storage cells (MCOs).

[0097] In addition, a readout blocking voltage V is supplied to the word lines WLO_n-1~WLO_n+1. BB Additionally, a grounding voltage V is supplied to the word lines WLO_n-2 and WLO_n+2. SS Therefore, channels will not form in the channel regions of the storage cells MCO that are connected to them.

[0098] Additionally, a voltage V is supplied to the gate lines SGS and SGSb on the source side. SG Therefore, by selecting the channel region of transistor STS and STSb on the source side, an electron channel will be formed.

[0099] Here, when an electron channel is formed in the channel region of the selected memory cell (MCI), current flows through the bit line BL. Conversely, when an electron channel is not formed in the channel region of the selected memory cell (MCI), no current flows through the bit line BL. During the readout operation, current is generated by utilizing the sensing amplification module (SAM). Figure 1 By detecting the current in the bit line BL, the data of the selected storage cell MCI can be read out.

[0100] In addition, Figure 8 In the middle, the readout blocking voltage V is supplied to the word lines WLO_n-1~WLO_n+1. BB The readout voltage V is supplied to the word lines WLO_0~WLO_n-3, WLO_n+3~WLO_m. READ However, this configuration is ultimately just an example, and the specific method can be adjusted as needed. For example, a readout blocking voltage V can also be supplied to all word lines WLO_0 to WLO_m. BB .

[0101] [Delete action]

[0102] Next, refer to Figure 9 The deletion operation of the semiconductor memory device in this embodiment will be explained. Figure 9 This is a schematic flowchart used to illustrate the deletion action.

[0103] In step S101, the memory block BLK (hereinafter referred to as "selected memory block BLK") selected as the object of the deletion operation is... S The multiple memory cells MCI and MCO contained in the ") perform a double-sided deletion voltage supply operation. The double-sided deletion voltage supply operation is the operation of supplying deletion voltage to the multiple memory cells MCI and MCO, thereby reducing the threshold voltage of the memory cells MCI and MCO.

[0104] In step S102, the selected memory block BLK is... S The multiple memory cells (MCIs) within the system perform deletion verification actions. Therefore, it is determined whether the threshold voltage of the memory cell (MCI) is lower than a reference voltage. Figure 7 The described deletion verification voltage V VFYEr .

[0105] In step S103, the selected memory block BLK is... S The multiple storage cells (MCOs) within the system perform deletion verification actions. Therefore, it is determined whether the threshold voltage of the storage cell (MCO) is lower than a reference voltage. Figure 7 The described deletion verification voltage V VFYEr .

[0106] In step S104, the results of the deletion verification actions in steps S102 and S103 are determined. For example, if the ratio of the MCI of the storage cells detected in the off state in step S102 is above a certain value, and the ratio of the MCO of the storage cells detected in the off state in step S103 is above a certain value, the deletion verification is determined to have failed, and the process proceeds to step S101. On the other hand, if the ratio of the MCI of the storage cells detected in the off state in step S102 is below a certain value, or the ratio of the MCO of the storage cells detected in the off state in step S103 is below a certain value, the deletion verification is determined to have succeeded, and the process proceeds to step S105.

[0107] In step S105, the result of the deletion verification action performed just before step S105 within the deletion verification actions of steps S102 and S107 is determined. For example, if the ratio of the MCI of the storage cells detected in the off state in step S102 or S107 is above a certain value, the deletion verification is determined to have failed, and the process proceeds to step S106. On the other hand, if the ratio of the MCI of the storage cells detected in the off state in step S102 or S107 is below a certain value, the deletion verification is determined to have succeeded, and the process proceeds to step S108.

[0108] In step S106, the selected memory block BLK is... S The multiple memory cells (MCIs) included in the process perform a one-sided deletion voltage supply operation. The one-sided deletion voltage supply operation in step S106 involves supplying a deletion voltage to the multiple memory cells (MCIs) to reduce the threshold voltage of the MCIs. Furthermore, in step S106, supplying a deletion voltage to the memory cells (MCOs) is prohibited.

[0109] In step S107, similar to step S102, a deletion verification action is performed on the storage cell MCI.

[0110] In step S108 ( Figure 9In step S103 and S110, the result of the deletion verification action performed just before step S108 is determined. For example, if the ratio of storage cells with MCO detected in the off state in step S103 or S110 is above a certain value, the deletion verification is determined to have failed, and the process proceeds to step S109. On the other hand, if the ratio of storage cells with MCO detected in the off state in step S103 or S110 is below a certain value, the deletion verification is determined to have succeeded, and the deletion action ends.

[0111] In step S109, the selected memory block BLK is... S The multiple memory cells (MCOs) included in the system perform a one-sided deletion voltage supply operation. The one-sided deletion voltage supply operation in step S109 involves supplying deletion voltage to the multiple memory cells (MCOs) to reduce the threshold voltage of the memory cells (MCOs). Furthermore, in step S109, the supply of deletion voltage to the memory cells (MCIs) is prohibited.

[0112] In step S110, similar to step S103, a deletion verification action is performed on the storage cell MCI.

[0113] [Double-sided voltage supply removal action]

[0114] Next, refer to Figure 10 and Figure 11 The operation of the double-sided deletion voltage supply is explained. Figure 10 It is a schematic cross-sectional view used to illustrate the double-sided voltage supply operation. Figure 11 It is a schematic waveform diagram used to illustrate the double-sided voltage supply operation.

[0115] Furthermore, the double-sided deletion voltage supply operation in this embodiment is applied to the selected memory block BLK. S All storage cells in the system are uniformly executed by MCI and MCO.

[0116] Additionally, in the following description, the selection memory block BLK may sometimes be mentioned. S Other memory blocks (BLKs) are called "non-selective memory blocks (BLKs)". U Additionally, sometimes non-selective memory blocks (BLKs) are included. U The select gate lines SGDT, SGD, SGS, and SGSb included are referred to as "select gate lines USGDT, USGD, USGS, and USGSb".

[0117] During the double-sided deletion voltage supply operation at timing t101, voltage V is supplied to the select gate lines SGDT, SGD, SGS, SGSb and the dummy word lines WLDD, WLDS. CC Additionally, voltage V is supplied to the word lines WLI and WLO.ISO Voltage V CC Smaller than reference Figure 7 The readout is achieved through voltage V. READ Additionally, voltage V ISO Less than voltage V CC .

[0118] At timing t102 of the double-sided deletion voltage supply operation, deletion voltage V is supplied to bit line BL and source line SL. ERA Delete voltage V ERA Greater than reference Figure 7 The readout is achieved through voltage V. READ Additionally, remove voltage V. ERA With voltage V ISO The difference is greater than the threshold voltage required for the storage cell MCI,MCO to operate as a PMOS (P-Channel Metal Oxide Semiconductor) transistor. Therefore, for example, as Figure 10 As shown, channels for electrical holes will form in the channel regions of the storage cells MCI and MCO.

[0119] During the double-sided removal voltage supply operation at timing t103, voltage V is supplied to the select gate lines SGDT, SGD, SGS, and SGSb. SG_ERA At this point, the voltages of the gate lines SGDT, SGD, SGS, and SGSb are selected to rise in a manner that keeps the voltage difference with the bit line BL and the source line SL approximately constant, thereby reaching voltage V. SG_ERA Voltage V SG_ERA Less than the deletion voltage V ERA Additionally, voltage V SG_ERA With the removal voltage V ERA The difference is greater than the threshold voltage required for the selected transistors STDT, STD, STS, STSb to operate as PMOS transistors. Therefore, for example, as... Figure 10 As shown, in the channel regions of selected transistors STDT, STD, STS, and STSb, channels for electrical holes will be formed.

[0120] Additionally, during the timing t103 of the double-sided removal voltage supply operation, voltage V is supplied to the select gate lines USGDT, USGD, USGS, and USGSb. RD Voltage V RD Less than the deletion voltage V ERA Additionally, voltage V RD With the removal voltage V ERA The difference is less than the threshold voltage required for the select transistors STDT, STD, STS, and STSb to operate as PMOS transistors. Therefore, in the non-select memory block BLK UThe channel regions of the selected transistors STDT, STD, STS, and STSb will not form channels.

[0121] At timing t104 of the double-sided deletion voltage supply operation, voltage V is supplied to the dummy word lines WLDD and WLDS. WLU_ERA At this point, the voltages of the gate lines SGDT, SGD, SGS, and SGSb are selected to rise in a manner that keeps the voltage difference with the bit line BL and the source line SL approximately constant, thereby reaching voltage V. WLU_ERA Voltage V WLU_ERA Less than voltage V SG_ERA Greater than voltage V ISO Additionally, voltage V WLU_ERA With the removal voltage V ERA The difference is greater than the threshold voltage required for the selected transistors STDT, STD, STS, STSb to operate as PMOS transistors. Therefore, for example, as... Figure 10 As shown, in the channel regions of the dummy storage cells MCDD and MCDS, channels of electrical holes will be formed.

[0122] During the period from timing t104 to timing t105, a relatively large voltage is supplied between the drain and gate of the selection transistor STDT,STSb. Consequently, GIDL (Gate Induced Drain Leakage) is generated in the selection transistor STDT,STSb, thereby supplying holes to the channel region of the memory cell MCI,MCO.

[0123] Additionally, during the time interval t104 to t105, a relatively large voltage is supplied between the channel and gate of the memory cell MCI,MCO. Consequently, holes in the channel region of the memory cell MCI,MCO tunnel through the tunnel insulation layer 131 via FN (Fowler-Nordheim) tunneling. Figure 5 , Figure 6 ), moved to charge storage layer 132 ( Figure 5 , Figure 6 As a result, the threshold voltage of the storage cell MCI,MCO decreases.

[0124] At timing t105 of the double-sided deletion voltage supply operation, the source line SL, bit line BL, select gate lines SGDT, SGD, SGS, SGSb, and dummy word lines WLDD, WLDS are discharged. Additionally, in the illustrated example, a voltage V is supplied to word lines WLI, WLO at this time. CC .

[0125] At timing t106 of the double-sided deletion voltage supply operation, voltage V is supplied to the source line SL, bit line BL, select gate lines SGDT, SGD, SGS, SGSb, and dummy word lines WLDD, WLDS. CC .

[0126] At timing t107 of the double-sided deletion voltage supply operation, ground voltage V is supplied to the source line SL, bit line BL, select gate lines SGDT, SGD, SGS, SGSb, dummy word lines WLDD, WLDS, and word lines WLI, WLO. SS .

[0127] [Delete verification action]

[0128] Next, refer to Figures 12-14 This section explains the deletion verification action.

[0129] The deletion verification action in this embodiment includes odd-number verification actions and even-number verification actions.

[0130] Figure 12 It is a schematic cross-sectional view used to illustrate the odd-number verification action. Figure 12 This example illustrates an odd-numbered verification action for the memory cell MCI. An odd-numbered verification action checks the state of the memory cell MCI,MCO, which is the odd-numbered cell from the bottom. The execution and reference of the odd-numbered verification action are explained below. Figure 8 The described reading actions are largely the same. But as Figure 12 As illustrated, in odd-numbered verification operations, a reference is provided to the storage cell MCI,MCO, which is the odd-numbered cell from the bottom. Figure 7 The described deletion verification voltage V VFYEr Provide reference to the even-numbered storage cell MCI,MCO from the bottom. Figure 7 The readout is achieved through voltage V. READ Additionally, during odd-numbered verification operations, a readout blocking voltage V is supplied to the word lines WLI_0~WLI_m and WLO_0~WLO_m that are not targeted for the operation. BB Additionally, a readout blocking voltage V is supplied to the corresponding dummy word lines WLDD and WLDS. BB .

[0131] Figure 13 It is a schematic cross-sectional view used to illustrate the even-number verification action. Figure 13 This example illustrates an even-numbered verification action for the storage cell MCI. An even-numbered verification action checks the state of the storage cell MCI,MCO, which is the even-numbered cell from the bottom. The execution and reference of the even-numbered verification action are explained below. Figure 8 The described reading actions are largely the same. But as Figure 13As illustrated, in even-numbered verification operations, a reference is provided to the storage cell MCI,MCO, which is the even-numbered cell from the bottom. Figure 7 The described deletion verification voltage V VFYEr Provide reference to the storage cell MCI,MCO, which is the odd-numbered cell from the bottom. Figure 7 The readout is achieved through voltage V. READ Additionally, during even-numbered verification operations, a readout blocking voltage V is supplied to word lines WLI_0~WLI_m and word lines WLO_0~WLO_m that are not targeted for the operation. BB Additionally, a readout blocking voltage V is supplied to the corresponding dummy word lines WLDD and WLDS. BB .

[0132] Figure 14 It is a schematic waveform diagram used to illustrate the odd-number verification action and the even-number verification action. Figure 14 Examples of odd-numbered or even-numbered validation actions for the storage cell MCI are shown. Furthermore, Figure 14 The voltages of the select word line WLI_sel and the non-select word line WLI_usel are marked. For example, in an odd-numbered verification operation of the memory cell MCI, the word line WLI in the odd-numbered position from the bottom is the select word line WLI_sel, and the word line WLI in the even-numbered position from the bottom is the non-select word line WLI_usel. Conversely, in an even-numbered verification operation of the memory cell MCI, the word line WLI in the even-numbered position from the bottom is the select word line WLI_sel, and the word line WLI in the odd-numbered position from the bottom is the non-select word line WLI_usel.

[0133] During the timing t201 of the odd-number verification operation and the even-number verification operation, voltage V is supplied to the select gate lines SGDT, SGD_SEL, SGS, SGSb, the dummy word lines WLDD, WLDS, and the non-select word line WLI_usel. DD .

[0134] During the timing t202 of both odd-numbered and even-numbered verification actions, a reference is provided to each wiring other than the selection word line WLI_sel. Figure 12 or Figure 13 The voltage described.

[0135] During the timing t203 of both odd-numbered and even-numbered verification operations, a deletion verification voltage V is supplied to the select word line WLI_sel. VFYEr .

[0136] During the timing of odd-numbered and even-numbered verification actions t204, a grounding voltage V is supplied to each wiring. SS .

[0137] [Single-sided voltage supply deletion action]

[0138] Next, refer to Figure 15 and Figure 16 The single-sided deletion voltage supply operation is explained. Figure 15 It is a schematic cross-sectional view used to illustrate the single-sided voltage supply deletion operation. Figure 16 This is a schematic waveform diagram used to illustrate the single-sided voltage supply operation. Furthermore, Figure 15 and Figure 16 An example is shown of the single-sided deletion voltage supply operation for the storage cell MCI.

[0139] Furthermore, the single-sided deletion voltage supply operation in this embodiment is uniformly executed on all memory cells MCI in a specified memory block BLK, or on all memory cells MCO in a specified memory block BLK.

[0140] Execution and reference of single-sided voltage supply deletion action Figure 10 and Figure 11 The described double-sided removal voltage supply operation is roughly the same. However, if Figure 15 and Figure 16 As illustrated, in a single-sided deletion voltage supply operation, a deletion voltage V is supplied to word lines WLI_0~WLI_m and word lines WLO_0~WLO_m that are not targeted for the operation. ERA Or a voltage close to it. Additionally, a deletion voltage V is supplied to the corresponding dummy word lines WLDD and WLDS. ERA Or a voltage close to it.

[0141] Here, during the single-sided deletion voltage supply operation, a relatively large voltage is supplied between the channel and gate of one of the memory cells MCI and MCO. Consequently, holes in the channel region of one of the memory cells MCI and MCO tunnel through the FN layer 131 and move to the charge storage layer 132. As a result, the threshold voltage of one of the memory cells MCI and MCO decreases.

[0142] On the other hand, during the single-sided deletion voltage supply operation, such a large voltage is not supplied to the channel-gate interface of the other memory cell MCI and memory cell MCO. Therefore, FN tunneling of holes will not occur in memory cells MCI and MCO. Consequently, the threshold voltage of memory cells MCI and MCO will not decrease.

[0143] [Comparative Example]

[0144] Next, refer to Figure 17 The deletion action in the comparative example is explained. Figure 17 This is a schematic flowchart used to illustrate the deletion action of the comparative example.

[0145] In the comparative example deletion operation, step S114 is executed instead of step S104. In step S114, if, for example, the ratio of the memory cells MCI detected in the off state in step S102 is above a certain value, or the ratio of the memory cells MCO detected in the off state in step S103 is above a certain value, the deletion verification is determined to have failed, and the process proceeds to step S101. On the other hand, if, for example, the ratio of the memory cells MCI detected in the off state in step S102 is below a certain value, and the ratio of the memory cells MCO detected in the off state in step S103 is below a certain value, the deletion verification is determined to have succeeded.

[0146] Additionally, in the deletion action of the comparative example, the reference is not executed. Figure 9 The processing follows steps S105 to S110 as described above. Therefore, if the deletion verification is successful in step S114, the deletion action ends.

[0147] [Effect]

[0148] For example, consider the following situation: Figure 18 As illustrated, when selecting memory block BLK S In this context, the threshold voltages of multiple storage cells MCO are distributed in a range lower than the threshold voltages of multiple storage cells MCI.

[0149] In the comparison example, the deletion action ( Figure 17 In this process, the threshold voltages of both storage cells MCI and MCO will decrease until both storage cells MCI and MCO are successfully deleted. Therefore, in the process of... Figure 18 The illustrated state selection memory block BLK S In the case where the deletion action of the comparison example is performed, for example, such as Figure 19 As shown, there is a risk that the threshold voltage of the memory cell MCO may need to be reduced beyond what is necessary. In this case, the voltage of a portion of the memory cell MCO may fall below the readout blocking voltage V. BB .

[0150] Here, as referenced Figure 8 As explained, during the readout operation, a readout blocking voltage V is supplied to the gate electrode of the non-selected memory cell MCO (hereinafter, sometimes referred to as the "backside memory cell MCO"), which corresponds to the same semiconductor layer 120 as the selected memory cell MCI and is located at the same height. BB This causes the back-side storage cell MCO to be in the off state. However, the threshold voltage of the back-side storage cell MCO is lower than the readout blocking voltage V. BBIn this situation, the back-side memory cell MCO cannot be turned off. Regardless of whether the selected memory cell MCI is on or off, the bit line BL and source line SL will be turned on via the back-side memory cell MCO, causing current to flow in the bit line BL. This results in the inability to accurately detect the threshold voltage of the selected memory cell MCI.

[0151] Here, the deletion action in the first embodiment ( Figure 9 In the process, at the point when deletion verification is successful for either storage cell MCI or MCO, the supply of deletion voltage V to either storage cell MCI or MCO is prohibited. ERA Instead, the deletion voltage V is supplied only to the storage cell MCI, MCO. ERA Therefore, in the context of Figure 18 The illustrated state selection memory block BLK S When the deletion action of the first embodiment is performed, for example, such as Figure 20 As shown, it can effectively adjust the threshold voltage of the storage cell MCI.

[0152] Furthermore, the deletion action in the first embodiment ( Figure 9 In this embodiment, if the verification action corresponding to either storage cell MCI or MCO is successful, the verification action for either storage cell MCI or MCO will be omitted in subsequent actions. Therefore, the deletion action in the first embodiment can be executed at a higher speed than the deletion action in the comparative example.

[0153] [Second Implementation]

[0154] Next, refer to Figure 21 and Figure 22 The semiconductor memory device of the second embodiment will be described. Figure 21 This is a schematic cross-sectional view used to illustrate the single-sided deletion voltage supply operation of the semiconductor memory device according to the second embodiment. Figure 22 This is a schematic waveform diagram used to illustrate the single-sided deletion voltage supply operation of the second embodiment.

[0155] The semiconductor memory device of the second embodiment has a configuration that is basically the same as that of the semiconductor memory device of the first embodiment. However, the deletion operation of the second embodiment differs from that of the first embodiment. The execution of the deletion operation of the second embodiment is basically the same as that of the first embodiment. However, the single-sided deletion voltage supply operation of the second embodiment differs from that of the first embodiment. The execution of the single-sided deletion voltage supply operation of the second embodiment is substantially the same as that of the first embodiment.

[0156] However, as referenced Figure 15 and Figure 16 As explained, in the single-sided deletion voltage supply operation of the first embodiment, the deletion voltage V is supplied to word lines WLI_0 to WLI_m and word lines WLO_0 to WLO_m that are not targeted for operation. ERA Or a voltage close to it. Additionally, a deletion voltage V is supplied to the corresponding dummy word lines WLDD and WLDS. ERA Or a voltage close to it.

[0157] And such Figure 21 and Figure 22 As illustrated, in the single-sided deletion voltage supply operation of the second embodiment, the word lines WLI_0 to WLI_m and WLO_0 to WLO_m that are not targeted for operation are made to float, rather than being supplied with a fixed voltage. Furthermore, the corresponding dummy word lines WLDD and WLDS are made to float, rather than being supplied with a fixed voltage.

[0158] In addition, the method for making word lines WLI_0~WLI_m, WLO_0~WLO_m and dummy word lines WLDD, WLDS float can be adjusted as appropriate.

[0159] For example, in Figure 21 In the example, all word lines WLI_0 to WLI_m or all word lines WLO_0 to WLO_m and dummy word lines WLDD, WLDS are made to float. In this case, for example, it could be considered to turn off at least one of the transistors located in all current paths used to supply voltage to word lines WLI_0 to WLI_m, WLO_0 to WLO_m and dummy word lines WLDD, WLDS. For example, in... Figure 3 In the example, all current paths used to supply voltage to word lines WLI_0~WLI_m, WLO_0~WLO_m and dummy word lines WLDD, WLDS are the word lines WLI_0~WLI_m, WLO_0~WLO_m and dummy word lines WLDD, WLDS and the voltage generation circuit VG. Figure 3 All current paths between WLI_0 and WLI_m, WLO_0 and WLO_m, and dummy word lines WLDD and WLDS, and the supplied ground voltage V SS The bonding pad electrode P ( Figure 3 All current paths between ).

[0160] Here, multiple transistors T connected to the signal supply line BLKSEL BLKThis is configured in all current paths used to supply voltage to word lines WLI_0~WLI_M, WLO_0~WLO_M, and dummy word lines WLDD, WLDS. Therefore, in order to turn off at least one of the transistors configured in the current paths used to supply voltage to word lines WLI_0~WLI_M, WLO_0~WLO_M, and dummy word lines WLDD, WLDS, for example, the AND selection memory block BLK in the line decoder RD could also be turned off. S The signal supply line BLKSEL corresponds to the word lines WLI_0~WLI_M, WLO_0~WLO_M and the dummy word lines WLDD, WLDS. Figure 3 It becomes the "L" state.

[0161] Additionally, for example, WLSEL connected to multiple signal supply lines S and multiple signal supply lines WLSEL U Multiple transistors T WL This is configured in all current paths used to supply voltage to word lines WLI_0~WLI_M, WLO_0~WLO_M, and dummy word lines WLDD, WLDS. Therefore, in order to turn off at least one of the transistors configured in the current paths used to supply voltage to word lines WLI_0~WLI_M, WLO_0~WLO_M, and dummy word lines WLDD, WLDS, for example, all signal supply lines WLSEL in the line decoder RD could also be turned off. S and signal supply line WLSEL U All of them become "L" state.

[0162] Additionally, for example, multiple transistors T connected to multiple signal supply lines VSEL DRV This is configured in all current paths used to supply voltage to word lines WLI_0~WLI_M, WLO_0~WLO_M, and dummy word lines WLDD, WLDS. Therefore, in order to turn off at least one of the transistors configured in the current paths used to supply voltage to word lines WLI_0~WLI_M, WLO_0~WLO_M, and dummy word lines WLDD, WLDS, for example, all signal supply lines VSEL in the line decoder RD can also be set to the "L" state.

[0163] Alternatively, a fixed voltage can be supplied to the dummy word lines WLDD and WLDS, causing the word lines WLI_0~WLI_M and WLO_0~WLO_M to float, or only a portion of the word lines WLI_0~WLI_M and WLO_0~WLO_M to float. In this case, for example, the dummy word lines WLDD and WLDS can be connected to the voltage generation circuit VG, or only a portion of the dummy word lines WLDD and WLDS and the word lines WLI_0~WLI_M and WLO_0~WLO_M can be connected to the voltage generation circuit VG. Furthermore, it is possible to consider connecting the word lines WLI_0~WLI_M and WLO_0~WLO_M to the voltage generation circuit VG. Figure 3 At least a portion of the current path between, and word lines WLI_0~WLI_M, WLO_0~WLO_M and the supplied ground voltage V SS The bonding pad electrode P ( Figure 3 In at least a portion of the current path between the transistors, at least one of the transistors disposed in the current path is turned off.

[0164] [Third Implementation]

[0165] Next, refer to Figures 23-28 The deletion operation in the third embodiment will be explained. Figure 23 and Figure 24 This is a schematic flowchart used to illustrate the deletion operation in the third embodiment. Figure 25 and Figure 26 This is a schematic cross-sectional view used to illustrate the deletion verification operation in the third embodiment. Figure 27 and Figure 28 This is a schematic cross-sectional view used to illustrate the single-sided deletion voltage supply operation of the third embodiment.

[0166] The semiconductor memory device of the third embodiment is basically the same as that of the semiconductor memory device of the first embodiment. However, the deletion operation of the third embodiment is different from that of the first embodiment.

[0167] That is, in the deletion operation of the first embodiment, as referred to Figure 9 As explained above, after the deletion verification is successful in step S104, the selected memory block BLK is then... S The MCI of the included storage cells performs a single-sided deletion voltage supply operation, or performs a single-sided deletion voltage supply operation on the MCO of the included storage cells.

[0168] In the deletion operation of the third embodiment, after determining that the deletion verification is successful in step S106, at least one of the following operations is performed: Select memory block BLK SA single-sided erase voltage supply operation is performed on the upper half of the memory cells MCI (e.g., when m is even, the memory cells MCI connected to word lines WLI_m / 2+1 to WLI_m) within all the memory cells MCI included; a single-sided erase voltage supply operation is performed on the lower half of the memory cells MCI (e.g., when m is even, the memory cells MCI connected to word lines WLI_0 to WLI_m / 2-1); a single-sided erase voltage supply operation is performed on the upper half of the memory cells MCO (e.g., when m is even, the memory cells MCO connected to word lines WLO_m / 2+1 to WLO_m); and a single-sided erase voltage supply operation is performed on the lower half of the memory cells MCO (e.g., when m is even, the memory cells MCO connected to word lines WLO_0 to WLO_m / 2-1).

[0169] Furthermore, in the semiconductor memory device of the third embodiment, the memory cell MCI connected to word line WLI_m / 2 and the memory cell MCO connected to word line WLO_m / 2 are used as dummy cells and are not used for data recording. Therefore, in the following examples, the single-sided deletion voltage supply operation and deletion verification operation are not performed on the memory cells MCI and MCO.

[0170] Step S301 ( Figure 23 ) Execution and reference Figure 9 The steps described are the same as S101.

[0171] The execution of step S302 is basically the same as that of the reference. Figure 9 The steps described are the same as S102. However, in step S102, the memory block BLK is selected. S The deletion verification action is performed on all memory cells (MCIs) contained therein. In step S302, the selected memory block (BLK) is... S The upper half of the storage cells within all the storage cells contained in the MCI are subject to deletion verification.

[0172] For example, in Figure 9 In the odd-number verification action of step S102, as shown in the reference... Figure 12 As explained, the deletion verification voltage V is supplied to the odd-numbered word lines WLI from the bottom within the multiple word lines WLI_0 to WLI_m. VFYEr The readout voltage V is supplied to the even-numbered word line WLI from the bottom. READ In the odd-number verification action of step S302, such as Figure 25 As shown, a deletion verification voltage V is supplied to the word lines WLI in the odd-numbered positions from the bottom within multiple word lines WLI_m / 2+1 to WLI_m. VFYErThe readout voltage V is supplied to the even-numbered word line WLI from the bottom. READ Furthermore, in this odd-number verification operation, a read-through voltage V is supplied to multiple word lines WLI_0 to WLI_m / 2. READ .

[0173] Additionally, for example in Figure 9 In the even-numbered verification action of step S102, as shown in the reference... Figure 13 As explained, the deletion verification voltage V is supplied to the even-numbered word lines WLI from the bottom within the multiple word lines WLI_0 to WLI_m. VFYEr The readout voltage V is supplied to the odd-numbered word line WLI from the bottom. READ In the even-numbered verification action of step S302, such as Figure 26 As shown, a deletion verification voltage V is supplied to the even-numbered word lines WLI from the bottom within a range of multiple word lines WLI_m / 2+1 to WLI_m. VFYEr The readout voltage V is supplied to the odd-numbered word line WLI from the bottom. READ Furthermore, in this even-number verification operation, a read-through voltage V is supplied to multiple word lines WLI_0 to WLI_m / 2. READ .

[0174] The execution of step S303 is basically the same as the reference. Figure 9 The steps described are the same as S102. However, in step S102, the memory block BLK is selected. S The deletion verification action is performed on all memory cells (MCIs) contained therein. In step S303, the selected memory block (BLK) is... S The lower half of the storage cells within all the storage cells contained in the MCI are subject to deletion verification.

[0175] The execution of step S304 is basically the same as the reference. Figure 9 The steps described are the same as S103. However, in step S103, the memory block BLK is selected. S The deletion verification action is performed on all memory cells (MCOs) contained therein. In step S304, the selected memory block (BLK) is... S The upper half of the storage cells within all the storage cells contained in the MCO performs a deletion verification action.

[0176] The execution of step S305 is basically the same as that of the reference. Figure 9 The steps described are the same as S103. However, in step S103, the memory block BLK is selected. S The deletion verification action is performed on all memory cells (MCOs) contained therein. In step S305, the selected memory block (BLK) is...S The lower half of the storage cells within all the storage cells contained in the MCO perform a deletion verification action.

[0177] In step S306 ( Figure 23 In step S302, the result of the deletion verification action in steps S302 to S305 is determined. For example, if the ratio of the number of storage cells detected in the closed state in each of steps S302 to S305 is above a certain value, the deletion verification is determined to have failed, and the process proceeds to step S301. On the other hand, if the ratio of the number of storage cells detected in the closed state in at least one of steps S302 to S305 is below a certain value, the deletion verification is determined to have succeeded, and the process proceeds to step S307. Figure 24 ).

[0178] In step S307, the result of the deletion verification action performed just before step S307 within the deletion verification actions of steps S302 and S309 is determined. For example, if the ratio of the MCI of the storage cells detected in the closed state in step S302 or S309 is above a certain value, the deletion verification is determined to have failed, and the process proceeds to step S308. On the other hand, if the ratio of the MCI of the storage cells detected in the closed state in step S302 or S309 is below a certain value, the deletion verification is determined to have succeeded, and the process proceeds to step S310.

[0179] The execution of step S308 is basically the same as the reference. Figure 9 The steps described are the same as S106. However, in step S106, the memory block BLK is selected. S All memory cells (MCIs) contained herein undergo a single-sided deletion voltage supply operation. In step S308, the selected memory block (BLK) is... S The upper half of the storage cells within the MCI (Multi-Cell Module) performs a single-sided deletion voltage supply operation.

[0180] For example, in Figure 9 In step S106, during the single-sided voltage supply removal operation, as shown in the reference... Figure 15 As explained, this means supplying voltage V to all multiple word lines WLI_0 to WLI_m. ISO And in Figure 24 In step S308, during the single-sided voltage supply removal operation, such as... Figure 27 The diagram shows the supply of voltage V to multiple word lines WLI_m / 2+1 to WLI_m. ISO Voltage V is supplied to multiple word lines WLI_0 to WLI_m / 2-1 P_ERA A voltage V is supplied to the word lines WLI_m / 2 between them. P_ERAA voltage half the size of the voltage. Voltage V P_ERA Greater than voltage V ISO Less than the deletion voltage V ERA Additionally, remove voltage V. ERA With voltage V P_ERA The difference is greater than the threshold voltage required for the storage cell MCI,MCO to operate as a PMOS transistor. Therefore, for example, as... Figure 27 As shown, in the channel region of the lower half of the storage cell MCI, a hole channel will form. However, the threshold voltage of the lower half of the storage cell MCI will not decrease.

[0181] In step S309, similar to step S302, a deletion verification action is performed on the upper half of the storage cell MCI.

[0182] In step S310, the result of the deletion verification action performed just before step S310 within the deletion verification actions of steps S303 and S312 is determined. For example, if the ratio of the MCI of the storage cells detected in the off state in step S303 or S312 is above a certain value, the deletion verification is determined to have failed, and the process proceeds to step S311. On the other hand, if the ratio of the MCI of the storage cells detected in the off state in step S303 or S312 is below a certain value, the deletion verification is determined to have succeeded, and the process proceeds to step S313.

[0183] The execution of step S311 is basically the same as the reference. Figure 9 The steps described are the same as S106. However, in step S106, the memory block BLK is selected. S All memory cells (MCIs) contained herein undergo a single-sided deletion voltage supply operation. In step S311, the selected memory block (BLK) is... S The lower half of the MCI cells in all the memory cells contained therein performs a single-sided deletion voltage supply operation.

[0184] For example, in Figure 9 In step S106, during the single-sided voltage supply removal operation, as shown in the reference... Figure 15 As explained, this means supplying voltage V to all multiple word lines WLI_0 to WLI_m. ISO And in Figure 24 In step S311, during the single-sided removal voltage supply operation, such as Figure 28 The diagram shows the supply of voltage V to multiple word lines WLI_0 to WLI_m / 2-1. ISO Voltage V is supplied to multiple word lines WLI_m / 2+1 to WLI_m. P_ERA A voltage V is supplied to the word lines WLI_m / 2 between them. P_ERA A voltage that is half the size of the voltage.

[0185] In step S312, similar to step S303, a deletion verification action is performed on the lower half of the storage cell MCI.

[0186] In step S313, the result of the deletion verification action just performed before step S313 within the deletion verification actions of steps S304 and S315 is determined. For example, if the ratio of storage cells with MCO detected in the off state in step S304 or S315 is above a certain value, the deletion verification is determined to have failed, and the process proceeds to step S314. On the other hand, if the ratio of storage cells with MCO detected in the off state in step S304 or S315 is below a certain value, the deletion verification is determined to have succeeded, and the process proceeds to step S316.

[0187] The execution of step S314 is basically the same as the reference. Figure 9 The steps described are the same as S109. However, in step S109, the memory block BLK is selected. S All memory cells (MCOs) contained therein undergo a single-sided deletion voltage supply operation. In step S314, the selected memory block (BLK) is... S The upper half of the storage cells within the MCO (Memory Control Center) performs a single-sided deletion voltage supply operation.

[0188] In step S315, similar to step S304, a deletion verification action is performed on the upper half of the storage cell MCO.

[0189] In step S316, the result of the deletion verification action just performed before step S316 within the deletion verification actions of steps S305 and S318 is determined. For example, if the ratio of storage cells with MCO detected in the off state in step S305 or S318 is above a certain value, the deletion verification is determined to have failed, and the process proceeds to step S317. On the other hand, if the ratio of storage cells with MCO detected in the off state in step S305 or S318 is below a certain value, the deletion verification is determined to have succeeded, and the deletion action ends.

[0190] The execution of step S317 is basically the same as that of the reference. Figure 9 The steps described are the same as S109. However, in step S109, the memory block BLK is selected. S All memory cells (MCOs) contained herein undergo a single-sided deletion voltage supply operation. In step S317, the selected memory block (BLK) is... S The lower half of the storage cells within all the storage cells contained in the MCO perform a single-sided deletion voltage supply action.

[0191] In step S318, similar to step S305, a deletion verification action is performed on the lower half of the storage cell MCO.

[0192] [Other Implementation Methods]

[0193] The semiconductor memory devices of the first to third embodiments have been illustrated above. However, the configurations shown in the first to third embodiments are merely illustrative, and the specific configurations of the semiconductor memory devices can be adjusted as appropriate. Furthermore, the operations shown in the first to third embodiments are also merely illustrative, and the magnitude of the voltage, the timing of the supplied voltage, etc., can be adjusted as appropriate.

[0194] For example, a semiconductor memory device may also be configured to perform two or more deletion operations in the first to third embodiments.

[0195] Furthermore, for example, in the single-sided deletion voltage supply operation of the third embodiment, a fixed voltage is supplied to one of the word lines WLI and WLO, similar to the single-sided deletion voltage supply operation of the first embodiment. However, in the single-sided deletion voltage supply operation of the third embodiment, one of the word lines WLI and WLO may also be made to float, similar to the single-sided deletion voltage supply operation of the second embodiment.

[0196] Additionally, for example, in the deletion operation of the third embodiment, the selected memory block BLK is... S The multiple memory cells MCI and MCO contained therein are divided into upper half memory cells MCI, lower half memory cells MCI, upper half memory cells MCO, and lower half memory cells MCO. Furthermore, for the four groups, the single-sided deletion voltage supply operation and deletion verification operation are performed independently. Here, in the deletion operation of the third embodiment, the selected memory block BLK can also be selected. S The multiple storage cells (MCI, MCO) contained therein are divided into 3 groups, or even more than 5 groups. In addition, if some of the groups are determined to have successfully deleted, while more than 2 groups are not determined to have successfully deleted, a single-sided deletion voltage supply action can be uniformly performed on these 2 or more groups.

[0197] Furthermore, in the above example, during the deletion voltage supply operation, the deletion voltage V is supplied to both the bit line BL and the source line SL. ERA However, during the deletion operation, the deletion voltage V can also be supplied to only one of the bit line BL and the source line SL. ERA .

[0198] Furthermore, the above example illustrates an instance where the upper and lower ends of semiconductor layer 120 are connected to an n-type semiconductor layer. However, at least one of the upper and lower ends of semiconductor layer 120 may also be connected to a p-type semiconductor layer such as boron (B). In this case, during the voltage supply removal operation, a hole may be supplied to semiconductor layer 120 via the p-type semiconductor layer from at least one of the source line SL and bit line BL, instead of generating a GIDL to supply a hole to semiconductor layer 120.

[0199] [other]

[0200] Several embodiments of the present invention have been described, but these embodiments are merely illustrative examples and are not intended to limit the scope of the invention. The novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. The embodiments and their variations are included in the scope and spirit of the invention, and are also included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor memory device, comprising: Multiple first conductive layers are arranged along a first direction; A plurality of second conductive layers are disposed at a distance from the plurality of first conductive layers in a second direction intersecting the first direction, and are arranged along the first direction; A first semiconductor layer is disposed between the plurality of first conductive layers and the plurality of second conductive layers, extends along the first direction, and faces the plurality of first conductive layers and the plurality of second conductive layers; A charge storage layer includes a first portion disposed between the plurality of first conductive layers and the first semiconductor layer, and a second portion disposed between the plurality of second conductive layers and the first semiconductor layer; and The first wiring is electrically connected to the first semiconductor layer; and A portion of the first semiconductor layer corresponding to the first portion of the charge storage layer is designated as the first channel region; A portion of the first semiconductor layer corresponding to the second portion of the charge storage layer is designated as the second channel region; It is configured to perform deletion actions that include a first deletion loop and a second deletion loop. In the first deletion cycle, a first voltage is supplied to at least a portion of the plurality of first conductive layers, the first voltage is supplied to at least a portion of the plurality of second conductive layers, and a deletion voltage greater than the first voltage is supplied to the first wiring. In the second deletion cycle, the first voltage is supplied to at least a portion of the plurality of first conductive layers, a second voltage greater than the first voltage is supplied to at least a portion of the plurality of second conductive layers, and the deletion voltage is supplied to the first wiring.

2. The semiconductor memory device according to claim 1, wherein In the deletion action, the second deletion loop is executed after the first deletion loop.

3. The semiconductor memory device according to claim 1, wherein... In the deletion action, the first deletion loop and the second deletion loop are executed multiple times.

4. The semiconductor memory device according to claim 1, wherein The configuration allows for the execution of a third deletion loop in addition to the first and second deletion loops. One of the plurality of first conductive layers is designated as the third conductive layer. When one of the plurality of first conductive layers is designated as the fourth conductive layer... In the second deletion cycle, the first voltage is supplied to the third conductive layer, and a third voltage greater than the first voltage is supplied to the fourth conductive layer. In the third deletion cycle, the third voltage is supplied to the third conductive layer, and the first voltage is supplied to the fourth conductive layer.

5. The semiconductor memory device according to claim 4, wherein In the deletion action, the third deletion loop is executed after the first deletion loop.

6. The semiconductor memory device according to claim 4, wherein In the deletion action, the third deletion loop is executed multiple times.

7. The semiconductor memory device according to claim 1, wherein It is configured to perform the deletion action, which includes a first deletion verification action and a second deletion verification action, and In the first deletion verification operation, a deletion verification voltage is supplied to at least a portion of the plurality of first conductive layers, a fourth voltage less than the deletion verification voltage is supplied to at least a portion of the plurality of second conductive layers, and a fifth voltage less than the deletion verification voltage is supplied to the first wiring. In the second deletion verification operation, a deletion verification voltage is supplied to at least a portion of the plurality of second conductive layers, a fourth voltage is supplied to at least a portion of the plurality of first conductive layers, and a fifth voltage is supplied to the first wiring.

8. The semiconductor memory device according to claim 7, wherein In the deletion action, the first deletion verification action and the second deletion verification action are performed between the second deletion loop and the first deletion loop.

9. The semiconductor memory device according to claim 7, wherein In the deletion action, the first deletion verification action is performed after the second deletion loop.

10. The semiconductor memory device according to claim 7, wherein In the deletion action, The first deletion verification action is executed multiple times. The second deletion verification action is performed multiple times.

11. A semiconductor memory device, comprising: Multiple first conductive layers are arranged along a first direction; A plurality of second conductive layers are disposed at a distance from the plurality of first conductive layers in a second direction intersecting the first direction, and are arranged along the first direction; A first semiconductor layer is disposed between the plurality of first conductive layers and the plurality of second conductive layers, extends along the first direction, and faces the plurality of first conductive layers and the plurality of second conductive layers; A charge storage layer includes a first portion disposed between the plurality of first conductive layers and the first semiconductor layer, and a second portion disposed between the plurality of second conductive layers and the first semiconductor layer; The first wiring is electrically connected to the first semiconductor layer; Multiple voltage supply lines supply voltage to at least one of the multiple first conductive layers and the multiple second conductive layers; Multiple first current paths are current paths between the multiple first conductive layers and the multiple voltage supply lines, each containing a first transistor; and Multiple second current paths are current paths between the multiple second conductive layers and the multiple voltage supply lines, each containing a second transistor; and A portion of the first semiconductor layer corresponding to the first portion of the charge storage layer is designated as the first channel region; A portion of the first semiconductor layer corresponding to the second portion of the charge storage layer is designated as the second channel region; It is configured to perform deletion actions that include a first deletion loop and a second deletion loop. In the first deletion cycle, a first voltage is supplied to at least a portion of the plurality of first conductive layers, the first voltage is supplied to at least a portion of the plurality of second conductive layers, and a deletion voltage greater than the first voltage is supplied to the first wiring. In the second deletion cycle, the first voltage is supplied to at least a portion of the plurality of first conductive layers, and in the second current path corresponding to at least a portion of the plurality of second conductive layers, a first signal voltage that turns the second transistor off is supplied to the gate electrode of at least one of the second transistors, and the deletion voltage is supplied to the first wiring.

12. The semiconductor memory device according to claim 11, wherein In the deletion action, the second deletion loop is executed after the first deletion loop.

13. The semiconductor memory device according to claim 11, wherein In the deletion action, the first deletion loop and the second deletion loop are executed multiple times.

14. The semiconductor memory device of claim 11, wherein The configuration allows for the execution of a third deletion loop in addition to the first and second deletion loops. One of the plurality of first conductive layers is designated as the third conductive layer. When another of the plurality of first conductive layers is designated as the fourth conductive layer. In the second deletion cycle, the first voltage is supplied to the third conductive layer, and a third voltage greater than the first voltage is supplied to the fourth conductive layer. In the third deletion cycle, the third voltage is supplied to the third conductive layer, and the first voltage is supplied to the fourth conductive layer.

15. The semiconductor memory device of claim 14, wherein... In the deletion action, the third deletion loop is executed after the first deletion loop.

16. The semiconductor memory device of claim 14, wherein In the deletion action, the third deletion loop is executed multiple times.

17. The semiconductor memory device of claim 11, wherein... It is configured to perform the deletion action, which includes a first deletion verification action and a second deletion verification action, and In the first deletion verification operation, a deletion verification voltage is supplied to at least a portion of the plurality of first conductive layers, a fourth voltage less than the deletion verification voltage is supplied to at least a portion of the plurality of second conductive layers, and a fifth voltage less than the deletion verification voltage is supplied to the first wiring. In the second deletion verification operation, a deletion verification voltage is supplied to at least a portion of the plurality of second conductive layers, a fourth voltage is supplied to at least a portion of the plurality of first conductive layers, and a fifth voltage is supplied to the first wiring.

18. The semiconductor memory device according to claim 17, wherein In the deletion action, the first deletion verification action and the second deletion verification action are performed between the second deletion loop and the first deletion loop.

19. The semiconductor memory device according to claim 17, wherein In the deletion action, the first deletion verification action is performed after the second deletion loop.

20. The semiconductor memory device of claim 17, wherein In the deletion action, The first deletion verification action is executed multiple times. The second deletion verification action is performed multiple times.

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