Three-dimensional memory and methods of controlling the same

Abstract

The present application relates to a kind of control methods of three-dimensional memory, three-dimensional memory includes multiple storage strings and multiple word lines, each storage string includes the multiple storage units that are sequentially connected from top to bottom, each word line is connected with the storage unit at the same height in each storage string, method includes: determining selected word line for programming verification operation;And when programming verification operation, first conduction voltage is applied to the first word line region on the side of selected word line, and second conduction voltage is applied to the second word line region on the other side of selected word line;Wherein, the storage unit connected with the word line in first word line region is programmed state, the storage unit connected with the word line in second word line region is unprogrammed state, and the size of second conduction voltage is adjustable.

Description

[0001] This application is a divisional application of the patent filed on January 28, 2021, with application number 202110118819.8, entitled "Three-dimensional memory and control method thereof". Technical Field

[0002] This invention relates to a control method for a three-dimensional memory, which can effectively improve the back-model effect of the three-dimensional memory without the need for an additional voltage source. Background Technology

[0003] As technology advances, the semiconductor industry is constantly seeking new ways to manufacture memory devices, enabling each memory die to have a greater number of memory cells. In non-volatile memories, such as NAND memory, one way to increase memory density is by using vertical memory arrays, i.e., 3D NAND (three-dimensional NAND) memory; with increasing integration, 3D NAND memory has evolved from 32 layers to 64 layers and even higher.

[0004] As market demands for storage density continue to increase, the industry is developing programming methods with more programming states to enable each physical storage cell to represent more bits of information. However, implementing more programming states places higher demands on the fabrication process of individual storage cells and the uniformity of distribution among multiple storage cells. Therefore, how to increase the storage density of storage cells and improve the performance of 3D memory is a pressing technical problem that needs to be solved. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a control method for a three-dimensional memory, which can effectively improve the back model effect of the three-dimensional memory without the need for an additional voltage source.

[0006] The technical solution adopted by the present invention to solve the above-mentioned technical problems is to provide a control method for a three-dimensional memory. The three-dimensional memory includes multiple memory strings and multiple word lines. Each memory string includes multiple memory cells connected in series from top to bottom. Each word line is connected to a memory cell at the same height in each memory string. The method includes: determining a selected word line for programming verification operation; and applying a first on-state voltage to a first word line region located on one side of the selected word line and applying a second on-state voltage to a second word line region located on the other side of the selected word line during the programming verification operation; wherein the memory cells connected to the word lines in the first word line region are in a programmed state, the memory cells connected to the word lines in the second word line region are in an unprogrammed state, and the magnitude of the second on-state voltage is adjustable.

[0007] In one embodiment of the present invention, the magnitude of the second conduction voltage gradually increases during the programming verification operation of the plurality of word lines.

[0008] In one embodiment of the present invention, the plurality of word lines are divided into a plurality of consecutive word line groups, wherein when the programming verification operation is performed on the word lines in each of the word line groups, the magnitude of the second on-state voltage is the same; wherein the magnitude of the second on-state voltage gradually increases during the programming verification operation on the plurality of word line groups.

[0009] In one embodiment of the present invention, each character line group includes 1 to 20 character lines.

[0010] In one embodiment of the present invention, the method further includes applying a third conduction voltage to at least one word line located between the selected word line and the first word line region and at least one word line located between the selected word line and the second word line region.

[0011] In one embodiment of the present invention, the method further includes: applying a programming verification voltage to the selected word line during the programming verification operation.

[0012] In one embodiment of the present invention, the magnitude of the second conduction voltage is 1V to 3V.

[0013] In one embodiment of the present invention, the magnitude of the first turn-on voltage and / or the third turn-on voltage is 6V to 8V.

[0014] In one embodiment of the present invention, the magnitudes of the first conduction voltage and / or the third conduction voltage are fixed.

[0015] In one embodiment of the present invention, the programming is either forward programming or reverse programming.

[0016] Another aspect of the present invention provides a three-dimensional memory, the three-dimensional memory including a plurality of memory strings and a plurality of word lines, each memory string including a plurality of memory cells connected in series from top to bottom, each word line being connected to a memory cell at the same height in each memory string, the three-dimensional memory further including: a control circuit configured to determine a selected word line for a programming verification operation; and, during the programming verification operation, to apply a first on-state voltage to a first word line region located on one side of the selected word line, and to apply a second on-state voltage to a second word line region located on the other side of the selected word line; wherein the memory cells connected to the word lines in the first word line region are in a programmed state, the memory cells connected to the word lines in the second word line region are in an unprogrammed state, and the magnitude of the second on-state voltage is adjustable.

[0017] In one embodiment of the present invention, the magnitude of the second conduction voltage gradually increases during the programming verification operation of the plurality of word lines.

[0018] In one embodiment of the present invention, the plurality of word lines are divided into a plurality of consecutive word line groups, wherein when the programming verification operation is performed on the word lines in each of the word line groups, the magnitude of the second on-state voltage is the same; wherein the magnitude of the second on-state voltage gradually increases during the programming verification operation on the plurality of word line groups.

[0019] Because the present invention adopts the above technical solution, it has the following significant advantages compared with the prior art:

[0020] The control method of the three-dimensional memory of the present invention applies a first conduction voltage to the programmed first word line region located on one side of the selected word line during the programming verification operation, and applies a second conduction voltage to the unprogrammed second word line region located on the other side of the selected word line, and makes the magnitude of the second conduction voltage adjustable. This control method can effectively improve the back model effect of the three-dimensional memory without the need for an additional voltage source. Attached Figure Description

[0021] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0022] Figure 1 This is a flowchart of a control method for a three-dimensional memory according to an embodiment of the present invention;

[0023] Figure 2 This is a schematic diagram of a control method for a three-dimensional memory according to an embodiment of the present invention;

[0024] Figure 3 This is a schematic diagram of another control method for a three-dimensional memory according to an embodiment of the present invention;

[0025] Figure 4 This is a voltage schematic diagram of a control method for a three-dimensional memory according to an embodiment of the present invention;

[0026] Figure 5 This is an architectural diagram of a three-dimensional memory according to an embodiment of the present invention. Detailed Implementation

[0027] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some examples or embodiments of this application. For those skilled in the art, these drawings can be applied to other similar scenarios without creative effort. Unless obvious from the context or otherwise specified, the same reference numerals in the drawings represent the same structures or operations.

[0028] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the invention is not limited to the specific embodiments disclosed below.

[0029] As indicated in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" are not specifically singular and may include plural forms. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0030] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps described in these embodiments do not limit the scope of this application. It should also be understood that, for ease of description, the dimensions of the various parts shown in the drawings are not drawn to actual scale. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following drawings denote similar items; therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0031] In detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure will be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0032] In the description of this application, it should be understood that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is usually based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0033] For ease of description, spatial relation terms such as “below,” “below,” “lower than,” “below,” “above,” “upper,” etc., may be used herein to describe the relationship of an element or feature shown in the accompanying drawings to other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, the orientation of an element described as “below,” “below,” or “below” to other elements or features will change to “above” said other elements or features. Thus, the exemplary terms “below” and “below” can encompass both upward and downward directions. The device may also have other orientations (rotated 90 degrees or in other orientations), and therefore the spatial relation descriptors used herein should be interpreted accordingly. Furthermore, it will be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more layers in between.

[0034] In the context of this application, the structure described above the second feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0035] It should be understood that when a component is referred to as "on another component," "connected to another component," "coupled to another component," or "in contact with another component," it can be directly on, connected to, coupled to, or in contact with that other component, or there may be an inserting component. In contrast, when a component is referred to as "directly on another component," "directly connected to," "directly coupled to," or "directly in contact with" another component, there is no inserting component.

[0036] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, these terms have no special meaning and therefore should not be construed as limiting the scope of protection of this application. In addition, although the terminology used in this application is selected from commonly known and used terms, some terms mentioned in this application's specification may have been chosen by the applicant according to his or her judgment, and their detailed meanings are explained in the relevant sections of this description. Moreover, this application should be understood not only through the actual terms used, but also through the meaning implied by each term.

[0037] In three-dimensional memory (e.g., 3D NAND), the back-pattern effect (BPD) is mainly due to the different programming states of memory cells above the selected word line during programming verification and read operations.

[0038] For example, when performing a programming verification operation on a selected word line WLn, the memory cells corresponding to word lines WLn+1 and above are in an erase state. However, when performing a read operation on a selected word line WLn, the memory cells corresponding to word lines WLn+1 and above are already in a random pattern programming state. This causes a significant increase in the series resistance of the memory cells corresponding to word lines WLn+1 and above during the read operation, resulting in an increase in the threshold voltage during the read operation and a broadening of the threshold voltage distribution.

[0039] To address the above problems, the following embodiments of the present invention propose a control method for a three-dimensional memory, which can effectively improve the back-model effect of the three-dimensional memory without the need for an additional voltage source.

[0040] The three-dimensional memory of the present invention includes multiple memory strings and multiple word lines. Each memory string includes multiple memory cells connected in series from top to bottom. Each word line is connected to a memory cell at the same height in each memory string.

[0041] The control method of the three-dimensional memory includes: determining a selected word line for programming verification operation; and applying a first on-state voltage to a first word line region located on one side of the selected word line and applying a second on-state voltage to a second word line region located on the other side of the selected word line during the programming verification operation; wherein, the memory cell connected to the word line in the first word line region is in a programmed state, the memory cell connected to the word line in the second word line region is in an unprogrammed state, and the magnitude of the second on-state voltage is adjustable.

[0042] Figure 1 This is a flowchart of a control method for a three-dimensional memory according to an embodiment of the present invention. The following is in conjunction with… Figure 1The control method will be described below. It is understood that the following description is merely exemplary, and those skilled in the art can make various changes without departing from the spirit of the invention.

[0043] refer to Figure 1 As shown, the method includes the following steps:

[0044] Step S10: Determine the selected word line for the programming verification operation.

[0045] Figure 2 This is a schematic diagram of a control method for a three-dimensional memory according to an embodiment of the present invention. Figure 3 This is a schematic diagram of another control method for a three-dimensional memory according to an embodiment of the present invention.

[0046] refer to Figure 2 and Figure 3 As shown, first determine the selected word line WLm for the programming verification operation.

[0047] In some examples, the three-dimensional memory includes multiple memory strings and multiple word lines. Each memory string includes multiple memory cells connected in series from top to bottom, and each word line is connected to the memory cells at the same height in each memory string.

[0048] For example, each memory string may include multiple top select tubes, multiple dummy memory cells at the top, multiple memory cells, multiple dummy memory cells at the bottom, and multiple bottom select tubes (not shown in the figure) connected in series from top to bottom.

[0049] Multiple top select transistors can be connected to the top select gate (TSG), and multiple dummy memory cells located at the top can be connected to dummy word lines of corresponding heights (e.g., multiple top dummy word lines, Top DMY). Multiple memory cells can also be connected to word lines of corresponding heights (e.g.,... Figure 2 or Figure 3 The word lines WLm-1, WLm, and WLm+1 shown are connected. Multiple dummy memory cells at the bottom are connected to dummy word lines at corresponding heights (e.g., multiple bottom dummy word lines Btm DMY). Multiple bottom select tubes are connected to the bottom select gate (BSG).

[0050] Preferably, the three-dimensional memory can be a 3D NAND.

[0051] In one embodiment of the present invention, programming can be either forward programming or reverse programming. For example, forward programming can refer to a bottom-up programming sequence, and reverse programming can refer to a top-down programming sequence, but the present invention is not limited thereto.

[0052] For example, in Figure 2 In one example shown, the programming order is forward programming. Figure 3 In one example shown, the programming order is reverse programming.

[0053] In step S20, during the programming verification operation, a first conduction voltage is applied to the first word line region located on one side of the selected word line, and a second conduction voltage is applied to the second word line region located on the other side of the selected word line.

[0054] In this configuration, the memory cells connected to the word lines in the first word line region are in a programmed state, the memory cells connected to the word lines in the second word line region are in an unprogrammed state, and the magnitude of the second on-state voltage is adjustable.

[0055] refer to Figure 2 As shown, in one embodiment of the present invention, when programming is forward programming, a first on-state voltage Vpass1 can be applied to the first word line region located on one side of the selected word line WLm, that is, word lines WLm-2 and below, during the programming verification operation, and a second on-state voltage Vpass2 can be applied to the second word line region located on the other side of the selected word line WLm, that is, word lines WLm+2 and above.

[0056] The memory cells connected to the word lines in the first word line region (e.g., word lines WL0 to WLm-2) are in a programmed state, and the memory cells connected to the word lines in the second word line region (e.g., word lines WLm+2 to WLn) are in an unprogrammed state. The magnitude of the second on-state voltage Vpass2 is adjustable.

[0057] refer to Figure 3 As shown, in another embodiment of the present invention, when programming is reverse programming, a first on-state voltage Vpass1 can be applied to the first word line region located on one side of the selected word line WLm, that is, word lines WLm-2 and above, and a second on-state voltage Vpass2 can be applied to the second word line region located on the other side of the selected word line WLm, that is, word lines WLm+2 and below.

[0058] The memory cells connected to the word lines in the first word line region (e.g., word lines WL0 to WLm-2) are in a programmed state, and the memory cells connected to the word lines in the second word line region (e.g., word lines WLm+2 to WLn) are in an unprogrammed state. The magnitude of the second on-state voltage Vpass2 is adjustable.

[0059] For example, a programmed memory cell can be in a programmed state; an unprogrammed memory cell can be in an erased state.

[0060] In one embodiment of the present invention, the magnitude of the second conduction voltage Vpass2 gradually increases during the programming verification operation of multiple word lines.

[0061] For example, in Figure 2 Forward programming or Figure 3 In the reverse programming embodiment shown, during the programming verification operation of multiple word lines (e.g., word lines WL0 to WLn), the magnitude of the second on-state voltage Vpass2 can be gradually increased.

[0062] refer to Figure 2 As shown, as a non-restrictive example, following the forward programming order, when the selected word lines are word line WLm-1, word line WLm, and word line WLm+1, the corresponding second word line regions are word lines WLm+1 and above, word lines WLm+2 and above, and word lines WLm+3 and above, respectively, and the corresponding second on-state voltage Vpass2 values ​​are V1, V2, and V3.

[0063] During the programming verification operation, the magnitude of the second conduction voltage Vpass2 applied to the second word line region gradually increases, therefore: V1≤V2≤V3.

[0064] Similarly, see reference Figure 3 As shown, as a non-restrictive example, following the reverse programming order, when the selected word lines are word line WLm-1, word line WLm, and word line WLm+1, the corresponding second word line regions are word lines WLm+1 and below, word lines WLm+2 and below, and word lines WLm+3 and below, respectively, and the corresponding second turn-on voltage Vpass2 values ​​are V1, V2, and V3, respectively.

[0065] During the programming verification operation, the magnitude of the second conduction voltage Vpass2 applied to the second word line region gradually increases, therefore: V1≤V2≤V3.

[0066] In one embodiment of the present invention, the multiple word lines can be further divided into multiple consecutive word line groups. When performing programming verification operations on the word lines in each word line group, the magnitude of the second on-state voltage is the same. The magnitude of the second on-state voltage gradually increases during the programming verification operations on the multiple word line groups.

[0067] In some examples, each character line group includes 1 to 20 character lines. The number of character lines in each character line group can be the same or different.

[0068] For example, refer to Figure 2As shown, during forward programming, when each word line group contains the same number of word lines, which is 10, multiple word lines (e.g., word lines WL0 to WLn) can be divided into (n+1) / 10 word line groups from bottom to top. That is, the first word line group is from word lines WL0 to WL9, the second word line group is from word lines WL10 to WL19, and so on.

[0069] Specifically, when performing programming verification operations on word lines in each sub-line group (e.g., the first word line group, etc.), the magnitude of the second on-state voltage Vpass2 is the same. The magnitude of the second on-state voltage Vpass2 gradually increases during the programming verification operations on multiple word line groups (e.g., the first word line group, the second word line group, and the third word line group).

[0070] For example, when performing programming verification operations on the word lines in the first word line group, the second word line group, and the third word line group, the magnitudes of the corresponding second conduction voltage Vpass2 are Vg1, Vg2, and Vg3, respectively.

[0071] During the programming verification operation, the magnitude of the second conduction voltage Vpass2 applied to the second word line region gradually increases according to the word line group, therefore: Vg1≤Vg2≤Vg3.

[0072] For example, refer to Figure 3 As shown, during reverse programming, when each word line group contains the same number of word lines, which is 10, multiple word lines (e.g., word lines WL0 to WLn) can be divided into (n+1) / 10 word line groups from top to bottom. That is, the first word line group is from word lines WL0 to WL9, the second word line group is from word lines WL10 to WL19, and so on.

[0073] Specifically, when performing programming verification operations on word lines in each sub-line group (e.g., the first word line group, etc.), the magnitude of the second on-state voltage Vpass2 is the same. The magnitude of the second on-state voltage Vpass2 gradually increases during the programming verification operations on multiple word line groups (e.g., the first word line group, the second word line group, and the third word line group).

[0074] For example, when performing programming verification operations on the word lines in the first word line group, the second word line group, and the third word line group, the magnitudes of the corresponding second conduction voltage Vpass2 are Vg1, Vg2, and Vg3, respectively.

[0075] During the programming verification operation, the magnitude of the second conduction voltage Vpass2 applied to the second word line region gradually increases according to the word line group, therefore: Vg1≤Vg2≤Vg3.

[0076] In one embodiment of the present invention, the control method further includes applying a third conduction voltage to at least one word line located between the selected word line and the first word line region and to at least one word line located between the selected word line and the second word line region.

[0077] For example, refer to Figure 2 As shown, during forward programming, a third on-state voltage Vpass3 can be applied to word line WLm-1 located between the selected word line WLm and the first word line region (i.e., word lines WLm-2 and below), and word line WLm+1 located between the selected word line WLm and the second word line region (i.e., word lines WLm+2 and above).

[0078] refer to Figure 3 As shown, during reverse programming, a third on-state voltage Vpass3 can be applied to word line WLm-1 located between the selected word line WLm and the first word line region (i.e., word lines WLm-2 and above), and word line WLm+1 located between the selected word line WLm and the second word line region (i.e., word lines WLm+2 and below).

[0079] In some embodiments, the control method of the three-dimensional memory of the present invention further includes: applying a programming verification voltage to a selected word line during a programming verification operation.

[0080] Figure 4 This is a voltage schematic diagram of a control method for a three-dimensional memory according to an embodiment of the present invention. (Reference) Figure 4 As shown, it is possible to... Figure 2 or Figure 3 The selected word line WLm is shown with a programming verification voltage Vverify applied.

[0081] In some embodiments, the magnitude of the second on-state voltage Vpass2 can be from 1V to 3V. Preferably, the magnitude of the second on-state voltage Vpass2 is 2V, but the invention is not limited thereto.

[0082] In some embodiments, the magnitude of the first turn-on voltage Vpass1 can be from 6V to 8V. Preferably, the magnitude of the first turn-on voltage Vpass1 is 6.6V, but the invention is not limited thereto.

[0083] In one embodiment of the present invention, the magnitude of the third conduction voltage Vpass3 is 6V to 8V.

[0084] Preferably, in the above embodiments of the present invention, the magnitude of the second conduction voltage Vpass2 is smaller than the magnitude of the first conduction voltage Vpass1, and the magnitude of the first conduction voltage Vpass1 is different from the magnitude of the third conduction voltage Vpass3.

[0085] In some embodiments, the magnitudes of the first on-state voltage Vpass1 and / or the third on-state voltage Vpass3 are fixed.

[0086] It should be understood that those skilled in the art can make corresponding adjustments to the magnitudes of the first conduction voltage Vpass1, the second conduction voltage Vpass2, and the third conduction voltage Vpass3 according to actual needs, and the present invention is not limited thereto.

[0087] The control method of the three-dimensional memory of the present invention applies a first on-state voltage Vpass1 to the programmed first word line region located on one side of the selected word line WLm during the programming verification operation, and applies a second on-state voltage Vpass2 to the unprogrammed second word line region located on the other side of the selected word line WLm, and makes the magnitude of the second on-state voltage Vpass2 adjustable, thereby effectively improving the back model (BPD) effect of the three-dimensional memory without the need for an additional voltage source.

[0088] Used here Figure 1 The flowchart shown illustrates the steps / operations performed by the control method according to embodiments of this application. It should be understood that these steps / operations are not necessarily performed precisely in sequence. Instead, various steps / operations can be processed in reverse order or simultaneously. Furthermore, other steps / operations may be added to these processes, or one or more steps / operations may be removed from these processes.

[0089] The above embodiments of the present invention propose a control method for a three-dimensional memory, which can effectively improve the back model effect of the three-dimensional memory without the need for an additional voltage source.

[0090] Another aspect of the present invention proposes a three-dimensional memory that can effectively improve the back-model effect of the three-dimensional memory without the need for an additional voltage source through its control circuit.

[0091] Figure 5 This is an architectural diagram of a three-dimensional memory according to an embodiment of the present invention. The following is in conjunction with... Figure 5 The three-dimensional memory will now be described. It is understood that the following description is merely exemplary, and those skilled in the art can make various changes without departing from the spirit of the invention.

[0092] It should be noted that the above-described control method of the present invention can be used in, for example... Figure 5 The invention is implemented in the three-dimensional memory 500 shown or in variations thereof, but is not limited thereto.

[0093] refer to Figure 5As shown, the three-dimensional memory 500 of the present invention includes multiple memory strings and multiple word lines. Each memory string includes multiple memory cells connected in series from top to bottom, and each word line is connected to memory cells at the same height in each memory string. The three-dimensional memory also includes a control circuit 510. The control circuit 510 is configured to determine a selected word line for programming verification operation; and during the programming verification operation, apply a first on-state voltage to a first word line region located on one side of the selected word line, and apply a second on-state voltage to a second word line region located on the other side of the selected word line. Memory cells connected to word lines in the first word line region are in a programmed state, memory cells connected to word lines in the second word line region are in an unprogrammed state, and the magnitude of the second on-state voltage is adjustable.

[0094] Preferably, the three-dimensional memory can be a 3D NAND.

[0095] In one embodiment of the present invention, programming can be either forward programming or reverse programming. For example, forward programming can refer to a bottom-up programming sequence, and reverse programming can refer to a top-down programming sequence, but the present invention is not limited thereto.

[0096] refer to Figure 2 As shown, in one embodiment of the present invention, when programming is forward programming, the control circuit 510 can apply a first on-state voltage Vpass1 to the first word line region located on one side of the selected word line WLm, that is, word lines WLm-2 and below, and apply a second on-state voltage Vpass2 to the second word line region located on the other side of the selected word line WLm, that is, word lines WLm+2 and above.

[0097] The memory cells connected to the word lines in the first word line region (e.g., word lines WL0 to WLm-2) are in a programmed state, and the memory cells connected to the word lines in the second word line region (e.g., word lines WLm+2 to WLn) are in an unprogrammed state. The magnitude of the second on-state voltage Vpass2 is adjustable.

[0098] refer to Figure 3 As shown, in another embodiment of the present invention, when programming is reverse programming, the control circuit 510 can apply a first on-state voltage Vpass1 to the first word line region located on one side of the selected word line WLm, that is, word lines WLm-2 and above, and apply a second on-state voltage Vpass2 to the second word line region located on the other side of the selected word line WLm, that is, word lines WLm+2 and below.

[0099] In this configuration, memory cells connected to word lines in the first word line region (e.g., word lines WL0 to WLm-2) are in a programmed state, while memory cells connected to word lines in the second word line region (e.g., word lines WLm+2 to WLn) are in an unprogrammed state. The magnitude of the second on-state voltage Vpass2 is adjustable.

[0100] In one embodiment of the present invention, the magnitude of the second conduction voltage Vpass2 gradually increases during the programming verification operation of multiple word lines.

[0101] For example, in Figure 2 Forward programming or Figure 3 In the reverse programming embodiment shown, during the programming verification operation of multiple word lines (e.g., word lines WL0 to WLn), the magnitude of the second on-state voltage Vpass2 can be gradually increased.

[0102] refer to Figure 2 As shown, as a non-restrictive example, following the forward programming order, when the selected word lines are word line WLm-1, word line WLm, and word line WLm+1, the corresponding second word line regions are word lines WLm+1 and above, word lines WLm+2 and above, and word lines WLm+3 and above, respectively, and the corresponding second on-state voltage Vpass2 values ​​are V1, V2, and V3.

[0103] During the programming verification operation, the magnitude of the second conduction voltage Vpass2 applied by the control circuit 510 to the second word line region gradually increases, so V1≤V2≤V3.

[0104] Similarly, see reference Figure 3 As shown, as a non-restrictive example, following the reverse programming order, when the selected word lines are word line WLm-1, word line WLm, and word line WLm+1, the corresponding second word line regions are word lines WLm+1 and below, word lines WLm+2 and below, and word lines WLm+3 and below, respectively, and the corresponding second turn-on voltage Vpass2 values ​​are V1, V2, and V3, respectively.

[0105] During the programming verification operation, the magnitude of the second conduction voltage Vpass2 applied by the control circuit 510 to the second word line region gradually increases, so V1≤V2≤V3.

[0106] In one embodiment of the present invention, the multiple word lines can be further divided into multiple consecutive word line groups. When performing programming verification operations on the word lines in each word line group, the magnitude of the second on-state voltage is the same. The magnitude of the second on-state voltage gradually increases during the programming verification operations on the multiple word line groups.

[0107] In some examples, each character line group includes 1 to 20 character lines. The number of character lines in each character line group can be the same or different.

[0108] For example, refer to Figure 2 As shown, during forward programming, when each word line group contains the same number of word lines, which is 10, multiple word lines (e.g., word lines WL0 to WLn) can be divided into (n+1) / 10 word line groups from bottom to top. That is, the first word line group is from word lines WL0 to WL9, the second word line group is from word lines WL10 to WL19, and so on.

[0109] Specifically, when performing programming verification operations on word lines in each sub-line group (e.g., the first word line group, etc.), the magnitude of the second on-state voltage Vpass2 is the same. The magnitude of the second on-state voltage Vpass2 gradually increases during the programming verification operations on multiple word line groups (e.g., the first word line group, the second word line group, and the third word line group).

[0110] For example, when performing programming verification operations on the word lines in the first word line group, the second word line group, and the third word line group, the magnitudes of the corresponding second conduction voltage Vpass2 are Vg1, Vg2, and Vg3, respectively.

[0111] During the programming verification operation, the magnitude of the second conduction voltage Vpass2 applied to the second word line region gradually increases according to the word line group, therefore: Vg1≤Vg2≤Vg3.

[0112] For example, refer to Figure 3 As shown, during reverse programming, when each word line group contains the same number of word lines, which is 10, multiple word lines (e.g., word lines WL0 to WLn) can be divided into (n+1) / 10 word line groups from top to bottom. That is, the first word line group is from word lines WL0 to WL9, the second word line group is from word lines WL10 to WL19, and so on.

[0113] Specifically, when performing programming verification operations on word lines in each sub-line group (e.g., the first word line group, etc.), the magnitude of the second on-state voltage Vpass2 is the same. The magnitude of the second on-state voltage Vpass2 gradually increases during the programming verification operations on multiple word line groups (e.g., the first word line group, the second word line group, and the third word line group).

[0114] For example, when performing programming verification operations on the word lines in the first word line group, the second word line group, and the third word line group, the magnitudes of the corresponding second conduction voltage Vpass2 are Vg1, Vg2, and Vg3, respectively.

[0115] During the programming verification operation, the magnitude of the second conduction voltage Vpass2 applied to the second word line region gradually increases according to the word line group, therefore: Vg1≤Vg2≤Vg3.

[0116] Further implementation details of the three-dimensional memory 500 in this embodiment can be found in [reference]. Figures 1 to 4 The described embodiments will not be elaborated further here. Those skilled in the art can make appropriate adjustments to the internal structure of the three-dimensional memory 500 according to actual needs, and the present invention is not limited thereto.

[0117] The three-dimensional memory 500 of the present invention effectively improves the back model (BPD) effect of the three-dimensional memory without the need for an additional voltage source by configuring the control circuit 510 to apply a first on-state voltage Vpass1 to the programmed first word line region located on one side of the selected word line WLm during the programming verification operation, and to apply a second on-state voltage Vpass2 to the unprogrammed second word line region located on the other side of the selected word line WLm, and making the magnitude of the second on-state voltage Vpass2 adjustable.

[0118] The above embodiments of the present invention propose a three-dimensional memory that can effectively improve the back-model effect of the three-dimensional memory without the need for an additional voltage source through its control circuit.

[0119] It is understood that although some inventive embodiments that are currently considered useful have been discussed through various examples in the above disclosure, it should be understood that such details are for illustrative purposes only, and the appended claims are not limited to the disclosed embodiments. On the contrary, the claims are intended to cover any combination of modifications and equivalents that conform to the substance and scope of the embodiments of this application.

[0120] The computer-readable storage media referred to in this application may include, but are not limited to, magnetic storage devices (e.g., hard disks, floppy disks, magnetic stripes), optical disks (e.g., compact discs (CDs), digital multifunction discs (DVDs)), smart cards, and flash memory devices (e.g., electrically erasable programmable read-only memory (EPROM), cards, sticks, key drives). Furthermore, the various storage media described herein can represent one or more devices and / or other machine-readable media for storing information. The term "machine-readable media" may include, but is not limited to, wireless channels and various other media (and / or storage media) capable of storing, containing, and / or carrying code and / or instructions and / or data.

[0121] It should be understood that the embodiments described above are merely illustrative. The embodiments described herein can be implemented in hardware, software, firmware, middleware, microcode, or any combination thereof. For hardware implementation, the processing unit can be implemented within one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, and / or other electronic units designed to perform the functions described herein, or combinations thereof.

[0122] The basic concepts have been described above. Obviously, for those skilled in the art, the above disclosure is merely illustrative and does not constitute a limitation of this application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and corrections to this application. Such modifications, improvements, and corrections are suggested in this application, and therefore remain within the spirit and scope of the exemplary embodiments of this application.

[0123] Furthermore, this application uses specific terms to describe embodiments of the application. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic related to at least one embodiment of the application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0124] The computer program code required for the operation of each part of this application can be written in any one or more programming languages, including object-oriented programming languages ​​such as Java, Scala, Smalltalk, Eiffel, JADE, Emerald, C++, C#, VB.NET, Python, etc., conventional procedural programming languages ​​such as C, Visual Basic, Fortran 2003, Perl, COBOL 2002, PHP, ABAP, dynamic programming languages ​​such as Python, Ruby, and Groovy, or other programming languages. This program code can run entirely on the user's computer, or as a standalone software package on the user's computer, or partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer through any network, such as a local area network (LAN) or wide area network (WAN), or connected to an external computer (e.g., via the Internet), or in a cloud computing environment, or used as a service such as Software as a Service (SaaS).

[0125] Furthermore, unless expressly stated in the claims, the order of processing elements and sequences, the use of numbers and letters, or other names described in this application are not intended to limit the order of the processes and methods of this application. Although the foregoing disclosure has discussed some currently considered useful embodiments of the invention through various examples, it should be understood that such details are for illustrative purposes only, and the appended claims are not limited to the disclosed embodiments; rather, the claims are intended to cover all modifications and equivalent combinations that conform to the substance and scope of the embodiments of this application. For example, while the system components described above can be implemented using hardware devices, they can also be implemented solely through software solutions, such as installing the described system on existing servers or mobile devices.

[0126] Similarly, it should be noted that, in order to simplify the description of the present application and thus aid in the understanding of one or more embodiments, the foregoing description of the embodiments of the present application sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of the present application requires more features than those mentioned in the claims. In fact, the embodiments contain fewer features than all the features of the single embodiments disclosed above.

[0127] In some embodiments, numbers describing the quantity of components and attributes are used. It should be understood that such numbers used in the description of embodiments are modified in some examples with the terms "approximately," "approximately," or "generally." Unless otherwise stated, "approximately," "approximately," or "generally" indicates that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may be changed depending on the characteristics required by individual embodiments. In some embodiments, numerical parameters should take into account specified significant digits and employ a general method of digit reservation. Although the numerical ranges and parameters used to confirm their breadth of scope in some embodiments of this application are approximate values, in specific embodiments, such values ​​are set as precisely as feasible.

[0128] Although the present invention has been described with reference to specific embodiments, those skilled in the art should recognize that the above embodiments are merely illustrative of the invention, and various equivalent changes or substitutions can be made without departing from the spirit of the invention. Therefore, any changes or modifications to the above embodiments within the essential spirit of the invention will fall within the scope of the claims of this application.

Claims

1. A control method for a three-dimensional memory, characterized in that, The three-dimensional memory comprises multiple memory strings; each memory string includes multiple memory cells connected in series; the method includes: When performing a programming verification operation on a memory cell connected to a selected word line, a programming verification voltage is applied to the selected word line, a first conduction voltage is applied to a first word line region located on one side of the selected word line, and a second conduction voltage is applied to a second word line region located on the other side of the selected word line. In this configuration, the memory cells connected to the word lines in the first word line region are in a programmed state, and the memory cells connected to the word lines in the second word line region are in an unprogrammed state; the first on-state voltage is greater than the second on-state voltage; and the word lines in the first word line region and the word lines in the second word line region are not adjacent to the selected word line.

2. The control method according to claim 1, characterized in that, The method further includes: When performing different programming verification operations on memory cells connected to different selected word lines, different second on-voltages are applied to the second word line regions located on different selected word lines.

3. The control method according to claim 1, characterized in that, The method further includes: when performing a programming verification operation on the memory cell connected to the selected word line, applying a third conduction voltage to the word line adjacent to the selected word line; wherein the magnitude of the first conduction voltage is different from the magnitude of the third conduction voltage.

4. The control method according to claim 1, characterized in that, The three-dimensional memory further includes multiple word lines that are respectively connected to the plurality of memory cells; the plurality of word lines are divided into multiple consecutive word line groups; the plurality of word line groups include at least a first word line group and a second word line group.

5. The control method according to claim 4, characterized in that, When performing a programming verification operation on a memory cell connected to two different word lines in the same word line group of the plurality of word line groups, the same second on-state voltage is applied to the second word line regions located on different selected word lines.

6. The control method according to claim 4, characterized in that, The plurality of character line groups further includes a third character line group; the method further includes: When performing different programming verification operations on selected word lines from the first word line group, the second word line group, and the third word line group, different second on-voltages are applied to the second word line regions located on different selected word lines. If the programming verification operations performed on the selected word lines in the first word line group, the second word line group, and the third word line group are executed sequentially, the second conduction voltage will increase sequentially.

7. The control method according to claim 2, characterized in that, When different programming verification operations are performed sequentially on memory cells connected to different selected word lines, the second on-state voltage applied to the second word line region when the programming verification operation is performed later is greater than the second on-state voltage applied to the second word line region when the programming verification operation is performed earlier.

8. The control method according to claim 1, characterized in that, The magnitude of the second turn-on voltage is 1V to 3V.

9. A three-dimensional memory, characterized in that, The three-dimensional memory comprises multiple memory strings; each memory string includes multiple memory cells connected in series, and the three-dimensional memory further includes: The control circuit is configured to apply a programming verification voltage to the selected word line, apply a first conduction voltage to a first word line region located on one side of the selected word line, and apply a second conduction voltage to a second word line region located on the other side of the selected word line when performing a programming verification operation on the memory cell connected to the selected word line. In this configuration, the memory cells connected to the word lines in the first word line region are in a programmed state, and the memory cells connected to the word lines in the second word line region are in an unprogrammed state; the first on-state voltage is greater than the second on-state voltage; and the word lines in the first word line region and the word lines in the second word line region are not adjacent to the selected word line.

10. The three-dimensional memory according to claim 9, characterized in that, When performing different programming verification operations on memory cells connected to different selected word lines, different second on-voltages are applied to the second word line regions located on different selected word lines.

11. The three-dimensional memory according to claim 9, characterized in that, When performing a programming verification operation on the memory cell connected to the selected word line, a third conduction voltage is applied to the word line adjacent to the selected word line; wherein the magnitude of the first conduction voltage is different from the magnitude of the third conduction voltage.

12. The three-dimensional memory according to claim 9, characterized in that, The three-dimensional memory further includes multiple word lines that are respectively connected to the plurality of memory cells; the plurality of word lines are divided into multiple consecutive word line groups; the plurality of word line groups include at least a first word line group and a second word line group.

13. The three-dimensional memory according to claim 12, characterized in that, When performing a programming verification operation on a memory cell connected to two different word lines in the same word line group of the plurality of word line groups, the same second on-state voltage is applied to the second word line regions located on different selected word lines.

14. The three-dimensional memory according to claim 12, characterized in that, The plurality of word line groups further includes a third word line group; the control circuit is further configured to... When performing different programming verification operations on selected word lines from the first word line group, the second word line group, and the third word line group, different second on-voltages are applied to the second word line regions located on different selected word lines. If the programming verification operations performed on the selected word lines in the first word line group, the second word line group, and the third word line group are executed sequentially, the second conduction voltage will increase sequentially.

15. The three-dimensional memory according to claim 10, characterized in that, When different programming verification operations are performed sequentially on memory cells connected to different selected word lines, the second on-state voltage applied to the second word line region when the programming verification operation is performed later is greater than the second on-state voltage applied to the second word line region when the programming verification operation is performed earlier.

16. The three-dimensional memory according to claim 9, characterized in that, The magnitude of the second turn-on voltage is 1V to 3V.

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