Semiconductor structure and method of forming the same

Abstract

The present application provides a semiconductor structure and a forming method thereof. The method comprises sequentially forming an epitaxial layer and a semiconductor layer on a substrate. A recess is formed in the epitaxial layer and the semiconductor layer. A first dielectric layer and a second dielectric layer are conformally formed on the recess. The dielectric constant of the second dielectric layer is greater than that of the first dielectric layer. A first conductive layer is formed on the second dielectric layer. The first conductive layer and the second dielectric layer are etched back so that the top surface of the first conductive layer and the top surface of the second dielectric layer are flush. A second conductive layer is formed on the first conductive layer.

Description

Technical Field

[0001] This application relates to semiconductor structures and methods for forming them, and in particular to semiconductor structures with excellent reliability and methods for forming them. Background Technology

[0002] Trench MOSFETs have a trench structure, which allows for smaller device pitch and lower gate-drain capacitance. gd This can effectively reduce the on-resistance (R). on It reduces switching losses and is suitable for use in high-power components.

[0003] Among these, shielded gate trench (SGT) MOSFETs have been developed. SGT MOSFETs incorporate a source electrode that serves as a shield electrode, meaning they include a source-shielded structure. Therefore, SGT MOSFETs can achieve lower on-resistance and lower switching losses based on charge-balancing techniques. However, with increasing demands, transistors are expected to have smaller dimensions to improve integration density. However, reducing transistor size typically requires a corresponding reduction in trench width, and the aspect ratio increases with decreasing trench width, leading to manufacturing difficulties.

[0004] Therefore, although existing semiconductor structures and their fabrication methods have gradually met their intended applications, they still do not completely meet the requirements in all aspects. Consequently, there are still some issues to be overcome regarding semiconductor structures and their fabrication methods that can be further processed into SGT-MOSFETs. Summary of the Invention

[0005] In view of the aforementioned problems, this application improves the reliability and electrical performance of the subsequently formed SGT-MOSFET by setting a dielectric layer with a high dielectric constant, such as a second dielectric layer between the first conductive layer and the second conductive layer, and by performing a specific process sequence of deposition and etching processes, thereby reducing and / or avoiding undesirable structures such as voids, holes, seam defects, and / or depressions on the top surface of the shielding electrode.

[0006] According to some embodiments, a method for forming a semiconductor structure is provided. The method includes: sequentially forming an epitaxial layer and a semiconductor layer on a substrate; forming a recess in the epitaxial layer and the semiconductor layer; conformally forming a first dielectric layer and a second dielectric layer on the recess, wherein the dielectric constant of the second dielectric layer is greater than the dielectric constant of the first dielectric layer; forming a first conductive layer on the second dielectric layer; etching back the first conductive layer and the second dielectric layer to make the top surfaces of the first conductive layer and the second dielectric layer flush; and forming the second conductive layer on the first conductive layer.

[0007] According to some embodiments, a semiconductor structure is provided. The semiconductor structure includes: a substrate, an epitaxial layer, a semiconductor layer, a first dielectric layer, a second dielectric layer, a first conductive layer, and a second conductive layer. The substrate has a first conductivity type. The epitaxial layer has a first conductivity type. The epitaxial layer is disposed on the substrate and includes a recess. The semiconductor layer has a second conductivity type different from the first conductivity type. The semiconductor layer is disposed on the epitaxial layer but not on the recess. The first dielectric layer is disposed on the recess. The second dielectric layer is disposed on the first dielectric layer. The dielectric constant of the second dielectric layer is greater than the dielectric constant of the first dielectric layer. The first conductive layer is disposed on the second dielectric layer. The second dielectric layer covers the bottom surface and side surfaces of the first conductive layer. The second conductive layer is directly disposed on the first conductive layer.

[0008] The semiconductor structure of this application can be applied to various types of semiconductor devices. To make the components and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0009] The following detailed description, in conjunction with the accompanying drawings, will provide a better understanding of the embodiments of this application. It is worth noting that, according to industry standard practice, some features may not be drawn to scale. In fact, for clarity of discussion, the dimensions of different features may be increased or decreased.

[0010] Figures 1 to 14 These are cross-sectional schematic diagrams illustrating the formation of semiconductor structures at various stages, based on some embodiments of this application.

[0011] Figure 15 This is a cross-sectional schematic diagram of a semiconductor structure according to some other embodiments of this application.

[0012] Icon labels:

[0013] 1,2: Semiconductor Structure

[0014] 100: Substrate

[0015] 200: Epitaxial layer

[0016] 210: concave part

[0017] 300: Semiconductor layer

[0018] 301: First doped region

[0019] 302: Second doped region

[0020] 303: Contact Material

[0021] 310: First dielectric layer

[0022] 400: Second dielectric layer

[0023] 500: First conductive layer

[0024] 510: Third dielectric layer

[0025] 600: Second conductive layer

[0026] 610: Gate dielectric layer

[0027] 700: Gate electrode

[0028] 800: Interlayer dielectric layer

[0029] 810: Metal layer

[0030] h1: First Height

[0031] t1: First thickness

[0032] t2: Second thickness

[0033] w1: First width

[0034] w2: Second width Detailed Implementation

[0035] The following description provides many different embodiments or examples for implementing various components of the provided semiconductor structure. Specific examples of each component and its configuration are described below to simplify the embodiments of this application. Of course, these are merely examples and are not intended to limit this application. For example, if the description mentions that a first component is formed on top of a second component, it may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components so that they are not in direct contact. Furthermore, component symbols and / or characters may be repeated in different examples of the embodiments of this application. Such repetition is for brevity and clarity, and is not intended to indicate a relationship between the different embodiments and / or styles discussed.

[0036] The following describes some variations of the embodiments. In embodiments with different figures and descriptions, similar component symbols are used to identify similar components. It is understood that additional operations may be provided before, during, or after the method, and some described operations may be replaced or deleted for other embodiments of the foregoing method.

[0037] Furthermore, spatial terms such as "above," "below," "over," "under," and similar expressions include not only the orientation shown in the diagrams but also the different orientations of the device during use or operation. When the device is turned to another orientation (rotated 90 degrees or other orientations), the spatial relative descriptions used here can also be interpreted according to the orientation after rotation. Here, "approximately," "substantially," or similar terms generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities; that is, even without specific mention of "approximately," "substantially," or similar terms, their meaning may still be implied.

[0038] Figures 1 to 14 This is a cross-sectional schematic diagram illustrating the formation of semiconductor structure 1 at various stages according to some embodiments of this application.

[0039] Reference Figure 1An epitaxial layer 200 and a semiconductor layer 300 are sequentially formed on a substrate 100. In some embodiments, the substrate 100 may be or include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or a similar substrate. Generally, an SOI substrate includes a semiconductor film layer formed on an insulator. For example, the aforementioned insulating layer may be a silicon oxide layer, a silicon nitride layer, a polysilicon layer, or a combination thereof. The aforementioned insulating layer is provided on a substrate that is typically silicon or aluminum nitride (AlN). The substrate 100 may be a doped substrate (e.g., using p-type or n-type dopant) or an undoped substrate. The substrate 100 may also be other types of substrates, such as a multi-layered substrate or a gradient substrate. In some embodiments, the substrate 100 may be an elemental semiconductor, and the aforementioned elemental semiconductor may include silicon and germanium; the substrate 100 may also be a compound semiconductor, and the aforementioned compound semiconductor may include, for example, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, but is not limited thereto; the substrate 100 may also be an alloy semiconductor, and the aforementioned alloy semiconductor may include, for example, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or any combination thereof, but is not limited thereto. In some embodiments, the substrate 100 is a silicon substrate.

[0040] In some embodiments, the epitaxial layer 200 and / or the semiconductor layer 300 may include silicon, germanium, silicon-germanium, III-V compounds, or combinations thereof. The aforementioned epitaxial layer 200 and / or semiconductor layer 300 may be formed by deposition or epitaxial processes such as metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), combinations thereof, or similar processes.

[0041] In some embodiments, the substrate 100 and epitaxial layer 200 have a first conductivity type, and the semiconductor layer 300 has a second conductivity type different from the first conductivity type. In some embodiments, if the first conductivity type of the substrate 100 and epitaxial layer 200 is N-type, then the second conductivity type of the semiconductor layer 300 is P-type. In some embodiments, if the first conductivity type of the substrate 100 and epitaxial layer 200 is P-type, then the second conductivity type of the semiconductor layer 300 is N-type. The first and second conductivity types can be adjusted as needed, and the doping concentration, doping depth, and size of the doped region can also be adjusted as needed. In some embodiments, the semiconductor layer 300 can also be formed on the epitaxial layer 200 after the gate electrode is formed subsequently. For ease of explanation, in the following embodiments, it will be described that the substrate 100 and epitaxial layer 200 have an N-type conductivity type, and the semiconductor layer 300 has a P-type conductivity type.

[0042] Reference Figure 2 A recess 210 is formed in the epitaxial layer 200 and the semiconductor layer 300. In some embodiments, the recess 210 penetrates the semiconductor layer 300 but not the epitaxial layer 200. In some embodiments, a patterned hard shielding layer with openings is formed on the semiconductor layer 300, and a portion of the top surface of the semiconductor layer 300 is exposed through the openings of the patterned hard shielding layer. Then, the patterned hard shielding layer is used as an etching shield to etch the semiconductor layer 300 and the epitaxial layer 200 to remove a portion of the semiconductor layer 300 and the epitaxial layer 200, thereby forming the recess 210. In some embodiments, the etching process may include dry etching, wet etching, or other etching processes. Dry etching may include, but is not limited to, plasma etching, plasma-free gas etching, sputter etching, ion milling, and reactive ion etching (RIE). Wet etching may include, but is not limited to, using an acidic solution, an alkaline solution, or a solvent to remove at least a portion of the structure to be removed. Afterward, the patterned hard shielding layer is removed. Understandably, it is possible to select appropriate patterned hard shielding layers, etching processes, and removal processes based on process conditions, and to adjust the size of the recess 210 according to subsequent electrical requirements.

[0043] Reference Figure 3A first dielectric layer 310 is formed conformally on the recess 210. In some embodiments, the first dielectric layer 310 has a shape corresponding to the recess 210. In some embodiments, the first dielectric layer 310 covers the top surface of the semiconductor layer 300 and the side and bottom surfaces of the recess 210. In some embodiments, the first dielectric layer 310 can be formed by a deposition process or a thermal oxidation process. The deposition process can be low-pressure chemical vapor deposition (LPCVD), low-temperature chemical vapor deposition (LTCVD), rapid thermal chemical vapor deposition (RTCVD), PECVD, atomic layer deposition (ALD), or other suitable deposition processes. In some embodiments, the first dielectric layer 310 can be formed by a thermal oxidation process.

[0044] In some embodiments, the first dielectric layer 310 may be silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material, any other suitable dielectric material, or a combination thereof. The aforementioned high-k dielectric material may be a metal oxide, metal nitride, metal silicide, transition metal oxide, transition metal nitride, transition metal silicide, metal oxynitride, metal aluminate, zirconium silicate, or zirconium aluminate. In some embodiments, the first dielectric layer 310 may include an oxide. In some embodiments, the first dielectric layer 310 may include silicon oxide. In some embodiments, the first dielectric layer 310 may have a first thickness t1. The first thickness t1 of the first dielectric layer 310 may be adjusted according to electrical requirements.

[0045] Reference Figure 4 A second dielectric layer 400 is compliantly formed on the first dielectric layer 310. In some embodiments, the second dielectric layer 400 has a shape corresponding to the first dielectric layer 310 and the recess 210. The second dielectric layer 400 covers the top surface of the semiconductor layer 300 and the side and bottom surfaces of the recess 210, and forms a trench with a first width w1 in the recess 210. In other words, the second dielectric layers 400 located on the side surfaces of the recess 210 have a first width w1 between them. In some embodiments, the first dielectric layer 310 is located between the second dielectric layer 400 and the semiconductor layer 300, and between the second dielectric layer 400 and the epitaxial layer 200. In some embodiments, the second dielectric layer 400 may be formed using the same or different processes as the first dielectric layer 310.

[0046] In some embodiments, the dielectric constant of the second dielectric layer 400 is greater than that of the first dielectric layer 310, and the second dielectric layer 400 may also be silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant dielectric material, any other suitable dielectric material, or a combination thereof. In some embodiments, the difference between the dielectric constant of the second dielectric layer 400 and the dielectric constant of the first dielectric layer 310 may be greater than or equal to 2, 2.5, or 3. For example, the dielectric constant of silicon oxide is approximately 4, and the dielectric constant of silicon nitride is approximately 7. In some embodiments, when the first dielectric layer 310 is silicon oxide, the second dielectric layer 400 is a material having a higher dielectric constant than silicon oxide, such as silicon nitride. In some embodiments, because the second dielectric layer 400 has a higher dielectric material than the first dielectric layer 310, the second dielectric layer 400 can reduce the electric field strength in the epitaxial layer 200, thereby improving the uniformity of charge distribution, reducing the on-resistance and / or increasing the breakdown voltage of the semiconductor structure. Detailed explanations will follow.

[0047] Reference Figure 5 A first conductive layer 500 is formed on the second dielectric layer 400. In some embodiments, the first conductive layer 500 is formed directly on the second dielectric layer 400. The first conductive layer 500 can be formed by chemical vapor deposition, sputtering, resistance heating evaporation, electron beam evaporation, or any other suitable deposition process. Figure 5 As shown, the first conductive layer 500 can be formed by filling the trenches formed in the second dielectric layer 400 with a first conductive material. Therefore, the first conductive layer 500 can be formed on the top surface of the semiconductor layer 300 and in the trenches formed in the second dielectric layer 400. In some embodiments, the first conductive material may include polycrystalline silicon, amorphous silicon, metal, metal nitride, conductive metal oxide, other suitable materials, or combinations thereof. In some embodiments, the first conductive material of the first conductive layer 500 may be polycrystalline silicon.

[0048] Reference Figure 6 The first conductive layer 500 and the second dielectric layer 400 are etched back to make the top surfaces of the first conductive layer 500 and the second dielectric layer 400 flush. In some embodiments, the top surfaces of the first conductive layer 500 and the second dielectric layer 400 may be lower than the top surface of the semiconductor layer 300. In some embodiments, the top surfaces of the first conductive layer 500 and the second dielectric layer 400 may be lower than the top surface of the epitaxial layer 200. In some embodiments, due to the miniaturization of the semiconductor structure, such as Figure 5When the filling material is used to form the first conductive layer 500, voids, holes, seam defects, or depressions may occur in the first conductive layer 500 due to excessive aspect ratio, excessively fast deposition rate, or even the characteristics of the conductive material. Therefore, an etching-back process can be performed to remove these defects, thereby improving the integrity and reliability of the first conductive layer 500. In some embodiments, the depth of the etching-back process may depend on the location of any defects in the first conductive layer 500 and / or the required electrical properties. Therefore, the etching-back process can remove any defects in the first conductive layer 500 and improve its reliability.

[0049] In some embodiments, since the top surfaces of the first conductive layer 500 and the second dielectric layer 400 are flush after the etch-back process, the first conductive layer 500 and the second dielectric layer 400 have substantially the same etching rate. For example, when the first conductive layer 500 is polysilicon, the second dielectric layer 400 may be silicon nitride. In some embodiments, the etching rate of the first conductive layer 500 and / or the second dielectric layer 400 can be adjusted by an implantation process such as p-type doping or n-type doping to make the first conductive layer 500 and the second dielectric layer 400 have substantially the same etching rate.

[0050] It should be noted that in some embodiments, after the etch-back process, the second dielectric layer 400 covers the bottom and side surfaces of the first conductive layer 500. That is, the first conductive layer 500 can be housed within the U-shaped second dielectric layer 400, effectively separating the first conductive layer 500 from the epitaxial layer 200 through the second dielectric layer 400. The second dielectric layer 400 and the first dielectric layer 310 can be located between the first conductive layer 500 and the epitaxial layer 200. Since the dielectric constant of the second dielectric layer 400, which is closer to the first conductive layer 500, is greater than that of the first dielectric layer 310, which is farther from the first conductive layer 500, the second dielectric layer 400 can adjust the capacitance in the epitaxial layer 200, reduce the electric field strength in the epitaxial layer 200, and improve the uniformity of charge distribution, thereby reducing the on-resistance and / or increasing the breakdown voltage of the semiconductor structure. Furthermore, maintaining the gate charge while reducing on-resistance and increasing breakdown voltage improves the performance index (Figure of Merits, FOM) of the formed SGT-MOSFET, thereby reducing switching and conduction losses and / or improving efficiency.

[0051] Reference Figure 7The first dielectric layer 310 is etched back to expose the side surfaces of the recess 210. In some embodiments, the first dielectric layer located on the semiconductor layer 300 is removed, and a portion of the first dielectric layer 310 located on the side surfaces of the recess 210 is also removed. In some embodiments, the aspect ratio of the trench used to form the subsequent second conductive layer is increased by etching back the first dielectric layer 310. In some embodiments, after etching back the first dielectric layer 310, the top surface of the first dielectric layer 310 is substantially flush with or below the top surfaces of the first conductive layer 500 and the second dielectric layer 400. In other words, the top surface of the first conductive layer 500 is substantially flush with the top surface of the second dielectric layer 400, and substantially higher than or flush with the top surface of the first dielectric layer 310. Therefore, there may be a first height difference h1 between the top surface of the first dielectric layer 310 and the top surfaces of the first conductive layer 500 and the second dielectric layer 400, wherein the first height h1 may be greater than or equal to 0. The first height h1 may affect the shape of the subsequently formed second conductive layer. For ease of explanation, the following embodiments are described with the first height h1 being greater than 0, but this application is not limited thereto.

[0052] Reference Figure 8 A third dielectric layer 510 is formed to cover the exposed side surface of the recess 210. In some embodiments, the third dielectric layer 510 is formed on the top surface of the semiconductor layer 300 and the side surface of the recess 210. In some embodiments, the third dielectric layer 510 may be formed using the same or different process as the first dielectric layer 310.

[0053] In some embodiments, the dielectric constant of the second dielectric layer 400 is greater than the dielectric constant of the third dielectric layer 510, and the third dielectric layer 510 may also be silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant dielectric material, any other suitable dielectric material, or a combination thereof. For example, in some embodiments, when the third dielectric layer 510 is silicon oxide, the second dielectric layer 400 is a material having a higher dielectric constant than silicon oxide, such as silicon nitride. In some embodiments, the dielectric constant of the second dielectric layer 400 is greater than the dielectric constants of the first dielectric layer 310 and the third dielectric layer 510. For example, the first dielectric layer 310 and the third dielectric layer 510 are silicon oxide, and the second dielectric layer 400 is silicon nitride.

[0054] It should be noted that in some embodiments, the third dielectric layer 510 may have a second thickness t2, and the second thickness t2 of the third dielectric layer is equal to or less than the first thickness t1 of the first dielectric layer. Therefore, there is a second width w2 between the third dielectric layers 510 on the side surface of the recess 210, and the second width w2 is greater than or equal to the first width w1 between the second dielectric layers 400 on the side surface of the recess 210. Thus, when the depth of the recess 210 is a constant, the aspect ratio of the material filling the first conductive layer 500 in the recess 210 is greater than the aspect ratio of the material subsequently filled into the second conductive layer in the recess 210. Therefore, by providing a third dielectric layer with a second thickness t2 equal to or less than the first thickness t1, the aspect ratio of the material subsequently filled into the second conductive layer can be reduced, thereby reducing and / or avoiding voids, holes, seam defects, and / or depressions at the top surface of the second conductive layer, thus improving the reliability of the second conductive layer. For ease of explanation, the following description uses an example where the second thickness t2 is less than the first thickness t1.

[0055] Reference Figure 9 A second conductive layer 600 is formed in the recess 210. In some embodiments, the second conductive layer 600 is formed on the first conductive layer 500. In some embodiments, the second conductive layer 600 may be formed directly on the first conductive layer 500 and the second dielectric layer 400. In some embodiments, the second conductive layer 600 may be formed using the same or different processes as the first conductive layer 500. Figure 9 As shown, the second conductive layer 600 can be formed by filling a trench formed by the third dielectric layer 510, the first dielectric layer 310, the second dielectric layer 400, and the first conductive layer 500 with a second conductive material. Therefore, the second conductive layer 600 can be formed on the top surface of the semiconductor layer 300 and on the first dielectric layer 310, the second dielectric layer 400, and the first conductive layer 500. In some embodiments, the third dielectric layer 510 and the second dielectric layer 400 may be spaced apart in the lateral direction, so the material for filling the second conductive layer 600 can be placed between the third dielectric layer 510 and the second dielectric layer 400. In some embodiments, the second conductive layer 600 is in contact with the third dielectric layer 510. In some embodiments, the second dielectric layer 400, the first conductive layer 500, and the second conductive layer 600 are in contact with each other.

[0056] In some embodiments, the second conductive layer 600 may include polycrystalline silicon, amorphous silicon, metal, metal nitride, conductive metal oxide, other suitable materials, or combinations thereof. In some embodiments, the second conductive material of the second conductive layer 600 may be polycrystalline silicon. In some embodiments, since the first conductive layer 500 and the second conductive layer 600 may be formed of the same material, the first conductive layer 500 and the second conductive layer 600 do not have a clear interface and can be regarded as a whole.

[0057] Reference Figure 10 The second conductive layer 600 is etched back to make its top surface lower than the top surface of the semiconductor layer 300. In some embodiments, the top surface of the second conductive layer 600 may be lower than the top surface of the epitaxial layer 200. In some embodiments, even if the aspect ratio of the trench used to form the second conductive layer 600 is smaller than that of the trench used to form the first conductive layer 500, undesirable structures such as voids, holes, seam defects, and / or depressions at the top surface of the second conductive layer 600 may still occur in the second conductive layer 600. Therefore, undesirable structures can be removed by performing an etching back process. The depth of etching back the second conductive layer 600 may depend on the location of the undesirable structures that may exist in the second conductive layer 600 and / or the required electrical properties. Therefore, the etching back process can remove undesirable structures that may exist in the second conductive layer 600 and improve the reliability of the second conductive layer 600.

[0058] It should be noted that, in some embodiments, the first conductive layer 500 and the second conductive layer 600 can be integrally regarded as shield electrodes in the SGT-MOSFET obtained after subsequent processing. In some embodiments, the shield electrode can be connected to the source electrode of the SGT-MOSFET obtained after subsequent processing, or the shield electrode can be regarded as part of the source electrode of the SGT-MOSFET obtained after subsequent processing. In some embodiments, since the second conductive layer 600 can be directly formed on the first conductive layer 500 and the second dielectric layer 400, the top surface of the second conductive layer 600 is larger than the top surface of the first conductive layer 500. In some embodiments, the width of the top surface of the second conductive layer 600 is a second width w2, and the width of the top surface of the first conductive layer 500 is a first width w1. Therefore, the first conductive layer 500 and the second conductive layer 600, which serve as shield electrodes in this application, can have a shape that is wider at the top and narrower at the bottom. For example, the shield electrode can have a T-shaped cross-section.

[0059] Accordingly, in the SGT-MOSFET obtained after subsequent processing, the first dielectric layer 310 and the third dielectric layer 510 can also be regarded as a shielded dielectric layer as a whole. Therefore, the first dielectric layer 310 and the third dielectric layer 510, which serve as shielded dielectric layers in this application, can have a shape that is wider at the bottom and narrower at the top. For example, the shielded dielectric layer can have a step-shaped cross-section. Thus, when the shielding electrode has a T-shaped cross-section and the shielded dielectric layer has a step-shaped cross-section, the electric field distribution can be made more uniform, thereby reducing the on-resistance and / or increasing the breakdown voltage of the semiconductor structure. When the shielded dielectric layer near the bottom surface of the recess 210 has a thicker thickness, the electric field concentrated at the bottom surface of the recess 210 can be reduced, resulting in a more uniform charge.

[0060] like Figure 10 As shown, in embodiments where the second thickness t2 of the third dielectric layer 510 is less than the first thickness t1 of the first dielectric layer 310, the second conductive layer 600 extends beyond the second dielectric layer 400 in the lateral direction. In some embodiments, the second conductive layer 600 may include a portion extending toward the substrate 100. In some embodiments, the aforementioned portion of the second conductive layer 600 extending toward the substrate 100 may be located between the second dielectric layer 400 and the third dielectric layer 510, thereby achieving the beneficial effect of a more uniform electric field distribution.

[0061] In some embodiments, the aforementioned portion of the second conductive layer 600 extending toward the substrate 100 may cover the side surface of the second dielectric layer 400 near the third dielectric layer 510. Therefore, the second conductive layer 600 may cover the upper portion of the first conductive layer 500. This allows the shielding electrode to form a smooth profile during subsequent gate dielectric layer formation, preventing an increase in the electric field between the subsequently formed gate electrode and the shielding electrode, thus avoiding increased leakage current. In other words, the contours of the first conductive layer 500 and the second conductive layer 600, which can be considered as a whole as shielding electrodes, are relatively flat, which is beneficial for forming the gate electrode above the shielding electrode. Furthermore, by providing a shielding electrode with a relatively flat contour, the problem of increased electric field between the shielding electrode and the gate electrode can be prevented or avoided. In some embodiments, the second conductive layer 600 covers the top surface of the first conductive layer 500 and the top surface of the second dielectric layer 400. In some embodiments, the second conductive layer 600 may have a cap-shaped cross-section.

[0062] In some embodiments, the second dielectric layer 400 is disposed between the first conductive layer 500 and the second conductive layer 600, thereby achieving the beneficial effect of reducing the critical electric field.

[0063] Reference Figure 11A gate dielectric layer 610 is formed on the second conductive layer 600, wherein forming the gate dielectric layer 610 removes a portion of the third dielectric layer 510, leaving only a portion flush with or below the top surface of the second conductive layer 600. In some embodiments, the top surface of the third dielectric layer 510 may be flush with the top surface of the second conductive layer 600. In some embodiments, after removing a portion of the third dielectric layer 510, the gate dielectric layer 610 is compliantly formed on the semiconductor layer 300, the third dielectric layer 510, and the second conductive layer 600. In some embodiments, the gate dielectric layer 610 may be silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, a combination thereof, or other suitable dielectric materials, but is not limited thereto. In some embodiments, the gate dielectric layer 610 may include an oxide. In some embodiments, the gate dielectric layer 610 and the first dielectric layer 310 and / or the third dielectric layer 510 may be formed using the same or different processes.

[0064] Reference Figure 12 A gate electrode 700 is formed on the gate dielectric layer 610. In some embodiments, the gate dielectric layer 610 may be formed using the same or different materials and processes as the first conductive layer 500 and / or the second conductive layer 600. In some embodiments, the process for forming the gate electrode 700 includes an etch-back process or a chemical mechanical polishing (CMP) process. In some embodiments, the top surface of the gate electrode 700 may be substantially flush with the top surface of the gate dielectric layer 610. In some embodiments, the gate dielectric layer 610 located on the semiconductor layer 300 may be removed, thereby making the top surface of the gate electrode 700 substantially flush with the top surface of the semiconductor layer 300. In some embodiments, since the thickness of the gate dielectric layer 610 may be less than that of the first conductive layer 500 and / or the second conductive layer 600, the gate dielectric layer 610 may be formed on the gate dielectric layer 610. Figure 3 The first dielectric layer 310 shown has a first thickness t1, therefore the width of the gate electrode 700 can be greater than that shown. Figure 10 The first width w1 of the first conductive layer 500 is shown. In some embodiments, since the thickness of the gate dielectric layer 610 can be substantially the same as that shown... Figure 8 The second thickness t2 of the third dielectric layer 510 shown is the same, therefore the width of the gate electrode 700 can be substantially the same as that shown. Figure 10 The second width w2 of the second conductive layer 600 shown is the same. However, the thickness of the gate dielectric layer 610 and the width of the gate electrode 700 can be adjusted according to electrical requirements.

[0065] Reference Figure 13A first doped region 301 is formed on the surface of the semiconductor layer 300 away from the substrate 100. The first doped region 301 can be formed by ion implantation or diffusion processes, but is not limited to these. In addition, the implanted dopant can also be activated by a rapid thermal annealing (RTA) process.

[0066] In some embodiments, an interlayer dielectric layer 800 may be formed on the gate electrode 700. Specifically, the interlayer dielectric layer 800 may be formed on the gate dielectric layer 610 and the gate electrode 700. In some embodiments, the interlayer dielectric layer 800 may be formed using the same or different materials and processes as the first dielectric layer 310, the third dielectric layer 510, and / or the gate dielectric layer 610.

[0067] Reference Figure 14 The diagram shows a cross-sectional view of semiconductor structure 1. For example... Figure 14 As shown in the semiconductor structure 1, a contact via can be further formed. In some embodiments, the contact via penetrates the interlayer dielectric layer 800, the gate dielectric layer 610, and the first doped region 301 to the semiconductor layer 300, but does not penetrate the semiconductor layer 300. Next, a second doped region 302 is formed below the contact via. The second doped region 302 has a different conductivity type than the first doped region 301. Then, a via material is filled into the contact via to form a contact 303. In some embodiments, the via material may include a metallic material, a conductive material, other suitable materials, or a combination thereof. A metal layer 810 is then formed on the interlayer dielectric layer 800, so that the metal layer 810 and the contact 303 are in contact with each other to obtain the semiconductor structure 1. In some embodiments, the metal layer 810 may include a metallic material, a conductive material, other suitable materials, or a combination thereof. The semiconductor structure 1 may be, or may be further processed, to serve as an SGT-MOSFET.

[0068] In some embodiments, the substrate 100, the epitaxial layer 200, and the first doped region 301 have a first conductivity type. The doping concentration of the first doped region 301 may be higher than the doping concentration of the substrate 100 and the epitaxial layer 200. The semiconductor layer 300 and the second doped region 302 have a second conductivity type different from the first conductivity type. The doping concentration of the second doped region 302 may be higher than the doping concentration of the semiconductor layer 300. Specifically, when the substrate 100 and the epitaxial layer 200 are N-type and the semiconductor layer 300 is P-type, the first doped region 301 may be a heavily doped N+ type, and the second doped region 302 may be a heavily doped P+ type.

[0069] Reference Figure 15This is a cross-sectional schematic diagram of semiconductor structure 2 according to some other embodiments of this application. Figure 15 As shown in semiconductor structure 2, in an embodiment where the second thickness t2 of the third dielectric layer 510 is substantially equal to the first thickness t1 of the first dielectric layer 310, the second conductive layer 600 is substantially flush with the second dielectric layer 400 in the lateral direction. In some embodiments, the second conductive layer 600 is directly disposed on the first conductive layer 500 and the second dielectric layer 400. In some embodiments, the side surface of the second conductive layer 600 is flush with the side surface of the second dielectric layer 400 near the epitaxial layer 200. By adjusting the relationship between the thicknesses of the first dielectric layer 310, the second dielectric layer 400, and the third dielectric layer 510, it is easier to adjust the shape of the shielding dielectric layer, which is wider at the bottom and narrower at the top, making it easier to achieve a suitable stepped profile. This allows for a more uniform electric field distribution, thereby reducing the on-resistance and / or increasing the breakdown voltage of the semiconductor structure. In some embodiments, the width of the gate electrode 700 may be greater than the widths of the second conductive layer 600 and the first conductive layer 500. In other words, the width of the gate electrode 700 can be greater than the width of the shield electrode, thereby making the electric field distribution more uniform and improving the process margin for subsequent gate contact formation.

[0070] In summary, according to some embodiments of this application, the formation method of this application, through a two-stage formation process of first forming a first conductive layer and then etching back the first conductive layer; then forming a second conductive layer and then etching back the second conductive layer, respectively improves the reliability of the first and second conductive layers, thereby avoiding / reducing undesirable structures such as voids, holes, seam defects, and / or depressions at the top surfaces of the first and second conductive layers, and thus improving the overall electrical performance and reliability of the semiconductor structure. The formation method of this application, by forming a second dielectric layer with a higher dielectric constant in the first and second conductive layers before forming the first conductive layer, reduces the electric field in the epitaxial layer, thereby improving electrical performance. For example, it can reduce on-resistance and switching losses.

[0071] Furthermore, in the semiconductor structure of this application, the area of ​​the top surface of the second conductive layer is larger than the area of ​​the top surface of the first conductive layer. Therefore, when the first and second conductive layers together serve as shielding electrodes, the shielding electrodes can have a shape that is wider at the top and narrower at the bottom. Since the shielding electrodes have a smaller area near the bottom surface of the recess, the electric field strength concentrated at the bottom surface of the recess can be reduced. Moreover, in the semiconductor structure of this application, the thickness of the first dielectric layer can be greater than the thickness of the third dielectric layer. Therefore, when the first and third dielectric layers together serve as shielding dielectric layers located around the shielding electrodes, the shielding dielectric layers can have a shape that is wider at the bottom and narrower at the top. Since the shielding dielectric layers have a larger area near the bottom surface of the recess, the electric field strength concentrated at the bottom surface of the recess can be reduced. In addition, the second dielectric layer, which has a higher dielectric constant, can also reduce the concentrated electric field strength. Therefore, through the above configuration, the on-resistance can be further reduced, the switching loss reduced, and the electrical performance of the semiconductor structure improved.

[0072] The scope of protection of this application is not limited to the processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps described in the specific embodiments of the specification. Any person skilled in the art can understand, from the disclosure of some embodiments of this application, current or future developed processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps. Any such processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps that can perform substantially the same function or obtain substantially the same results in the embodiments described herein can be used according to some embodiments of this application. Therefore, the scope of protection of this application includes the aforementioned processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps. Furthermore, each patent claim constitutes an individual embodiment, and the scope of protection of this application also includes combinations of various patent claims and embodiments.

[0073] The above outlines several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments described herein. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of this application to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of this application, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of this application.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: An epitaxial layer and a semiconductor layer are sequentially formed on a substrate; A recess is formed in the epitaxial layer and the semiconductor layer; A first dielectric layer and a second dielectric layer are compliantly formed on the recess, wherein the dielectric constant of the second dielectric layer is greater than the dielectric constant of the first dielectric layer; A first conductive layer is formed on the second dielectric layer; The first conductive layer and the second dielectric layer are etched back to make the top surface of the first conductive layer and the top surface of the second dielectric layer flush. After etching back the first conductive layer and the second dielectric layer, the first dielectric layer is etched back to expose one side surface of the recess; A third dielectric layer is formed to cover the side surface of the recess; as well as A second conductive layer is formed on the first conductive layer and the second dielectric layer, so that the second conductive layer is in direct contact with the first conductive layer, the second dielectric layer and the third dielectric layer. The second conductive layer further includes a portion extending toward the substrate, and the portion of the second conductive layer is located between the second dielectric layer and the third dielectric layer.

2. The forming method according to claim 1, characterized in that, The first dielectric layer is etched back so that the top surface of the first dielectric layer is substantially lower than the top surface of the first conductive layer.

3. The forming method according to claim 1, characterized in that, The thickness of the third dielectric layer is less than the thickness of the first dielectric layer.

4. The forming method according to claim 1, characterized in that, Also includes: A gate dielectric layer is formed on the second conductive layer; as well as A gate electrode is formed on the gate dielectric layer.

5. The forming method according to claim 4, characterized in that, Also includes: A first doped region and a second doped region are formed in the semiconductor layer; A dielectric layer is formed on the gate electrode; A contact is formed, which passes through the interlayer dielectric layer and the first doped region to contact the second doped region; as well as A metal layer is formed on the interlayer dielectric layer, and the metal layer is electrically connected to the second doped region through the contact.

6. The forming method according to claim 5, characterized in that, The substrate, the epitaxial layer, and the first doped region have a first conductivity type, and the semiconductor layer and the second doped region have a second conductivity type different from the first conductivity type.

7. A semiconductor structure, characterized in that, include: A substrate having a first conductivity type; An epitaxial layer having the first conductivity type is disposed on the substrate and includes a recess; A semiconductor layer having a second conductivity type different from the first conductivity type is disposed on the epitaxial layer but not on the recess; A first dielectric layer is disposed on the recess, and the first dielectric layer exposes one side surface of the recess; A second dielectric layer is disposed on the first dielectric layer, and the dielectric constant of the second dielectric layer is greater than the dielectric constant of the first dielectric layer; A third dielectric layer is disposed on the side surface of the recess; A first conductive layer is disposed on the second dielectric layer, and the second dielectric layer covers a bottom surface and a side surface of the first conductive layer; as well as A second conductive layer is directly disposed on the first conductive layer and the second dielectric layer, and the second conductive layer is in direct contact with the first conductive layer and the second dielectric layer. The second conductive layer further includes a portion extending toward the substrate, and the portion of the second conductive layer is located between the second dielectric layer and the third dielectric layer.

8. The semiconductor structure according to claim 7, characterized in that, The thickness of the third dielectric layer is less than the thickness of the first dielectric layer.

9. The semiconductor structure according to claim 7, characterized in that, Also includes: A gate dielectric layer is disposed on the second conductive layer; and A gate electrode is disposed on the gate dielectric layer.

10. The semiconductor structure according to claim 9, characterized in that, Also includes: A first doped region and a second doped region are disposed in the semiconductor layer; An interlayer dielectric layer is disposed on the gate electrode; A contact material passes through the interlayer dielectric layer and the first doped region to contact the second doped region; as well as A metal layer is disposed on the interlayer dielectric layer, and the metal layer is electrically connected to the second doped region through the contact material.

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