Three-dimensional integrated structure and method of manufacturing the same

Abstract

The application provides a three-dimensional integrated structure and a manufacturing method thereof. The three-dimensional integrated structure comprises heat dissipation fins stacked along the thickness direction on a first device substrate and arranged adjacently, which improves the heat dissipation capacity of the three-dimensional integrated structure. The metal heat dissipation layer in the heat dissipation fin can be manufactured through a film forming process, and the heat dissipation is performed relative to the manufacturing of heat dissipation channels, so that the manufacturing difficulty is greatly reduced, the yield and reliability of the product are ensured, and the cost is low because the heat dissipation fins are stacked with the first device substrate and do not affect the lateral area of the three-dimensional integrated structure. The manufacturing method of the three-dimensional integrated structure can be used for manufacturing the three-dimensional integrated structure.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a three-dimensional integrated structure and its fabrication method. Background Technology

[0002] As Moore's Law slows down, in order to continue improving the performance of integrated circuits (ICs), IC manufacturing is gradually moving towards three-dimensional (3D) integration technology. This process can increase chip bandwidth and improve computing performance.

[0003] 3D integration technology stacks and interconnects multiple wafers or chips with different functions or fabricated using different processes in three dimensions. While achieving superior functionality in a small area, it is prone to heat accumulation, resulting in a high heat flux density in the formed 3D integrated chip and heat buildup problems. At the same time, due to the different heat resistance of different internal components, the thermal reliability of the 3D integrated chip is prone to be poor.

[0004] To improve heat dissipation, one proposed method is to design heat dissipation microchannel structures within the 3D integrated chip. This utilizes coolant for heat conduction and solid-liquid heat diffusion, effectively removing heat from the 3D integrated chip and mitigating heat accumulation. However, designing complex microchannel structures within the 3D integrated chip increases manufacturing complexity and significantly reduces product yield and reliability. Another proposed method is to design additional heat dissipation and heat conduction areas on the 3D integrated chip. Heat generated by the underlying chip is then dissipated through heat dissipation pipes within the 3D integrated chip. While this can improve heat accumulation, the heat dissipation and heat conduction areas and pipes occupy a portion of the lateral area of ​​the 3D integrated chip, increasing the difficulty of miniaturization and significantly increasing costs. Summary of the Invention

[0005] To improve the heat dissipation capacity of the three-dimensional integrated structure while avoiding a significant increase in manufacturing difficulty and cost, this invention provides a three-dimensional integrated structure and a method for manufacturing the three-dimensional integrated structure.

[0006] On one hand, the present invention provides a three-dimensional integrated structure, including a first device substrate and a heat sink stacked adjacent to each other along the thickness direction; wherein, the first device substrate includes a top metal layer and a first bonding layer, the top metal layer and the heat sink are respectively located on both sides of the first bonding layer, the top metal layer includes a hot spot, and the first bonding layer is provided with a first metal bonding pad connected to the hot spot; the heat sink includes:

[0007] The substrate includes opposing first and second surfaces; and

[0008] A first dielectric layer, a first metal heat dissipation layer, and a second bonding layer are sequentially formed on the first surface. The second bonding layer is provided with a second metal bonding pad that is connected to the first metal heat dissipation layer. The second metal bonding pad is bonded to the first metal bonding pad.

[0009] Optionally, the first metal heat dissipation layer includes a heat-spreading structure extending along the surface of the first dielectric layer and formed around the second metal bonding pad, wherein the heat-spreading structure is a solid metal layer or a perforated metal layer.

[0010] Optionally, the heat dissipation structure includes multiple intersecting metal wires.

[0011] Optionally, the heat sink further includes:

[0012] A second dielectric layer and a second metal heat dissipation layer are sequentially formed on the second surface;

[0013] TSV thermal vias pass through the substrate and the first dielectric layer, and are connected at both ends to the first metal heat dissipation layer and the second metal heat dissipation layer, respectively.

[0014] Optionally, the three-dimensional integrated structure further includes:

[0015] The second device substrate is disposed on the other side of the heat sink relative to the first device substrate;

[0016] The TSV conduction structure passes through the heat sink and is electrically connected to the second device substrate and the first device substrate respectively. The TSV conduction structure is insulated from the first metal heat sink and the second metal heat sink.

[0017] Optionally, the three-dimensional integrated structure further includes:

[0018] A third device substrate is stacked on the side of the first device substrate away from the heat sink, and the third device substrate is electrically interconnected with the first device substrate.

[0019] On one hand, the present invention provides a method for fabricating a three-dimensional integrated structure, comprising:

[0020] A first device substrate is formed, the first device substrate includes a top metal layer and a first bonding layer located on the top metal layer, the top metal layer includes a hot spot, and a first metal bonding pad connected to the hot spot is disposed in the first bonding layer.

[0021] A heat sink is formed, the heat sink including a substrate having opposing first and second surfaces, the heat sink further including a first dielectric layer, a first metal heat dissipation layer, and a second bonding layer sequentially formed on the first surface, the second bonding layer having a second metal bonding pad connected to the first metal heat dissipation layer; and

[0022] The first device substrate and the heat sink are bonded through the second bonding layer and the first bonding layer, wherein the second metal bonding pad is bonded to the first metal bonding pad.

[0023] Optionally, each of the second metal bonding pads is bonded to one or more of the first metal bonding pads.

[0024] Optionally, the heat sink further includes a TSV thermally conductive hole, one end of which is connected to the first metal heat dissipation layer, and the other end passes through the first dielectric layer and a portion of the substrate; after bonding the first device substrate and the heat sink, the fabrication method further includes:

[0025] The substrate is thinned from one side of the second surface to expose the other end of the TSV thermal via; and

[0026] A second metal heat dissipation layer is formed on the second surface, and the second metal heat dissipation layer is connected to the other end of the TSV heat conduction hole.

[0027] Optionally, the manufacturing method further includes:

[0028] A TSV conduction structure is formed, which passes through the heat sink and the first bonding layer and is electrically connected to the top metal layer of the first device substrate. The TSV conduction structure is insulated from the first metal heat sink.

[0029] A second device substrate is bonded to the TSV conduction structure, thereby connecting the TSV conduction structure to the circuitry on the second device substrate.

[0030] The three-dimensional integrated structure provided by the present invention includes heat sinks stacked and adjacent to each other on a first device substrate along the thickness direction, which improves the heat dissipation capability of the three-dimensional integrated structure. The first metal heat dissipation layer in the heat sink can be made by film deposition process, which greatly reduces the manufacturing difficulty compared to making heat dissipation pipes, and helps to ensure the yield and reliability of the product. Furthermore, since the heat sink is stacked with the first device substrate, it does not affect the lateral area of ​​the three-dimensional integrated structure, and the cost is low.

[0031] The method for fabricating the three-dimensional integrated structure provided by this invention belongs to the same overall concept as the above-mentioned three-dimensional integrated structure and has the same or similar advantages. Attached Figure Description

[0032] Figure 1 This is a cross-sectional schematic diagram of the first device substrate and heat sink in a three-dimensional integrated structure according to an embodiment of the present invention.

[0033] Figure 2 This is a planar schematic diagram of the heat dissipation structure and the second metal bonding pad in one embodiment of the present invention.

[0034] Figure 3 This is a cross-sectional schematic diagram of the first device substrate and heat sink in a three-dimensional integrated structure according to another embodiment of the present invention.

[0035] Figure 4 This is a flowchart illustrating a method for fabricating a three-dimensional integrated structure according to an embodiment of the present invention.

[0036] Figures 5A to 5E This is a schematic diagram of the cross-sectional structure obtained at different steps in the fabrication method of a three-dimensional integrated structure according to an embodiment of the present invention.

[0037] Explanation of reference numerals in the attached figures:

[0038] 100 - First device substrate; 110 - Top metal layer; 111 - Hot spot; 112 - Circuit connection point; 120 - First bonding layer; 121 - First metal bonding pad; 200 - Heat sink; 210 - Substrate; 210a - First surface; 210b - Second surface; 220 - First dielectric layer; 230 - First metal heat dissipation layer; 240 - Second bonding layer; 241 - Second metal bonding pad; 250 - Second dielectric layer; 260 - Second metal heat dissipation layer; 201 - TSV thermal via; 270 - Third dielectric layer; 271 - TSV via; 280 - Fourth dielectric layer; 281 - Metal interconnect layer; 290 - Third bonding layer; 291 - Third metal bonding pad; 300 - Second device substrate; 310 - Fourth bonding layer; 311 - Fourth metal bonding pad; 320 - Bonding pad. Detailed Implementation

[0039] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, further illustrates the three-dimensional integrated structure and its fabrication method of the present invention. The advantages and features of the present invention will become clearer from the following description. It should be understood that the accompanying drawings are in a very simplified form and use non-precise proportions, intended only to facilitate and clarify the illustration of the embodiments of the present invention.

[0040] This invention relates to a three-dimensional integrated structure. The three-dimensional integrated structure may include at least two device substrates (e.g., a first device substrate 100 and a second device substrate 300 hereinafter referred to as such) that are three-dimensionally stacked and interconnected. Each device substrate may include electronic components formed on a semiconductor substrate using semiconductor processes. These electronic components may include at least one of MOS devices, sensor devices, memory devices, and passive devices. The sensor device may be a photosensitive device or a MEMS sensor, etc. The memory device may include non-volatile memory or random access memory, etc. The non-volatile memory may include NOR flash memory, NAND flash memory, ferroelectric memory, or phase-change memory, etc. The passive devices may include resistors or capacitors, etc. The electronic components may be planar devices or three-dimensional devices, such as Fin-FETs (Fin Field-Effect Transistors) or three-dimensional memory. The electronic components can be covered by a dielectric material, which can be a single layer or a stack of layers. The dielectric material can include one or a combination of dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, and nitrogen-doped silicon carbide, and can also include borosilicate glass (BPSG), undoped silicate glass (USG), spin-coated glass (SOG), tetraethyl orthosilicate (TEOS), or high-density plasma CVD (HDP-CVD) oxide, etc. Each device substrate can also have an interconnect structure formed in a vertical space. The interconnect structure can include at least one layer of metal interconnects and contact plugs for interconnecting different layers of metal interconnects. The device substrate can have a wafer-level or chip-level size. The device substrate can be a wafer structure or a chip, such as a photoelectric chip, a biochip, a memory chip, a logic chip, a computing chip, etc. For example, in one embodiment, the three-dimensional integrated structure includes three-dimensionally stacked logic chips and memory chips to facilitate high-speed computation using the logic chips and high-speed storage using the memory chips.

[0041] To improve the heat dissipation capability of the three-dimensional integrated structure while avoiding a significant increase in manufacturing difficulty and cost, the three-dimensional integrated structure of this invention includes at least one heat sink stacked along the thickness direction of the device substrate. The heat sink can be disposed at the bottom, top, or between the device substrates of the three-dimensional integrated structure. Specific details are as follows.

[0042] Reference Figure 1 The three-dimensional integrated structure of this invention includes a first device substrate 100 and a heat sink 200 stacked adjacent to each other along the thickness direction. The heat sink 200 is bonded to the first device substrate 100, for example, using hybrid bonding or other suitable bonding methods. (See also...) Figure 1As an example, in one embodiment, the heat sink 200 is disposed at the bottom or top of the three-dimensional integrated structure, and other device substrates are stacked on the side of the first device substrate 100 away from the heat sink 200.

[0043] The first device substrate 100 includes a top metal layer 110 and a first bonding layer 120, the first bonding layer 120 being bonded to a heat sink 200, i.e., the top metal layer 110 and the heat sink 200 are located on opposite sides of the first bonding layer 120. The first bonding layer 120 may include a dielectric material and first metal bonding pads 121 embedded in the dielectric material. The top metal layer 110 is the top metal of the first device substrate 100 near the heat sink 200, and the top metal layer 110 may include metal interconnects. The top metal layer 110 may include one or more hot spots 111, the hot spots being, for example, locations in the top metal layer 110 where heat easily accumulates or where heat dissipation components are easily connected. In one embodiment, the hot spots 111 are obtained by performing thermal simulation on the first device substrate 100. The first bonding layer 120 is provided with a first metal bonding pad 121 connected to the hot spot 111. After the heat sink 200 is bonded, the heat of the hot spot 111 can be dispersed to the heat sink 200 through the first metal bonding pad 121.

[0044] The heat sink 200 includes a substrate 210, which may include silicon, germanium, silicon-germanium, silicon carbide, gallium oxide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide, or may include other materials (e.g., GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP), or combinations of the above materials. Electronic components may or may not be formed on the substrate 210. In this embodiment of the invention, the substrate 210 is, for example, a silicon substrate, which utilizes the good thermal conductivity of silicon to achieve better heat dissipation.

[0045] The substrate 210 includes a first surface 210a and a second surface 210b opposite to each other. For example, the first surface 210a is the front side of the substrate 210, and the second surface 210b is the back side of the substrate 210. In other embodiments, the first surface 210a may also be the back side of the substrate 210, and correspondingly, the second surface 210b is the front side of the substrate 210.

[0046] The heat sink 200 further includes a first dielectric layer 220, a first metal heat dissipation layer 230, and a second bonding layer 240 sequentially formed on the first surface 210a of the substrate 210. The first dielectric layer 220 may include at least one dielectric material such as silicon oxide, silicon nitride, and silicon oxynitride. The second bonding layer 240 is provided with a second metal bonding pad 241 connected to the first metal heat dissipation layer 230. The second metal bonding pad 241 is bonded to the first metal bonding pad 121, that is, the hot spot 111 in the top metal layer 110 of the first bonding substrate 100 is connected to the first metal heat dissipation layer 230 in the heat sink 200 through the first metal bonding pad 121 and the second metal bonding pad 241.

[0047] The first metal heat dissipation layer 230 may include a heat-spreading structure extending along the surface of the first dielectric layer 220 and formed around the second metal bonding pad 241, so as to disperse and dissipate the heat of the conductive points 111 transferred by the second metal bonding pad 241 and the first metal bonding pad 121 along the heat conduction path in a two-dimensional plane on the first surface 210a of the substrate 210, and further dissipate heat through the substrate 210. The heat-spreading structure may be a solid metal layer (non-perforated) or a perforated metal layer. The first metal heat dissipation layer 230 may be formed of a metal material with good thermal conductivity, such as at least one of metals such as tungsten, aluminum, and copper. (Refer to...) Figure 2 In one embodiment, the heat dissipation structure includes multiple intersecting metal lines, which facilitate heat transfer and dissipation, thereby increasing the heat dissipation capacity of the heat sink 200. The heat dissipation structure is, for example, a mesh structure, wherein the cross-section of the perforated mesh can be triangular, square, circular, or other suitable shapes. It should be noted that... Figure 2 In the heat dissipation structure shown, each metal line has the same length and width and extends only in two mutually perpendicular directions. However, the present invention is not limited to this. The length and / or width of each metal line in the heat dissipation structure may also be different. Furthermore, the extension direction of each metal line may not be limited to two mutually perpendicular directions and can be set according to the overall structure of the three-dimensional integrated structure and the heat dissipation effect.

[0048] Figure 1 In the three-dimensional integrated structure shown in the embodiment, the heat dissipation components of the heat sink 200 mainly include a first metal bonding pad 121, a second metal bonding pad 241, a first metal heat dissipation layer 230, and a substrate 210. The first metal bonding pad 121, the second metal bonding pad 241, the first metal heat dissipation layer 230, the first dielectric layer 220, and the substrate 210 constitute the heat dissipation path of the hot spot 111.

[0049] Figure 3 This is a cross-sectional schematic diagram of the first device substrate and heat sink in a three-dimensional integrated structure according to another embodiment of the present invention. (Refer to...) Figure 3 To enhance heat dissipation, the heat dissipation assembly of the heat sink 200, in addition to the first metal bonding pad 121, the second metal bonding pad 241, the first metal heat dissipation layer 230, and the substrate 210, also includes a TSV thermal conductive hole 201 and a second metal heat dissipation layer 260. The first metal bonding pad 121, the second metal bonding pad 241, the first metal heat dissipation layer 230, the TSV thermal conductive hole 201, the substrate 210, and the second metal heat dissipation layer 260 constitute the heat dissipation path of the heat dissipation point 111. Figure 1 Compared to the three-dimensional integrated structure in the illustrated embodiment, Figure 3 In the embodiment shown, the number of heat dissipation components is increased, and all heat dissipation components on the heat dissipation path are connected by metal, resulting in higher heat dissipation efficiency.

[0050] Specifically, refer to Figure 3 In another embodiment, the heat sink 200 further includes a second dielectric layer 250 and a second metal heat dissipation layer 260 sequentially formed on the second surface 210b of the substrate 210. The second dielectric layer may include at least one dielectric material selected from silicon oxide, silicon nitride, and silicon oxynitride. The second metal heat dissipation layer 260 may include at least one metal selected from tungsten, aluminum, and copper. Furthermore, the heat sink 200 also includes at least one TSV heat conduction hole 201, which passes through the substrate 210 and the first dielectric layer 220, and its two ends are respectively connected to the first metal heat dissipation layer 230 and the second metal heat dissipation layer 260. The second metal heat dissipation layer 260 may include a heat homogenization structure extending along the surface of the second dielectric layer 250 and formed around the TSV heat conduction hole 201 to homogenize and dissipate heat along the heat conduction path in a two-dimensional plane on the second surface 210b of the substrate 210. The heat homogenization structure may be a solid metal layer or a perforated metal layer, for example, it may include multiple intersecting metal lines or other shaped mesh structures.

[0051] In the three-dimensional integrated structure of this invention, other device substrates or heat sinks may be stacked on the side of the first device substrate 100 away from the heat sink 200 and / or on the side of the heat sink 200 away from the first device substrate 100.

[0052] Reference Figure 5EIn one embodiment, in addition to the first device substrate 100 and the heat sink 200 described above, the three-dimensional integrated structure further includes a second device substrate 300, with the heat sink 200 sandwiched between the first device substrate 100 and the second device substrate 300. In this embodiment, the heat sink 200 is disposed between the device substrates of the three-dimensional integrated structure. The second device substrate 300 and the heat sink 200 are bonded together, for example, using hybrid bonding or other suitable bonding methods. Optionally, the top metal layer of the second device substrate 300 facing the heat sink 200 may also have hot spots (not shown). These hot spots can be connected to the second metal heat dissipation layer 260 via bonding pads respectively disposed on the second device substrate 300 and the heat sink 200, so that the heat generated by the second device substrate 300 can also be dissipated through the heat sink 200. For example, the first device substrate 100 includes a logic chip, the second device substrate 300 includes a memory chip, and a heat sink 200 is disposed between the logic chip and the memory chip. The heat sink 200 serves as a buffer layer to evenly release the heat generated by the logic chip during high-speed operation, while reducing the impact on the memory chip.

[0053] To enable electrical interconnection between electronic components on the second device substrate 300 and electronic components on the first device substrate 100, the three-dimensional integrated structure may further include a TSV conduction structure (see reference). Figure 5E The TSV via 271 and metal interconnect layer 281 are configured in the heat sink 200 to electrically connect to the second device substrate 300 and the first device substrate 100, respectively. To avoid the influence of the heat sink on the circuit, the TSV via is insulated from the first metal heat sink layer 230 and the second metal heat sink layer 260. For example, when passing through the heat sink 200, the TSV via avoids the first metal heat sink layer 230 and the second metal heat sink layer 260. The first metal heat sink layer 230 and the second metal heat sink layer 260 can dissipate heat and distribute heat evenly, but are not used to transmit electrical signals.

[0054] Optional, Figure 1 , Figure 3 as well as Figure 5E The illustrated three-dimensional integrated structure may further include a third device substrate (not shown), which is stacked on the side of the first device substrate 100 away from the heat sink 200. The third device substrate is, for example, bonded to the surface of the first device substrate 100 away from the heat sink 200. Electronic components on the third device substrate can communicate with electronic components on the first device substrate 100, i.e., the third device substrate and the first device substrate 100 are electrically interconnected.

[0055] The three-dimensional integrated structure of this invention includes heat sinks 200 stacked and adjacent to each other on a first device substrate 100 along the thickness direction, which improves the heat dissipation capability of the three-dimensional integrated structure. The first metal heat dissipation layer 230 in the heat sink 200 can be fabricated by a film forming process, which greatly reduces the manufacturing difficulty compared to fabricating heat dissipation pipes, and helps to ensure the yield and reliability of the product. Furthermore, since the heat sink 200 is stacked with the first device substrate 100, it does not affect the lateral area of ​​the three-dimensional integrated structure, resulting in lower cost.

[0056] This invention also relates to a method for fabricating a three-dimensional integrated structure, which can be used to fabricate the three-dimensional integrated structure described in the above embodiments. (Refer to...) Figure 4 The manufacturing method includes the following steps:

[0057] S1: Form a first device substrate, the first device substrate including a top metal layer and a first bonding layer located on the top metal layer, the top metal layer including a hot spot, and a first metal bonding pad connected to the hot spot is formed in the first bonding layer;

[0058] S2: Form a heat sink, the heat sink including a substrate, the substrate having a first surface and a second surface opposite to each other, the heat sink further including a first dielectric layer, a first metal heat dissipation layer and a second bonding layer sequentially formed on the first surface, and a second metal bonding pad connected to the first metal heat dissipation layer is formed in the second bonding layer.

[0059] S3: The first device substrate and the heat sink are bonded together through the second bonding layer and the first bonding layer, wherein the second metal bonding pad is bonded to the first metal bonding pad.

[0060] The following combination Figure 4 and Figures 5A-5E The manufacturing method is described in detail below.

[0061] Reference Figure 4 and Figure 5A The fabrication method includes step S1: forming a first device substrate 100, the first device substrate 100 including a top metal layer 110 and a first bonding layer 120 located on the top metal layer 110, the top metal layer 110 including a hot spot 111, and the first bonding layer 120 having a first metal bonding pad 121 connected to the hot spot 111.

[0062] Specifically, the top metal layer 110 is a metal layer in the first device substrate 100 adjacent to the first bonding layer 120, and the top metal layer 110 can be electrically connected to electronic components in the first device substrate 100. The top metal layer 110 may include metal interconnects. The top metal layer 110 includes one or more hot spots 111, which are, for example, locations in the top metal layer that are prone to heat accumulation or locations that facilitate the setting of heat dissipation structures. In one embodiment, hot spots distributed in the top metal layer 110 are determined by performing thermal simulation on the first device substrate 100, and are designated as hot spots 111. In addition, in order to interconnect with adjacent device substrates in the three-dimensional integrated structure, the top metal layer 110 may also include one or more circuit connection points 112.

[0063] The first bonding layer 120 is used to bond a heat sink 200 onto the first device substrate 100. The first bonding layer 120 may include a dielectric material and a first metal bonding pad 121 formed in the dielectric material. The dielectric material may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and may be formed as a single layer or multiple layers. The first metal bonding pad 121 is used for thermal conductivity and is connected to a hot spot 110, for example, by making the first metal bonding pad 121 directly contact the top metal layer 110 at the corresponding hot spot 111. Figure 5A As shown, optionally, each hot spot 111 can be connected to one or more first metal bonding pads 121. The top metal layer 110 and the first metal bonding pads 121 can be made of metal materials with good thermal conductivity, such as copper or aluminum.

[0064] Reference Figure 4 and Figure 5B The fabrication method includes step S2: forming a heat sink 200, which is used to stack on the first bonding substrate 100 and to dissipate the heat generated by the first bonding substrate 100 as quickly as possible during the operation of the first bonding substrate 100. It can be understood that the heat sink 200 and the first device substrate 100 can be formed simultaneously or asynchronously, that is, steps S2 and S1 can be performed sequentially or simultaneously.

[0065] Reference Figure 5B The heat sink 200 includes a substrate 210, which has a first surface 210a and a second surface 210b. The heat sink 200 further includes a first dielectric layer 220, a first metal heat dissipation layer 230, and a second bonding layer 240 sequentially formed on the first surface 210a. The second bonding layer 240 has a second metal bonding pad 241 connected to the first metal heat dissipation layer 230. The substrate 210 is, for example, a silicon substrate or other substrates with good thermal conductivity to improve the heat dissipation capacity of the heat sink 200. The first surface 210a is, for example, the front side of the substrate 210.

[0066] The second bonding layer 240 may include a dielectric material and a second metal bonding pad 241 formed in the dielectric material. The dielectric material may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and may be formed as a single layer or multiple layers. The second metal bonding pad 241 may correspond one-to-one with the first metal bonding pad 121 in the first bonding layer 120, so that each pair of corresponding first metal bonding pads 121 and second metal bonding pads 241 can be bonded. However, this is not a limitation. In this embodiment of the invention, the second metal bonding pad 241 and the first metal bonding pad 121 are used for heat dissipation and not as electrical components. Therefore, the number of first metal bonding pads 121 and second metal bonding pads 241 may not correspond (for example, one second metal bonding pad 241 may be bonded to two or more first metal bonding pads 121, or one first metal bonding pad 121 may be bonded to two or more second metal bonding pads 241), as long as they can be connected by bonding to form a metal heat conduction path.

[0067] The first metal heat dissipation layer 230 may include a heat-spreading structure extending along the surface of the first dielectric layer 220 and surrounding the second metal bonding pad 241. This heat-spreading structure facilitates the dispersion and dissipation of heat transferred from the second metal bonding pad 241 along a two-dimensional heat conduction path on the first surface 210a of the substrate 210 after bonding to the first bonding substrate 100, and further dissipates heat through the substrate 210. Optionally, the heat sink 200 further includes at least one TSV thermally conductive hole 201, one end of which is connected to the first metal heat dissipation layer 230, and the other end passing through the first dielectric layer 220 and at least a portion of the thickness of the substrate 210. The TSV thermally conductive hole 201 is used to connect the second metal heat dissipation layer to the first metal heat dissipation layer 230 when the second metal heat dissipation layer is subsequently formed on the second surface 210b of the substrate 210, forming a metal heat conduction path between the second metal bonding pad 241 and the second metal heat dissipation layer. Optionally, the lateral distance between the TSV thermal hole 201 and the second metal bonding pad 241 is less than a set value, so as to shorten the length of the heat conduction path when the second metal bonding pad 241 conducts heat through the TSV thermal hole 201 and the second metal heat dissipation layer.

[0068] Reference Figure 4 and Figure 5CThe fabrication method includes step S3: bonding the first device substrate 100 and the heat sink 200 through the first bonding layer 120 and the second bonding layer 240, wherein the second metal bonding pad 241 is bonded to the first metal bonding pad 121, for example, by using a hybrid bonding process. When bonding the first device substrate 100 and the heat sink 200, each first metal bonding pad 121 and a second metal bonding pad 241 can be bonded together, wherein the first metal bonding pad 121 and the second metal bonding pad 241 can be aligned or misaligned and bonded together. Furthermore, the dielectric material in the first bonding layer 120 and the dielectric material in the second bonding layer 240 can also be bonded together. When a heterogeneous interface between the dielectric material and the metal is formed, the materials on both sides of the heterogeneous interface can also be bonded together.

[0069] Reference Figure 5C Optionally, after bonding the first device substrate 100 and the heat sink 200, the fabrication method may further include the following steps: thinning the substrate 210 from one side of the second surface 210b (e.g., thinning by 1 μm to 50 μm) to expose the end of the TSV heat-conducting hole 201 away from the first metal heat dissipation layer 230. Thinning the substrate 210 reduces thermal resistance and facilitates heat dissipation. Then, a second dielectric layer 250 and a second metal heat dissipation layer 260 are sequentially formed on the second surface 210b. The second metal heat dissipation layer 260 is connected to the end of the TSV heat-conducting hole 201 away from the first metal heat dissipation layer 230. The second metal heat dissipation layer 260 may include a heat-spreading structure extending along the surface of the second dielectric layer 250 and formed around the TSV heat-conducting hole 201. The heat-spreading structure may be a solid metal layer or a perforated metal layer, for example, it may include multiple intersecting metal lines or other types of mesh structures. The second metal heat dissipation layer 260 may be made of a material with good thermal conductivity, such as copper or aluminum. The heat from the hot spots 111 in the first device substrate 100 can be dissipated through the first metal bonding pad 121, the second metal bonding pad 241, the first metal heat dissipation layer 230, the substrate 210, the TSV thermal via 201, and the second metal heat dissipation layer 260, resulting in high heat dissipation efficiency and excellent heat dissipation effect. The second metal heat dissipation layer 260 can also be used to connect the device wafers subsequently stacked on one side of the second surface 210b of the substrate 210 and to disperse and dissipate the heat generated on one side of the second surface 210b of the substrate 210.

[0070] Reference Figure 5D and Figure 5EIn order to stack other device substrates on the side of the heat sink 200 opposite to the first bonding substrate 100 and interconnect them with the first device substrate 100, the fabrication method may further include the following process: forming a TSV conductive structure, such that the TSV conductive structure passes through the heat sink 200 and the first bonding layer 120 and is electrically connected to the top metal layer 110 of the first device substrate 100 (specifically, it can be connected to the circuit connection point 112 in the top metal layer 110), the TSV conductive structure is insulated from the first metal heat dissipation layer 230 and the second metal heat dissipation layer 260 (if a second metal heat dissipation layer 260 is formed) to avoid the influence of the first metal heat dissipation layer 230 and the second metal heat dissipation layer 260 on the circuit in the three-dimensional integrated structure; then, bonding the second device substrate 300 to the TSV conductive structure, so that the TSV conductive structure is also connected to the circuit on the second device substrate 300.

[0071] Specifically, refer to Figure 5D For example, the process of forming the TSV conductive structure is as follows: First, a third dielectric layer 270 is deposited on the second dielectric layer 250 and the second metal heat dissipation layer 260; then, avoiding the second metal heat dissipation layer 260 and the first metal heat dissipation layer 230, a TSV via 271 is formed using a TSV process. The TSV via 271 passes through the third dielectric layer 270, the second dielectric layer 250, the substrate 210, the first dielectric layer 220, the second bonding layer 240, and the first bonding layer 120 and is connected to the circuit connection point 112 in the top metal layer 110; then, a fourth dielectric layer 280 and a metal interconnect layer 281 are sequentially formed on the third dielectric layer 270, so that the metal interconnect layer 281 passes through the fourth dielectric layer 280 and is electrically connected to the TSV via 271. The metal interconnect layer 281 and the TSV via 271 constitute the TSV conductive structure.

[0072] Reference Figure 5E For example, the process of bonding the second device substrate 300 on the TSV conduction structure is as follows: a third bonding layer 290 is formed on the TSV conduction structure and the fourth dielectric layer 280, and a third metal bonding pad 291 is formed in the third bonding layer 290 to be connected to the TSV conduction structure (more specifically, to the metal interconnect layer 281); a second device substrate 300 is provided, the second device substrate 300 including a fourth bonding layer 310, and a fourth metal bonding pad 311 is formed in the fourth bonding layer 310; the second device substrate 300 is bonded on the heat sink 200 through the third bonding layer 290 and the fourth bonding layer 310.

[0073] Optionally, the second device substrate 300 may have hot spots, and the fourth bonding layer 310 may have metal bonding pads (not shown) connecting the hot spots, and the third bonding layer 290 may have metal bonding pads connected to the second metal heat dissipation layer 260. When bonding the second device substrate 300, the metal bonding pads in the fourth bonding layer 310 connecting the hot spots can be bonded to the corresponding metal bonding pads in the third bonding layer 290 connected to the second metal heat dissipation layer 260, so that the hot spots in the second device substrate 300 can dissipate heat through the second metal heat dissipation layer 260 and other heat dissipation components in the heat sink 200, thereby improving the heat dissipation effect of the three-dimensional integrated structure. Figure 5E As shown, in one embodiment, in addition to the substrate 210 and the first dielectric layer 220, the first metal heat dissipation layer 230 and the second bonding layer 240 formed on the first surface 210a side of the substrate 210, the second dielectric layer 250, the second metal heat dissipation layer 260, the third dielectric layer 270, the fourth dielectric layer 280 and the third bonding layer 290 formed on the second surface 210b side of the substrate 210 can all be used as part of the heat sink 200, which is sandwiched between the first device substrate 100 and the second device substrate 300.

[0074] Based on the integration and heat dissipation requirements of the three-dimensional integrated structure, other device substrates or heat sinks can be stacked on the side of the second device substrate 300 away from the heat sink 200. Furthermore, TSV conduction structures can be formed in the second device substrate 300 and the device substrates or heat sinks stacked on its side away from the heat sink 200 to electrically connect the various device substrates, and a pad can be formed on the topmost device substrate. In one embodiment, a pad 320 is formed on the side of the second device substrate 300 away from the heat sink 200.

[0075] In addition, the fabrication method may further include: stacking a third device substrate (not shown) on the side of the first device substrate 100 away from the heat sink 200 before or after bonding with the heat sink 200, and electrically interconnecting the third device substrate with the first device substrate 100.

[0076] Using the fabrication method of the three-dimensional integrated structure in this embodiment of the invention, the first device substrate 100 and the heat sink 200 are bonded together. The heat conducted by the hot spots 111 in the first device substrate 100 can be quickly and effectively dissipated through the heat sink 200, thereby improving the heat dissipation capacity of the three-dimensional integrated structure. The first metal heat dissipation layer 230 can be fabricated by a film deposition process, which can reduce the process difficulty compared to fabricating heat dissipation pipes, ensuring product yield and reliability. Furthermore, since the heat sink 200 is stacked with the device substrate in the three-dimensional integrated structure, it does not affect the lateral area of ​​the three-dimensional integrated structure, resulting in lower cost.

[0077] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A three-dimensional integrated structure, characterized in that, The device comprises a first device substrate, a heat sink, and a second device substrate stacked adjacent to each other along the thickness direction, and a TSV via; wherein the first device substrate includes a top metal layer and a first bonding layer, the top metal layer and the heat sink being located on opposite sides of the first bonding layer, the top metal layer including a hot spot, and the first bonding layer having a first metal bonding pad connected to the hot spot; the heat sink includes: The substrate includes opposing first and second surfaces; A first dielectric layer, a first metal heat dissipation layer, and a second bonding layer are sequentially formed on the first surface. The second bonding layer is provided with a second metal bonding pad that is connected to the first metal heat dissipation layer. The second metal bonding pad is bonded to the first metal bonding pad. The first metal heat dissipation layer extends along the surface of the first dielectric layer. A second dielectric layer, a second metal heat dissipation layer, and a third bonding layer are formed on one side of the second surface. The second device substrate is bonded to the third bonding layer. The second metal heat dissipation layer extends along the surface of the second dielectric layer. The TSV via penetrates the substrate and extends beyond the first and second metal heat dissipation layers at both ends, respectively, and is electrically connected to the first and second device substrates, respectively. TSV thermal vias pass through the substrate and the first dielectric layer, and are connected at both ends to the first metal heat dissipation layer and the second metal heat dissipation layer, respectively.

2. The three-dimensional integrated structure as described in claim 1, characterized in that, The first metal heat dissipation layer includes a heat-spreading structure extending along the surface of the first dielectric layer and formed around the second metal bonding pad, wherein the heat-spreading structure is a solid metal layer or a perforated metal layer.

3. The three-dimensional integrated structure as described in claim 2, characterized in that, The heat dissipation structure includes multiple intersecting metal wires.

4. The three-dimensional integrated structure as described in claim 1, characterized in that, The three-dimensional integrated structure also includes: The TSV conduction structure passes through the heat sink and is electrically connected to the second device substrate and the first device substrate respectively. The TSV conduction structure is insulated from the first metal heat sink and the second metal heat sink.

5. The three-dimensional integrated structure as described in any one of claims 1 to 4, characterized in that, The three-dimensional integrated structure also includes: A third device substrate is stacked on the side of the first device substrate away from the heat sink, and the third device substrate is electrically interconnected with the first device substrate.

6. A method for fabricating a three-dimensional integrated structure, characterized in that, include: A first device substrate is formed, the first device substrate includes a top metal layer and a first bonding layer located on the top metal layer, the top metal layer includes a hot spot, and a first metal bonding pad connected to the hot spot is formed in the first bonding layer; A heat sink is formed, the heat sink including a substrate having opposing first and second surfaces, the heat sink further including a first dielectric layer, a first metal heat dissipation layer and a second bonding layer sequentially formed on the first surface, the second bonding layer having a second metal bonding pad connected to the first metal heat dissipation layer, the first metal heat dissipation layer extending along the surface of the first dielectric layer, the heat sink further including a TSV thermally conductive hole, one end of the TSV thermally conductive hole being connected to the first metal heat dissipation layer, and the other end passing through the first dielectric layer and a portion of the substrate; The first device substrate and the heat sink are bonded together by the second bonding layer and the first bonding layer, wherein the second metal bonding pad is bonded to the first metal bonding pad; The substrate is thinned from one side of the second surface to expose the other end of the TSV thermal via; A second metal heat dissipation layer, a TSV via, and a third bonding layer are formed on one side of the second surface, and the second metal heat dissipation layer is connected to the other end of the TSV via. as well as On one side of the second surface, the second device substrate is bonded to the third bonding layer, wherein the TSV via penetrates the substrate and extends beyond the first metal heat dissipation layer and the second metal heat dissipation layer at both ends and is electrically connected to the first device substrate and the second device substrate, respectively.

7. The manufacturing method as described in claim 6, characterized in that, Each of the second metal bonding pads is bonded to one or more of the first metal bonding pads.

8. The manufacturing method as described in claim 6, characterized in that, After bonding the first device substrate and the heat sink, the fabrication method further includes: A TSV conduction structure is formed, which passes through the heat sink and the first bonding layer and is electrically connected to the top metal layer of the first device substrate. The TSV conduction structure is insulated from the first metal heat sink layer. A second device substrate is bonded to the TSV conduction structure, thereby connecting the TSV conduction structure to the circuitry on the second device substrate.

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