Waveguide integrated graphene photomixer chip and method of manufacture

Abstract

The application discloses a waveguide integrated graphene photoelectric mixer chip and a preparation method thereof. The substrate of the waveguide integrated graphene photoelectric mixer chip is standard SOI material, and the structure comprises a vertical coupling grating, an optical waveguide and a graphene device group. The gate electrode of the graphene device group is a double-gate structure, and plasma enhancement is realized. An optical carrier radio frequency signal is input into the optical waveguide through the vertical coupling grating, and an intrinsic signal is input into the graphene device group through the gate electrode. After photoelectric conversion and mixing of the graphene device group, an intermediate frequency signal is obtained, and the intermediate frequency signal is output from a drain electrode. The design of the silicon ridge waveguide increases the space of the active region of the device, and facilitates the alignment lithography of the double-gate electrode and the silicon ridge waveguide. In addition, the double-gate electrode and the silicon ridge waveguide are designed and prepared, plasma enhancement mode is realized, the interaction between the graphene and the light wave is improved, higher light detection and action efficiency are realized, and the performance of the graphene photoelectric mixer is improved.

Description

Technical Field

[0001] This invention relates to the field of integrated microwave photonic signal processing technology, and in particular to a waveguide integrated graphene optoelectronic mixer chip and its fabrication method. Background Technology

[0002] Microwave photonics technology boasts significant advantages such as large bandwidth, low transmission loss, resistance to electromagnetic interference, and tunability. By modulating radio frequency microwave signals onto a continuous optical wave, it enables signal generation, modulation, processing, and long-distance, low-loss transmission at optical frequencies. This makes it a key technology leading the future communications industry and applications in new radar systems, electronic warfare, and other fields. Microwave photonic signal processing, a research hotspot, has already implemented numerous photonic signal processing functions, including optical mixing, optical filtering, optical switching, optical delay, differentiation, integration, and Hilbert transform. Furthermore, the receiver end of a microwave photonic communication link typically needs to implement microwave mixing, filtering, and photoelectric conversion functions. Photoelectric mixing technology is an indispensable part of microwave photonic systems and is a functional unit in applications such as satellite antenna fiber optic remote systems, optical wireless systems, and microwave photonic radar. Generally, the frequency of the radio frequency signal received by the receiver is not fixed, requiring high-frequency signal conversion to low-frequency or baseband for processing.

[0003] Graphene, as a two-dimensional material, possesses excellent photoresponse characteristics. Graphene has a very broad absorption spectrum, covering visible and near-infrared light, and the electrical bandwidth of devices is limited only by the RC constant, with a theoretical bandwidth reaching up to 500 GHz. Utilizing the radio frequency optoelectronic properties and nonlinearity of graphene transistors, graphene opto-mixers can be fabricated. However, current opto-mixers based on the intrinsic absorption effect of graphene on light suffer from low photodetection efficiency, resulting in low intermediate frequency signal power after mixing. Summary of the Invention

[0004] To address the above problems, this invention proposes a waveguide-integrated graphene optoelectronic mixer chip and its fabrication method.

[0005] To achieve the purpose of this invention, a waveguide-integrated graphene optoelectronic mixer chip is provided, comprising: a silicon substrate, a buried oxide layer, an optical waveguide, a vertically coupled grating, a silicon oxide cladding dielectric layer, a graphene device group, and a BCB thin film layer.

[0006] The optical waveguide includes: a plurality of silicon strip waveguides and silicon ridge waveguides;

[0007] The graphene device assembly includes: a graphene thin film layer, a first gate dielectric layer, a second gate dielectric layer, a source electrode, a drain electrode, a first gate electrode, a second gate electrode, and a passivation dielectric layer;

[0008] The silicon substrate, buried oxide layer, and silicon device layer are stacked sequentially, forming a standard SOI substrate. The vertically coupled grating, silicon strip waveguide, and silicon ridge waveguide are disposed within the silicon device layer. The silicon strip waveguides are connected to both ends of the ridge of the silicon ridge waveguide. A silicon oxide cladding dielectric layer covers the silicon device layer. A BCB thin film layer covers the silicon oxide cladding dielectric layer. A graphene thin film layer is attached to the surface of the BCB thin film layer, located directly above and completely covering the silicon ridge waveguide. The first gate dielectric layer and the second gate dielectric layer are respectively attached to the surface of the graphene thin film layer, with a predetermined distance between them. The first gate electrode and the second gate electrode... Electrodes are respectively disposed on the surfaces of the first gate dielectric layer and the second gate dielectric layer; the passivation dielectric layer is attached to the upper surfaces of the first gate electrode and the second gate electrode, and completely covers the first gate dielectric layer, the second gate dielectric layer, the first gate electrode, and the second gate electrode; the source electrode is located on the side of the first gate electrode away from the second gate electrode, and the drain electrode is located on the side of the second gate electrode away from the first gate electrode, and the source electrode is partially attached to the surface of the graphene film layer and the other part is attached to the surface of the BCB film layer; the drain electrode is partially attached to the surface of the graphene film layer and the other part is attached to the surface of the BCB film layer.

[0009] The optical radio frequency signal is input into the silicon strip waveguide through the vertically coupled grating, then through the silicon ridge waveguide, and finally reaches the graphene device group; the intrinsic signal is input into the graphene device group through the first gate electrode and the second gate electrode; the optical radio frequency signal and the intrinsic signal are converted and mixed by the graphene device group to obtain an intermediate frequency signal, and the intermediate frequency signal is output through the drain electrode.

[0010] Furthermore, the spacing between the first gate electrode and the second gate electrode is 20-100 nm.

[0011] This invention also provides a method for fabricating a waveguide-integrated graphene optoelectronic mixer chip, comprising the following steps:

[0012] S1: First, electron beam resist mask patterns of vertically coupled gratings and silicon ridge waveguides are prepared on a pre-prepared standard SOI substrate wafer using electron beam direct writing exposure and development technology. Then, using electron beam resist as a mask, vertically coupled gratings and silicon ridge waveguides are etched using inductively coupled plasma technology. Finally, resist is removed and cleaned.

[0013] S2: The electron beam resist mask pattern of the silicon strip waveguide is prepared by electron beam direct writing exposure and development technology. Then, the silicon strip waveguide is etched by inductively coupled plasma process using electron beam resist as a mask. Finally, the resist is removed and cleaned.

[0014] S3: Grow a dielectric layer on top of silicon oxide and polish the wafer surface using a chemical mechanical polishing process;

[0015] S4: A BCB thin film layer is coated on the surface of the dielectric layer on silicon oxide using a spin coating process and then cured.

[0016] S5: The pre-fabricated graphene film is transferred to the wafer surface using a wet gold transfer process, then dried, followed by immersion and cleaning with acetone and ethanol in sequence, and finally baked in an oven for a preset duration.

[0017] S6: A graphene photoresist mask for the graphene device region is prepared using a photolithography and development process, and then the graphene thin film layer is patterned using a gold etching process and an oxygen plasma etching process.

[0018] S7: The source electrode and drain electrode patterns are prepared by photolithography and development process, and then the source electrode and drain electrode are prepared by electron beam evaporation and stripping process;

[0019] S8: The channel region pattern is prepared by photolithography and development technology, and then the gold in the channel region is removed by gold etching process. Then an insulating material is grown as the gate dielectric layer.

[0020] S9: Electron beam photomask patterns of the first gate electrode and the second gate electrode are prepared by electron beam direct writing exposure and development process, respectively. Then, the first gate electrode and the second gate electrode are prepared by electron beam evaporation and stripping process, respectively.

[0021] S10: HSQ electron beam negative adhesive is applied using a spin coating method, followed by electron beam direct writing exposure and development process to prepare a passivation dielectric layer.

[0022] Furthermore, in step S1, the etching gas used is sulfur hexafluoride gas, and the etching depth is 80 nanometers.

[0023] Furthermore, in step S2, the etching gas used is sulfur hexafluoride gas, and the etching depth is 220 nanometers.

[0024] Furthermore, in step S3, a silicon oxide overlay dielectric layer is deposited using plasma-enhanced chemical vapor deposition, and the thickness of the silicon oxide overlay dielectric layer is 2-3 micrometers.

[0025] Furthermore, in step S4, the thickness of the BCB film layer is 5-15 nanometers, the curing temperature is 180-200 degrees Celsius, and the curing time is 5-15 minutes.

[0026] Furthermore, in step S7, the metals required to prepare the source electrode and the drain electrode include: 20 nm titanium, 180 nm gold, and 10 nm titanium.

[0027] Furthermore, in step S9, the metals required to prepare the first gate electrode and the second gate electrode include: 10 nanometer titanium and 50-100 nanometer gold.

[0028] Furthermore, in step S10, the thickness of the passivation dielectric layer is 400-700 nanometers.

[0029] Compared with the prior art, the present invention has the following beneficial technical effects:

[0030] (1) The space of the active region of the device is increased by the silicon ridge waveguide design, which facilitates the alignment of the dual gate electrode and the silicon ridge waveguide in photolithography.

[0031] (2) By designing and fabricating dual-gate electrodes and silicon ridge waveguides to realize plasma enhancement mode, the interaction between graphene and light waves is improved, higher light detection and interaction efficiency is achieved, and the performance of graphene optoelectronic mixer is enhanced. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the cross-sectional structure of a waveguide-integrated graphene optoelectronic mixer integrated chip according to one embodiment.

[0033] Figure 2 This is a schematic diagram of the core components of a waveguide-integrated graphene optoelectronic mixer chip according to one embodiment;

[0034] Figure 3 This is a schematic diagram of a standard SOI substrate material in one embodiment;

[0035] Figure 4 This is a schematic diagram of the fabrication of a ridge waveguide in one embodiment;

[0036] Figure 5 This is a schematic diagram of the fabrication of a strip waveguide according to one embodiment;

[0037] Figure 6 This is a schematic diagram illustrating the fabrication of the upper coating dielectric layer in one embodiment;

[0038] Figure 7 This is a schematic diagram of graphene transfer in one embodiment;

[0039] Figure 8 This is a schematic diagram illustrating the fabrication of the source and drain electrodes in one embodiment;

[0040] Figure 9 This is a schematic diagram of gate dielectric growth in one embodiment;

[0041] Figure 10This is a schematic diagram of the fabrication of a dual-gate electrode according to one embodiment;

[0042] Figure 11 This is a schematic diagram of channel passivation in one embodiment.

[0043] Figure reference numerals: 1-Silicon substrate, 2-Buried oxide layer, 3-Optical waveguide, 31-Silicon strip waveguide, 32-Silicon ridge waveguide, 4-Coupled grating, 5-Silicon oxide cladding dielectric layer, 6-Graphene device group, 61-Graphene thin film layer, 62-First gate dielectric layer, 63-Second gate dielectric layer, 64-Source electrode, 65-Drain electrode, 66-First gate electrode, 67-Second gate electrode, 68-Passivation dielectric layer, 7-BCB thin film layer, 8-Silicon device layer, A-Optical radio frequency signal, B-Intrinsic signal, C-Intermediate frequency signal. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0045] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0046] refer to Figure 1 , Figure 2 As shown, a waveguide integrated graphene optoelectronic mixer chip includes: a silicon substrate 1, a buried oxide layer 2, an optical waveguide 3, a vertically coupled grating 4, a silicon oxide cladding dielectric layer 5, a graphene device group 6, and a BCB thin film layer 7.

[0047] The optical waveguide 3 includes: a plurality of silicon strip waveguides 31 and silicon ridge waveguides 32;

[0048] The graphene device group 6 includes: a graphene thin film layer 61, a first gate dielectric layer 62, a second gate dielectric layer 63, a source electrode 64, a drain electrode 65, a first gate electrode 66, a second gate electrode 67, and a passivation dielectric layer 68.

[0049] The silicon substrate 1, buried oxide layer 2, and silicon device layer 8 are stacked sequentially to form a standard SOI substrate. The vertically coupled grating 4, silicon strip waveguide 31, and silicon ridge waveguide 32 are disposed within the silicon device layer 8. The silicon strip waveguide 31 is connected to both ends of the ridge of the silicon ridge waveguide 32. A silicon oxide cladding dielectric layer 5 covers the silicon device layer 8. A BCB thin film layer 7 covers the silicon oxide cladding dielectric layer 5. A graphene thin film layer 61 is attached to the surface of the BCB thin film layer 7, located directly above and completely covering the silicon ridge waveguide 32. The first gate dielectric layer 62 and the second gate dielectric layer 63 are respectively attached to the surface of the graphene thin film layer 61, with a predetermined distance between them. The first gate electrode 66 and the second gate electrode 67 are respectively... The passivation dielectric layer 68 is disposed on the surfaces of the first gate dielectric layer 62 and the second gate dielectric layer 63; the passivation dielectric layer 68 is attached to the upper surfaces of the first gate electrode 66 and the second gate electrode 67, and completely covers the first gate dielectric layer 62, the second gate dielectric layer 63, the first gate electrode 66 and the second gate electrode 67; the source electrode 64 is located on the side of the first gate electrode 66 away from the second gate electrode 67, and the drain electrode 65 is located on the side of the second gate electrode 67 away from the first gate electrode 66, and the source electrode 64 is partially attached to the surface of the graphene thin film layer 61 and the other part is attached to the surface of the BCB thin film layer 7; the drain electrode 65 is partially attached to the surface of the graphene thin film layer 61 and the other part is attached to the surface of the BCB thin film layer 7.

[0050] The optical radio frequency signal A is input to the silicon strip waveguide 31 through the vertically coupled grating 4, then through the silicon ridge waveguide 32, and finally reaches the graphene device group 6; the intrinsic signal B is input to the graphene device group 6 through the first gate electrode 65 and the second gate electrode 66; the optical radio frequency signal A and the intrinsic signal B are converted and mixed by the graphene device group 6 to obtain the intermediate frequency signal C, and the intermediate frequency signal C is output through the drain electrode 64.

[0051] In one embodiment, the spacing between the first gate electrode 65 and the second gate electrode 66 is 20-100 nm.

[0052] In one embodiment, a method for fabricating a waveguide-integrated graphene optoelectronic mixer chip specifically includes the following steps:

[0053] 1) First on a standard SOI substrate ( Figure 3Electron beam photoresist patterns for vertically coupled grating 4 and silicon ridge waveguide 32 were fabricated on a wafer using electron beam direct writing exposure and development. AR-P 6200 electron beam photoresist was used. Using the electron beam photoresist as a mask, inductively coupled plasma based on sulfur hexafluoride was employed to etch the vertically coupled grating 4 and silicon ridge waveguide 32 to a depth of 80 nanometers. The remaining photoresist was then removed sequentially using N-methylpyrrolidone, acetone, and ethanol. Figure 4 As shown.

[0054] 2) An electron beam resist mask pattern for the silicon strip waveguide 31 was fabricated using electron beam direct writing exposure and development. AR-P 6200 electron beam resist was used. Using the electron beam resist as a mask, inductively coupled plasma based on sulfur hexafluoride was used to etch the silicon strip waveguide 31 to a depth of 220 nm. The remaining photoresist was then removed sequentially using N-methylpyrrolidone, acetone, and ethanol. Figure 5 As shown;

[0055] 3) A 2-micron silicon oxide overlay dielectric layer 5 is grown using plasma-enhanced chemical vapor deposition, and the wafer surface is thinned and polished using chemical mechanical polishing (CMP). Figure 6 As shown;

[0056] 4) A BCB thin film layer 7 is coated on the surface of the dielectric layer 5 on silicon oxide using a spin coating process and then cured. The thickness of the BCB thin film layer 7 is 10 nanometers, the curing temperature is 190 degrees Celsius, and the curing time is 10 minutes.

[0057] 5) The graphene film was transferred to the wafer surface using a wet gold transfer process. After drying, it was soaked and cleaned with acetone and ethanol in sequence, and then baked in an oven for a long time at a temperature of 90 degrees Celsius for 12 hours.

[0058] 6) A graphene photoresist mask for the graphene device region is prepared using photolithography and development. Then, gold on the graphene surface is etched away using a gold etching solution, and oxygen plasma etching is used to remove part of the graphene, completing the patterning of the graphene thin film layer 61. Figure 7 As shown;

[0059] 7) Source and drain electrode patterns were fabricated using photolithography and development. Then, 20 nm titanium, 180 nm gold, and 10 nm titanium were sequentially evaporated using electron beam evaporation as source and drain metals. Source electrode 64 and drain electrode 65 were then fabricated by stripping. Figure 8 As shown;

[0060] 8) The channel region pattern is prepared using photolithography and development. The gold in the channel region is removed by etching with a gold etching solution. Then, an aluminum oxide layer is grown on an atomic layer substrate as the gate dielectric layer. The gate dielectric layer is 10 nanometers thick. Figure 9 As shown;

[0061] 9) Electron beam photomask patterns for the first gate electrode 66 and the second gate electrode 67 were prepared using electron beam direct writing exposure and development. Then, 10 nm titanium and 50 nm gold were sequentially evaporated using electron beam evaporation. The gate electrodes were fabricated using a lift-off process. Figure 10 As shown;

[0062] 10) A 450 nm thick HSQ electron beam negative resist was spin-coated, and a passivation dielectric layer 68 was prepared using electron beam direct writing exposure and development to complete the chip fabrication. Figure 11 As shown.

[0063] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0064] It should be noted that the terms "first," "second," and "third" used in the embodiments of this application are merely to distinguish similar objects and do not represent a specific order of objects. It is understood that "first," "second," and "third" can be interchanged in a specific order or sequence where permitted. It should be understood that the objects distinguished by "first," "second," and "third" can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in an order other than those illustrated or described herein.

[0065] The terms "comprising" and "having," and any variations thereof, in this application are intended to cover non-exclusive inclusion. For example, a process, method, apparatus, product, or device that includes a series of steps or modules is not limited to the steps or modules listed, but may optionally include steps or modules not listed, or may optionally include other steps or modules inherent to such processes, methods, products, or devices.

[0066] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A waveguide-integrated graphene optoelectronic mixer chip, characterized in that, include: Silicon substrate (1), buried oxide Layer (2), optical waveguide (3), vertically coupled grating (4), silicon oxide cladding dielectric layer (5), graphene device group (6) and BCB thin film layer (7); The optical waveguide (3) includes: a plurality of silicon strip waveguides (31) and silicon ridge waveguides (32). The graphene device assembly (6) includes: a graphene thin film layer (61), a first gate dielectric layer (62), and a second gate dielectric layer. Dielectric layer (63), source electrode (64), drain electrode (65), first gate electrode (66), second gate electrode (67) and passivation dielectric layer (68); The silicon substrate (1), buried oxide layer (2), and silicon device layer (8) are stacked in sequence to form a standard SOI substrate; the vertically coupled grating (4), silicon strip waveguide (31), and silicon ridge waveguide (32) are disposed in the silicon device layer (8); the plurality of silicon strip waveguides (31) are respectively connected to the two ends of the ridge of the silicon ridge waveguide (32); the silicon oxide cladding dielectric layer (5) covers the silicon device layer (8); the BCB thin film layer (7) covers the silicon oxide cladding dielectric layer (5); the graphene thin film layer (61) is attached to the surface of the BCB thin film layer (7) and is located directly above the silicon ridge waveguide (32) and completely covers it; the first gate dielectric layer (62) and the second gate dielectric layer (63) are respectively attached to the surface of the graphene thin film layer (61) and are spaced apart by a preset distance; the first gate electrode (66) and the second gate electrode (67) are respectively attached to the surface of the graphene thin film layer (61). The passivation dielectric layer (68) is disposed on the surface of the first gate dielectric layer (62) and the second gate dielectric layer (63); the passivation dielectric layer (68) is attached to the upper surface of the first gate electrode (66) and the second gate electrode (67), and completely covers the first gate dielectric layer (62), the second gate dielectric layer (63), the first gate electrode (66) and the second gate electrode (67); the source electrode (64) is located on the side of the first gate electrode (66) away from the second gate electrode (67), the drain electrode (65) is located on the side of the second gate electrode (67) away from the first gate electrode (66), and the source electrode (64) is partially attached to the surface of the graphene film layer (61) and the other part is attached to the surface of the BCB film layer (7); the drain electrode (65) is partially attached to the surface of the graphene film layer (61) and the other part is attached to the surface of the BCB film layer (7); The optical radio frequency signal (A) is input to the silicon strip waveguide (31) through the vertically coupled grating (4), and then... The signal passes through the silicon ridge waveguide (32) and then reaches the graphene device group (6); the intrinsic signal (B) is input into the graphene device group (6) through the first gate electrode (66) and the second gate electrode (67); the optical radio frequency signal (A) and the intrinsic signal (B) are converted and mixed by the graphene device group (6) to obtain the intermediate frequency signal (C), and the intermediate frequency signal (C) is output through the drain electrode (65).

2. The waveguide integrated graphene optoelectronic mixer chip according to claim 1, characterized in that, The first The spacing between the first gate electrode (66) and the second gate electrode (67) is 20-100 nm.

3. The fabrication method of the waveguide integrated graphene optoelectronic mixer chip according to claim 1, its features... The characteristics include the following steps: S1: First, electron beam direct writing exposure and development technology is used on a pre-prepared standard SOI substrate wafer to fabricate... Prepare electron beam resist mask patterns for vertically coupled grating (4) and silicon ridge waveguide (32), and then use electron beam resist as a mask to etch vertically coupled grating (4) and silicon ridge waveguide (32) using inductively coupled plasma process. Finally, remove resist and clean. S2: Electron beam photomask pattern of silicon strip waveguide (31) was fabricated using electron beam direct writing exposure and development technology. Using electron beam resist as a mask, silicon strip waveguides (31) are etched using inductively coupled plasma technology, and finally the resist is removed and cleaned. S3: Grow a dielectric layer on top of silicon oxide (5), and polish the wafer surface using a chemical mechanical polishing process; S4: A BCB thin film layer (7) is coated on the surface of the dielectric layer (5) on silicon oxide using a spin coating process, and then... It undergoes a curing process; S5: The pre-fabricated graphene film is transferred to the wafer surface using a wet gold transfer process, followed by a drying operation. Next, it is soaked and cleaned with acetone and ethanol in sequence, and finally baked in an oven for a preset duration. S6: A graphene photoresist mask for the graphene device region is prepared using a photolithography and development process, followed by etching. The graphene thin film layer (61) was patterned using a combination of lithography and oxygen plasma etching processes. S7: The patterns of the source electrode (64) and drain electrode (65) are prepared using a photolithography and development process, and then... The source electrode (64) and drain electrode (65) were prepared by electron beam evaporation and stripping processes. S8: The trench region pattern is prepared using photolithography and development technology, and then the gold in the trench region is etched using a gold etching process. After etching to remove the material, an insulating material is grown as the gate dielectric layer. S9: The first gate electrode (66) and the second gate electrode were fabricated using electron beam direct writing exposure and development processes, respectively. (67) Electron beam photomask pattern, and then the first gate electrode (66) and the second gate electrode (67) are prepared by electron beam evaporation and stripping processes, respectively. S10: Apply HSQ electron beam negative photoresist using a spin coating method, followed by electron beam direct writing exposure and development process. A passivation dielectric layer (68) was prepared.

4. The method for fabricating a waveguide-integrated graphene optoelectronic mixer chip according to claim 3, characterized in that... In step S1, the etching gas used is sulfur hexafluoride gas, and the etching depth is 80 nanometers.

5. The method for fabricating a waveguide-integrated graphene optoelectronic mixer chip according to claim 4, characterized in that... In step S2, the etching gas used is sulfur hexafluoride gas, and the etching depth is 220 nanometers.

6. The method for fabricating a waveguide-integrated graphene optoelectronic mixer chip according to claim 5, characterized in that... In step S3, a silicon oxide overcoating dielectric layer (5) is deposited by plasma-enhanced chemical vapor deposition, and the thickness of the silicon oxide overcoating dielectric layer (5) is 2-3 micrometers.

7. The method for fabricating a waveguide-integrated graphene optoelectronic mixer chip according to claim 6, characterized in that... In step S4, the thickness of the BCB film layer (7) is 5-15 nanometers, the curing temperature is 180-200 degrees Celsius, and the curing time is 5-15 minutes.

8. The method for fabricating a waveguide-integrated graphene optoelectronic mixer chip according to claim 7, characterized in that... In step S7, the metals required for preparing the source electrode (64) and drain electrode (65) include: 20-nanometer titanium, 180-nanometer gold, and 10-nanometer titanium.

9. The method for fabricating a waveguide-integrated graphene optoelectronic mixer chip according to claim 8, characterized in that, In step S9, the metals required to prepare the first gate electrode (66) and the second gate electrode (67) include: 10 nanometer titanium and 50-100 nanometer gold.

10. The method for fabricating a waveguide-integrated graphene optoelectronic mixer chip according to claim 9, characterized in that, In step S10, the thickness of the passivation medium layer (68) is 400-700 nanometers.

Images