Switched capacitor power converter

Abstract

This invention relates to a switched-capacitor power converter, comprising multiple switches connected in series between system ground and an input voltage bus. A high-voltage side switch located between the input voltage bus and the output terminal of the switched-capacitor power converter, and adjacent to the output terminal, is configured as an isolation switch, comprising two back-to-back connected diodes and a body terminal, wherein the body terminal is configured to have an adjustable voltage potential. This method improves the power conversion efficiency of the switched-capacitor power converter.

Description

[0001] Priority claims and cross-references

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 106,730, filed October 28, 2020, entitled “Gate drive device and control method for switched capacitor power converter,” which is hereby incorporated by reference. Technical Field

[0003] This invention relates to the field of gate drive device technology, and in particular to a gate drive device and control method for a switched capacitor power converter. Background Technology

[0004] With further technological advancements, various portable devices, such as mobile phones, tablet PCs, digital cameras, MP3 players, and / or similar devices, have become widespread. Each portable device can employ multiple rechargeable battery cells. These multiple rechargeable battery cells can be connected in series or parallel to form a rechargeable battery pack for storing electrical energy.

[0005] As power consumption becomes increasingly critical, there is a growing need to shorten battery charging times. Fast charging has emerged as a viable solution to meet evolving consumer demands. Fast charging systems utilize switched-capacitor power converters to deliver high current to the battery while keeping the input current (e.g., USB cable current) low. Switched-capacitor power converters offer numerous advantages, such as monolithic integrated converters that eliminate the need for external inductors and high power conversion efficiency. They enable safe and rapid charging of large-capacity batteries.

[0006] A switched-capacitor power converter comprises multiple switches connected in series between the input power supply and ground. The ungrounded switch is typically referred to as the high-side switch, and the grounded switch is typically referred to as the low-side switch. The gates of the low-side and high-side switches are controlled by separate low-side drive circuits and multiple high-side drive circuits. The low-side drive circuit is biased from a regulated bias voltage source. The high-side drive circuits may require a gate voltage higher than the input power supply voltage. Summary of the Invention

[0007] The present invention aims to provide a gate driving device and control method for a switched capacitor power converter, which can improve the power conversion efficiency of the switched capacitor power converter.

[0008] To achieve the above objectives, in a first aspect, the present invention provides an apparatus comprising:

[0009] A first gate driving transistor and a second gate driving transistor are connected in series. The common node of the first gate driving transistor and the second gate driving transistor is connected to the gate of the power switch. The second gate driving transistor is configured as an independent body terminal switch whose body terminal is connected to the body terminal of the power switch.

[0010] A first auxiliary transistor connected between the body terminal and the source terminal of the power switch;

[0011] A second auxiliary transistor coupled between the gate of the power switch and system ground; and

[0012] A third auxiliary transistor is coupled between the logic control ground and the system ground, wherein the second auxiliary transistor and the third auxiliary transistor are configured to pull the gate of the power switch and the logic control ground to the system ground in response to the shutdown of the device.

[0013] In one alternative approach, the device is shut down if a disable signal is received or a fault is detected.

[0014] In one alternative embodiment, the power switch is an isolation switch comprising two diodes;

[0015] The first diode is located between the body terminal and the source terminal of the power switch, and the second diode is located between the body terminal and the drain terminal of the power switch. The two diodes are connected back to back.

[0016] In an alternative embodiment, the device further includes:

[0017] A fourth auxiliary transistor coupled between the source of the power switch and the logic control ground;

[0018] The fourth auxiliary transistor is turned off in response to the device being turned off, thereby isolating the source of the power switch from the logic control ground.

[0019] In one alternative, the first auxiliary transistor is turned off in response to the power switch being turned off, thereby isolating the body terminal of the power switch from the source terminal of the power switch.

[0020] In an alternative embodiment, the device further includes:

[0021] A fifth auxiliary transistor connected between the body terminal and the system ground;

[0022] The fifth auxiliary transistor is turned on in response to the device being turned off, so as to pull down the body terminal of the power switch to the system ground.

[0023] In one alternative embodiment, the power switch is a third switch of the switched capacitor power converter;

[0024] The power switch is connected between the output terminal of the switched capacitor power converter and the flying capacitor.

[0025] In one alternative embodiment, the switched-capacitor power converter includes:

[0026] A first switch, a second switch, a third switch, and a fourth switch connected in series between the system ground and the input voltage bus; and

[0027] The flying capacitor is connected between the common node of the first and second switches and the common node of the third and fourth switches.

[0028] In a second aspect, the present invention provides a method for controlling a driver, the driver being used to generate a gate drive signal for a power switch, the method comprising:

[0029] After enabling the driver, connect the source of the power switch to the logic control ground of the driver, and connect the body terminal of the power switch to the source of the power switch; and

[0030] After disabling the driver, disconnect the source of the power switch from the logic control ground of the driver, and disconnect the body terminal of the power switch from the source of the power switch.

[0031] In an alternative approach, the method further includes:

[0032] After enabling the driver, connect the driver's power supply voltage bus to the input voltage bus; and

[0033] After disabling the driver, disconnect the driver's power supply voltage bus from the input voltage bus.

[0034] In an alternative approach, the method further includes:

[0035] After disabling the driver, connect the body terminal of the power switch, the gate of the power switch, and the logic control ground to system ground.

[0036] In one alternative embodiment, the power switch is a third switch of a switched-capacitor power converter, the switched-capacitor power converter comprising:

[0037] A first switch, a second switch, a third switch, and a fourth switch connected in series between system ground and the input voltage bus; and

[0038] A flying capacitor connected between the common node of the first and second switches and the common node of the third and fourth switches.

[0039] In an alternative approach, the method further includes:

[0040] After the driver is disabled, a first voltage clamping circuit is activated to limit the voltage across the drain and body terminals of the power switch, and a second voltage clamping circuit is activated to limit the voltage across the two power buses of the driver.

[0041] In an alternative approach, the method further includes:

[0042] If a fault is detected or a disable signal is received, the driver is disabled.

[0043] Thirdly, the present invention provides a system comprising:

[0044] Switched capacitor power converters; and

[0045] A driver configured to drive a third switch of the switched capacitor power converter, wherein the driver includes:

[0046] A first gate drive transistor and a second gate drive transistor connected in series;

[0047] The common node of the first gate driving transistor and the second gate driving transistor is connected to the gate of the third switch, and the second gate driving transistor is configured as an independent body terminal switch whose body terminal is connected to the body terminal of the power switch.

[0048] A first auxiliary transistor connected between the body terminal and the source terminal of the third switch;

[0049] A second auxiliary transistor coupled between the gate of the third switch and system ground; and

[0050] A third auxiliary transistor is coupled between the logic control ground and the system ground, wherein the second auxiliary transistor and the third auxiliary transistor are configured to pull the gate of the power switch and the logic control ground to the system ground in response to the shutdown of the device.

[0051] In one alternative embodiment, the switched-capacitor power converter includes:

[0052] A first switch, a second switch, a third switch, and a fourth switch connected in series between the system ground and the input voltage bus; and

[0053] A flying capacitor connected between the common node of the first and second switches and the common node of the third and fourth switches.

[0054] In an alternative embodiment, the system further includes:

[0055] A fourth auxiliary transistor coupled between the source of the third switch and the logic control ground;

[0056] The fourth auxiliary transistor is turned off in response to the driver's shutdown, thereby isolating the source of the third switch from the logic control ground.

[0057] In an alternative embodiment, the system further includes:

[0058] A fifth auxiliary transistor and a discharge resistor are connected in series between the body terminal and the system ground;

[0059] The fifth auxiliary transistor is turned on in response to the driver being turned off, so as to pull down the body terminal of the third switch to the system ground.

[0060] In an alternative embodiment, the system further includes:

[0061] A first voltage clamping circuit coupled between the drain of the third switch and the body terminal;

[0062] A second voltage clamping circuit coupled between the input voltage bus and the power supply voltage bus of the driver; and

[0063] A third voltage clamping circuit coupled between the power supply voltage bus and the logic control ground;

[0064] If the driver is turned off or a fault occurs in the system, the first voltage clamping circuit, the second voltage clamping circuit, and the third voltage clamping circuit are activated.

[0065] In one alternative approach, the driver is shut down if a disable signal is received or a fault is detected in the system.

[0066] The beneficial effects of the embodiments of the present invention are as follows: The gate driving device of the switched capacitor power converter provided by the present invention includes a first gate driving transistor and a second gate driving transistor connected in series. The common node of the first gate driving transistor and the second gate driving transistor is connected to the gate of a power switch. The second gate driving transistor is configured as an independent body terminal switch whose body terminal is connected to the body terminal of the power switch. A first auxiliary transistor is connected between the body terminal and the source of the power switch. A second auxiliary transistor is coupled between the gate of the power switch and the system ground. A third auxiliary transistor is coupled between the logic control ground and the system ground. The second auxiliary transistor and the third auxiliary transistor are configured to pull the gate of the power switch and the logic control ground to the system ground in response to the shutdown of the device. In this way, the power conversion efficiency of the switched capacitor power converter can be improved. Attached Figure Description

[0067] To gain a more complete understanding of this disclosure and its advantages, the following description is now taken in conjunction with the accompanying drawings, in which:

[0068] Figure 1 A schematic diagram of a switched-capacitor power converter according to various embodiments of the present disclosure is shown;

[0069] Figure 2 Various embodiments according to this disclosure are shown as follows: Figure 1 A schematic diagram of a first implementation of the gate driver for a switched-capacitor power converter is shown.

[0070] Figure 3 Various embodiments according to this disclosure are shown as follows: Figure 1 A schematic diagram of a second implementation of the gate driver for the switched capacitor power converter is shown.

[0071] Figure 4 Various embodiments according to this disclosure are shown as follows: Figure 1 A schematic diagram of a third implementation of the gate driver for a switched capacitor power converter is shown.

[0072] Figure 5 Various embodiments according to this disclosure are shown as follows: Figure 4 The diagram shows two alternative implementation schemes for the voltage clamping circuit.

[0073] Figure 6 Various embodiments according to this disclosure are shown as follows: Figure 4 The timing diagram of the gate driver is shown;

[0074] Figure 7 The diagram shows timing diagrams of the gate driver after a fault is detected in a switched-capacitor power converter according to various embodiments of the present disclosure.

[0075] Unless otherwise indicated, corresponding numbers and symbols in different figures generally refer to corresponding parts. The accompanying drawings are provided to clearly illustrate relevant aspects of various embodiments and are not necessarily drawn to scale. Detailed Implementation

[0076] The following describes in detail the making and use of the presently preferred embodiments. However, it should be understood that this disclosure provides many applicable inventive concepts that can be implemented in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of particular ways of making and using this disclosure and are not intended to limit the scope of this disclosure.

[0077] This disclosure will be described in a specific context, namely, within a single-stage battery charger system, with regard to preferred embodiments. However, the invention is also applicable to various power systems. Various embodiments will be explained in detail below with reference to the accompanying drawings.

[0078] Figure 1 Schematic diagrams of switched-capacitor power converters according to various embodiments of this application are shown. The switched-capacitor power converter has an input terminal coupled to an input voltage bus VIN and an output terminal coupled to an output voltage bus VOUT. For example... Figure 1 As shown, the input voltage bus discharge circuit is connected between the input voltage bus VIN and ground. The input voltage bus discharge circuit includes a resistor Rpd connected in series and a switch S2. The input voltage bus discharge circuit is used to discharge the input voltage bus VIN so that the voltage on the input voltage bus VIN is close to zero volts after the switched capacitor power converter is turned off. This ensures that at the beginning of the next power-on, the voltage on the input voltage bus VIN is approximately zero.

[0079] like Figure 1 As shown, the switched-capacitor power converter includes a first switch SW1, a second switch SW2, a third switch SW3, and a fourth switch SW4 connected in series between ground (GND) and the input voltage bus VIN. The common node of switches SW2 and SW3 is connected to the output voltage bus VOUT. A load, such as a battery, is connected between the output voltage bus VOUT and GND. In any embodiment of this application, as Figure 1 The GND shown is also called the system ground.

[0080] like Figure 1As shown, each switch has a dedicated driver. Specifically, a first gate drive signal GD1 is fed to a first driver DR1 via a first level shifter 112. The output of the first driver DR1 is connected to the gate of the first switch SW1. A second gate drive signal GD2 is fed to a second driver DR2 via a second level shifter 114. The output of the second driver DR2 is connected to the gate of the second switch SW2. A third gate drive signal GD3 is fed to a third driver DR3 via a third level shifter 116. The output of the third driver DR3 is connected to the gate of the third switch SW3. A fourth gate drive signal GD4 is fed to a fourth driver DR4 via a fourth level shifter 118. The output of the fourth driver DR4 is connected to the gate of the fourth switch SW4.

[0081] like Figure 1 As shown, the positive terminal of each driver is connected to the drain of the adjacent upper switch (i.e., the switch preceding the adjacent switch). For example, the positive terminal of the second driver DR2 is connected to the drain of the third switch SW3. The fourth switch SW4 does not have an adjacent upper switch. The positive terminal of the fourth driver DR4 is connected to the positive terminal of the bootstrap capacitor Cbst. The bootstrap capacitor Cbst is connected between the voltage bus BST and node CFH. A bootstrap voltage is established on the bootstrap capacitor Cbst by a bootstrap circuit including a level shifter 106, a driver 104, and a bootstrap switch / diode device 102. The bootstrap switch / diode device 102 includes a bootstrap switch or bootstrap diode configured to charge the bootstrap capacitor Cbst. The bootstrap capacitor is configured to provide bias power to the high-voltage side driver (e.g., the driver of the fourth switch SW4). Bootstrap circuits are well known in the art and will not be described further here.

[0082] Furthermore, the switched-capacitor power converter includes a flying capacitor Cfly and an output capacitor Cout. The flying capacitor Cfly is connected between the common node (CFH) of the third switch SW3 and the fourth switch SW4 and the common node (CFL) of the first switch SW1 and the second switch SW2. An active discharge circuit (not shown in the figure) is connected in parallel with the flying capacitor Cfly. After the switched-capacitor power converter is turned off, the active discharge circuit is used to discharge the voltage across the flying capacitor Cfly.

[0083] The output capacitor Cout is connected between the output voltage bus VOUT and system ground. The output capacitor Cout is connected in parallel with the load.

[0084] In some embodiments, the third switch SW3 is used as an isolating switch. Specifically, the third switch SW3 provides isolation between the load (e.g., battery) and the input power source (e.g., charging power source). Figure 1As shown, the body terminal of the third switch SW3 is not connected to the source terminal of the third switch SW3. The third switch SW3 includes two diodes. The first diode is located between the body terminal and the source terminal. The second diode is located between the body terminal and the drain terminal. These two diodes are connected back-to-back. Due to the back-to-back connected diodes, the third switch SW3 can act as an isolating switch. After a turn-off signal is applied to the gate of the third switch SW3, the third switch SW3 can provide isolation between the output voltage bus VOUT and node CFH. Furthermore, when node CFH is shorted to ground, the third switch SW3 can prevent excessive current from being drawn from the load (e.g., a battery) coupled to the output voltage bus VOUT.

[0085] like Figure 1 As shown, the body control circuit 110 is connected to the common node of the two back-to-back diodes. The body control circuit 110 is used to adjust the voltage potential at the body terminal of the third switch SW3 to control the characteristics of the channel of the third switch SW3. In some embodiments, the body control circuit 110 is also used to pull the body terminal of the third switch SW3 to ground when the switched-capacitor power converter is in the off state. When the switched-capacitor power converter is ready to turn on, and before toggling the gate terminal of each of the four power switches mentioned above, the body terminal of the third switch SW3 will be connected to the switch (e.g., as shown in the diagram). Figure 3 The PM3 shown is connected to the source of the third switch SW3.

[0086] It should be noted that, Figure 1 The switching element can be a metal-oxide-semiconductor field-effect transistor (MOSFET) device. Alternatively, the switching element can be any controllable switch, such as an insulated-gate bipolar transistor (IGBT) device, an integrated gate rectifier thyristor (IGCT) device, a gate turn-off thyristor (GTO) device, a silicon controlled rectifier (SCR) device, a junction-gate field-effect transistor (JFET) device, a MOS-controlled thyristor (MCT) device, a gallium nitride (GaN)-based power device, or a silicon carbide (SiC)-based power device.

[0087] It should be noted that, although Figure 1 The diagram illustrates the implementation of the first switch SW1, the second switch SW2, the third switch SW3, and the fourth switch SW4 as a single n-type transistor; however, those skilled in the art will recognize that other variations, modifications, and alternatives are possible. For example, depending on the specific application and design requirements, all or at least some of the switches SW1, SW2, SW3, and SW4 can be implemented as p-type transistors. Furthermore, as... Figure 1Each switch shown can be implemented as multiple switches connected in parallel. Furthermore, a capacitor can be connected in parallel with a switch to achieve zero-voltage switching (ZVS) / zero-current switching (ZCS).

[0088] In practical applications, the switched-capacitor power converter operates in two distinct phases. In the first phase, the fourth switch SW4 and the second switch SW2 are turned on, while the third switch SW3 and the first switch SW1 are turned off. After the fourth switch SW4 and the second switch SW2 are turned on, the input voltage VIN charges the flying capacitor Cfly and the output capacitor Cout. In the first phase, the flying capacitor Cfly is connected in series with the output capacitor Cout. In the second phase, the third switch SW3 and the first switch SW1 are turned on, while the fourth switch SW4 and the second switch SW2 are turned off. After the third switch SW3 and the first switch SW1 are turned on, the flying capacitor Cfly is connected in parallel with the output capacitor Cout, discharging the energy stored in the flying capacitor Cfly and the output capacitor Cout to the load (e.g., a battery connected in parallel with the output capacitor Cout).

[0089] Figure 2 As provided for the embodiments of the present invention Figure 1 The diagram illustrates a first implementation of the gate driver for a switched-capacitor power converter. That is, it can employ a method such as... Figure 2 The gate driver shown is used to drive, for example Figure 1 The first switch SW1, the second switch SW2, the third switch SW3, and the fourth switch SW4 are shown. Specifically, [the following is used]... Figure 2 The gate driver in the upper part drives the first switch SW1 and the second switch SW2. Figure 2 The gate driver in the lower half drives the fourth switch SW4. The gate drivers in these two parts are similar, except that the drain of the fourth switch SW4 is not connected to any other switches, and the BST node is used to power the driver of SW4. For simplicity, only a detailed description is provided. Figure 2 The gate driver in the upper half. For example... Figure 2 As shown, the gate driver includes a p-type transistor PM1, an n-type transistor NM1, a control logic unit 206, and a set of level shifters 202 and 204. Each level shifter in this set has four voltage terminals: voltage terminal VL, voltage terminal G, voltage terminal VH, and voltage terminal GH. Figure 2 As shown, voltage terminal VL is connected to the bias voltage VDD (e.g., a 5V bias voltage). Voltage terminal G is grounded. Voltage terminal VH is connected to the first voltage bus VPOS. Voltage terminal GH is connected to the second voltage bus VNEG.

[0090] like Figure 2As shown, each level shifter in this set is configured to receive an enable signal EN_LV and a gate drive signal FET_ON_LV. This set of level shifters uses a well-known level offset technique to shift the control signal from a low-voltage domain (e.g., a voltage domain formed by the bias voltage VDD and ground GND) to the power MOSFET gate driver domain (e.g., a voltage domain formed by the first voltage bus VPOS and the second voltage bus VNEG).

[0091] like Figure 2 As shown, the enable signal EN_LV and the gate drive signal FET_ON_LV are converted into the enable signal EN_HV and the gate drive signal FET_ON_HV in the gate drive voltage domain. The enable signal EN_HV and the gate drive signal FET_ON_HV are then fed into the control logic unit 206. The control logic unit 206 includes a series of logic buffers for driving the p-type transistor PM1 and the n-type transistor NM1. The control logic unit 206 also includes an inverted signal for generating the FET_ON_HV signal. The circuit.

[0092] p-type transistor PM1 and n-type transistor NM1 are connected in series between the first voltage bus VPOS and the second voltage bus VNEG. The common node of p-type transistor PM1 and n-type transistor NM1 is used to generate a gate drive signal applied to the gate of the power MOSFET (e.g., the first switch SW1 and the second switch SW2).

[0093] Transistor PM1 acts as a pull-up transistor. Transistor PM1 can pull the gate voltage up to VPOS. Transistor NM1 acts as a pull-down transistor. Transistor NM1 can pull the gate voltage down to VNEG.

[0094] like Figure 2 As shown, in the power MOSFET gate drive domain, a second voltage bus VNEG is connected to the source node of the power MOSFET. The second voltage bus VNEG can also be referred to as the ground network of the gate drive domain. A first voltage bus VPOS is connected to a node with a stable voltage higher than the second voltage bus VNEG. In some embodiments, the first voltage bus VPOS is connected to the drain of an adjacent high-side power MOSFET in a switched-capacitor power converter. For example, if the power MOSFET is as follows... Figure 1 As shown in the diagram, the first switch SW1 is connected to the drain of the second switch SW2. If the power MOSFET is the fourth switch SW4, and the fourth switch SW4 does not have a high-voltage side power MOSFET, then the first voltage bus VPOS of the corresponding driver is connected to the drain of the second switch SW2. Figure 1The bootstrap capacitor is shown at node BST. The voltage at node BST is charged and maintained at a voltage level approximately equal to VIN-VOUT.

[0095] like Figure 2 The gate driver shown is not suitable for driving the third switch SW3. There are at least two possible reasons. First, when the power MOSFET is off, Figure 2 Transistor NM1 is turned on. The turned-on transistor NM1 connects the gate of the power MOSFET to the second voltage bus VNEG. This connection between the gate of the power MOSFET and the second voltage bus VNEG cannot completely turn off the third switch SW3 because the third switch SW3 is reverse-conducting. Specifically, when the switched-capacitor power converter is off, the input voltage bus VIN discharges to 0V. (Return to Reference) Figure 1 The voltage clamping circuit at node CFH clamps the voltage to approximately 0V plus the forward voltage drop of the diode (the body diode voltage drop of the fourth switch SW4). The gate of the third switch SW3 is connected to the output voltage bus VOUT. The output voltage bus is connected to the battery. The battery voltage ranges from approximately 2.6V to approximately 4.6V. The drain voltage is clamped at node CFH and is equal to the forward voltage of the diode (approximately 0.6V). Therefore, the gate voltage of the third switch SW3 is greater than the drain voltage of the third switch SW3. Due to this drain-gate voltage relationship, the third switch SW3 conducts in reverse. Furthermore, the body diode of transistor NM1 clamps the gate of the third switch SW3 to approximately VOUT minus the forward voltage drop of the diode. Therefore, the gate voltage of the third switch SW3 is much higher than the voltage at node CFH. Because the gate voltage of the third switch SW3 is higher than the drain voltage of the third switch SW3, the control circuit cannot turn off the third switch SW3.

[0096] The two problems mentioned above can be addressed in the following section. Figure 3 and Figure 4 The gate driver is discussed to overcome this.

[0097] Figure 3 The embodiments of the present invention are shown as follows: Figure 1 The second implementation of the gate driver for the switched capacitor power converter is shown. The gate driver includes p-type transistor PM1, n-type transistor NM1, control logic unit 206, a set of level shifters 202 and 204, and transistors NM3, PM3, NM2, NM4, and NM5.

[0098] p-type transistor PM1 and n-type transistor NM1 are connected in series between the input voltage bus VIN and the output voltage bus VOUT. The common node of p-type transistor PM1 and n-type transistor NM1 is configured to generate a gate drive signal applied to the gate of switch SW3. A first bias terminal (e.g., bias voltage) of control logic unit 206 is connected to VIN, and a second bias terminal (e.g., logic control ground) is connected to FGND. FGND is also referred to as the control logic ground network or control logic ground.

[0099] The above has already been about Figure 2 The transistor PM1, control logic unit 206, and level shifters 202 and 204 have already been discussed, and will not be repeated here. Figure 3 As shown, transistor NM1 can be used as a body-terminal switch. The structure of transistor NM1 is similar to that of the third switch SW3. The body terminal of transistor NM1 is connected to the body terminal of the third switch SW3. Figure 3 As shown, transistor PM3 is connected between the body terminal and the source terminal of the third switch SW3. When the switched-capacitor power converter is ready to turn on, and before powering on the switched-capacitor power converter, the body terminal of the third switch SW3 is connected to the source terminal of the third switch SW3. Upon receiving a disable signal (e.g., a falling edge of EN_LV) or detecting a system fault, the gate driver is disabled, the switched-capacitor power converter is turned off, and transistor PM3 is turned off. As a result of turning off transistor PM3, the body terminal of the third switch SW3 is disconnected from the source terminal of the third switch SW3.

[0100] resistor R pd_gate Transistor NM5 is connected in series between the gate of the third switch SW3 and system ground. The third switch NM2 is connected between the output voltage bus VOUT and the control logic ground FGND. Resistor R... pd_FGND It is connected in series with transistor NM4 between control logic ground FGND and system ground.

[0101] like Figure 3 As shown, the body terminal of transistor NM1 is connected to the body terminal of the third switch SW3. This connection eliminates the diode clamping path described in the second problem above. Furthermore, as... Figure 3 As shown, the source and body terminals of transistor NM2 are connected together. Transistor NM2 acts as a switch to isolate the control logic ground FGND of control logic unit 206 from VOUT. Figure 3As shown, the output voltage bus VOUT is connected to the source of transistor NM1. In some embodiments, transistor NM2 is controlled by an enable signal EN_HV. When the enable signal EN_HV goes high (e.g., when the enable signal EN_HV is connected to the input voltage bus VIN), transistor NM2 is turned on. Conversely, when the enable signal EN_HV goes low (e.g., when the enable signal EN_HV is connected to the output voltage bus VOUT), transistor NM2 is turned off. When the third switch SW3 is off, transistor NM2 is used to isolate the control logic ground FGND from the output voltage bus VOUT.

[0102] In some embodiments, when a shutdown signal is applied to the switched-capacitor power converter, the enable signal EN_LV becomes 0V. The enable signal EN_LV acts as a disable signal applied to the gate driver. This disable signal turns on transistor NM4. The turned-on transistor NM4 and resistor R... pd_FGND This pulls the voltage on the control logic ground FGND down to system ground. Additionally, this disable signal also turns on transistor NM5. The turned-on transistor NM5 and resistor R... pd_gate The gate of the third switch SW3 is pulled to system ground. Additionally, this disable signal also turns on transistor NM3. The turned-on transistor NM3 and resistor R... pd_bulk Pull the body terminal of the third switch SW3 to system ground.

[0103] Transistors NM2, NM4, and NM5 pull the gate of the third switch SW3 down to system ground. The gate voltage of the third switch SW3 is lower than its drain voltage. The third switch SW3 can be completely turned off. This circuit solves the problem described in the first example above.

[0104] Figure 4 The embodiments of the present invention are shown as follows: Figure 1 The third implementation of the gate driver for the switched-capacitor power converter is shown. For example... Figure 4 The gate driver shown is Figure 3 Similar to the gate driver, except that it uses three voltage clamping circuits 402, 404 and 406 to reduce voltage stress.

[0105] Return to reference Figure 3 The devices in the level shifter, control logic unit, buffer, and transistor PM1 have a voltage stress equal to the input voltage bus VIN minus GND (system ground). Three voltage clamping circuits 402, 404, and 406 are used to smooth the turn-off process, thereby keeping the voltage stress on the devices in the driver within the safe operating area (SOA). Figure 4As shown, the first voltage clamping circuit 402 includes multiple diodes. The first voltage clamping circuit 402 and transistor PM4 are connected in series between node CFH and the body terminal of the third switch SW3.

[0106] The second voltage clamping circuit 404 includes multiple diodes. The second voltage clamping circuit 404 and transistor PM2 are connected in parallel between the input voltage bus VIN and node FNW. Transistor PM2 is added to isolate the driver's power supply voltage bus from the input voltage bus VIN. Figure 4 As shown, the power supply voltage bus of the driver is represented as FNW.

[0107] The third voltage clamping circuit 406 includes multiple diodes. The third voltage clamping circuit 406 and transistor PM5 are connected in series between the power supply voltage bus FNW and the control logic ground FGND.

[0108] The first voltage clamping circuit 402 and the third voltage clamping circuit 406 are activated by controlling transistors PM4 and PM5, respectively. When the gate driver is enabled (or turned on), transistors PM4 and PM5 are turned off to disengage the clamping circuits from normal operation. When the driver is disabled (or turned off), transistors PM4 and PM5 are turned on so that the rail-to-rail voltage across the driver (e.g., power supply voltage bus FNW - control logic ground FGND) does not exceed the trigger voltage of the third voltage clamping circuit 406. In the event that node CFH is shorted to the input voltage bus VIN due to any fault in the system, the drain-body voltage of the third switch SW3 will not exceed its safe operating region.

[0109] Figure 5 The embodiments of the present invention are shown as follows: Figure 4 The diagram shows two alternative implementation schemes for the voltage clamping circuit. For example... Figure 4 The voltage clamping circuit shown can be implemented in several ways, among which Figure 5 Two alternative implementation schemes are shown. The number of devices arranged in series in the clamping circuit can be varied based on a specific SOA value. For example, for example, in... Figure 4 The 5V device used in the gate driver shown may include a clamping circuit such as Figure 4-5 The diagram shows three diodes or MOS transistors connected in series. On the other hand, for a 1.8V device, the number of diodes or MOS transistors connected in series can be reduced to one or two.

[0110] like Figure 5 As shown, the voltage clamping circuit 502 includes three p-type transistors M1, M2, and M3 connected in series between the anode and cathode. Each of these three p-type transistors is configured as a diode. Specifically, as... Figure 5As shown, the gate of each transistor is directly connected to its drain. These three p-type transistors are equivalent to three diodes connected in series (e.g., as shown in Figure 1). Figure 4 The first voltage clamping circuit 402 shown.

[0111] The voltage clamping circuit 504 includes three n-type transistors M4, M5, and M6 connected in series between the anode and cathode. Each of these three n-type transistors is configured as a diode. Specifically, as Figure 5 As shown, the gate of each transistor is directly connected to its drain. These three n-type transistors are equivalent to three diodes connected in series (e.g., as shown in Figure 1). Figure 4 The first voltage clamping circuit 402 shown.

[0112] Figure 6 The embodiments of the present invention are shown as follows: Figure 4 The timing diagram of the gate driver is shown. Figure 6 The horizontal axis represents the time interval. There are 13 vertical axes. The first vertical axis represents the fault signal (FAULT). The second vertical axis represents the enable signal (EN_LV). The third vertical axis represents the gate drive signal (FET_ON_LV). The fourth vertical axis represents the on / off state of transistor NM1 (logic high indicates transistor NM1 is on). The fifth vertical axis represents the on / off state of transistor PM1 (logic high indicates transistor PM1 is on). The sixth vertical axis represents the on / off state of transistor NM2 (logic high indicates transistor NM2 is on). The seventh vertical axis represents the on / off state of transistor PM2 (logic high indicates transistor PM2 is on). The eighth vertical axis represents the on / off state of transistor NM3 (logic high indicates transistor NM3 is on). The ninth vertical axis represents the on / off state of transistor PM3 (logic high indicates transistor PM3 is on). The tenth vertical axis represents the on / off state of transistor NM4 (logic high indicates transistor NM4 is on). The eleventh vertical axis represents the on / off state of transistor PM4 (a logic high state indicates that transistor PM4 is on). The twelfth vertical axis represents the on / off state of transistor NM5 (a logic high state indicates that transistor NM5 is on). The thirteenth vertical axis represents the on / off state of transistor PM5 (a logic high state indicates that transistor PM5 is on).

[0113] exist Figure 6 In the code, for transistors NM1-NM5 and PM1-PM5, a logic high state indicates that the corresponding transistor is turned on. A logic low state indicates that the corresponding transistor is turned off. The rising edge of the fault signal indicates that a fault has occurred in the system.

[0114] At time t1, the rising edge of the enable signal EN_LV is applied to the gate driver. The logic high state of the enable signal indicates that the switched-capacitor power converter is ready to turn on. In response to the rising edge of the enable signal EN_LV, transistors NM2, PM2, and PM3 are turned on. (Return to Reference) Figure 4 After transistor NM2 is turned on, the output voltage bus VOUT is connected to the control logic ground FGND. After transistor PM2 is turned on, the gate driver's power supply voltage bus is connected to the input voltage bus VIN. After transistor PM3 is turned on, the body terminal of the third switch SW3 is connected to the source terminal of the third switch SW3. At this point, the switched capacitor power converter is ready to be turned on.

[0115] After a preset delay, at time t2, the rising edge of the gate drive signal FET_ON_LV is applied to the gate driver of the third switch SW3. The logic high state of the gate drive signal FET_ON_LV indicates that a high gate drive voltage is applied to the gate of the third switch SW3, and the third switch SW3 is turned on in response to this high gate drive voltage. Figure 6 As shown, in response to the rising edge of the gate drive signal FET_ON_LV, transistors NM2, PM2, and PM3 remain on, and transistor PM1 is turned on. After transistor PM1 is turned on, a high gate drive voltage is applied to the gate of the third switch SW3, thereby turning SW3 on accordingly.

[0116] At time t3, the falling edge of the gate drive signal FET_ON_LV is applied to the gate driver of the third switch SW3. The logic low state of the gate drive signal FET_ON_LV indicates that a low gate drive voltage is applied to the gate of the third switch SW3, and the third switch SW3 is turned off in response to this low gate drive voltage. Figure 6 As shown, in response to the falling edge of the gate drive signal FET_ON_LV, transistors NM2, PM2, and PM3 remain on, while transistor NM1 is turned on. After transistor NM1 is turned on, the gate of the third switch SW3 is shorted to the source of the third switch SW3, thereby turning off the third switch SW3 accordingly.

[0117] During the period from time t4 to time t5, the transistor's on / off state is similar to that during the period from time t2 to time t3, and will not be described again here. At time t6, a falling edge of the enable signal EN_LV is applied to the gate driver. The logic low state of the enable signal EN_LV indicates that the switched-capacitor power converter is ready to turn off. Figure 6As shown, in response to the falling edge of the enable signal EN_LV, transistors NM1, PM1, NM2, PM2 and PM3 are turned off, and transistors NM3, NM4, PM4, NM5 and PM5 are turned on.

[0118] After transistor NM2 is turned off, the control logic ground FGND is disconnected from the output voltage bus VOUT. After transistor PM3 is turned off, the body terminal of the third switch SW3 is disconnected from the source terminal of the third switch SW3. After transistor PM2 is turned off, the driver's power supply voltage bus is disconnected from the input voltage bus VIN.

[0119] After transistor NM5 is turned on, the gate of the third switch SW3 is pulled down to system ground. After transistor PM5 is turned on, the rail-to-rail voltage (power supply bus FNW - control logic ground FGND) across the driver is clamped to a voltage level lower than the trigger voltage of the third voltage clamping circuit 406. After transistor PM4 is turned on, the drain-body voltage of the third switch SW3 does not exceed the SOA of the third switch SW3. After transistor NM3 is turned on, the body terminal of the third switch SW3 is pulled down to system ground. After transistor NM4 is turned on, the control logic ground FGND is pulled down to system ground.

[0120] Figure 7 This diagram illustrates the timing of the gate driver after a fault is detected in a switched-capacitor power converter, according to an embodiment of the present invention. Figure 7 The horizontal axis represents the time interval. There are 13 vertical axes. The first vertical axis represents the fault signal (FAULT). The second vertical axis represents the enable signal (EN_LV). The third vertical axis represents the gate drive signal (FET_ON_LV). The fourth vertical axis represents the on / off state of transistor NM1. The fifth vertical axis represents the on / off state of transistor PM1. The sixth vertical axis represents the on / off state of transistor NM2. The seventh vertical axis represents the on / off state of transistor PM2. The eighth vertical axis represents the on / off state of transistor NM3. The ninth vertical axis represents the on / off state of transistor PM3. The tenth vertical axis represents the on / off state of transistor NM4. The eleventh vertical axis represents the on / off state of transistor PM4. The twelfth vertical axis represents the on / off state of transistor NM5. The thirteenth vertical axis represents the on / off state of transistor PM5. Figure 7 In the diagram, for transistors NM1-NM5 and PM1-PM5, a logic high state indicates that the corresponding transistor is turned on, and a logic low state indicates that the corresponding transistor is turned off.

[0121] like Figure 7 The timing diagram shown is similar to... Figure 6The timing diagrams shown are similar and will not be elaborated further here, as they are readily understood by those skilled in the art. However, it should be noted that, as Figure 7 The timing diagram shown is similar to... Figure 6 The difference in the timing diagram shown is that the driver enters a shutdown state after a fault is detected (rising edge of the fault signal) and before a disable signal is applied to the driver.

[0122] Although embodiments of the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations may be made herein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

[0123] Furthermore, it is not intended that the scope of this application be limited to specific embodiments of the processes, machines, manufactures, compositions of matter, methods, and steps described herein. Those skilled in the art will readily understand from the disclosure of this document that processes, machines, manufactures, compositions of matter, methods, or steps, whether currently existing or later developed, can be utilized to perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein. Therefore, it is intended that the appended claims encompass such processes, machines, manufactures, compositions of matter, methods, or steps within their scope.

Claims

1. A switched capacitor power converter, comprising: Multiple switches are connected in series between system ground and input voltage bus, wherein a high-voltage side switch located between the input voltage bus and the output terminal of the switched capacitor power converter, and adjacent to the output terminal, is configured as an isolating switch, including two back-to-back connected diodes and a body terminal, the body terminal being configured to have an adjustable voltage potential; A driver for driving the high-voltage side switch, the driver including a body terminal switch, the body terminal of the body terminal switch being connected to the body terminal of the high-voltage side switch.

2. The switched capacitor power converter according to claim 1, characterized in that, The plurality of switches includes a first switch, a second switch, and a third switch connected in sequence, wherein the third switch is the high-voltage side switch, the first switch and the second switch are located between the output terminal and the system ground, the common node of the second switch and the third switch is configured as the output terminal of the switched-capacitor power converter, and the third switch has a first terminal connected to the output terminal and a second terminal coupled to the input voltage bus; the switched-capacitor power converter further includes: A flying capacitor is connected between the common node of the first and second switches and the second terminal of the third switch.

3. The switched capacitor power converter according to claim 2, characterized in that, The plurality of switches also includes: Fourth switch; The first switch, the second switch, the third switch, and the fourth switch are connected in series in sequence, and the third switch and the fourth switch are located between the input voltage bus and the output terminal; The flying capacitor is connected between the common node of the first and second switches and the common node of the third and fourth switches.

4. The switched capacitor power converter according to any one of claims 1-3, characterized in that, The body terminal is configured to be connected to the system ground or to the source of the high-voltage side switch.

5. The switched capacitor power converter according to any one of claims 1-3, characterized in that, Of the two back-to-back connected diodes, the first diode is located between the body terminal and the source terminal of the high-voltage side switch, and the second diode is located between the body terminal and the drain terminal of the high-voltage side switch.

6. The switched capacitor power converter according to claim 5, characterized in that, The cathode of the first diode is connected to the source of the high-voltage side switch; The anode of the first diode is connected to the body terminal of the high-voltage side switch; The cathode of the second diode is connected to the drain of the high-voltage side switch; and The anode of the second diode is connected to the body terminal of the high-voltage side switch.

7. The switched capacitor power converter according to any one of claims 1-3, characterized in that, The switched capacitor power converter also includes a body control circuit, and the body terminal of the high-voltage side switch is connected to the body control circuit; The body control circuit is configured to pull the body terminal of the high-voltage side switch to ground when the switched capacitor power converter is in the off state; and / or, When the switched capacitor power converter is ready to be turned on, the body terminal of the high-voltage side switch is connected to the source terminal of the high-voltage side switch via a switch.

8. The switched capacitor power converter according to claim 1, characterized in that, The driver includes: A first gate driving transistor and a second gate driving transistor are connected in series. The common node of the first gate driving transistor and the second gate driving transistor is connected to the gate of the high-voltage side switch. The second gate driving transistor is the body terminal switch.

9. The switched capacitor power converter according to claim 1, characterized in that, The driver includes: A first auxiliary transistor connected between the body terminal and the source terminal of the high-voltage side switch; Wherein, the first auxiliary transistor is configured to connect the body terminal of the high-voltage side switch to the source terminal of the high-voltage side switch when the switched capacitor power converter is turned on, and / or, in response to receiving a disable signal or detecting a system fault, the first auxiliary transistor is turned off, disconnecting the connection between the body terminal of the high-voltage side switch and the source terminal of the high-voltage side switch.

10. The switched capacitor power converter according to claim 1, characterized in that, The driver includes: A second auxiliary transistor coupled between the gate of the high-voltage side switch and system ground; The second auxiliary transistor is configured to pull down the gate of the high-voltage side switch to system ground in response to the switched capacitor power converter receiving a disable signal or detecting a fault.

11. The switched capacitor power converter according to claim 1, characterized in that, The driver includes: A third auxiliary transistor coupled between the logic control ground and the system ground; and A fourth auxiliary transistor coupled between the source of the high-voltage side switch and the logic control ground; The third auxiliary transistor is configured to pull the logic control ground to the system ground in response to the switched capacitor power converter receiving a disable signal or detecting a fault; the fourth auxiliary transistor isolates the source of the high-voltage side switch from the logic control ground in response to the switched capacitor power converter receiving a disable signal or detecting a fault, and the source of the high-voltage side switch is connected to the output terminal.

12. The switched capacitor power converter according to claim 1, characterized in that, The driver includes: A fifth auxiliary transistor connected between the body terminal of the high-voltage side switch and the system ground; The fifth auxiliary transistor is configured to pull down the body terminal of the high-voltage side switch to system ground when the switched capacitor power converter receives a disable signal or detects a fault.

13. The switched capacitor power converter according to any one of claims 1-3, characterized in that, The high-voltage side switch is configured to provide isolation between the load coupled to the output and the input power supply coupled to the input voltage bus.

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