A digitally controlled variable gain amplifier

Abstract

The application discloses a variable gain amplifier based on digital control, which comprises a data selector, a VGA core circuit, a DC offset elimination circuit and a bias current generation module; the data selector is used for controlling the VGA core circuit to work alone or controlling the VGA core circuit and the DC offset elimination circuit to work together; the VGA core circuit comprises first to third differential amplifiers connected in sequence and is used for providing variable gain in a preset range; the DC offset elimination circuit samples an offset voltage of the VGA core circuit, processes the offset voltage and feeds back the processed offset voltage to the VGA core circuit, so as to adjust the substrate voltage of the input pair tube of the VGA core circuit; and the bias current generation module provides bias currents for the VGA core circuit and the DC offset elimination circuit. By adopting the embodiment of the application, the difficulty of circuit design is reduced through the cascade of differential amplifiers, meanwhile, the embodiment has a higher gain range and higher calibration accuracy.

Description

Technical Field

[0001] This invention relates to the field of variable gain amplifier technology, and more particularly to a variable gain amplifier based on digital control. Background Technology

[0002] When a wireless receiver receives a signal, factors such as changes in transmission distance and transmitter power can cause signal loss and noise interference during transmission, resulting in a wide range of signal strength variation. To reduce the adverse effects of signal strength variation and ensure stable output signal amplitude or variation within a specific range, an automatic gain control (AGA) circuit is needed to control the link gain to follow the changes in received signal strength. The VGA (Variable Gain Amplifier) ​​is a key module in the AGA circuit, and its performance directly affects the overall receiver's gain, bandwidth, noise, and transmission power range. VGAs are classified into two types based on their gain variation method: one type is controlled by a digital signal, with discrete gain variation; the other type is controlled by an analog signal, with continuous gain variation. In modern receivers, signal strength detection is generally performed in the digital domain. If an analog-controlled VGA were used, a digital-to-analog converter would be required, which would increase circuit power consumption and area. Therefore, digitally controlled VGAs are generally preferred. VGAs can also be classified into open-loop VGAs and closed-loop VGAs according to their circuit structure: Closed-loop VGAs are generally composed of an operational amplifier and a resistor feedback network, and the gain is changed by setting the resistance value of the feedback network to be variable; Open-loop VGA circuits are relatively simple. Common open-loop VGAs include cascode VGAs that operate in the linear region, VGAs based on variable load, and VGAs based on source negative feedback.

[0003] Traditional open-loop structures offer advantages such as simplicity, high gain, and large bandwidth, but suffer from less stable performance and lower linearity. Traditional closed-loop structures, on the other hand, offer stable performance and high linearity, but their design becomes more complex when high gain, large bandwidth, and low noise are required. Furthermore, in practical circuits, various defects caused by manufacturing processes make it difficult to achieve perfect matching between the input transistors of a VGA, resulting in input offset voltage. Even small input offset voltages, after amplification, can introduce offset errors at the output. Input offset voltages can be positive or negative, making it difficult to easily and accurately calibrate them in applications. Summary of the Invention

[0004] This invention provides a digitally controlled variable gain amplifier to solve the technical problems of complex design and difficulty in high-precision calibration when meeting the requirements of VGA high gain range and calibration input offset voltage.

[0005] To address the aforementioned technical problems, this invention provides a digitally controlled variable gain amplifier, comprising: a data selector, a VGA core circuit, a DC offset cancellation circuit, and a bias current generation module. The output of the data selector is connected to the first input of the VGA core circuit; the output of the VGA core circuit is connected to the input of the DC offset cancellation circuit; and the output of the DC offset cancellation circuit is connected to the second input of the VGA core circuit. The data selector is used to control the VGA core circuit to work alone, or to control the VGA core circuit and the DC offset cancellation circuit to work together. The VGA core circuit includes a first differential amplifier, a second differential amplifier, and a third differential amplifier, used to provide variable gain within a preset range; wherein, the first differential amplifier and the third differential amplifier both adopt an open-loop structure, and the second differential amplifier adopts a closed-loop structure; the first differential amplifier, the second differential amplifier, and the third differential amplifier are cascaded in sequence to form an open-loop structure; The DC offset cancellation circuit is used to sample the output offset voltage of the VGA core circuit, process the output offset voltage and feed it back to the VGA core circuit to adjust the substrate voltage of the input transistors of the VGA core circuit. The bias current generation module is used to provide bias current for the VGA core circuit and the DC offset elimination circuit.

[0006] In the VGA core circuit of this invention, the first, second, and third differential amplifiers are cascaded in an open-loop structure, thus eliminating the need to consider loop stability and compensation capacitors, reducing the complexity of circuit design. The second differential amplifier uses a closed-loop structure, which is beneficial for expanding bandwidth, while the first and third differential amplifiers use an open-loop structure, which is beneficial for improving gain. Furthermore, the cascaded open-loop structure only requires connecting a DC offset cancellation circuit to the output terminal of the last differential amplifier to eliminate the output offset voltage, improving accuracy while reducing the complexity of circuit design. The bias current generation module provides a stable bias current for other circuits or modules to improve circuit stability. The DC offset cancellation circuit, in conjunction with the data selector, adjusts the substrate voltage of the input pair transistors of the differential amplifiers in the VGA core circuit, thereby calibrating the input offset voltage with high precision.

[0007] Furthermore, the first differential amplifier, the second differential amplifier, and the third differential amplifier are cascaded in sequence in an open-loop structure, specifically as follows: The VGA core circuit's first input terminal includes a first sub-input terminal and a second sub-input terminal; the VGA core circuit's output terminal includes a first sub-output terminal and a second sub-output terminal; and the VGA core circuit's second input terminal includes a third sub-input terminal and a fourth sub-input terminal. The inverting input of the first differential amplifier is connected to the first sub-input terminal, the non-inverting input of the first differential amplifier is connected to the second sub-input terminal, the substrate of the transistor at the inverting input terminal of the first differential amplifier is connected to the third sub-input terminal, the substrate of the transistor at the non-inverting input terminal of the first differential amplifier is connected to the fourth sub-input terminal, the negative output terminal of the first differential amplifier is connected to the inverting input of the second differential amplifier, and the positive output terminal of the first differential amplifier is connected to the non-inverting input of the second differential amplifier. The negative output terminal of the second differential amplifier is connected to the inverting input of the third differential amplifier, and the positive output terminal of the second differential amplifier is connected to the non-inverting input of the third differential amplifier. The negative output terminal of the third differential amplifier is connected to the first sub-output terminal, and the positive output terminal of the third differential amplifier is connected to the second sub-output terminal.

[0008] The first, second, and third differential amplifiers of this invention are cascaded in an open-loop structure. On the one hand, this eliminates the need to consider loop stability and compensation capacitors, improving the stability of the circuit operation and simplifying the structure. On the other hand, the differential amplifiers adopt a combination of open-loop and closed-loop structures, which can provide different levels of gain by adjusting the resistance value of the circuit, and effectively eliminate gain ranges with large gain errors and severe distortion, thus having a larger variable gain range.

[0009] Furthermore, the first differential amplifier, the second differential amplifier, and the third differential amplifier all include several resistors, MOS switches, differential transconductance amplifiers, and inverters; wherein, the second differential amplifier further includes digital logic circuitry.

[0010] Furthermore, the first differential amplifier A1 is used to provide 0dB and 24dB gain; the second differential amplifier A0 is used to provide 0dB, 1dB, 2dB, 3dB, 4dB and 5dB gain; and the third differential amplifier A2 is used to provide 0dB, 6dB, 12dB and 18dB gain.

[0011] Based on the open-loop structure formed by the sequential cascading of the first differential amplifier, the second differential amplifier, and the third differential amplifier, and the gain provided by each differential amplifier, the VGA core circuit can provide a variable gain range of 0-47dB, thus having a large variable gain range.

[0012] Furthermore, the DC offset cancellation circuit includes: a comparator, a successive approximation register, a digital-to-analog converter, and a low-pass filter; The comparator, the successive approximation register, the digital-to-analog converter, and the low-pass filter are connected in sequence. The comparator is used to sample the output offset voltage of the VGA core circuit, convert the output offset voltage into a level signal and output it to the successive approximation register. The successive approximation register is used to output a digital control signal to the digital-to-analog converter according to the level signal; The digital-to-analog converter is used to output a first voltage signal to the low-pass filter according to the digital control signal; The low-pass filter is used to reduce the frequency of change of the first voltage signal and output the processed second voltage signal to the substrate of the input pair of the first differential amplifier.

[0013] This invention samples the output offset voltage using a comparator, then processes the output offset voltage into a first voltage signal using a successive approximation register and a digital-to-analog converter. Finally, the first voltage signal is processed by a low-pass filter to control its frequency change before being output to the substrate of the input pair transistors of a differential amplifier, thus achieving high-precision calibration of the input offset voltage. The low-pass filter reduces the voltage change frequency of the first voltage signal, preventing circuit oscillations caused by excessively high voltage change frequencies and improving circuit stability.

[0014] Furthermore, the comparator, the successive approximation register, the digital-to-analog converter, and the low-pass filter are connected sequentially, specifically as follows: The DC offset cancellation circuit includes a fifth sub-input terminal and a sixth sub-input terminal at its input terminals; and a third sub-output terminal and a fourth sub-output terminal at its output terminals. The inverting input of the comparator is connected to the fifth sub-input, the non-inverting input of the comparator is connected to the sixth sub-input, and the output of the comparator is connected to the successive approximation register. The output of the successive approximation register is connected to the input of the digital-to-analog converter; The output terminal of the digital-to-analog converter is connected to the input terminal of the low-pass filter, the first output terminal of the low-pass filter is connected to the third sub-output terminal, and the second output terminal of the low-pass filter is connected to the fourth sub-output terminal.

[0015] Furthermore, the step of outputting a digital control signal to the digital-to-analog converter based on the level signal specifically includes: Based on the level signal, the level value of the digital control signal is determined bit by bit. After a preset number of comparisons, a binary digital control signal is output to the digital-to-analog converter.

[0016] The successive approximation register of this invention is used for logic control and converts the sampled level signal to provide digital control signals for the subsequent conversion of the first voltage signal and the adjustment of the substrate voltage of the input pair transistors.

[0017] Further, the step of outputting a first voltage signal to the low-pass filter according to the digital control signal specifically includes: Based on the digital control signal, the digital control signal is converted into the first voltage signal by controlling the magnitude of the current flowing through the load resistor, and the first voltage signal is output to the low-pass filter.

[0018] The digital-to-analog converter of the present invention converts a digital control signal into a first voltage signal. After the rate of change of the first voltage signal is reduced by a low-pass filter, it is used to adjust the substrate voltage of the input pair of transistors of the first differential amplifier, thereby achieving high-precision calibration of the input offset voltage.

[0019] Furthermore, the successive approximation register includes several digital logic gate units.

[0020] Furthermore, the data selector is a two-to-one data selector. Attached Figure Description

[0021] Figure 1 A schematic diagram of the structure of an embodiment of a digitally controlled variable gain amplifier provided by the present invention; Figure 2 This is a schematic diagram of the structure of one embodiment of the first differential amplifier provided by the present invention; Figure 3 This is a schematic diagram of the structure of one embodiment of the second differential amplifier provided by the present invention; Figure 4 This is a schematic diagram of the structure of one embodiment of the digital-to-analog converter provided by the present invention; Figure 5 Amplitude-frequency curve of a digitally controlled variable gain amplifier provided for this invention; Figure 6 The noise curve of the digitally controlled variable gain amplifier provided for this invention; Figure 7 Transient curve of a digitally controlled variable gain amplifier provided for this invention; Figure 8 A graph showing the time-varying input voltage, output voltage, and substrate voltage of a digitally controlled variable gain amplifier provided by the present invention; Figure 9 Another graph showing the time-varying input voltage, output voltage, and substrate voltage of the digitally controlled variable gain amplifier provided for this invention; Detailed Implementation The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] Example 1 Please refer to Figure 1 This is a schematic diagram of an embodiment of a digitally controlled variable gain amplifier provided by the present invention, including: a data selector, a VGA core circuit, a DC offset cancellation circuit, and a bias current generation module.

[0023] The output of the data selector is connected to the first input of the VGA core circuit; the output of the VGA core circuit is connected to the input of the DC offset cancellation circuit; and the output of the DC offset cancellation circuit is connected to the second input of the VGA core circuit. The data selector is used to control the VGA core circuit to work alone, or to control the VGA core circuit and the DC offset cancellation circuit to work together. The VGA core circuit includes a first differential amplifier, a second differential amplifier, and a third differential amplifier, used to provide variable gain within a preset range; wherein, the first differential amplifier and the third differential amplifier both adopt an open-loop structure, and the second differential amplifier adopts a closed-loop structure; the first differential amplifier, the second differential amplifier, and the third differential amplifier are cascaded in sequence to form an open-loop structure; The DC offset cancellation circuit is used to sample the output offset voltage of the VGA core circuit, process the output offset voltage and feed it back to the VGA core circuit to adjust the substrate voltage of the input transistors of the VGA core circuit. The bias current generation module is used to provide bias current for the VGA core circuit and the DC offset elimination circuit.

[0024] In this embodiment, the data selector is a two-to-one data selector; wherein, MUX-I and MUX-II of the two-to-one data selector are respectively connected to the first input terminal of the VGA core circuit. When the VGA core circuit is controlled to work alone, the variable gain amplifier operates in amplification mode. When the VGA core circuit and the DC offset cancellation circuit are controlled to work together, the variable gain amplifier operates in calibration mode.

[0025] In this embodiment, the first differential amplifier and the third differential amplifier both adopt an open-loop structure, specifically an open-loop fully differential structure, in which the common-mode feedback circuit can provide a stable output common-mode voltage, which is beneficial to improving the gain; while the second differential amplifier adopts a closed-loop structure, specifically a parallel closed-loop negative feedback structure, which is beneficial to expanding the bandwidth.

[0026] Furthermore, the first differential amplifier, the second differential amplifier, and the third differential amplifier are cascaded in sequence in an open-loop structure, specifically as follows: The VGA core circuit's first input terminal includes a first sub-input terminal and a second sub-input terminal; the VGA core circuit's output terminal includes a first sub-output terminal and a second sub-output terminal; and the VGA core circuit's second input terminal includes a third sub-input terminal and a fourth sub-input terminal. The inverting input of the first differential amplifier is connected to the first sub-input terminal, the non-inverting input of the first differential amplifier is connected to the second sub-input terminal, the substrate of the transistor at the inverting input terminal of the first differential amplifier is connected to the third sub-input terminal, the substrate of the transistor at the non-inverting input terminal of the first differential amplifier is connected to the fourth sub-input terminal, the negative output terminal of the first differential amplifier is connected to the inverting input of the second differential amplifier, and the positive output terminal of the first differential amplifier is connected to the non-inverting input of the second differential amplifier. The negative output terminal of the second differential amplifier is connected to the inverting input of the third differential amplifier, and the positive output terminal of the second differential amplifier is connected to the non-inverting input of the third differential amplifier. The negative output terminal of the third differential amplifier is connected to the first sub-output terminal, and the positive output terminal of the third differential amplifier is connected to the second sub-output terminal.

[0027] In this embodiment, MUX-I in the 2-to-1 data selector is connected to the first sub-input terminal of the VGA core circuit, and MUX-II in the 2-to-1 data selector is connected to the second sub-input terminal of the VGA core circuit.

[0028] Please refer to Figure 2 and Figure 3The diagrams shown are schematic diagrams of an embodiment of the first differential amplifier and the second differential amplifier provided by the present invention. Each of the first, second, and third differential amplifiers includes several resistors, a MOS switch, a differential transconductance amplifier, and an inverter. The second differential amplifier further includes digital logic circuitry. The several resistors include, but are not limited to, adjustable resistors.

[0029] In this embodiment, the inverter of the first differential amplifier generates a control signal to control the MOS switch to turn on or off, thereby controlling the resistance value Radj in the circuit and enabling the differential amplifier to provide different levels of gain. The circuit adopts an open-loop fully differential connection, which is beneficial for providing high gain. The first and third differential amplifiers have similar structures and functions.

[0030] In this embodiment, the control signal generated by the digital logic circuit controls the MOS switch to open or close, thereby controlling the resistance value Radj in the access circuit. By controlling the resistance value Radj in the access circuit, a single-stage VGA can provide different levels of gain. The single-stage VGA does not need to provide continuously variable gain, and the gain range with large gain errors and severe distortion can be easily and effectively eliminated. The transconductance amplifier has a common-mode feedback circuit, which helps the second differential amplifier output a more accurate common-mode voltage.

[0031] Furthermore, the first differential amplifier is used to provide 0dB and 24dB gain; the second differential amplifier is used to provide 0dB, 1dB, 2dB, 3dB, 4dB and 5dB gain; and the third differential amplifier is used to provide 0dB, 6dB, 12dB and 18dB gain.

[0032] Please refer to Figure 5 The figure shows the amplitude-frequency curve of the digitally controlled variable gain amplifier provided by the present invention, wherein the gain of the VGA is 6dB and the unity-gain bandwidth of the VGA is 2.35MHz.

[0033] Please refer to Figure 6 The diagram shows the noise curve of the digitally controlled variable gain amplifier provided by this invention. The gain of the VGA is 6dB, and the noise level decreases as the frequency increases. The noise level at 1kHz is 26.2nV / sqrt(Hz).

[0034] Please refer to Figure 7 The transient curve of the digitally controlled variable gain amplifier provided by this invention is shown, wherein the gain of VGA is 6dB; further, the gain at this time is... With a gain error of 0.035 dB, the VGA exhibits high dB linearity.

[0035] Please refer to Figure 8 This invention provides a graph showing the time-varying input voltage, output voltage, and substrate voltage of a digitally controlled variable gain amplifier. The input voltage is divided into a VGA input voltage with a gain of 47dB and no offset, and an input voltage with an offset of -20mV. From 0-1.5ms, the VGA input is a DC voltage with a -20mV offset. Under the operation of the DC offset cancellation circuit, the absolute value of the differential output offset voltage continuously decreases until it is adjusted to -349μV. The substrate differential voltage of the input transistors in the VGA core circuit follows the differential output voltage, eventually reaching 251mV. From 1.5ms onwards, the VGA core circuit input is a sinusoidal signal, with a peak-to-peak value of 0.8mV for the offset differential input voltage and 177.6mV for the offset differential output voltage, while the substrate differential voltage remains constant. At this time, the gain is... The gain error is -0.07dB, and the calibrated input offset voltage is... .

[0036] Please refer to Figure 9 This invention provides another graph showing the time-varying input voltage, output voltage, and substrate voltage of a digitally controlled variable gain amplifier. The input voltage is divided into a zero-offset input voltage with a gain of 47dB for the VGA core circuit and an offset input voltage with +20mV. During the 0-1.5ms period, the input to the VGA core circuit is a DC voltage with a +20mV offset. Under the operation of the DC offset cancellation circuit, the absolute value of the differential output offset voltage continuously decreases until it is adjusted to -547μV. The substrate differential voltage of the input transistors in the VGA core circuit follows the differential output voltage change, eventually reaching -233mV. From 1.5ms onwards, the input to the VGA core circuit is a sinusoidal signal, with a peak-to-peak value of 0.8mV for the offset differential input voltage and 179.3mV for the offset differential output voltage, while the substrate differential voltage remains constant. At this time, the gain is... The gain error is +0.01dB, and the calibrated input offset voltage is... .

[0037] In this embodiment, the VGA main amplification unit achieves a variable gain range of 0-47dB, which is a larger variable gain range.

[0038] The first, second, and third differential amplifiers of this invention are cascaded in an open-loop structure. On the one hand, this eliminates the need to consider loop stability and compensation capacitors, improving the stability of the circuit operation and simplifying the structure. On the other hand, the differential amplifiers adopt a combination of open-loop and closed-loop structures, which can provide different levels of gain by adjusting the resistance value of the circuit, and effectively eliminate gain ranges with large gain errors and severe distortion, thus having a larger variable gain range.

[0039] Furthermore, the DC offset cancellation circuit includes: a comparator, a successive approximation register, a digital-to-analog converter, and a low-pass filter; The comparator, the successive approximation register, the digital-to-analog converter, and the low-pass filter are connected in sequence. The comparator is used to sample the output offset voltage of the VGA core circuit, convert the output offset voltage into a level signal and output it to the successive approximation register. The successive approximation register is used to output a digital control signal to the digital-to-analog converter according to the level signal; The digital-to-analog converter is used to output a first voltage signal to the low-pass filter according to the digital control signal; The low-pass filter is used to reduce the frequency of the change of the first voltage signal and output the processed second voltage signal to the substrate of the input pair of the first differential amplifier.

[0040] In this embodiment, the level signal includes a high level signal and a low level signal; the comparator converts the output offset voltage of the VGA core circuit, i.e., the DC offset voltage, into a 1V high level signal or a 0V low level signal.

[0041] Furthermore, the comparator, the successive approximation register, the digital-to-analog converter, and the low-pass filter are connected sequentially, specifically as follows: The DC offset cancellation circuit includes a fifth sub-input terminal and a sixth sub-input terminal at its input terminals; and a third sub-output terminal and a fourth sub-output terminal at its output terminals. The inverting input of the comparator is connected to the fifth sub-input, the non-inverting input of the comparator is connected to the sixth sub-input, and the output of the comparator is connected to the successive approximation register. The output of the successive approximation register is connected to the input of the digital-to-analog converter; The output terminal of the digital-to-analog converter is connected to the input terminal of the low-pass filter, the first output terminal of the low-pass filter is connected to the third sub-output terminal, and the second output terminal of the low-pass filter is connected to the fourth sub-output terminal.

[0042] In this embodiment, the digital-to-analog converter is a current-mode digital-to-analog converter; the low-pass filter is an RC low-pass filter.

[0043] Furthermore, the step of outputting a digital control signal to the digital-to-analog converter based on the level signal specifically includes: Based on the level signal, the level value of the digital control signal is determined bit by bit. After a preset number of comparisons, a binary digital control signal is output to the digital-to-analog converter.

[0044] In this embodiment, the initial value of the digital control signal can be a binary digital control signal, and the initial value can be 10b'1000000000; the preset number of times can be 9 times, and the output signal is determined bit by bit starting from the highest bit of the digital control signal.

[0045] The successive approximation register of this invention is used for logic control and converts the sampled level signal to provide digital control signals for the subsequent conversion of the first voltage signal and the adjustment of the substrate voltage of the input pair transistors.

[0046] Please refer to Figure 4 This is a schematic diagram of the structure of an embodiment of the digital-to-analog converter provided by the present invention, wherein the successive approximation register includes a plurality of digital logic gate units; the step of outputting a first voltage signal to the low-pass filter according to the digital control signal specifically includes: Based on the digital control signal, the digital control signal is converted into the first voltage signal by controlling the magnitude of the current flowing through the load resistor, and the first voltage signal is output to the low-pass filter.

[0047] In this embodiment, each bit in the digital control signal controls the current of a corresponding branch. When the digital control signal is low, the digital-to-analog converter controls the current to flow through the first load resistor and converts the digital control signal into a first analog voltage signal. When the digital control signal is high, the digital-to-analog converter controls the current to flow through the second load resistor and converts the digital control signal into a second analog voltage signal. The first voltage signal includes a first analog voltage signal and a second analog voltage signal.

[0048] The digital-to-analog converter of the present invention converts a digital control signal into a first voltage signal. After the rate of change of the first voltage signal is reduced by a low-pass filter, it is used to adjust the substrate voltage of the input pair of transistors of the first differential amplifier, thereby achieving high-precision calibration of the input offset voltage.

[0049] This invention samples the output offset voltage using a comparator, then processes the output offset voltage into a first voltage signal using a successive approximation register and a digital-to-analog converter. Finally, the first voltage signal is processed by a low-pass filter to control its frequency change before being output to the substrate of the input pair transistors of a differential amplifier, thus achieving high-precision calibration of the input offset voltage. The low-pass filter reduces the voltage change frequency of the first voltage signal, preventing circuit oscillations caused by excessively high voltage change frequencies and improving circuit stability.

[0050] Example 2 In this embodiment, the digitally controlled variable gain amplifier provided by the present invention is used. The process includes: calibrating the input offset voltage of the VGA, selecting the gain provided by the VGA, and performing small-signal amplification on the VGA. Specifically, calibrating the input offset voltage of the VGA includes: When the input control signal CAL is at a low level of 0V, both the 2-to-1 selector MUX-I and MUX-II select channel A, enabling the VGA to operate in calibration mode; at this time, the input of the VGA core circuit is a DC level V. CM The comparator samples and amplifies the output offset voltage of the VGA core circuit, and outputs a 1V high-level signal or a 0V low-level signal to the successive approximation register.

[0051] Furthermore, when the input reset signal NRST is a low-level signal of 0V, the digital control signal OUT<9:0> of the successive approximation register is reset to the initial value 10b'1000000000; when the input reset signal NRST is a high-level signal of 1V, the high or low level of the 10-bit digital signal output by the successive approximation register is determined bit by bit through 9 comparisons starting from the most significant bit, based on whether the comparator outputs a high-level signal or a low-level signal, and a determined 10-bit digital control signal OUT<9:0> is output to the current-mode digital-to-analog converter.

[0052] Furthermore, the current-mode digital-to-analog converter controls the flow through the first load resistor R based on the 10-bit digital control signal OUT<9:0> output from the successive approximation register. N Second load resistor R P The magnitude of the current is determined by each bit of the digital control signal OUT<9:0>, which controls one branch current. A 1V high-level signal controls the current flowing through the second load resistor R. P A low-level 0V signal controls the current to flow through the first load resistor R. N This converts the 10-bit digital signal into a first analog voltage signal VBN and a second analog voltage signal V. BP .

[0053] Furthermore, the analog voltage signal output by the current-mode digital-to-analog converter is passed through an RC low-pass filter to reduce V. BP and V BN The frequency is changed and then input to the substrate of the input pair of transistors in the first differential amplifier A1 to prevent circuit oscillation caused by excessively high voltage change frequency; wherein, the input pair is a PMOS input pair; wherein, the substrate bias voltage V of the PMOS input pair of transistors in the first differential amplifier A1 is... BP and V BN The change causes the threshold voltage V of the PMOS transistor to change. TH and gate-source voltage V GS Change, thereby changing the input offset voltage V IO This achieves the purpose of calibrating the input offset voltage.

[0054] In this embodiment, the gain provided by the VGA is selected, specifically including: A 6-bit digital signal S<5:0> is input to the VGA core circuit; the lower 3 bits S<2:0> of the digital signal S<5:0> control the second differential amplifier A0 to provide a gain of 0 / 1 / 2 / 3 / 4 / 5dB, and the highest bit S<5:0>... <5> The first differential amplifier A1 is controlled to provide a gain of 0 / 24dB, and the middle two bits of the digital control signal S<5:0>, S<4:3>, control the third differential amplifier A2 to provide a gain of 0 / 6 / 12 / 18dB.

[0055] Furthermore, the gain of differential amplifiers A0-A2 is determined based on the input digital signal S<5:0>, and the gain provided by differential amplifiers A0-A2 is added together to obtain the gain of VGA. VGA can provide a gain variation range of 0-47dB.

[0056] In this embodiment, the VGA performs small signal amplification, specifically including: When the input control signal CAL is 1V high, both the MUX-I and MUX-II multiplexers select channel B, enabling the VGA to operate in amplification mode. The input offset voltage has been calibrated by the DC offset cancellation circuit DCOC. At this time, the input of the VGA core circuit is a sine wave signal. The small signal is amplified accordingly based on the VGA gain determined by the digital signal S<5:0>, without needing to consider the influence of the input offset voltage.

[0057] In the VGA core circuit of this invention, the first, second, and third differential amplifiers are cascaded in an open-loop structure, thus eliminating the need to consider loop stability and compensation capacitors, reducing the complexity of circuit design. The second differential amplifier uses a closed-loop structure, which is beneficial for expanding bandwidth, while the first and third differential amplifiers use an open-loop structure, which is beneficial for improving gain. Furthermore, the cascaded open-loop structure only requires connecting a DC offset cancellation circuit to the output terminal of the last differential amplifier to eliminate the output offset voltage, improving accuracy while reducing the complexity of circuit design. The bias current generation module provides a stable bias current for other circuits or modules to improve circuit stability. The DC offset cancellation circuit, in conjunction with the data selector, adjusts the substrate voltage of the input pair transistors of the differential amplifiers in the VGA core circuit, thereby calibrating the input offset voltage with high precision.

[0058] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A variable gain amplifier based on digital control, characterized in that, include: Data selector, VGA core circuit, DC offset elimination circuit and bias current generation module; The output of the data selector is connected to the first input of the VGA core circuit; the output of the VGA core circuit is connected to the input of the DC offset cancellation circuit; and the output of the DC offset cancellation circuit is connected to the second input of the VGA core circuit. The data selector is used to control the VGA core circuit to work alone, or to control the VGA core circuit and the DC offset cancellation circuit to work together. The VGA core circuit includes: a first differential amplifier, a second differential amplifier, and a third differential amplifier, used to provide variable gain within a preset range; wherein, the first differential amplifier and the third differential amplifier both adopt an open-loop structure, and the second differential amplifier adopts a closed-loop structure; the first differential amplifier, the second differential amplifier, and the third differential amplifier are cascaded sequentially in an open-loop structure; the first differential amplifier, the second differential amplifier, and the third differential amplifier each include several resistors, MOS switches, differential transconductance amplifiers, and inverters; wherein, the second differential amplifier further includes: digital logic circuitry; In the first and third differential amplifiers, the input pairs of the differential transconductance amplifiers respectively receive the input signals; a variable resistor network composed of several resistors and MOS switches is connected in parallel in the signal path of the differential transconductance amplifier. In the second differential amplifier, the differential input terminal of the differential transconductance amplifier is used to receive the output signal from the previous stage, and the output terminal and input terminal of the differential transconductance amplifier form a parallel closed-loop negative feedback path through a variable resistor network composed of several resistors and MOS switches. Externally input digital control signals enter the digital logic circuit for decoding. The output of the digital logic circuit generates multiple control signals. These multiple control signals are then transmitted to the gate of the corresponding MOS switch after being generated by an inverter to produce complementary control voltages. This drives the MOS switch to open or close, thereby controlling the effective resistance value of the variable resistor network connected to the circuit and adjusting the gain. The DC offset cancellation circuit is used to sample the output offset voltage of the VGA core circuit, process the output offset voltage and feed it back to the VGA core circuit to adjust the substrate voltage of the input transistors of the VGA core circuit. The bias current generation module is used to provide bias current for the VGA core circuit and the DC offset elimination circuit.

2. The variable gain amplifier based on digital control as described in claim 1, characterized in that, The first differential amplifier, the second differential amplifier, and the third differential amplifier are cascaded in sequence to form an open-loop structure, specifically: The VGA core circuit's first input terminal includes a first sub-input terminal and a second sub-input terminal; the VGA core circuit's output terminal includes a first sub-output terminal and a second sub-output terminal; and the VGA core circuit's second input terminal includes a third sub-input terminal and a fourth sub-input terminal. The inverting input of the first differential amplifier is connected to the first sub-input terminal, the non-inverting input of the first differential amplifier is connected to the second sub-input terminal, the substrate of the transistor at the inverting input terminal of the first differential amplifier is connected to the third sub-input terminal, the substrate of the transistor at the non-inverting input terminal of the first differential amplifier is connected to the fourth sub-input terminal, the negative output terminal of the first differential amplifier is connected to the inverting input of the second differential amplifier, and the positive output terminal of the first differential amplifier is connected to the non-inverting input of the second differential amplifier. The negative output terminal of the second differential amplifier is connected to the inverting input of the third differential amplifier, and the positive output terminal of the second differential amplifier is connected to the non-inverting input of the third differential amplifier. The negative output terminal of the third differential amplifier is connected to the first sub-output terminal, and the positive output terminal of the third differential amplifier is connected to the second sub-output terminal.

3. The variable gain amplifier based on digital control as described in claim 1, characterized in that, The first differential amplifier is used to provide 0dB and 24dB gain; the second differential amplifier is used to provide 0dB, 1dB, 2dB, 3dB, 4dB and 5dB gain; and the third differential amplifier is used to provide 0dB, 6dB, 12dB and 18dB gain.

4. The variable gain amplifier based on digital control as described in claim 1, characterized in that, The DC offset cancellation circuit includes: a comparator, a successive approximation register, a digital-to-analog converter, and a low-pass filter; The comparator, the successive approximation register, the digital-to-analog converter, and the low-pass filter are connected in sequence. The comparator is used to sample the offset voltage of the VGA core circuit, convert the offset voltage into a level signal and output it to the successive approximation register; The successive approximation register is used to output a digital control signal to the digital-to-analog converter according to the level signal; The digital-to-analog converter is used to output a first voltage signal to the low-pass filter according to the digital control signal; The low-pass filter is used to reduce the frequency of the change of the first voltage signal and output the processed second voltage signal to the substrate of the input pair of the first differential amplifier.

5. The variable gain amplifier based on digital control as described in claim 4, characterized in that, The comparator, the successive approximation register, the digital-to-analog converter, and the low-pass filter are connected sequentially, specifically as follows: The DC offset cancellation circuit includes a fifth sub-input terminal and a sixth sub-input terminal at its input terminals; and a third sub-output terminal and a fourth sub-output terminal at its output terminals. The inverting input of the comparator is connected to the fifth sub-input, the non-inverting input of the comparator is connected to the sixth sub-input, and the output of the comparator is connected to the successive approximation register. The output of the successive approximation register is connected to the input of the digital-to-analog converter; The output terminal of the digital-to-analog converter is connected to the input terminal of the low-pass filter, the first output terminal of the low-pass filter is connected to the third sub-output terminal, and the second output terminal of the low-pass filter is connected to the fourth sub-output terminal.

6. The variable gain amplifier based on digital control as described in claim 4, characterized in that, The step of outputting a digital control signal to the digital-to-analog converter based on the level signal specifically involves: Based on the level signal, the level value of the digital control signal is determined bit by bit. After a preset number of comparisons, a binary digital control signal is output to the digital-to-analog converter.

7. The variable gain amplifier based on digital control as described in claim 4, characterized in that, The step of outputting a first voltage signal to the low-pass filter according to the digital control signal specifically involves: Based on the digital control signal, the digital control signal is converted into the first voltage signal by controlling the magnitude of the current flowing through the load resistor, and the first voltage signal is output to the low-pass filter.

8. The variable gain amplifier based on digital control as described in any one of claims 4-7, characterized in that, The successive approximation register includes several digital logic gate units.

9. The variable gain amplifier based on digital control as described in any one of claims 1-7, characterized in that, The data selector is a two-to-one data selector.

Images