An automatic gain adjustment circuit applied to a 25Gbps transimpedance amplifier

Abstract

The application discloses an automatic gain adjusting circuit applied to a 25Gbps transimpedance amplifier, which comprises a core amplifier Tia_core, a single-ended to differential amplifier S2D, an output buffer Buffer and an automatic gain adjusting circuit AGC; a direct current offset eliminating current inputted from outside is received by the input end of the core amplifier Tia_core and is converted into a single-ended voltage signal; the single-ended to differential amplifier S2D converts the single-ended voltage signal from the core amplifier Tia_core into a differential voltage; the output buffer Buffer receives the differential voltage from the single-ended to differential amplifier S2D, outputs a differential signal and guarantees impedance matching in the transmission process; the automatic gain adjusting circuit AGC comprises a peak value detecting circuit, an amplitude setting circuit and a gain adjusting control signal generating circuit, and realizes automatic gain control on the circuit. With the automatic gain adjusting circuit, the output signal of the link can be guaranteed not to be distorted when the input current signal becomes large, and the safety of the chip and the signal transmission quality are improved.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to an automatic gain adjustment circuit for a 25Gbps transimpedance amplifier. Background Technology

[0002] As users demand higher network download speeds, 5G communication places higher demands on the transport network, such as...

[0003] Capacity, long distance, high bandwidth, low latency, and massive connectivity are key characteristics of 5G network infrastructure. The 5G transport network architecture (fronthaul, midhaul, and backhaul) reveals that a large number of optical modules are needed between the RRU and DU to carry 5G fronthaul services. The large-scale deployment of macro base stations and small base stations will drive significant demand for optical modules. The core electrical chips in these modules include transimpedance amplifier (TIA) chips that convert the high-frequency current output from photodiodes into differential voltage, and transceiver chips that further process the TIA output signal. The typical bit rate for signal processing is 25Gbps. The TIA chip, located at the very front of the signal link, is particularly sensitive to the dynamic range of the input current. When the input current is at a small level (µA), the TIA link operates normally. However, as the input current increases to a certain value, if the overall link gain is not reduced, it will lead to TIA link signal distortion. Therefore, an automatic gain control circuit needs to be designed to increase the dynamic range of the input current, maintaining the output signal amplitude at a certain level. Summary of the Invention

[0004] To solve the above-mentioned technical problems, or at least partially solve them, this disclosure provides an automatic gain control circuit for a 25Gbps transimpedance amplifier, which ensures that the output signal of the link is not distorted when the input current signal increases, thereby improving the safety of the chip and the signal transmission quality.

[0005] The purpose of this invention is to provide an automatic gain control circuit for a 25Gbps transimpedance amplifier, which includes a core amplifier Tia_core, a single-ended to differential amplifier S2D, an output buffer, and an automatic gain control circuit AGC.

[0006] The Vb_vga voltage output terminal of the Automatic Gain Regulator (AGC) circuit is connected to the Vb_vga voltage input terminal of the core amplifier Tia_core, and the Vb_sig voltage output terminal of the AGC circuit is connected to the Vb_sig voltage input terminal of the core amplifier Tia_core. The input terminal of the core amplifier Tia_core constitutes the input terminal of a 25Gbps transimpedance amplifier. The core amplifier Tia_core, based on its connection with the AGC circuit, performs DC offset cancellation based on the input terminal.

[0007] The current is converted into a single-ended voltage signal. The automatic gain control (AGC) circuit is used to increase the dynamic range of the DC offset cancellation current received by the core amplifier Tia_core and maintain the amplitude of the DC offset cancellation current. The negative output terminal of the core amplifier Tia_core is connected to the negative input terminal of the single-ended to differential amplifier S2D, and the positive output terminal of the core amplifier Tia_core is connected to the positive input terminal of the single-ended to differential amplifier S2D. The single-ended to differential amplifier S2D converts the single-ended voltage signal from the core amplifier Tia_core into a differential voltage. The positive output terminal of the single-ended to differential amplifier S2D is connected to the output buffer. The positive input terminal of the single-ended to differential amplifier S2D is connected to the negative output terminal of the output buffer. The negative and positive output terminals of the output buffer are respectively connected to external power supplies and form the output terminals of a 25Gbps transimpedance amplifier. The output buffer receives the differential voltage from the single-ended to differential amplifier S2D and outputs a differential signal, ensuring impedance matching during transmission. The negative input terminal of the automatic gain control circuit AGC is connected to the negative output terminal of the single-ended to differential amplifier S2D, and the positive input terminal of the automatic gain control circuit AGC is connected to the positive output terminal of the single-ended to differential amplifier S2D.

[0008] The core amplifier Tia_core includes transistors Q1, Q2, Q3, Q5, and Q6, and resistors R0, R1, R2, R3, and R4. The base of transistor Q1 is connected to one end of resistor R0, forming the input terminal of the core amplifier Tia_core, used to receive current. The collector of transistor Q1 is connected to the emitter of transistor Q2 and one end of resistor R4. The emitter of transistor Q1 is connected to one end of resistor R1 and grounded. The other end of resistor R0, the other end of resistor R1, and the emitter of transistor Q3 are connected. The base of transistor Q3 and the collector of transistor Q2 are connected to the emitter of transistor Q6.

[0009] The electrodes and one end of resistor R3 are connected together. The other end of resistor R3 is connected to the other end of resistor R4, the collector of transistor Q6, and one end of resistor R2. The base of transistor Q6 forms the Vb_vga voltage input terminal. The other end of resistor R2 is connected to the collector of transistor Q5. The connection point forms the output terminal of the core amplifier Tia_core. The base of transistor Q5 forms the Vb_sig voltage input terminal. When the Vb_sig voltage value remains constant, the increase in the Vb_vga voltage value will cause the current allocated to transistor Q6 to increase, thereby causing the current allocated to transistor Q5 and resistor R2 to decrease, thus achieving the function of adjusting the link gain.

[0010] The automatic gain control (AGC) circuit includes a peak detection circuit, an amplitude setting circuit, and a gain adjustment control signal generation circuit. The voltage receiving terminal of the peak detection circuit, Voutp2, is connected to the positive terminal of the single-ended to differential amplifier S2D, and the voltage receiving terminal of the peak detection circuit, Voutn2, is connected to the negative terminal of the single-ended to differential amplifier S2D. The voltage input terminal of the amplitude setting circuit, Vpeak, is connected to the voltage output terminal of the peak detection circuit, the voltage input terminal of the amplitude setting circuit, Vmean, is connected to the voltage output terminal of the peak detection circuit, and the output terminal of the amplitude setting circuit is connected to the input terminal of the gain adjustment control signal generation circuit.

[0011] The peak detection circuit includes current source I0, current source I1, capacitor C1, resistors R5, R6, R7, R8, R9, transistors Q7, Q8, and Q9. The base of transistor Q7 forms the voltage receiver Voutn2 of the peak detection circuit, receiving the transient output voltage Voutn2 of the single-ended to differential amplifier S2D. The base of transistor Q8 forms the voltage receiver Voutp2 of the peak detection circuit, receiving the transient output voltage Voutp2 of the single-ended to differential amplifier S2D. Outp2, the emitter of transistor Q7 and the emitter of transistor Q8, the positive terminal of current source I0, and one end of capacitor C1 are connected. This connection point forms the Vpeak voltage output terminal of the peak detection circuit. Current source I0 provides bias current to transistors Q7 and Q8. When one end of voltage Voutp2 and voltage Voutn2 is high and the other end is low, the emitters of transistors Q7 and Q8 capture the signal peak value Vpeak. When voltage Voutp2 and voltage Voutn2 are at a low level... During the rising or falling period, capacitor C1 maintains a relatively constant peak value Vpeak. The negative terminal of the single-ended to differential amplifier S2D is connected to one end of resistor R7, and the positive terminal of the single-ended to differential amplifier S2D is connected to one end of resistor R8. The other end of resistor R7, the other end of resistor R8, and the base of transistor Q9 are connected together to obtain the average value of the transient output voltage Voutp2 and the transient output voltage Voutn2 of the single-ended to differential amplifier S2D, and input this average value to transistor Q9. 9; The collector of transistor Q7 is connected to one end of resistor R5, the collector of transistor Q8 is connected to one end of resistor R6, the other end of resistor R5 is connected to the other end of resistor R6 and one end of resistor R9, the other end of resistor R9 is connected to the collector of transistor Q9, the emitter of transistor Q9 is connected to the positive terminal of current source, outputting Vmean voltage, which constitutes the Vmean voltage output terminal of peak detection circuit, the negative terminal of current source I1 is connected to the other end of capacitor C2 and the negative terminal of current source I0 and grounded.

[0012] The amplitude setting circuit includes a resistor R5, a current source I2, and an operational amplifier OP1. One end of the resistor R5 forms the Vpeak voltage input terminal of the amplitude setting circuit, and the other end of the resistor R5 is connected to the positive terminal of the current source I2 and the positive feedback terminal of the operational amplifier OP1. The negative terminal of the current source I2 is grounded. The negative feedback terminal of the operational amplifier OP1 forms the amplitude setting circuit.

[0013] The Vmean voltage input terminal and the output terminal of the operational amplifier OP1 form the output terminal of the amplitude setting circuit, which is used to output the control voltage Vctr. When the difference between the voltage Vpeak and the voltage Vmean exceeds the preset value, the control voltage Vctr output by the operational amplifier OP1 increases, and the product of the resistor R5 and the current source I2 is set as the detection threshold of the automatic gain control loop.

[0014] The gain adjustment control signal generation circuit includes current source I3, current source I4, operational amplifier OP2, PMOS transistor M0, resistor R11, transistor Q10, and the positive terminal of current source I4 is connected to the positive terminal of current source I3, forming the input terminal of the gain adjustment control signal generation circuit. The negative terminal of current source I4 is connected to one end of resistor R11, the base and collector of transistor Q10, and the connection point of the base and collector of transistor Q10 forms the voltage output terminal Vb_vga. The connection point of the negative terminal of current source I3 and the base and collector of transistor Q10 forms the voltage output terminal Vb_sig. 3 provides bias for transistor Q10; current source I4 provides bias for the parallel network of transistor Q10 and resistor R11. The other end of resistor R11 is connected to the emitter of transistor Q10, the emitter of transistor Q11, the drain of PMOS transistor M0, and the negative feedback terminal of operational amplifier OP2, outputting voltage Vcm; the positive feedback terminal of operational amplifier OP2 outputs a holding value Vref; variable current source I4 is controlled by voltage Vctr. When Vctr increases, the current of current source I4 increases, and the current through resistor R11 increases; the voltage Vcm at the lower end of resistor R11 remains constant, so the voltage Vb_vga at the upper end will increase as the current through resistor R6 increases.

[0015] Compared with the prior art, the beneficial effect of the present invention is that it ensures that the output signal of the link does not become distorted when the input current signal increases, thereby improving the safety of the chip and the signal transmission quality.

[0016] The invention will become clearer from the following description, taken in conjunction with the accompanying drawings, which are used to explain the invention. Attached Figure Description

[0017] Figure 1 Here is the overall block diagram of a 25Gbps transimpedance amplifier;

[0018] Figure 2 The circuit diagram for the core amplifier Tia_core;

[0019] Figure 3 This is a circuit diagram for peak detection.

[0020] Figure 4 Circuit diagram for setting amplitude;

[0021] Figure 5 Circuit diagram for generating gain adjustment control signal;

[0022] Figure 6 The large signal output eye diagram without the automatic gain control circuit of this invention;

[0023] Figure 7 This is a transient graph of the gain adjustment control signal;

[0024] Figure 8 The large signal output eye diagram of this invention patent is adopted. Detailed Implementation

[0025] Embodiments of the present invention will now be described with reference to the accompanying drawings, in which similar element reference numerals represent similar elements. As described above, the present invention provides an automatic gain control circuit for a 25Gbps transimpedance amplifier, which ensures that the output signal of the link is not distorted when the input current signal increases, thereby improving the safety of the chip and the signal transmission quality.

[0026] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0027] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0028] Figure 1 Here is the overall block diagram of a 25Gbps transimpedance amplifier, as shown below. Figure 1As shown, the transimpedance amplifier includes a core amplifier Tia_core, a single-ended to differential amplifier S2D, an output buffer, and an automatic gain control (AGC) circuit. The Vb_vga voltage output terminal of the AGC circuit is connected to the Vb_vga voltage input terminal of the core amplifier Tia_core, and the Vb_sig voltage output terminal of the AGC circuit is connected to the Vb_sig voltage input terminal of the core amplifier Tia_core. The input terminal of the core amplifier Tia_core forms the input terminal of the 25Gbps transimpedance amplifier. Based on its connection with the AGC circuit, the core amplifier Tia_core converts the DC offset cancellation current received at its input terminal into a single-ended voltage signal. The AGC circuit is used to increase the dynamic range of the DC offset cancellation current received by the core amplifier Tia_core and maintain the amplitude of the DC offset cancellation current. The negative output terminal of the core amplifier Tia_core is connected to the single-ended to differential amplifier S2D. The negative input terminal of amplifier D is connected to the positive output terminal of the core amplifier Tia_core, which is connected to the positive input terminal of the single-ended to differential amplifier S2D. The single-ended to differential amplifier S2D converts the single-ended voltage signal from the core amplifier Tia_core into a differential voltage. The positive output terminal of the single-ended to differential amplifier S2D is connected to the positive input terminal of the output buffer, and the negative output terminal of the single-ended to differential amplifier S2D is connected to the negative input terminal of the output buffer. The negative and positive output terminals of the output buffer are respectively connected to external power supplies and form the output terminals of a 25Gbps transimpedance amplifier. The output buffer receives the differential voltage from the single-ended to differential amplifier S2D and outputs a differential signal, ensuring impedance matching during transmission. The negative input terminal of the automatic gain control circuit AGC is connected to the negative output terminal of the single-ended to differential amplifier S2D, and the positive input terminal of the automatic gain control circuit AGC is connected to the positive output terminal of the single-ended to differential amplifier S2D.

[0029] Figure 2This is the circuit diagram for the core amplifier Tia_core. The core amplifier Tia_core includes transistors Q1, Q2, Q3, Q5, and Q6, and resistors R0, R1, R2, R3, and R4. The base of transistor Q1 is connected to one end of resistor R0, forming the input terminal of the core amplifier Tia_core, used to receive current. The collector of transistor Q1 is connected to the emitter of transistor Q2 and one end of resistor R4. The emitter of transistor Q1 is connected to one end of resistor R1 and grounded. The other end of resistor R0, the other end of resistor R1, and the emitter of transistor Q3 are connected. The base of transistor Q3... The collector of transistor Q2 and one end of resistor R3 are connected together. The other end of resistor R3 is connected to the other end of resistor R4, the collector of transistor Q6, and one end of resistor R2. The base of transistor Q6 forms the Vb_vga voltage input terminal. The other end of resistor R2 is connected to the collector of transistor Q5. The connection point forms the output terminal of the core amplifier Tia_core. The base of transistor Q5 forms the Vb_sig voltage input terminal. When the Vb_sig voltage value remains constant, the increase in the Vb_vga voltage value will cause the current allocated to transistor Q6 to increase, thereby causing the current allocated to transistor Q5 and resistor R2 to decrease, thus achieving the function of adjusting the link gain.

[0030] The automatic gain control (AGC) circuit includes a peak detection circuit, an amplitude setting circuit, and a gain adjustment control signal generation circuit. The voltage Voutp2 receiving terminal of the peak detection circuit is connected to the positive terminal of the single-ended to differential amplifier S2D, and the voltage Voutn2 receiving terminal of the peak detection circuit is connected to the negative terminal of the single-ended to differential amplifier S2D. The Vpeak voltage input terminal of the amplitude setting circuit is connected to the Vpeak voltage output terminal of the peak detection circuit, the Vmean voltage input terminal of the amplitude setting circuit is connected to the Vmean voltage output terminal of the peak detection circuit, and the output terminal of the amplitude setting circuit is connected to the input terminal of the gain adjustment control signal generation circuit.

[0031] Figure 3This is a peak detection circuit diagram. The peak detection circuit includes current source I0, current source I1, capacitor C1, resistors R5, R6, R7, R8, and R9, and transistors Q7, Q8, and Q9. The base of transistor Q7 forms the voltage receiver Voutn2 of the peak detection circuit, receiving the transient output voltage Voutn2 of the single-ended to differential amplifier S2D. The base of transistor Q8 forms the voltage receiver Voutp2 of the peak detection circuit, receiving the transient output voltage Voutp2 of the single-ended to differential amplifier S2D. The output voltage Voutp2 is connected to the emitters of transistors Q7 and Q8, the positive terminal of current source I0, and one end of capacitor C1. This connection point forms the Vpeak voltage output terminal of the peak detection circuit. Current source I0 provides bias current to transistors Q7 and Q8. When one end of voltage Voutp2 and voltage Voutn2 is high and the other end is low, the emitters of transistors Q7 and Q8 capture the signal peak value Vpeak. When voltage Voutp2 and voltage Voutn2 are high and low respectively, the emitters of transistors Q7 and Q8 capture the signal peak value Vpeak. During the rising or falling period of n2, capacitor C1 maintains a relatively constant peak value Vpeak. The negative terminal of the single-ended to differential amplifier S2D is connected to one end of resistor R7, and the positive terminal of the single-ended to differential amplifier S2D is connected to one end of resistor R8. The other end of resistor R7, the other end of resistor R8, and the base of transistor Q9 are connected together to obtain the average value of the transient output voltage Voutp2 and the transient output voltage Voutn2 of the single-ended to differential amplifier S2D, and input this value to the transistor. Transistor Q9; The collector of transistor Q7 is connected to one end of resistor R5, the collector of transistor Q8 is connected to one end of resistor R6, the other end of resistor R5 is connected to the other end of resistor R6 and one end of resistor R9, the other end of resistor R9 is connected to the collector of transistor Q9, the emitter of transistor Q9 is connected to the positive terminal of current source, outputting Vmean voltage, which constitutes the Vmean voltage output terminal of peak detection circuit, the negative terminal of current source I1 is connected to the other end of capacitor C2 and the negative terminal of current source I0 and grounded.

[0032] Figure 4The amplitude setting circuit diagram includes a resistor R5, a current source I2, and an operational amplifier OP1. One end of the resistor R5 forms the Vpeak voltage input terminal of the amplitude setting circuit, and the other end of the resistor R5 is connected to the positive terminal of the current source I2 and the positive feedback terminal of the operational amplifier OP1. The negative terminal of the current source I2 is grounded. The negative feedback terminal of the operational amplifier OP1 forms the Vmean voltage input terminal of the amplitude setting circuit, and the output terminal of the operational amplifier OP1 forms the output terminal of the amplitude setting circuit, used to output the control voltage Vctr. When the difference between the voltage Vpeak and the voltage Vmean exceeds the preset value, the control voltage Vctr output by the operational amplifier OP1 increases, and the product of the resistor R5 and the current source I2 is set as the detection threshold of the automatic gain control loop.

[0033] Figure 5 This is a circuit diagram for generating the gain adjustment control signal. The gain adjustment control signal generation circuit includes current source I3, current source I4, operational amplifier OP2, PMOS transistor M0, resistor R11, transistor Q10, and the positive terminal of current source I4 is connected to the positive terminal of current source I3. This connection point forms the input terminal of the gain adjustment control signal generation circuit. The negative terminal of current source I4 is connected to one end of resistor R11, and the base and collector of transistor Q10. The connection point between the base and collector of transistor Q10 forms the voltage output terminal Vb_vga. The connection point between the negative terminal of current source I3 and the base and collector of transistor Q10 forms the voltage output terminal Vb_sig. At the terminal, current source I3 provides bias for transistor Q10; current source I4 provides bias for the parallel network of transistor Q10 and resistor R11. The other end of resistor R11 is connected to the emitter of transistor Q10, the emitter of transistor Q11, the drain of PMOS transistor M0, and the negative feedback terminal of operational amplifier OP2, outputting voltage Vcm; the positive feedback terminal of operational amplifier OP2 outputs a holding value Vref; variable current source I4 is controlled by voltage Vctr. When Vctr increases, the current of current source I4 increases, and the current through resistor R11 increases; the voltage Vcm at the lower end of resistor R11 remains constant, so the voltage Vb_vga at the upper end will increase as the current through resistor R6 increases.

[0034] Figure 6 This is the large-signal output eye diagram without the automatic gain control circuit of this invention. Figure 7 This is a transient graph of the gain adjustment control signal. Figure 8 The large-signal output eye diagram using the patented invention is a schematic diagram illustrating the improvement of the large-signal output using this patented invention, as shown below. Figure 6 and Figure 8 As shown. Figure 6When the input current amplitude reaches 600 uApp, the output signal of a 25Gbps transimpedance amplifier with a gain of 5KΩ or higher will be distorted if the gain is not adjusted. However, by employing the automatic gain adjustment circuit of this patented invention, the distortion is mitigated. Figure 7 We can see that Vb_vga gradually increases and eventually stabilizes, and the gain of the transimpedance amplifier link also decreases to a stable value.

[0035] Figure 8 The results show that the distortion of the output signal is optimized when the input is 600uApp after adopting the present invention, the eye diagram amplitude is 280mV, the jitter is 1.18ps, and the crossover point and eye diagram quality are good.

Claims

1. An automatic gain adjustment circuit for a 25Gbps transimpedance amplifier, characterized in that, This includes the core amplifier Tia_core, the single-ended to differential amplifier S2D, the output buffer, and the automatic gain control (AGC) circuit. The Vb_vga voltage output terminal of the automatic gain control (AGC) circuit is connected to the Vb_vga voltage input terminal of the core amplifier Tia_core. The Vb_sig voltage output terminal of the AGC circuit is connected to the Vb_sig voltage input terminal of the core amplifier Tia_core. The input terminal of the core amplifier Tia_core forms the input terminal of a 25Gbps transimpedance amplifier. Based on its connection with the AGC circuit, the core amplifier Tia_core converts the DC offset cancellation current received at its input terminal into a single-ended voltage signal. The AGC circuit is used to increase the dynamic range of the DC offset cancellation current received by the core amplifier Tia_core and maintain the amplitude of the DC offset cancellation current. The negative output terminal of the core amplifier Tia_core is connected to the negative input terminal of the single-ended to differential amplifier S2D, and the positive output terminal of the core amplifier Tia_core is connected to... The positive input terminal of the single-ended to differential amplifier S2D is connected to the core amplifier Tia_core, which converts the single-ended voltage signal into a differential voltage. The positive output terminal of the single-ended to differential amplifier S2D is connected to the positive input terminal of the output buffer, and the negative output terminal of the single-ended to differential amplifier S2D is connected to the negative input terminal of the output buffer. The negative and positive output terminals of the output buffer are connected to external power supplies and form the output terminals of a 25Gbps transimpedance amplifier. The output buffer receives the differential voltage from the single-ended to differential amplifier S2D and outputs a differential signal, ensuring impedance matching during transmission. The negative input terminal of the automatic gain control (AGC) circuit is connected to the negative output terminal of the single-ended to differential amplifier S2D, and the positive input terminal of the AGC circuit is connected to the positive output terminal of the single-ended to differential amplifier S2D. The core amplifier Tia_core includes transistors Q1, Q2, Q3, Q5, and Q6, and resistors R0, R1, R2, R3, and R4. The base of transistor Q1 is connected to one end of resistor R0, forming the input terminal of the core amplifier Tia_core, used to receive current. The collector of transistor Q1 is connected to the emitter of transistor Q2 and one end of resistor R4. The emitter of transistor Q1 is connected to one end of resistor R1 and grounded. The other end of resistor R0, the other end of resistor R1, and the emitter of transistor Q3 are connected. The base of transistor Q3 and the collector of transistor Q2 are connected to the emitter of transistor Q6. The electrodes and one end of resistor R3 are connected together. The other end of resistor R3 is connected to the other end of resistor R4, the collector of transistor Q6, and one end of resistor R2. The base of transistor Q6 forms the Vb_vga voltage input terminal. The other end of resistor R2 is connected to the collector of transistor Q5. The connection point forms the output terminal of the core amplifier Tia_core. The base of transistor Q5 forms the Vb_sig voltage input terminal. When the Vb_sig voltage value remains constant, the increase in the Vb_vga voltage value will cause the current allocated to transistor Q6 to increase, thereby causing the current allocated to transistor Q5 and resistor R2 to decrease, thus achieving the function of adjusting the link gain.

2. The automatic gain adjustment circuit for a 25Gbps transimpedance amplifier as described in claim 1, characterized in that, The automatic gain control (AGC) circuit includes a peak detection circuit, an amplitude setting circuit, and a gain adjustment control signal generation circuit. The voltage Voutp2 receiving terminal of the peak detection circuit is connected to the positive terminal of the single-ended to differential amplifier S2D, and the voltage Voutn2 receiving terminal of the peak detection circuit is connected to the negative terminal of the single-ended to differential amplifier S2D. The Vpeak voltage input terminal of the amplitude setting circuit is connected to the Vpeak voltage output terminal of the peak detection circuit, the Vmean voltage input terminal of the amplitude setting circuit is connected to the Vmean voltage output terminal of the peak detection circuit, and the output terminal of the amplitude setting circuit is connected to the input terminal of the gain adjustment control signal generation circuit.

3. The automatic gain adjustment circuit for a 25Gbps transimpedance amplifier as described in claim 2, characterized in that, The peak detection circuit includes current source I0, current source I1, capacitor C1, resistors R5, R6, R7, R8, and R9, and transistors Q7, Q8, and Q9. The base of transistor Q7 forms the voltage receiver Voutn2 of the peak detection circuit, receiving the transient output voltage Voutn2 of the single-ended to differential amplifier S2D. The base of transistor Q8 forms the voltage receiver Voutp2 of the peak detection circuit, receiving the transient output voltage Voutp2 of the single-ended to differential amplifier S2D. tp2, the emitter of transistor Q7 and the emitter of transistor Q8, the positive terminal of current source I0, and one end of capacitor C1 are connected. The connection point forms the Vpeak voltage output terminal of the peak detection circuit. Current source I0 is used to provide bias current for transistors Q7 and Q8. When one end of voltage Voutp2 and voltage Voutn2 is at a high level and the other end is at a low level, the emitters of transistors Q7 and Q8 obtain the signal peak value Vpeak. When voltage Voutp2 and voltage Voutn2 are at a low level, the emitters of transistors Q7 and Q8 obtain the signal peak value Vpeak. During the rising or falling period, capacitor C1 maintains a relatively constant peak value Vpeak. The negative terminal of the single-ended to differential amplifier S2D is connected to one end of resistor R7, and the positive terminal of the single-ended to differential amplifier S2D is connected to one end of resistor R8. The other end of resistor R7, the other end of resistor R8, and the base of transistor Q9 are connected together to obtain the average value of the transient output voltage Voutp2 and the transient output voltage Voutn2 of the single-ended to differential amplifier S2D, and input this value to transistor Q9. 9; The collector of transistor Q7 is connected to one end of resistor R5, the collector of transistor Q8 is connected to one end of resistor R6, the other end of resistor R5 is connected to the other end of resistor R6 and one end of resistor R9, the other end of resistor R9 is connected to the collector of transistor Q9, the emitter of transistor Q9 is connected to the positive terminal of current source, outputting Vmean voltage, which constitutes the Vmean voltage output terminal of peak detection circuit, the negative terminal of current source I1 is connected to the other end of capacitor C2 and the negative terminal of current source I0 and grounded.

4. The automatic gain adjustment circuit for a 25Gbps transimpedance amplifier as described in claim 3, characterized in that, The amplitude setting circuit includes a resistor R5, a current source I2, and an operational amplifier OP1. One end of the resistor R5 forms the Vpeak voltage input terminal of the amplitude setting circuit, and the other end of the resistor R5 is connected to the positive terminal of the current source I2 and the positive feedback terminal of the operational amplifier OP1. The negative terminal of the current source I2 is grounded. The negative feedback terminal of the operational amplifier OP1 forms the Vmean voltage input terminal of the amplitude setting circuit, and the output terminal of the operational amplifier OP1 forms the output terminal of the amplitude setting circuit, which is used to output the control voltage Vctr. When the difference between the voltage Vpeak and the voltage Vmean exceeds the preset value, the control voltage Vctr output by the operational amplifier OP1 increases, and the product of the resistor R5 and the current source I2 is set as the detection threshold of the automatic gain control loop.

5. The automatic gain adjustment circuit for a 25Gbps transimpedance amplifier as described in claim 4, characterized in that, The gain adjustment control signal generation circuit includes current source I3, current source I4, operational amplifier OP2, PMOS transistor M0, resistor R11, transistor Q10, and the positive terminal of current source I4 is connected to the positive terminal of current source I3, forming the input terminal of the gain adjustment control signal generation circuit. The negative terminal of current source I4 is connected to one end of resistor R11, and the base and collector of transistor Q10, forming the voltage output terminal Vb_vga. The negative terminal of current source I3 is connected to the base and collector of transistor Q10, forming the voltage output terminal Vb_sig. The current source I4 provides bias for transistor Q10; the current source I4 provides bias for the parallel network of transistor Q10 and resistor R11. The other end of resistor R11 is connected to the emitter of transistor Q10, the emitter of transistor Q11, the drain of PMOS transistor M0, and the negative feedback terminal of operational amplifier OP2, outputting voltage Vcm; the positive feedback terminal of operational amplifier OP2 outputs a holding value Vref; the variable current source I4 is controlled by voltage Vctr. When Vctr increases, the current of current source I4 increases, and the current through resistor R11 increases; the voltage Vcm at the lower end of resistor R11 remains constant, so the voltage Vb_vga at the upper end will increase as the current through resistor R6 increases.

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