Voltage-controlled ring oscillator

Abstract

This invention provides a voltage-controlled ring oscillator (VCO), comprising a linear voltage-to-current conversion circuit, a wide-range bias voltage generation circuit, a ring oscillation circuit, and an output circuit. The linear voltage-to-current conversion circuit converts the input control voltage into current, the wide-range bias voltage generation circuit converts the current into a bias voltage for a current source transistor, the bias voltage controls the current source in the ring oscillation circuit, and the output circuit amplifies the signal for output. Source negative feedback resistors are added to the current source transistors in both the wide-range bias voltage generation circuit and the ring oscillation circuit. The linear voltage-to-current conversion circuit and the wide-range bias voltage generation circuit in this invention support a large control voltage range, increasing the linear range of the VCO. Simultaneously, the source negative feedback resistors of the current source transistors improve the matching degree between current sources and reduce the phase noise of the oscillator.

Description

Technical Field

[0001] This invention relates to the field of clock sources, and in particular to a voltage-controlled ring oscillator circuit. Background Technology

[0002] Voltage-controlled ring oscillators (VCOs) are widely used in phase-locked loops (PLLs) due to their advantages of small size, large oscillation amplitude, and wide frequency range. However, VCOs currently face two main drawbacks: first, the control voltage range is not wide enough, and ring oscillators are inherently sensitive to process and temperature variations. If the output frequency range corresponding to the control voltage cannot cover these variations, the PLL will lose lock. Second, ring oscillators have relatively high phase noise, limiting their application. For example, ring oscillators are rarely used to provide the local oscillator signal in communication systems where high phase noise is required. Summary of the Invention

[0003] Purpose of the invention: In order to overcome at least one problem of the prior art, the present invention provides a voltage-controlled ring oscillator with a large control voltage range and low noise.

[0004] To achieve the above objectives, the present invention adopts the following technical solution:

[0005] A voltage-controlled ring oscillator includes a linear voltage-to-current conversion circuit, a wide-range bias voltage generation circuit, a ring oscillation circuit, and an output circuit. The linear voltage-to-current conversion circuit converts an input control voltage into a current; the wide-range bias voltage generation circuit includes a current source transistor for converting the current into a bias voltage for the current source transistor; the ring oscillation circuit includes a current source for controlling the current source with the bias voltage to generate an oscillation signal; and the output circuit amplifies the oscillation signal for output.

[0006] Furthermore, the linear voltage-to-current conversion circuit uses a zero-threshold NMOS transistor with a source negative feedback resistor to achieve voltage-to-current conversion, supporting rail-to-rail control voltage input. At the same time, the source negative feedback resistor uses a resistor with a positive temperature coefficient to improve temperature stability.

[0007] Furthermore, the current source transistor in the wide-range bias voltage generation circuit is a PMOS transistor, and its gate voltage is generated by an NMOS source follower, enabling the input node voltage range of the wide-range bias voltage generation circuit to achieve rail-to-rail control voltage input. A source negative feedback resistor is added to the current source transistor, improving the matching degree between current sources and reducing flicker noise in the output bias voltage.

[0008] Furthermore, the wide-range bias voltage generation circuit also includes a source negative feedback resistor, one end of which is connected to the power supply voltage and the other end is connected to the source of the current source transistor.

[0009] Furthermore, the ring oscillator circuit includes N amplification stages, where N is an odd number greater than or equal to 3. Each amplification stage includes a current source, an amplifying transistor, and a load transistor. The current source is connected to the drain of the amplifying transistor, the drain of the load transistor, and the gate of the load transistor. When the oscillation frequency changes, the load transistor can reduce the change in oscillation amplitude.

[0010] Furthermore, the current source in the ring oscillator circuit also includes a source negative feedback resistor. One end of the source negative feedback resistor is connected to the power supply voltage, and the other end is connected to the source of the current source transistor. The addition of the source negative feedback resistor improves the matching degree between the current sources and reduces the phase noise of the oscillator.

[0011] Further, the linear voltage-to-current conversion circuit includes a first resistor R1, a first NMOS transistor M1, and a second NMOS transistor M2. Both the first NMOS transistor M1 and the second NMOS transistor M2 are zero-threshold NMOS transistors, and the first resistor R1 is a positive temperature coefficient resistor. The control voltage of the voltage-controlled ring oscillator is connected to the gates of the first NMOS transistor M1 and the second NMOS transistor M2. The sources of the first NMOS transistor M1 and the second NMOS transistor M2 are connected together and simultaneously connected to one end of the first resistor R1, while the other end of the first resistor R1 is connected to ground. The drain voltage of the first NMOS transistor M1 is denoted as the first voltage VD1, and the drain voltage of the second NMOS transistor M2 is denoted as the second voltage VD2. Since both the first NMOS transistor M1 and the second NMOS transistor M2 are zero-threshold NMOS transistors, the linear range of the control voltage can be approximated as rail-to-rail, i.e., the minimum is close to zero, while the maximum is the power supply voltage. The first NMOS transistor M1 and the second NMOS transistor M2 have the same dimensions, so the current at the first voltage VD1 node and the current at the second voltage VD2 node are the same.

[0012] Further, the wide-range bias voltage generation circuit includes a third PMOS transistor M3, a sixth PMOS transistor M6, a seventh PMOS transistor M7, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fourth NMOS transistor M4, a fifth NMOS transistor M5, an eighth NMOS transistor M8, a ninth NMOS transistor M9, and a tenth NMOS transistor M10. The drain of the third PMOS transistor M3 is connected to a first voltage VD1, and its source is connected to one end of the third resistor R3, the other end of which is connected to the power supply voltage. The gate of the fourth NMOS transistor M4 is connected to the first voltage VD1, its drain is connected to the power supply voltage, and its source is connected to the drain of the fifth NMOS transistor M5, and simultaneously connected to the gate of the third PMOS transistor M3, which forms the first bias voltage VP1. The source of the fifth NMOS transistor M5 is grounded, and its gate is connected to the gate of the ninth NMOS transistor M9 and the tenth NMOS transistor M10. The gate of the tenth NMOS transistor M10, the drain of the tenth NMOS transistor M10, and one end of the second resistor R2 are connected to the power supply voltage; the source of the tenth NMOS transistor M10 is grounded; the drain of the seventh PMOS transistor M7 is connected to the second voltage VD2, the source of the seventh PMOS transistor M7 is connected to the drain of the sixth PMOS transistor M6, the source of the sixth PMOS transistor M6 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is connected to the power supply voltage; the gate of the eighth NMOS transistor M8 is connected to the second voltage VD2, the drain of the eighth NMOS transistor M8 is connected to the power supply voltage, and the source of the eighth NMOS transistor M8 is connected to the drain of the ninth NMOS transistor M9, the gate of the sixth PMOS transistor M6, and the gate of the seventh PMOS transistor M7, which is the second bias voltage VP2; the source of the ninth NMOS transistor M9 is grounded; the third resistor R3 and the fourth resistor R4 have the same resistance value, and the first bias voltages VP1 and VP2 are the two bias voltages of the common-source common-gate current source.

[0013] Furthermore, the current source of each amplification stage in the ring oscillator circuit is a common-source, common-gate current source, including the i-th source negative feedback resistor Roi, the i-th common-source PMOS transistor MEi, and the i-th common-gate PMOS transistor MGi. The amplification transistor includes the i-th inverting NMOS transistor MAi, and the load transistor includes the i-th load NMOS transistor MBi, where 1 ≤ i ≤ N. The i-th source negative feedback resistor Roi and the third resistor R3 have the same resistance value. The i-th common-source PMOS transistor MEi and the third PMOS transistor M3 have the same dimensions. The i-th common-gate PMOS transistor MGi and the seventh PMOS transistor M7 have the same dimensions. The i-th inverting NMOS transistor MAi and the i-th load NMOS transistor MBi of each stage have the same dimensions. The gate of the i-th common-source PMOS transistor MEi is connected to the first bias voltage VP1. The source is connected to one end of the i-th source negative feedback resistor Roi, and the other end of the i-th source negative feedback resistor Roi is connected to the power supply voltage; the gate of the i-th common-gate PMOS transistor MGi is connected to the second bias voltage VP2, the source is connected to the drain of the i-th common-source PMOS transistor MEi, and the drain is connected to the drain of the i-th reverse amplifying NMOS transistor MAi; the source of the i-th reverse amplifying NMOS transistor MAi is grounded; the gate of each reverse amplifying NMOS transistor starting from the second amplification stage is connected to the drain of the previous reverse amplifying NMOS transistor, and the gate of the first-stage reverse amplifying NMOS transistor is connected to the drain of the N-stage reverse amplifying NMOS transistor; the source of the i-th load NMOS transistor MBi is grounded, the gate is connected to its own drain, and then connected to the drain of the i-th common-gate PMOS transistor MGi.

[0014] Furthermore, the output circuit includes a twelfth NMOS transistor M12, an eleventh PMOS transistor M11, and a fifth resistor R5. The fifth resistor R5 has the same resistance value as the third resistor R3. The eleventh PMOS transistor M11 has the same dimensions as the third PMOS transistor M3. The twelfth NMOS transistor M12 has the same dimensions as the i-th inverting NMOS transistor MAi. The gate of the eleventh PMOS transistor M11 is connected to the first bias voltage VP1, and the source is connected to one end of the fifth resistor R5. The other end of the fifth resistor R5 is connected to the power supply voltage. The drain of the eleventh PMOS transistor M11 is connected to the drain of the twelfth NMOS transistor M12. The source of the twelfth NMOS transistor M12 is grounded, and the gate is connected to the drain of the N-th load NMOS transistor MBN.

[0015] Beneficial effects: The linear voltage-to-current conversion circuit and the wide-range bias voltage generation circuit in the voltage-controlled ring oscillator of the present invention support a large control voltage range, which increases the linear range of the voltage-controlled ring oscillator. The positive temperature coefficient resistor in the linear voltage-to-current conversion circuit improves the temperature stability of the oscillator. At the same time, the source negative feedback resistor of the current source tube improves the matching degree between current sources and reduces the phase noise of the oscillator. Attached Figure Description

[0016] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments, and the advantages of the present invention in the above and / or other aspects will become clearer.

[0017] Figure 1 This is a structural block diagram of the voltage-controlled ring oscillator of the present invention.

[0018] Figure 2 This is the circuit diagram of the voltage-controlled ring oscillator of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] This embodiment provides a voltage-controlled ring oscillator that can be applied to MCUs (Microcontroller Units).

[0021] like Figure 1 As shown, the present invention provides a voltage-controlled ring oscillator, including a linear voltage-to-current conversion circuit, a wide-range bias voltage generation circuit, a ring oscillation circuit, and an output circuit.

[0022] The linear voltage-to-current conversion circuit is used to convert the input control voltage into current;

[0023] The wide-range bias voltage generation circuit includes a current source transistor for converting current into a bias voltage for the current source transistor.

[0024] The ring oscillator circuit includes a current source for controlling the current source with a bias voltage to generate an oscillation signal;

[0025] The output circuit is used to amplify the oscillation signal and output it.

[0026] As a preferred option, such as Figure 2As shown, the linear voltage-to-current conversion circuit includes a first resistor R1, a first NMOS transistor M1, and a second NMOS transistor M2. Both the first NMOS transistor M1 and the second NMOS transistor M2 are zero-threshold NMOS transistors. The first resistor R1 is a positive temperature coefficient resistor, meaning its resistance increases with temperature; common N-type active region resistors and N-type Poly resistors in CMOS processes are examples of positive temperature coefficient resistors. The control voltage of the voltage-controlled ring oscillator is connected to the gates of the first NMOS transistor M1 and the second NMOS transistor M2. The sources of the first NMOS transistor M1 and the second NMOS transistor M2 are connected together and simultaneously connected to one end of the first resistor R1, while the other end of the first resistor R1 is connected to ground. The drain of the first NMOS transistor M1 is connected to a first voltage VD1, and the drain of the second NMOS transistor M2 is connected to a second voltage VD2. Since both the first NMOS transistor M1 and the second NMOS transistor M2 are zero-threshold NMOS transistors, the linear range of the control voltage can be approximated as rail-to-rail, meaning the minimum is close to zero, while the maximum is the power supply voltage. The first NMOS transistor M1 and the second NMOS transistor M2 have the same dimensions, so the current at the first voltage node VD1 and the current at the second voltage node VD2 are the same. The threshold voltages of the first NMOS transistor M1 and the second NMOS transistor M2 have negative temperature coefficients. The first resistor R1, which has a positive temperature coefficient, can reduce the temperature coefficient of the drain current of the first NMOS transistor M1 and the second NMOS transistor M2, thereby improving temperature stability.

[0027] In this embodiment, as Figure 2As shown, the wide-range bias voltage generation circuit includes a third PMOS transistor M3, a sixth PMOS transistor M6, a seventh PMOS transistor M7, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fourth NMOS transistor M4, a fifth NMOS transistor M5, an eighth NMOS transistor M8, a ninth NMOS transistor M9, and a tenth NMOS transistor M10. The drain of the third PMOS transistor M3 is connected to the first voltage VD1, and its source is connected to one end of the third resistor R3. The other end of the third resistor R3 is connected to the power supply voltage. The gate of the fourth NMOS transistor M4 is connected to the first voltage VD1, its drain is connected to the power supply voltage, and its source is connected to the drain of the fifth NMOS transistor M5, and simultaneously connected to the gate of the third PMOS transistor M3, which constitutes the first bias voltage VP1. The source of the fifth NMOS transistor M5 is grounded. The gate of the fifth NMOS transistor M5 is connected to the gate of the ninth NMOS transistor M9, the gate of the tenth NMOS transistor M10, the drain of the tenth NMOS transistor M10, and one end of the second resistor R2. The other end of the second resistor R2 is connected to the power supply voltage. The source of the tenth NMOS transistor M10 is grounded. The drain of the seventh PMOS transistor M7 is connected to the second voltage VD2. The source of the seventh PMOS transistor M7 is connected to the drain of the sixth PMOS transistor M6. The source of the sixth PMOS transistor M6 is connected to one end of the fourth resistor R4. The other end of the fourth resistor R4 is connected to the power supply voltage. The gate of the eighth NMOS transistor M8 is connected to the second voltage VD2. The drain of the eighth NMOS transistor M8 is connected to the power supply voltage. The source of the eighth NMOS transistor M8 is connected to the drain of the ninth NMOS transistor M9, the gate of the sixth PMOS transistor M6, and the gate of the seventh PMOS transistor M7, which constitutes the second bias voltage VP2. The source of the ninth NMOS transistor M9 is grounded. The third resistor R3 and the fourth resistor R4 have the same resistance value. The first bias voltages VP1 and VP2 are the two bias voltages of the common source cascode current source.

[0028] In this embodiment, the addition of the fourth NMOS transistor M4 and the eighth NMOS transistor M8 as source followers allows the first voltage VD1 and the second voltage VD2 to approach the power supply voltage at most. The gate-source voltage |VD1| of the fourth NMOS transistor M4... GS4 |Less than the gate-source voltage of the third PMOS transistor M3| V GS3 |, thus the drain-source voltage V of the third PMOS transistor M3 DS3 Can be maintained at |V GS3 |-|V GS4 |. Gate-source voltage of the eighth NMOS transistor M8 |V GS8 |Less than the gate-source voltage of the seventh PMOS transistor M7|V GS7 | Therefore, the drain-source voltage V of the seventh PMOS transistor M7 DS7 Can be maintained at |V GS7 |-|VGS8 The sixth PMOS transistor, M6, operates in the linear resistance region. The addition of source negative feedback resistors R3 and R4 improves the matching degree between current sources and reduces flicker noise in the first bias voltage VP1 and the second bias voltage VP2.

[0029] In this embodiment, the ring oscillator circuit includes N amplification stages. Each amplification stage includes a current source, an amplifying transistor, and a load transistor connected to a diode. The diode connection indicates that the gate and drain of the load transistor are connected together, defining the load that limits the oscillation amplitude. Figure 2 As shown, the current source includes source negative feedback resistors Ro1, Ro2, ..., RoN; PMOS transistors ME1, ME2, ..., MEN and MG1, MG2, ..., MGN; NMOS transistors MA1, MA2, ..., MAN; and NMOS transistors MB1, MB2, ..., MBN connected to diodes. The source negative feedback resistors Ro1, Ro2, ..., RoN have the same resistance values ​​as the third resistor R3 and the fourth resistor R4. The PMOS transistors ME1, ME2, ..., MEN have the same dimensions as the third PMOS transistor M3. The PMOS transistors MG1, MG2, ..., MGN have the same dimensions as the seventh PMOS transistor M7. The NMOS transistors MA1, MA2, ..., MAN have the same dimensions, as do MB1, MB2, ..., MBN. The gates of ME1, ME2, ..., MEN are all connected to the first bias voltage VP1, and their sources are connected to one end of the source negative feedback resistors Ro1, Ro2, ..., RoN, respectively. The other ends of the source negative feedback resistors Ro1, Ro2, ..., RoN are all connected to the power supply voltage. The gates of MG1, MG2, ..., MGN are all connected to the second bias voltage VP2, and their sources are connected to the drains of ME1, ME2, ..., MEN, respectively. Their drains are connected to the drains of MA1, MA2, ..., MAN, respectively. The sources of MA1, MA2, ..., MAN are all grounded. The gate of MA2 is connected to the drain of MA1, the gate of MA3 is connected to the drain of MA2, ..., the gate of MAN is connected to the drain of MAN-1, and the gate of MA1 is connected to the drain of MAN. The sources of MB1, MB2, ..., MBN are all grounded, and their gates are connected to their respective drains, which are then connected to the drains of MG1, MG2, ..., MGN, respectively.

[0030] The source negative feedback resistors Ro1, Ro2, ..., RoN, along with PMOS transistors ME1, ME2, ..., MEN and MG1, MG2, ..., MGN, form N common-source and common-gate current sources with source resistor negative feedback in an N-stage amplifier. PMOS transistors ME1, ME2, ..., MEN are common-source transistors, while PMOS transistors MG1, MG2, ..., MGN are common-gate transistors. The addition of the source negative feedback resistors Ro1, Ro2, ..., RoN improves the matching degree of the current sources and reduces their flicker noise, thereby reducing the phase noise of the oscillator. NMOS transistors MB1, MB2, ..., MBN are diode-connected load transistors. When the oscillation frequency changes, the load transistors reduce the change in oscillation amplitude, maintaining a relatively stable oscillation amplitude.

[0031] In this embodiment, the output circuit includes a twelfth NMOS transistor M12, an eleventh PMOS transistor M11, and a fifth resistor R5. The fifth resistor R5 has the same resistance value as the third resistor R3. The eleventh PMOS transistor M11 has the same dimensions as the third PMOS transistor M3, and the twelfth NMOS transistor M12 has the same dimensions as the i-th inverting NMOS transistor MAi. In the output circuit, the gate of the eleventh PMOS transistor M11 is connected to the first bias voltage VP1, and its source is connected to one end of the fifth resistor R5. The other end of the fifth resistor R5 is connected to the power supply voltage. The drain of the eleventh PMOS transistor M11 is connected to the drain of the twelfth NMOS transistor M12. The source of the twelfth NMOS transistor M12 is grounded, and its gate is connected to the drain of the N-th load NMOS transistor MBN. The twelfth NMOS transistor M12 acts as an amplifier. The load consists only of the common-source transistor eleventh PMOS transistor M11 and the fifth resistor R5; no common-gate transistor is added, which amplifies the oscillation waveform to full amplitude.

[0032] This invention provides a voltage-controlled ring oscillator. Many methods and approaches exist for implementing this technical solution; the above description is merely a specific embodiment of this invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of this invention, and these improvements and modifications should also be considered within the scope of protection of this invention. All components not explicitly stated in this embodiment can be implemented using existing technology.

Claims

1. A voltage-controlled ring oscillator, characterized in that, Includes a linear voltage-to-current conversion circuit, a wide-range bias voltage generation circuit, a ring oscillator circuit, and an output circuit: The linear voltage-to-current conversion circuit is used to convert the input control voltage into current; The wide-range bias voltage generation circuit includes a current source transistor for converting current into a bias voltage for the current source transistor. The ring oscillator circuit includes a current source for controlling the current source with a bias voltage to generate an oscillation signal; The output circuit is used to amplify the oscillation signal and output it. The linear voltage-to-current conversion circuit uses a zero-threshold NMOS transistor with a source negative feedback resistor to achieve voltage-to-current conversion, supports rail-to-rail control voltage input, and the source negative feedback resistor is a resistor with a positive temperature coefficient. The current source transistor in the wide-range bias voltage generation circuit is a PMOS transistor, and its gate voltage, which is the bias voltage, is generated by an NMOS source follower, so that the voltage range of the input node of the wide-range bias voltage generation circuit can realize rail-to-rail control voltage input. The wide-range bias voltage generation circuit also includes a source negative feedback resistor, one end of which is connected to the power supply voltage and the other end is connected to the source of the current source transistor. The linear voltage-to-current conversion circuit includes a first resistor R1, a first NMOS transistor M1, and a second NMOS transistor M2. Both the first NMOS transistor M1 and the second NMOS transistor M2 are zero-threshold NMOS transistors. The first resistor R1 is a positive temperature coefficient resistor. The control voltage of the voltage-controlled ring oscillator is connected to the gates of the first NMOS transistor M1 and the second NMOS transistor M2. The sources of the first NMOS transistor M1 and the second NMOS transistor M2 are connected together and simultaneously connected to one end of the first resistor R1. The other end of the first resistor R1 is connected to ground. The drain voltage of the first NMOS transistor M1 is denoted as the first voltage VD1, and the drain voltage of the second NMOS transistor M2 is denoted as the second voltage VD2. The first NMOS transistor M1 and the second NMOS transistor M2 have the same dimensions. The wide-range bias voltage generation circuit includes a third PMOS transistor M3, a sixth PMOS transistor M6, a seventh PMOS transistor M7, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fourth NMOS transistor M4, a fifth NMOS transistor M5, an eighth NMOS transistor M8, a ninth NMOS transistor M9, and a tenth NMOS transistor M10. The drain of the third PMOS transistor M3 is connected to a first voltage VD1, and its source is connected to one end of the third resistor R3, the other end of which is connected to the power supply voltage. The gate of the fourth NMOS transistor M4 is connected to the first voltage VD1, its drain is connected to the power supply voltage, and its source is connected to the drain of the fifth NMOS transistor M5, and simultaneously connected to the gate of the third PMOS transistor M3, forming the first bias voltage VP1. The source of the fifth NMOS transistor M5 is grounded, and its gate is connected to the ninth NMOS transistor M10. The gate of transistor M9, the gate of the tenth NMOS transistor M10, the drain of the tenth NMOS transistor M10, and one end of the second resistor R2 are connected to the power supply voltage; the source of the tenth NMOS transistor M10 is grounded; the drain of the seventh PMOS transistor M7 is connected to the second voltage VD2, the source of the seventh PMOS transistor M7 is connected to the drain of the sixth PMOS transistor M6, the source of the sixth PMOS transistor M6 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is connected to the power supply voltage; the gate of the eighth NMOS transistor M8 is connected to the second voltage VD2, the drain of the eighth NMOS transistor M8 is connected to the power supply voltage, and the source of the eighth NMOS transistor M8 is connected to the drain of the ninth NMOS transistor M9, the gate of the sixth PMOS transistor M6, and the gate of the seventh PMOS transistor M7, which constitutes the second bias voltage VP2; the source of the ninth NMOS transistor M9 is grounded; the resistance values ​​of the third resistor R3 and the fourth resistor R4 are the same.

2. The voltage-controlled ring oscillator according to claim 1, characterized in that, The ring oscillator circuit includes N amplification stages, where N is an odd number greater than or equal to 3. Each amplification stage includes a current source, an amplifying transistor, and a load transistor. The current source is connected to the drain of the amplifying transistor, the drain of the load transistor, and the gate of the load transistor. When the oscillation frequency changes, the load transistor can reduce the change in oscillation amplitude.

3. A voltage-controlled ring oscillator according to claim 2, characterized in that, The current source in the ring oscillator circuit also includes a source negative feedback resistor, one end of which is connected to the power supply voltage and the other end is connected to the source of the current source transistor.

4. A voltage-controlled ring oscillator according to claim 3, characterized in that, In the ring oscillator circuit, the current source of each amplification stage is a common-source, common-gate current source, including the first... i Source negative feedback resistor Ro i , No. i Common source PMOS transistor ME i and the i MG common gate PMOS transistor i The amplifier tube includes the first i Inverting NMOS transistor MA i The load tube includes the first i Load NMOS transistor MB i ,1≤ i ≤N; No. i Source negative feedback resistor Ro i The resistance value is the same as that of the third resistor R3. i Common source PMOS transistor ME i The third PMOS transistor M3 has the same dimensions. i MG common gate PMOS transistor i The seventh PMOS transistor M7 has the same dimensions, and the first stage of each stage... i Inverting NMOS transistor MA i Same size, each level's first i Load NMOS transistor MB i Same size; No. i Common source PMOS transistor ME i The gate is connected to the first bias voltage VP1, and the source is connected to the first bias voltage VP1. i Source negative feedback resistor Ro i One end, the first i Source negative feedback resistor Ro i The other end is connected to the power supply voltage; No. i MG common gate PMOS transistor i The gate is connected to the second bias voltage VP2, and the source is connected to the first bias voltage VP2. i Common source PMOS transistor ME i The drain, the drain is connected to the first i Inverting NMOS transistor MA i The drain; the first i Inverting NMOS transistor MA i The source of the NMOS transistor is grounded; starting from the second stage, the gate of each inverting NMOS transistor is connected to the drain of the previous stage, and the gate of the first stage inverting NMOS transistor is connected to the drain of the Nth stage inverting NMOS transistor; i Load NMOS transistor MB i The source is grounded, the gate is connected to its own drain, and then connected to the first... i MG common gate PMOS transistor i The drain electrode.

5. A voltage-controlled ring oscillator according to claim 4, characterized in that, The output circuit includes a twelfth NMOS transistor M12, an eleventh PMOS transistor M11, and a fifth resistor R5. The fifth resistor R5 has the same resistance value as the third resistor R3. The eleventh PMOS transistor M11 has the same dimensions as the third PMOS transistor M3. The twelfth NMOS transistor M12 has the same dimensions as the eleventh PMOS transistor M11. i Inverting NMOS transistor MA i They are of the same size; the gate of the eleventh PMOS transistor M11 is connected to the first bias voltage VP1, and the source is connected to one end of the fifth resistor R5, the other end of the fifth resistor R5 is connected to the power supply voltage; the drain of the eleventh PMOS transistor M11 is connected to the drain of the twelfth NMOS transistor M12; the source of the twelfth NMOS transistor M12 is grounded, and the gate is connected to the drain of the Nth load NMOS transistor MBN.

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