Semiconductor structure and its fabrication method
By forming a filling layer on the target substrate of the semiconductor structure and performing planarization, the device defect problem caused by the longitudinal dimension difference of the capacitor is solved, ensuring the fabrication quality of the capacitor hole.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-11-01
- Publication Date
- 2026-07-17
AI Technical Summary
In semiconductor manufacturing processes, the longitudinal dimensional differences caused by the miniaturization of capacitors affect the formation quality of capacitor holes and lead to device defects.
First and second pattern layers are formed on the target substrate, and a fill layer is formed thereon. The longitudinal dimensional difference is eliminated by planarization process to ensure the fabrication quality of the capacitor holes.
It effectively eliminates longitudinal dimensional differences in semiconductor structures, avoids device defects, and ensures the manufacturing quality of capacitor holes.
Smart Images
Figure CN115581067B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and a method for fabricating the same. Background Technology
[0002] Dynamic Random Access Memory (DRAM), a type of semiconductor memory with high density and fast read / write speeds, has been widely used in electronic devices. Each memory cell includes a capacitor and a transistor; the capacitor, used to store or write data, is an indispensable component of the memory.
[0003] As manufacturing processes evolve, DRAM integration density continues to increase, and component sizes are shrinking, leading to smaller capacitors and higher capacitor densities. This miniaturization amplifies longitudinal dimensional differences during capacitor fabrication, impacting subsequent processes and potentially causing device defects.
[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0005] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a semiconductor structure and its fabrication method, which eliminates the longitudinal dimensional difference generated during the fabrication of semiconductor devices and overcomes device manufacturing defects.
[0006] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.
[0007] According to one aspect of this disclosure, a method for fabricating a semiconductor structure is provided, the method comprising:
[0008] A target substrate is provided, the target substrate including an array region, a peripheral region, and a boundary region connecting the array region and the peripheral region;
[0009] A first pattern layer and a second pattern layer are sequentially formed on the target substrate, wherein the first pattern layer has a first etch pattern and the second pattern layer has a second etch pattern;
[0010] A fill layer is formed on the second pattern layer, and the side of the fill layer away from the target substrate is planarized so that the top surface of the fill layer on the array area, the peripheral area and the boundary area is flush.
[0011] A mask is formed on the filling layer, the mask covering the peripheral area and the boundary area;
[0012] The target substrate is etched according to the first etching pattern and the second etching pattern to form capacitor holes.
[0013] In some embodiments of this disclosure, based on the foregoing scheme, the planarization process on the side of the filling layer opposite to the target substrate includes:
[0014] The side of the filling layer facing away from the target substrate is etched back, so that the side of the filling layer facing away from the target substrate is parallel to the top surface of the target substrate.
[0015] In some embodiments of this disclosure, based on the foregoing scheme, the method for forming the first pattern layer on the target substrate includes:
[0016] A first dielectric layer is formed on the target substrate, and the first dielectric layer is etched to form a first intermediate trench;
[0017] A first covering layer is formed on the bottom and side walls of the first intermediate groove and on top of the first medium layer.
[0018] In some embodiments of this disclosure, based on the foregoing scheme, after forming the first overlay layer, the method further includes:
[0019] A portion of the first cover layer is removed to expose the first dielectric layer, wherein the removed portion of the first cover layer is the first cover layer parallel to the top surface of the target substrate.
[0020] In some embodiments of this disclosure, based on the foregoing scheme, after exposing the first dielectric layer, the method further includes:
[0021] Remove the first dielectric layer to form the first etched pattern within the first patterning layer;
[0022] The first pattern layer includes an array region having the first etched pattern, a peripheral region without the first etched pattern, and a boundary region connecting the array region and the peripheral region.
[0023] In some embodiments of this disclosure, based on the foregoing scheme, after forming the first etching pattern, the method further includes:
[0024] A first fill layer is formed on the first pattern layer, and the first fill layer is planarized to make the first fill layer on the array area, the peripheral area and the boundary area flush.
[0025] In some embodiments of this disclosure, based on the foregoing scheme, the method for forming the second pattern layer includes:
[0026] A second dielectric layer is formed on the first pattern layer, and the second dielectric layer is etched to form a second intermediate trench;
[0027] A second cover layer is formed on the bottom and side walls of the second intermediate groove and on top of the second medium layer.
[0028] In some embodiments of this disclosure, based on the foregoing scheme, after forming the second overlay layer, the method further includes:
[0029] A portion of the second cover layer is removed to expose the second dielectric layer, wherein the removed portion of the second cover layer is a second cover layer parallel to the top surface of the first pattern layer.
[0030] In some embodiments of this disclosure, based on the foregoing scheme, after exposing the second dielectric layer, the method further includes:
[0031] Remove the second dielectric layer to form the second etched pattern within the second patterned layer;
[0032] The second pattern layer includes an array region having the second etched pattern, a peripheral region without the second etched pattern, and a boundary region connecting the array region and the peripheral region.
[0033] In some embodiments of this disclosure, based on the foregoing scheme, the filling layer is a spin-coated hard mask or a spin-coated carbon hard mask.
[0034] In some embodiments of this disclosure, based on the foregoing scheme, before forming the first pattern layer on the target substrate, the method further includes:
[0035] A polycrystalline silicon layer and a silicon oxide layer are formed on the target substrate.
[0036] According to another aspect of this disclosure, a semiconductor structure is provided, which is fabricated using the semiconductor structure fabrication method described above.
[0037] This disclosure provides a method for fabricating a semiconductor structure. By forming a fill layer on a patterned layer and planarizing the fill layer, the formation of the fill layer can eliminate the longitudinal dimensional difference between the array region and the peripheral region during the semiconductor structure fabrication process, thus preventing the formation of etch holes in locations where they should not be formed, which could lead to process defects in the device. On the other hand, in the semiconductor fabrication process, residual impurities can cause insufficient development in subsequent processes, affecting the formation quality of capacitor holes. This disclosure eliminates residual impurities by forming a sacrificial layer during the fabrication process, ensuring that the capacitor holes are fully open and thus guaranteeing the manufacturing quality of the device.
[0038] On the other hand, this disclosure also provides a semiconductor structure that solves the device defect problem caused by longitudinal dimensional differences in the process by forming a filling layer during semiconductor fabrication, thereby ensuring the fabrication quality of capacitor holes.
[0039] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0040] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0041] Figure 1 This is a flowchart of a semiconductor structure manufacturing method according to an exemplary embodiment of the present disclosure.
[0042] Figures 2-16 This is a cross-sectional view of a semiconductor structure in a semiconductor fabrication step according to an exemplary embodiment of the present disclosure.
[0043] Figure 17 This is a top view of a capacitor hole in a semiconductor structure according to an exemplary embodiment of the present disclosure.
[0044] Figure 18 This is a top view of a capacitor aperture in another semiconductor structure according to an exemplary embodiment of the present disclosure.
[0045] The reference numerals in the attached figures are explained as follows:
[0046] 100: Target substrate; 210: Polysilicon layer; 220: Silicon oxide layer; 300: First pattern layer; 310: First dielectric layer; 311: First photoresist; 320: First capping layer; 330: First intermediate trench; 400: Second pattern layer; 410: Second dielectric layer; 411: Second photoresist; 420: Second capping layer; 430: Second intermediate trench; 510: First filling layer; 530: Filling layer; 700: Mask; 900: Capacitor via; H: Vertical height difference. Detailed Implementation
[0047] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.
[0048] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.
[0049] Memory can store data groups temporarily or permanently. Dynamic Random Access Memory (DRAM) typically includes multiple capacitors that store charge to register information. It is a data storage medium that can read and write data information at a relatively fast speed and has temporary storage properties.
[0050] Dynamic random access memory (DRAM) consists of many repeating memory cells. Each memory cell typically includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the transistor to turn on or off, thereby reading the data information stored in the capacitor through the bit line, or writing the data information into the capacitor for storage through the bit line.
[0051] As the DRAM market expands and manufacturing processes improve, the size of capacitors in memory devices is decreasing while their density is increasing. This leads to less space between different capacitors during fabrication, increasing the aspect ratio of components. Vertical dimensional deviations amplify defects in the lateral layout of components, potentially severely impacting subsequent processes and causing device defects. This is particularly true in patterning processes using Self-Aligned Double Patterning (SADP) or Self-Aligned Quadruple Patterning (SAQP), where height differences in the vertical direction can affect the quality of capacitor via formation in subsequent processes, even leading to device defects.
[0052] Therefore, in order to solve the device defect problem caused by the vertical height difference generated in the patterning part during semiconductor process, this disclosure provides a method for fabricating a semiconductor structure. This method can eliminate the above-mentioned vertical height difference and effectively solve the impact of the height difference on subsequent process.
[0053] The semiconductor structure described in this disclosure is not limited. The following detailed description will use dynamic random access memory (DRAM) as an example of semiconductor structure. However, the embodiments provided in this disclosure are not limited to this. Other semiconductor structures are also possible.
[0054] This disclosure provides a method for fabricating a semiconductor structure, such as... Figure 1 As shown, the method includes:
[0055] Step S1: Provide the target substrate, which includes the array area, the peripheral area, and the boundary area connecting the array area and the peripheral area.
[0056] Step S2: Sequentially form a first pattern layer and a second pattern layer on the target substrate. The first pattern layer has a first etch pattern, and the second pattern layer has a second etch pattern. Target substrate, first pattern layer, first pattern layer;
[0057] Step S3: Form a fill layer on the second pattern layer and planarize the side of the fill layer away from the target substrate so that the top surface of the fill layer on the array area, the peripheral area and the boundary area is flush with the target substrate of the first pattern layer.
[0058] Step S4: Form a mask on the filler layer, the mask covering the outer area and the boundary area;
[0059] Step S5: Etch the target substrate according to the first etching pattern and the second etching pattern to form capacitor holes.
[0060] The semiconductor structure fabrication method disclosed herein involves sequentially forming a first pattern layer and a second pattern layer on a target substrate, and forming a planarized filling layer on the second pattern layer. By forming the filling layer, structural fabrication defects caused by longitudinal dimensional differences generated in the junction area during the semiconductor structure formation process are eliminated, thereby ensuring the fabrication quality of capacitor holes.
[0061] The semiconductor structure disclosed herein includes an array region Z, a peripheral region W, and a boundary region J connecting the array region Z and the peripheral region W. The peripheral region W surrounds the array region Z, and a memory cell array is formed on the array region Z. The peripheral region W is used to mount logic control devices, etc.
[0062] The following is combined Figures 1 to 18 The method for fabricating the semiconductor structure provided in this disclosure is described in detail below:
[0063] In step S1, a target substrate 100 is provided, which includes an array region Z, a peripheral region W, and a boundary region J connecting the array region Z and the peripheral region W.
[0064] The target substrate 100 includes a substrate and a stack formed on the substrate. The stack is used to form capacitor holes 900. There can be multiple capacitor holes 900, and these multiple capacitor holes 900 are arranged in an array on the target substrate 100. For example, the multiple capacitor holes 900 can be spaced apart in the stack and arranged in a regular pattern. The multiple capacitor holes 900 can be formed separately or simultaneously using a patterning process. To simplify the process, it is preferred that the multiple capacitor holes 900 be formed simultaneously.
[0065] Within the target substrate 100, the substrate can be made of polycrystalline silicon. The stacked layers can include multiple support layers and multiple sacrificial layers, which can be sequentially stacked on the substrate. The support layers can be made of silicon nitride, and the sacrificial layers can be made of silicon oxide. The stacked layers can be formed by multiple depositions, for example, by chemical vapor deposition. This disclosure does not specifically limit the number of support layers and sacrificial layers in the target substrate 100, which can be selected according to the specific structure of the semiconductor. The target substrate 100 needs to have a structure for forming multiple capacitor holes 900.
[0066] In addition, a polysilicon layer 210 and a silicon oxide layer 220 are also included on the target substrate 100. Specifically, the polysilicon layer 210 and the silicon oxide layer 220 are formed on the target substrate 100 before the first pattern layer 300 is formed. For example, a structure in which a polysilicon layer 210, a silicon oxide layer 220 and a polysilicon layer 210 are stacked sequentially on the target substrate 100.
[0067] The silicon oxide layer 220 may be doped with boron and / or phosphorus. For example, the silicon oxide layer 220 may be made of phosphorus silicon glass (PSG) or boron phosphorus silicon glass (BPSG). The specific stacking order and number of layers of the polycrystalline silicon layer 210 and the silicon oxide layer 220 can be selected according to the actual process.
[0068] In step S2, a first pattern layer 300 and a second pattern layer 400 are sequentially formed on the target substrate 100. The first pattern layer 300 has a first etch pattern, and the second pattern layer 400 has a second etch pattern.
[0069] Reference Figures 2 to 7 The first pattern layer 300 includes a first dielectric layer 310 and a first cover layer 320. The formation of the first pattern layer 300 on the target substrate 100 includes: forming the first dielectric layer 310 on the target substrate 100; etching the first dielectric layer 310 to form a first intermediate trench 330; and forming the first cover layer 320 on the bottom wall and side wall of the first intermediate trench 330 and on the top of the first dielectric layer 310.
[0070] Etching the first dielectric layer 310 to form the first intermediate trench 330 includes: forming a first photoresist 311 on the first dielectric layer 310, using the first photoresist 311 as a mask to etch the first dielectric layer 310, and removing the first photoresist 311 to form a plurality of first intermediate trenches 330 on the first dielectric layer 310.
[0071] In this disclosure, the first dielectric layer 310 located in the array region Z is etched by the first photoresist 311 to form a plurality of first intermediate trenches 330 on the first dielectric layer 310. In addition, the first dielectric layer 310 on the peripheral region W can be retained or removed. In this embodiment, the structure of removing the first dielectric layer 310 on the peripheral region W is described. The following fabrication method is also applicable to semiconductor structures on which the first dielectric layer 310 is formed on the peripheral region W.
[0072] Forming a first etched pattern on the first pattern layer 300 includes: removing a portion of the first cover layer 320 to expose the first dielectric layer 310, wherein the removed portion of the first cover layer 320 is a second cover layer 320 parallel to the top surface of the target substrate 100, that is, removing the first cover layer 310 located on top of the first dielectric layer 310 and on top of the target substrate 100; removing the first dielectric layer 310 to form a first etched pattern within the first pattern layer 300.
[0073] The first patterning layer 300 includes an array region Z with a first etched pattern and a peripheral region W without a first etched pattern, as well as a boundary region J connecting the array region Z and the peripheral region W. The array region Z, the peripheral region W, and the boundary region J of the first patterning layer 300 correspond to the array region Z, the peripheral region W, and the boundary region J in a semiconductor structure. The first etched pattern can be a plurality of first intermediate trenches 330 formed along a direction perpendicular to the top surface of the target substrate 100. The number of first intermediate trenches 330 can be multiple, and they are arranged in an array on the first patterning layer 300. The first etched pattern is located within the array region Z and the boundary region J.
[0074] The first intermediate groove 330 formed on the first pattern layer 300 is located within the array region Z and the boundary region J. Therefore, when the first pattern layer 300 is subsequently processed, for example, when the second pattern layer 400 is formed on the first pattern layer 300, since the first etched pattern protrudes from the top surface of the target substrate 100 and no first etched pattern is provided in the peripheral region W, in order to provide a flat surface for the subsequent formation of the second pattern layer 400, a first filling layer 510 is first formed on the first pattern layer 300 and the first filling layer 510 is planarized so that the first filling layer 510 can provide a flat film surface for the formation of the second pattern layer 400.
[0075] Planarization of the first filler layer 510 includes etching back the side of the first filler layer 510 away from the target substrate 100, so that the side of the first filler layer 510 away from the target substrate 100 is parallel to the top surface of the target substrate 100. This method improves the flatness of the top surface of the first filler layer 510 and eliminates semiconductor fabrication defects caused by longitudinal dimensional differences in subsequent processes.
[0076] The first filling layer 510 can be etched back using either dry etching or wet etching.
[0077] It should be noted that after the first filling layer 510 is formed in the first pattern layer 300, the longitudinal dimension difference formed in the junction region J of the semiconductor structure is often small and its impact on subsequent processes is often negligible. In addition, this longitudinal dimension difference can be eliminated when the first filling layer 510 is planarized, so as to provide a flat film surface for the formation of the second pattern layer 400.
[0078] Specifically, a portion of the first cover layer 320 is removed to expose the first dielectric layer 310. The removed portion of the first cover layer 320 is the first cover layer 310 parallel to the top surface of the target substrate 100. The first dielectric layer 310 is removed to form a first etched pattern within the first pattern layer 300.
[0079] In order to ensure the smoothness of the first etched pattern within the first pattern layer 300 and the horizontality between multiple first etched patterns, an etch stop layer can be formed on the target substrate 100 before forming the first dielectric layer 310, so as to ensure that each etched hole or etched pattern is at the same horizontal position when etching the first dielectric layer 310 or the first cover layer 320.
[0080] The etching of the first pattern layer 300 can be performed using dry etching or photolithography with a high selectivity to form the first intermediate trench 330 etched into the first pattern layer 300, so that the first intermediate trench 330 has high precision.
[0081] In one embodiment of this disclosure, a portion of the first capping layer 320 is removed, including the first capping layer 310 located on top of the first dielectric layer 310 and on top of the target substrate 100, which is referred to herein simply as the top and bottom walls of the first capping layer 320. An etching method can be used to simultaneously etch and remove the top and bottom walls of the first capping layer 320 in the array region Z and the boundary region J. In another embodiment of this disclosure, only the top and bottom walls of the first capping layer 320 located within the array region Z can be etched and removed, retaining the top and bottom walls of the first capping layer 320 in the outer region W outside the boundary region J. Both of the above embodiments' methods for removing a portion of the first capping layer 320 are applicable to the semiconductor structure fabrication method provided in this disclosure.
[0082] The first filler layer 510 can be selected as a spin-coated hard mask (SOH) or a spin-coated carbon hard mask (SOC).
[0083] Reference Figures 8 to 12 A second pattern layer 400 is formed on the first filler layer 510, and the second pattern layer 400 has a second etched pattern.
[0084] The second pattern layer 400 includes a second dielectric layer 410 and a second cover layer 420. The second pattern layer 400 is formed on the first fill layer 510, including: forming the second dielectric layer 410 on the first pattern layer 300; etching the second dielectric layer 410 to form a second intermediate trench 430; and forming the second cover layer 420 on the bottom wall and side wall of the second intermediate trench 430 and on the top of the second dielectric layer 410.
[0085] Etching the second dielectric layer 410 to form the second intermediate trench 430 includes: forming a second photoresist 411 on the second dielectric layer 410, using the second photoresist 411 as a mask to etch the second dielectric layer 410, and removing the second photoresist 411 to form a plurality of second intermediate trenches 430 on the second dielectric layer 410.
[0086] In this disclosure, the second dielectric layer 410 located in the array region Z is etched by the second photoresist 411 to form a plurality of second intermediate trenches 430 on the second dielectric layer 410. In addition, the second dielectric layer 410 on the peripheral region W can be retained or removed. In this embodiment, the structure with the second dielectric layer 410 removed from the peripheral region W is described. The fabrication method described below is also applicable to semiconductor structures with the second dielectric layer 410 formed on the peripheral region W.
[0087] Forming a second etched pattern on the second patterning layer 400 includes: removing a portion of the second cover layer 420 to expose the second dielectric layer 410, wherein the removed portion of the second cover layer 420 is a second cover layer 420 parallel to the top surface of the first patterning layer 300, that is, removing the second cover layer 410 located on top of the second dielectric layer 410 and on top of the target substrate 100; removing the second dielectric layer 410 to form a second etched pattern within the second patterning layer 400.
[0088] The second patterning layer 400 includes an array region Z with a second etched pattern and a peripheral region W without a second etched pattern, as well as a boundary region J connecting the array region Z and the peripheral region W. The array region Z, peripheral region W, and boundary region J of the second patterning layer 400 correspond to the array region Z, peripheral region W, and boundary region J in a semiconductor structure. The second etched pattern can be a plurality of second intermediate trenches 430 formed along a direction perpendicular to the top surface of the target substrate 100. The number of second intermediate trenches 430 can be multiple, and they are arranged in an array on the second patterning layer 400. The second etched pattern is located within the array region Z and the boundary region J.
[0089] Specifically, a portion of the second cover layer 420 is removed to expose the second dielectric layer 410. The removed portion of the second cover layer 420 is the second cover layer 420 located on top of the second dielectric layer 410 and on top of the target substrate 100 (hereinafter referred to as the top wall and bottom wall of the second cover layer 420); the second dielectric layer 410 is removed to form a second etched pattern within the second pattern layer 400.
[0090] In order to ensure the smoothness of the second etching pattern within the second pattern layer 400 and the horizontality between multiple second etching patterns, an etching stop layer can be formed between the first pattern layer 300 and the second dielectric layer 410 before forming the second dielectric layer 410, so as to ensure that each etching hole or etching pattern is at the same horizontal position when etching the second dielectric layer 410 or the second cover layer 420.
[0091] In the above steps, an etching method can be used to simultaneously etch and remove the top and bottom walls of the first capping layer 420 in the array region Z and the boundary region J. In another embodiment of this disclosure, only the top and bottom walls of the second capping layer 420 in the array region Z can be etched and removed, while retaining the top and bottom walls of the second capping layer 420 in the boundary region J and the peripheral region W. The removal methods of the second capping layer 420 in both of the above embodiments are applicable to the semiconductor structure fabrication method provided in this disclosure.
[0092] After the above steps, the remaining second dielectric layer 410 located in the array region Z, the peripheral region W and the boundary region J are removed, or the remaining second dielectric layer 410 located in the array region Z is removed, exposing the sidewalls of the second cover layer 420 to form the second intermediate groove 430 in the second pattern layer 400.
[0093] The second pattern layer 400 can be etched using a high-selectivity dry etching or photolithography method to form a second intermediate trench 430 etched into the interior of the second pattern layer 400, so that the second intermediate trench 430 has high precision.
[0094] In steps S4 and S5, a fill layer 530 is formed on the second pattern layer 400, and the side of the fill layer 530 facing away from the target substrate 100 is planarized to make the top surfaces of the fill layer 530 on the array region Z, the peripheral region W, and the boundary region J flush. The target substrate 100 is etched according to the first etching pattern and the second etching pattern to form capacitor holes 900.
[0095] Reference Figures 11 to 15 As shown in the embodiments of this disclosure, the first etching pattern can be a plurality of first intermediate grooves 330, and the second etching pattern can be a plurality of second intermediate grooves 430. In the embodiments of this disclosure, the plurality of first intermediate grooves 330 can be arranged in parallel within the first pattern layer 300, and the plurality of second intermediate grooves 430 can be arranged in parallel within the second pattern layer 400. Furthermore, the first projection of the first intermediate grooves 330 on the target substrate 100 and the second projection of the second intermediate grooves 430 on the target substrate can be perpendicularly distributed or intersectingly distributed, such as... Figure 17 and Figure 18 As shown, the overlapping area of the first projection and the second projection forms a capacitor hole 900. In this disclosure, if the first projection and the second projection are perpendicularly distributed, the capacitor hole 900 is in the shape of a rectangular slot, such as... Figure 17 As shown in the diagram; if the first projection and the second projection are arranged in an intersecting pattern, then the capacitor aperture 900 will have a parallelogram shape, such as... Figure 18 As shown in the image.
[0096] The target substrate 100 is etched along the first intermediate trench 330 and the second intermediate trench 430 to form a capacitor hole 900. The entire semiconductor structure is fabricated by forming a flashlight tube within the capacitor hole 900. For example, a conductive material can be formed on the hole wall of the capacitor hole 900 by deposition or electroplating to form a capacitor tube.
[0097] Before etching the target substrate 100 according to the first etching pattern and the second etching pattern, the method further includes: forming a filling layer 530 on the second pattern layer 400, and planarizing the side of the filling layer 530 away from the target substrate 100 so that the top surfaces of the filling layer 530 on the array region Z, the peripheral region W and the boundary region J are flush; and forming a preset mask 700 on the filling layer 530, the preset mask covering the peripheral region W and the boundary region J.
[0098] like Figure 13 As shown, after the second intermediate trench 430 is formed, it protrudes from the peripheral region W. During the subsequent etching of the target substrate 100, a vertical height difference H will be generated in the boundary region J or the peripheral region W. During the exposure, development, and aperture opening processes, holes will be generated in the boundary region J or even the peripheral region W, affecting the quality of the subsequent capacitor holes 900. Therefore, before etching the target substrate 100, a filling layer 530 needs to be formed on the second pattern layer 400. The filling layer 530 covers the array region Z, the peripheral region W, and the boundary region J, and the side of the filling layer 530 facing away from the target substrate 100 is planarized, as shown in the figure. Figures 14 to 15 As shown, the filler layer 530 can be etched back to remove the portion with the vertical height difference H, so that the side of the filler layer 530 facing away from the target substrate 100 is parallel to the top surface of the target substrate 100. The filler layer 530 provides a flat film for subsequent processes, avoiding manufacturing defects in the device.
[0099] After planarizing the fill layer 530, a mask 700 is formed on the fill layer 530. The mask 700 covers the peripheral region W and the boundary region J. The target substrate 100 located in the array region Z is etched according to the first etching pattern and the second etching pattern using photolithography and other processes to form a capacitor hole 900 in the array region Z.
[0100] The material of the filler layer 530 can be the same as or different from the material of the first filler layer 510. The filler layer 530 can also be SOH or SOC.
[0101] It should be noted that the first filling layer 510 and the filling layer 530 located in the array region Z can be removed by etching or other processes during the formation of the capacitor hole 900, and will not affect the semiconductor manufacturing process.
[0102] In the embodiments of this disclosure, the first pattern layer 300 includes, but is not limited to, the first dielectric layer 310 and the first capping layer 320, and the second pattern layer 400 includes, but is not limited to, the second dielectric layer 410 and the second capping layer 420. The first pattern layer 300 and the second pattern layer 400 in this disclosure may also form other film layers according to the actual process of semiconductor structure formation. In addition, the semiconductor structure provided in this disclosure may include multiple pattern layers, and is not limited to the first pattern layer 300 and the second pattern layer 400, but the principle of forming other pattern layers is the same as that of the first pattern layer 300, and is not listed one by one in this disclosure.
[0103] The semiconductor structure fabrication method disclosed herein forms a filling layer on the patterned layer and performs planarization treatment on the filling layer. The formation of the filling layer can eliminate the longitudinal dimensional difference between the array region Z and the peripheral region W in the semiconductor structure process, and avoid the formation of etching holes in places where etching holes should not be formed, which would cause process defects in the device, thereby ensuring the manufacturing quality of the device.
[0104] It should be noted that although the steps of the semiconductor structure fabrication method of this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.
[0105] This disclosure also provides a semiconductor structure, which is fabricated using the semiconductor structure fabrication method described above. The semiconductor structure formed by the above method has uniform depth of capacitor holes and avoids the formation of unnecessary openings outside the semiconductor array region Z, which would lead to semiconductor fabrication defects and improve the fabrication quality of the semiconductor structure.
[0106] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.
[0107] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, include: A target substrate is provided, the target substrate including an array region, a peripheral region, and a boundary region connecting the array region and the peripheral region; A first pattern layer and a second pattern layer are sequentially formed on the target substrate, wherein the first pattern layer has a first etch pattern and the second pattern layer has a second etch pattern; A fill layer is formed on the second pattern layer, and the side of the fill layer away from the target substrate is planarized so that the top surface of the fill layer on the array area, the peripheral area and the boundary area is flush. A mask is formed on the filling layer, the mask covering the peripheral area and the boundary area; The target substrate is etched according to the first etching pattern and the second etching pattern to form capacitor holes.
2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The planarization process on the side of the filling layer opposite to the target substrate includes: The side of the filling layer facing away from the target substrate is etched back, so that the side of the filling layer facing away from the target substrate is parallel to the top surface of the target substrate.
3. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The method for forming the first pattern layer on the target substrate includes: A first dielectric layer is formed on the target substrate, and the first dielectric layer is etched to form a first intermediate trench; A first covering layer is formed on the bottom and side walls of the first intermediate groove and on top of the first medium layer.
4. The method for fabricating a semiconductor structure according to claim 3, characterized in that, After forming the first covering layer, the method further includes: A portion of the first cover layer is removed to expose the first dielectric layer, wherein the removed portion of the first cover layer is the first cover layer parallel to the top surface of the target substrate.
5. The method for fabricating a semiconductor structure according to claim 4, characterized in that, After exposing the first dielectric layer, the method further includes: Remove the first dielectric layer to form the first etched pattern within the first patterning layer; The first pattern layer includes an array region having the first etched pattern, a peripheral region without the first etched pattern, and a boundary region connecting the array region and the peripheral region.
6. The method for fabricating a semiconductor structure according to claim 5, characterized in that, After forming the first etched pattern, the method further includes: A first fill layer is formed on the first pattern layer, and the first fill layer is planarized to make the first fill layer on the array area, the peripheral area and the boundary area flush.
7. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The method for forming the second pattern layer includes: A second dielectric layer is formed on the first pattern layer, and the second dielectric layer is etched to form a second intermediate trench; A second cover layer is formed on the bottom and side walls of the second intermediate groove and on top of the second medium layer.
8. The method for fabricating a semiconductor structure according to claim 7, characterized in that, After forming the second covering layer, the method further includes: A portion of the second cover layer is removed to expose the second dielectric layer, wherein the removed portion of the second cover layer is a second cover layer parallel to the top surface of the first pattern layer.
9. The method for fabricating a semiconductor structure according to claim 8, characterized in that, After exposing the second dielectric layer, the method further includes: Remove the second dielectric layer to form the second etched pattern within the second patterned layer; The second pattern layer includes an array region having the second etched pattern, a peripheral region without the second etched pattern, and a boundary region connecting the array region and the peripheral region.
10. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The filling layer is a spin-coated hard mask or a spin-coated carbon hard mask.
11. The method for fabricating a semiconductor structure according to any one of claims 1-10, characterized in that, Before forming the first pattern layer on the target substrate, the method further includes: A polycrystalline silicon layer and a silicon oxide layer are formed on the target substrate.
12. A semiconductor structure, characterized in that, The semiconductor structure is fabricated using the method described in any one of claims 1-11.