Anti-fuse type one-time-programmable non-volatile memory cell and memory thereof

Abstract

The present invention relates to a one-time programmable non-volatile memory cell of the antifuse type, comprising: a substrate provided with a first and a second adjacent well of opposite conductivity types, each of the two wells having a first and a second active region separated by an isolation region, the first and second active regions and the isolation region being arranged parallel to each other in a first direction; a first MOS transistor located in the first active region, comprising a floating gate and a gate oxide thereof; and an auxiliary gate and a gate oxide thereof, formed such that the floating gate and the oxide thereof extend from an end thereof, along a second direction perpendicular to the first direction, from the edge of the first active region, through the isolation region, and over a part or all of the second active region. The memory cell has an optimized structure and performance, and is smaller in size.

Description

Technical Field

[0001] This invention relates to a non-volatile memory cell and its memory, and more particularly to a one-time programmable non-volatile memory cell, especially an antifuse type one-time programmable memory cell and its array structure. Background Technology

[0002] As is well known, non-volatile memory includes multiple-programmable memory (MTP), once-programmable memory (OTP), and mask-mode read-only memory (Mask ROM).

[0003] For reprogrammable memory, users can program it multiple times and modify the stored data multiple times. For once-programmable memory, users can only program it once. Once the programming of once-programmable memory is completed, its stored data cannot be modified. As for photomask-mode read-only memory, all stored data is pre-recorded at the factory; users can only read the stored data in the memory, but cannot program it.

[0004] Based on their characteristics, one-time programmable memories (OTPs) can be classified into floating-gate OTPs, fuse-type OTPs, and antifuse-type OTPs. Floating-gate OTP cells achieve high- and low-resistance switching by changing the threshold voltage of the device after electron or hole injection into the floating gate. Fuse-type OTP cells have a low-resistance state before programming and a high-resistance state after programming, typically achieved through electromigration of the polysilicon gate. Antifuse-type OTP cells have a high-resistance state before programming and a low-resistance state after programming.

[0005] As semiconductor manufacturing processes continue to shrink, the electrons or holes trapped in floating-gate OTPs on advanced processes are easily leaked, leading to data loss. Fuse-type OTPs are limited by polysilicon gates, and their use is further restricted if metal gates are used instead in advanced processes. Antifuse-type OTPs, based on the physical breakdown mechanism of the gate oxide layer, eliminate the risk of electron or hole leakage and are not limited by polysilicon gates, exhibiting very high compatibility with advanced processes. Therefore, they have received considerable attention and made significant progress in recent years.

[0006] Currently, there is a growing demand in the industry to improve the structure of antifuse OTP memory, optimize its performance, and make it smaller in size. Summary of the Invention

[0007] This invention relates to an antifuse type, programmable-once, non-volatile memory cell and its memory.

[0008] A first aspect of the present invention relates to a one-time programmable non-volatile memory cell, comprising:

[0009] A substrate having a first conductive well and a second conductive well disposed adjacent to each other; the first conductive well has a first active region, the second conductive well has a second active region, and the first active region and the second active region are separated by an isolation region spanning the two wells; the first and second active regions and the isolation region are all arranged parallel to each other along a first direction;

[0010] A first MOS transistor is located on a first active region, the transistor comprising: a floating gate and gate oxide thereunder; and

[0011] An auxiliary gate and its underlying gate oxide are formed such that the floating gate and its oxide of the first MOS transistor extend from one end of the first active region along a second direction perpendicular to the first direction, through the isolation region, and continue to cover part or all of the second active region.

[0012] In a preferred embodiment, the ratio of the area of ​​the floating gate on the first active region to the area of ​​the auxiliary gate on the second active region is 2:1-40:1, more preferably 5:1-35:1, and even more preferably 10:1-30:1.

[0013] In another preferred embodiment, the thickness ratio of the floating gate oxide on the first active region to the thickness of the auxiliary gate oxide on the second active region is 1:1-5:1, more preferably 1.5:1-4.5:1, and even more preferably 2:1-4:1.

[0014] In another preferred embodiment, the auxiliary gate and its gate oxide extend in a second direction, covering the entire second active region. This forms the gate and its gate oxide layer of the second MOS transistor, located on the second active region. The second MOS transistor may also be referred to as an auxiliary MOS transistor.

[0015] In another preferred embodiment, the first conductive well is a P-well, and the first active region contains two N-type ion-doped regions located on both sides of the floating gate along the first direction, serving as the source and drain of the first MOS transistor, which is an NMOS transistor; the second conductive well is an N-well, and the second active region contains two P-type ion-doped regions located on both sides of the auxiliary gate along the first direction, thereby forming a second MOS transistor, which is a PMOS transistor.

[0016] In another preferred embodiment, the first conductivity type well is an N-well, and the first active region contains two P-type doped regions located on both sides of the floating gate along the first direction, serving as the source and drain of the first MOS transistor, which is a PMOS transistor; the second conductivity type well is a P-well, and the second active region contains two N-type doped regions located on both sides of the auxiliary gate along the first direction, thereby forming a second MOS transistor, which is an NMOS transistor.

[0017] The second aspect of the present invention relates to a one-time programmable non-volatile memory cell array comprising four memory cells as described in claims 1-6, arranged in a 2-row × 2-column array, wherein the substrates of all memory cells are integrated into one unit.

[0018] The two memory cells in each row are mirror-symmetrical, and the first conductive well, the second conductive well, the first active region, the second active region, and the isolation region of the two memory cells in each row are each merged into one, and the three regions are arranged parallel to each other along the first direction.

[0019] The two storage cells in each column are centrally symmetrical, and the two storage cells in each column are separated by an isolation zone between adjacent first active regions or adjacent second active regions.

[0020] In a preferred embodiment, the four storage units in the group have the same composition and structure.

[0021] A third aspect of the present invention relates to a one-time programmable non-volatile memory, comprising: at least one group of memory cells as described above, forming an array, wherein each group in the array is arranged in the same manner, and the substrates of the memory cells of all groups are merged into one to form the substrate of the array.

[0022] In the array, the first conductive well, the second conductive well, the first active region, the second active region, and the isolation region of all memory cells in each row are each merged into one unit, and the three regions are arranged parallel to each other along the first direction;

[0023] In the array, each column is separated by an isolation region between two adjacent first active regions or between two adjacent second active regions of two adjacent memory cells in odd and even rows.

[0024] Each column has one bit line and one common line, located on both sides of the column, and the bit line and common line are alternated in the array; the bit line and common line in each column are respectively connected to the drain and source of the first MOS transistor on the first active region of the memory cell in the column, or respectively connected to the source and drain of the first MOS transistor.

[0025] Each row has a word line that connects to one or two ion-doped regions on either side of the auxiliary gate on the second active region of all memory cells in that row, preferably two.

[0026] In a preferred embodiment, each group in the array has the same composition and structure.

[0027] In the antifuse-type programmable-once memory cell of the present invention, there is only one floating gate and an auxiliary gate extending from one end of it. A typical antifuse-type programmable-once memory cell generally has two transistors and two floating gates. Compared to this, the memory cell of the present invention has a simpler structure, fewer components, smaller size, and better performance.

[0028] In this invention, the area of ​​the auxiliary gate is preferably smaller than the area of ​​the floating gate of the first MOS transistor. When the operating voltage is applied to both the floating gate and the auxiliary gate simultaneously, the auxiliary gate on the second active region experiences a larger voltage division, making it easier for the auxiliary gate oxide layer to break down and become a low-resistance state for programming. Furthermore, the thickness of the auxiliary gate oxide is preferably thinner than that of the floating gate oxide of the first MOS transistor, which facilitates low-voltage breakdown of the auxiliary gate oxide layer and reduces the breakdown voltage required for programming.

[0029] Furthermore, a memory composed of multiple antifuse-type memory cells as described above can statistically improve the convergence of the resistivity distribution of the auxiliary gate oxide after breakdown. That is, the breakdown sites of the auxiliary gate oxides of all memory cells in the memory are closer and more concentrated.

[0030] Furthermore, the arrangement of the storage cell group and the memory it constitutes in this invention is more optimized, which can further reduce the size of the entire memory without affecting its performance. Attached Figure Description

[0031] Figure 1 A top view of an antifuse type memory cell according to one embodiment of the present invention is shown.

[0032] Figure 2 It shows Figure 1 A cross-sectional view of the storage unit along section line AA in the illustrated embodiment.

[0033] Figure 3 It shows Figure 1 A cross-sectional view of the storage unit along section line BB in the illustrated embodiment.

[0034] Figure 4 It shows Figure 1 A cross-sectional view of the storage unit along section line CC in the illustrated embodiment.

[0035] Figures 5a-5bFigure 5a shows a top view of a 2×2 array of memory cells according to one embodiment of the present invention. Figure 5b This is the circuit diagram of the array.

[0036] Figure 6 The bias signals connected to the memory array during different operations are shown in the embodiment shown in Figure 5.

[0037] Detailed description of the invention

[0038] The one-time programmable non-volatile memory cell of the present invention may or may not be made of monolayer polysilicon, but is preferably made of monolayer polysilicon. The gates of the first MOS transistor and the auxiliary MOS transistor may be the same or different, and are selected from monolayer polysilicon gates or metal gates. The gate oxides of the two MOS transistors may be the same or different, and are selected from oxides with high dielectric constants, such as SiO2, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, La2O3, ZrO2, or LaAlO, preferably both being silicon dioxide layers.

[0039] In the one-time programmable non-volatile memory cell of the present invention, the substrate is a conventional semiconductor substrate, but a P-type substrate is preferred.

[0040] In the memory cell described above in this invention, both the first conductive well and the second conductive well are located on the substrate and are arranged side by side adjacent to each other. However, the two wells have different conductivity types. For example, if the first conductive well is an N-well, then the second conductive well is a P-well; and vice versa.

[0041] An active region is a region in which active circuit components, such as transistors, are formed and operated; for example, the source and drain of a transistor are formed within an active region. A first active region is present in a first conductivity type well, and a second active region is present in a second conductivity type well. The first and second active regions are separated by an isolation region that spans across the two adjacent wells. The first and second active regions and the isolation region are all arranged parallel to each other.

[0042] In the first conductive well, the first active region includes two conductive ion-doped regions located on both sides of the floating gate and its gate oxide of the first MOS transistor, respectively constituting the source and drain of the first MOS transistor.

[0043] The conductive ion-doped regions in the first active region can be N-type or P-type. When the first conductivity type well is a P-well, both ion-doped regions in the first active region are N-type, and they respectively constitute the source and drain of the first MOS transistor, making the first MOS transistor an NMOS transistor. When the first conductivity type well is an N-well, both ion-doped regions in the first active region are P-type, and they respectively constitute the source and drain of the first MOS transistor, making the first MOS transistor a PMOS transistor.

[0044] The source and drain terminals in the first MOS transistor are the same and can be used interchangeably.

[0045] The first direction described in this invention is: within the top surface of the active region, the direction from the source to the drain, or the direction from the drain to the source, in the first MOS transistor. The second direction is: within the top surface of the active region, the direction perpendicular to the first direction.

[0046] The floating gate length of the first MOS transistor is the size of the floating gate between the source and drain terminals in the first direction. The floating gate width is the size of the floating gate in the first active region in the second direction. The length and width of the gate oxide under the floating gate are the same as those of the floating gate. The area of ​​the floating gate is the product of the length and width of the floating gate in the first active region, and the area of ​​the floating gate oxide is the same as that of the floating gate.

[0047] The floating gate and its gate oxide of the first MOS transistor extend from one end of the first active region along the width direction (i.e., the second direction) of the floating gate, through the isolation region, to the second active region, and continue to extend along this direction, covering part or all of the second active region, forming an auxiliary gate. The length and width of the auxiliary gate are defined the same as those of the floating gate. The area of ​​the auxiliary gate is the product of the length and width of the auxiliary gate on the second active region. The length and width of the gate oxide below the auxiliary gate are the same as those of the auxiliary gate, and their areas are also the same.

[0048] The area of ​​the auxiliary gate is smaller than that of the floating gate. The ratio of the floating gate area to the auxiliary gate area is 2:1 to 40:1.

[0049] In the second conductive well, the second active region comprises two conductive ion-doped regions. These are located on either side of the auxiliary gate, forming the source and drain electrodes, and together with the auxiliary gate and its gate oxide, constitute the second MOS transistor, also known as the auxiliary transistor. Alternatively, the second active region may comprise a single conductive ion-doped region located on one side of the auxiliary gate, forming a capacitor together with the auxiliary gate and its gate oxide. In this case, the length and width of the auxiliary gate are respectively the dimensions of the auxiliary gate along the first and second directions within the second active region. Preferably, the second active region comprises two conductive ion-doped regions.

[0050] When the auxiliary gate extends along the second direction and covers part but not all of the second active region, even if the second active region contains two conductive ion-doped regions located on both sides of the auxiliary gate, they together with the auxiliary gate and its gate oxide still form a capacitor, rather than a MOS transistor.

[0051] While extending the auxiliary gate to cover a portion of the second active region is more conducive to breakdown programming, it is preferable that the auxiliary gate extends to cover the entire second active region rather than a portion of it. This can improve the controllability and repeatability of the process fabrication, thereby increasing the product yield.

[0052] The conductive ion-doped region in the second active region can also be N-type or P-type. However, since the conductivity type of the second well differs from that of the first well, the type of conductive ion-doped region in the second active region also differs from that in the first active region. For example, when the first well is a P-well, the second well is an N-well, the ion-doped region in the second active region is P-type, and the second MOS transistor is a PMOS. When the first well is an N-well, the second well is a P-well, the ion-doped region in the second active region is N-type, and the second MOS transistor is an NMOS.

[0053] The isolation zone is also known as a shallow channel isolation zone (STI). In this invention, an isolation zone exists between each pair of adjacent active regions, separating them. The isolation zone spans across the two adjacent traps.

[0054] The first active zone, the second active zone, and the isolation zone are all arranged parallel to each other along the first direction.

[0055] In this invention, the floating gate area on the first active region is a conventional value in the industry. The area of ​​the auxiliary gate on the second active region is preferably smaller than the floating gate area on the first active region. The ratio between the floating gate area on the first active region and the auxiliary gate area on the second active region is preferably 2:1-40:1, more preferably 5:1-35:1, and even more preferably 10:1-30:1. This increases the voltage drop across the auxiliary gate, making the auxiliary gate oxide layer more prone to breakdown and becoming a low-resistance state for programming.

[0056] Furthermore, the thickness of the floating gate oxide layer on the first active region is a standard value in the industry. The thickness of the auxiliary gate oxide layer on the second active region can be the same as or thinner than the thickness of the floating gate oxide layer. The ratio of the thickness of the floating gate oxide layer to the thickness of the auxiliary gate oxide layer is 1:1 to 5:1, more preferably 1.5:1 to 4.5:1, and even more preferably 2:1 to 4:1. This reduces the breakdown voltage required to achieve the breakdown field strength, making it more conducive to achieving breakdown.

[0057] In the antifuse type one-time programmable memory cell group of the present invention, there are 4 memory cells of the present invention as described above, arranged in an array of 2 rows × 2 columns, and the substrates of all memory cells are merged into one.

[0058] The arrangement of the two memory cells in each row can be exactly the same or different. To facilitate the formation of a regular and compact small-sized array, it is preferred that the arrangement is different, for example, it is preferred that they are arranged in a left-right mirror symmetrical manner.

[0059] In each row, the first conductive well, second conductive well, first active region, second active region, and isolation region of two memory cells are each merged into one unit. That is, the two first wells of the two memory cells in each row are merged into one unit, the two second wells are merged into one unit, the two first active regions are merged into one active region, similarly, the two second active regions are merged into one active region, and the two isolation regions are also merged into one isolation region. The three regions are all arranged parallel to each other along the first direction.

[0060] The arrangement of the two storage cells in each column can be the same or different. To facilitate the formation of a regular and compact small-sized array, it is preferred that the arrangement be different, such as being mutually mirror-symmetrical or mutually centrally symmetrical. It is preferred that the two cells be centrally symmetrical. The centrally symmetrical arrangement means that either one can completely overlap with the other after rotating 180° around the center of symmetry.

[0061] In each column, two adjacent first active regions or two adjacent second active regions of two storage cells are also separated by an isolation region.

[0062] Preferably, the four storage units in the group have the same composition and structure.

[0063] The source and drain of the first MOS transistor in all memory cells in each group are the same and can be used interchangeably.

[0064] The preferred arrangement of the storage cells in the above-mentioned group of the present invention is beneficial to reducing the size of the storage cell group without affecting its performance.

[0065] The antifuse one-time programmable memory of the present invention comprises: at least one group of the aforementioned memory cells forming an array, wherein each group in the array is arranged in the same manner, and the substrates of all memory cells in all groups are merged into one to form the substrate of the array; in the array, the first conductive well and the second conductive well of all memory cells in each row are merged into one; the first active region, the second active region, and the isolation region are also each merged into one region, and the three regions are arranged parallel to each other along a first direction; in the array, two adjacent first active regions of memory cells in odd and even rows in each column are... Each second active region, or any two adjacent second active regions, is separated by an isolation region; each column has a bit line (BL) and a common line (COM), located on both sides of the column, and the bit line and common line are alternated in the array; the bit line and common line in each column are connected to the drain and source of the first MOS transistor on the first active region of the memory cell in the column, or to the source and drain of the first MOS transistor, respectively; each row has a word line (WL), connected to one or two of the ion-doped regions on both sides of the auxiliary gate on the second active regions of all memory cells in the row.

[0066] In the array, the source and drain of the first MOS transistor in each memory cell can be interchanged. Since the arrangement of the four memory cells in each group of the array is different, the bit line (BL) connecting one pole of all the first MOS transistors in each column is located on one side of the column, and the common line (COM) connecting the other pole is located on the other side of the column. The bit lines and common lines are alternated in the array.

[0067] Preferably, each group in the array has the same composition and structure.

[0068] The memory structure described above in this invention is simple, small in size, requires low breakdown voltage for programming, and the breakdown sites of the auxiliary gate oxide layers of multiple memory cells are closer and more concentrated.

[0069] The memory cells and memory of this invention can be fabricated using mature, conventional processes, such as 180nm, 130nm, 90nm, 55nm, or 40nm logic processes. Alternatively, they can be fabricated using 28nm, 22nm, 16nm, 10nm, 7nm, or 5nm logic processes. The floating gate area on the first active region and the auxiliary gate area on the second active region differ, with the floating gate area or auxiliary gate area depending on the pattern dimensions of their respective active regions and gates. They can be formed using industry-standard methods. For example, the patterns of the active regions and gates are generated by photolithography and dry etching using their corresponding photomasks, and their shapes and sizes are defined in the layout design. The thicknesses of the floating gate oxide layer and the auxiliary gate oxide layer also differ, and they are also formed using industry-standard growth methods. For example, using a thermal oxidation method, in the region where the floating gate oxide layer and the auxiliary gate oxide layer are to be formed, a gate oxide layer with a thickness of 1 is first grown. Then, the existing gate oxide layer in the region where the auxiliary gate oxide layer is to be formed is completely removed by a wet process. Finally, a new gate oxide layer is formed simultaneously in both gate oxide regions using a thermal oxidation method, achieving the desired thickness of the auxiliary gate oxide layer. Here, thickness 1 is the difference between the thickness of the floating gate oxide layer and the auxiliary gate oxide layer.

[0070] The present invention will now be described in detail with reference to specific embodiments. These specific examples are merely for illustrating and aiding in understanding the technical solutions of the present invention and do not constitute a limitation on the scope of protection of the present invention. Without departing from the spirit and scope of the present invention, those skilled in the art can make structural, logical, and electrical modifications to the following specific embodiments and apply them to other embodiments. All such modifications are within the scope of protection of the present invention.

[0071] Those skilled in the art will fully understand this invention through the following detailed description. Furthermore, some system configurations and process steps well-known in the art are not detailed herein, as these should be familiar to those skilled in the art.

[0072] Furthermore, the accompanying drawings of the specific embodiments are schematic diagrams and are not drawn strictly according to actual scale. Sometimes, to clearly show a certain local structure, the dimensions may be enlarged. In the various embodiments disclosed and described herein, where there are common or similar features, similar features are usually denoted by the same reference numerals for ease of illustration and description.

[0073] Although specific voltage values ​​are provided in the embodiments and figures, it should be understood that these values ​​are not necessarily precise values, but are used to express the general concept of the technical solution of the present invention.

[0074] According to one embodiment of the present invention, an antifuse type one-programmable single-layer polysilicon memory cell is provided. Figure 1 A top view of one of the storage units is shown. Figure 2-4These are cross-sectional views along section lines AA, BB, and CC, respectively.

[0075] In this embodiment, the cell is manufactured using a 40nm logic process. This process can provide transistors with different gate areas and different gate oxide thicknesses. All the processing steps required to form the memory cell described above are the same steps used in the logic process to form other circuits on the chip. No additional processing steps are required.

[0076] In this embodiment, the memory cell is constructed in a P-type silicon substrate 101. P-well 102 and N-well 103 are adjacent to each other and disposed in the P-substrate 101. Each P-well 102 and N-well 103 has a first active region and a second active region, separated by an isolation region (STI) spanning both wells. Both active regions and the isolation region are arranged parallel to each other along a first direction.

[0077] An NMOS transistor 200 is disposed on a first active region in a P-well 102. The first active region contains two N-type ion-doped regions 203 and 204, which respectively constitute the N-type source and drain of the NMOS transistor. The source and drain of the NMOS transistor are identical and interchangeable. That is, the drain and source can be doped regions 203 and 204, or they can be doped regions 204 and 203, respectively.

[0078] Doped region 203 includes a lightly doped N-region 203A and a heavily doped N+ region 203B. Doped region 204 includes a lightly doped N-region 204A and a heavily doped N+ region 204B. When doped region 203 is the drain, it is connected to the bit line (BL), and doped region 204 is the source, connected to the common line (COM). Figure 2 As shown.

[0079] Transistor 200 is surrounded by an isolation region (STI, also known as a shallow trench region). Between the source and drain is the channel region. Overlying the channel is a gate oxide layer 202. A conductive doped monolayer polysilicon gate 201 is placed on top of the gate oxide 202, forming the floating gate (FG) 201 of the NMOS transistor.

[0080] The floating gate (FG) 201 and its gate oxide 202 extend along the width direction of the floating gate (i.e., the second direction), pass through the isolation region STI, extend to the second active region in the N-well 103, and cover the entire second active region along the second direction, forming the auxiliary gate (CG) 301 and its gate oxide 302 on the second active region.

[0081] Both the floating gate 201 and the auxiliary gate 301 are surrounded by an isolation wall 110, which is generally formed of silicon nitride or silicon oxide.

[0082] In the second active region of the N-well 103, P-type ion-doped regions 303 and 304 are located on both sides of the auxiliary gate 301, forming the source and drain. These, together with the auxiliary gate and its gate oxide, constitute the second PMOS transistor, also known as the auxiliary transistor. The P-type ion-doped regions are 303 and 304. Doped region 303 includes a lightly doped P-region 303A and a heavily doped P+ region 303B, and doped region 304 includes a lightly doped region 304A and a heavily doped P+ region 304B. The source and drain of the second MOS transistor are connected to the word line (WL).

[0083] When forming an N+ or P+ region, the sidewall isolation layer 110 prevents N+ or P+ implants from entering the lightly doped N- or P-region.

[0084] In this embodiment, the area ratio of the floating gate FG201 to the auxiliary gate CG301 is 18:1 – 20:1, the ratio of the thickness of the floating gate oxide layer to the thickness of the auxiliary gate oxide layer is 2:1 – 3:1, and the area of ​​the floating gate FG201 and the thickness of the floating gate oxide layer are both conventional values, for example, the thickness can be 40-120 Å.

[0085] In most applications, multiple non-volatile memory cells can be placed together to form a memory array. For illustration purposes, Figures 5a-5b The text describes and illustrates a 2×2 memory array and its operation. The array contains four such arrays... Figure 1-4 The memory cells shown are arranged in 2 rows and 2 columns. Arrays of different sizes can be formed by increasing and / or decreasing the number of rows and / or columns. This memory array includes memory cells 400, 410, 420, and 430. The memory array includes NMOS transistors 401, 411, 421, and 431, and PMOS auxiliary transistors 402, 412, 422, and 432.

[0086] In one implementation, the WL lines of memory cells 400 and 410 are connected to WL0 to form a memory row, and the WL lines of memory cells 420 and 430 are connected to WL1 to form another memory row. The common line (COM) and bit line (BL) of cells 400 and 420 are connected to COM0 and BL0 respectively to form a memory column. Similarly, the common line (COM) and bit line (BL) of cells 410 and 430 are connected to COM1 and BL1 respectively to form another memory column.

[0087] The word line (WL) in each row is connected to the drain or source of each PMOS auxiliary transistor in that row.

[0088] The common line (COM) and bit line (BL) in each column are located on both sides of the column. The common line and bit line connect the source and drain of each NMOS transistor in the column, or the drain and source, respectively. The common line and bit line are arranged alternately in the array, as shown in Figure 5. The source and drain of each NMOS transistor can be interchanged.

[0089] The memory array is constructed on a P-type substrate. The N-wells and P-wells of all memory cells within a memory row are merged together. Thus, each memory row contains one N-well and one P-well. The two P-wells of adjacent odd and even rows are placed side-by-side, or they can be merged into one unit.

[0090] By merging the wells within a row, the memory cells in the array can be packaged more tightly because most of the space between wells is eliminated. The memory array is built on the same substrate as other logic circuitry on the chip, which requires the substrate to be grounded or at 0V.

[0091] In each storage row, the first active regions of all storage cells are merged into one region. Similarly, the second active regions and interval regions of all storage cells are also merged into one region each. In each storage row, the three regions are arranged parallel to each other along a first direction.

[0092] Each memory cell in the array can be programmed independently.

[0093] Figure 6 It shows Figures 5a-5b The bias voltage of the storage array in the illustrated embodiment under different operating modes.

[0094] In this embodiment, storage cell 400 is selected for individual programming, while the other three storage cells 410, 420, and 430 are not programmed.

[0095] Both the word line and bit line of cell 400 are selected. Its bit line potential is 0V, and the common line is floating. Therefore, the floating gate of its NMOS transistor 401 and the auxiliary gate potential of its auxiliary PMOS transistor 402 are both 0V. Simultaneously, the word line of cell 400 is driven to 6V. Due to the small capacitance of the auxiliary transistor, its auxiliary gate oxide layer withstands approximately 5V, causing it to break down and conduct, changing from a high-resistance state to a low-resistance state, thus initiating programming.

[0096] The word line of cell 410 is selected, but the bit line is not selected. Although its word line is also driven to 6V, because its bit line potential is 4V and the common line is floating, the bit line potential can couple to the floating gate and the auxiliary gate, causing the auxiliary gate oxide layer of its auxiliary transistor to withstand a voltage of about 2V, which cannot be broken down and conduction, and it remains in a high-impedance state, so programming does not occur.

[0097] The word line of cell 420 is not selected, but the bit line is selected. Its bit line potential is 0V, and the common line is floating. The floating gate of its NMOS transistor 421 and the auxiliary gate potential of its auxiliary PMOS transistor 422 are both 0V. Simultaneously, the word line of cell 420 is driven to 2V, causing the auxiliary gate oxide layer of its auxiliary transistor to withstand approximately 2V, preventing it from breaking down and conducting; it remains in a high-impedance state, and programming does not occur.

[0098] Neither the word line nor the bit line of cell 430 is selected. Its word line is driven to 2V, but because its bit line potential is 4V and the common line is floating, the bit line potential can couple to the floating gate and the auxiliary gate, causing the auxiliary gate oxide layer of its auxiliary transistor to withstand a voltage of about -2V, which cannot be broken down and conduction, and it remains in a high-impedance state, so programming does not occur.

[0099] During the read operation, both the word line and bit line of cell 400 are selected. Its word line, bit line, and common line are driven to 1.2V, 0V, and 2.5V, respectively. Since cell 400 is programmed, its auxiliary PMOS transistor is broken down and turned on, thereby giving the auxiliary gate and the floating gate of the NMOS transistor the same potential as the word line, 1.2V. Because the potential difference between the floating gate of the NMOS transistor and the bit line is 1.2V, which is greater than the NMOS transistor's threshold voltage of 0.7-0.8V, the channel between the source and drain of the NMOS transistor is turned on. Simultaneously, the voltage difference between the bit line and the common line connecting the source and drain is 2.5V, forming a transverse electric field, thereby generating a read current. The read current is then detected by a sensitive amplifier and driven to output a data signal with state "1".

[0100] The word line of cell 410 is selected, but the bit line is not. Its word line potential (1.2V) is less than the bit line (2.5V) and the common line (2.5V), so the effect of coupling to boost the potential of the auxiliary gate and floating gate is very small. Therefore, the floating gate potential of the NMOS transistor is less than its source-drain potential, and a channel cannot be formed between the source and drain. Simultaneously, the source and drain potentials are the same, and no transverse electric field is formed. Therefore, no read current is generated. The sensitive amplifier outputs a data signal indicating a state "0".

[0101] The word lines of cells 420 and 430 are not selected, and the bit line of cell 430 is also not selected. The word line potentials in these two cells are both 0V, preventing the coupling of the auxiliary gate and floating gate potentials. Since the floating gate potential of the NMOS transistors is lower than the potentials of the bit lines and common lines, both NMOS transistors remain off, and no read current is generated. The sensitive amplifier outputs a data signal indicating a state "0".

Claims

1. A one-time programmable non-volatile memory cell, characterized in that, include: A substrate having an adjacent first conductive N-type well and a second conductive P-type well. The first conductive N-type well has a first active region, and the second conductive P-type well has a second active region. The adjacent first active region and second active region are separated by an isolation region that spans the two wells. The first, second active regions and the isolation region are all arranged parallel to each other along a first direction. A first MOS transistor, located on a first active region, comprises: a floating gate and gate oxide thereunder; and A second MOS transistor includes: an auxiliary gate and a gate oxide thereunder, the auxiliary gate being connected to a floating gate, the auxiliary gate and the gate oxide being formed such that the floating gate and the oxide of the first MOS transistor extend from one end of the first active region along a second direction perpendicular to the first direction, through an isolation region, and continue to cover the entire second active region; The first active region contains two P-type ion-doped regions, located on both sides of the floating gate along the first direction, serving as the source and drain of the first MOS transistor, which is a PMOS transistor; the second active region contains two N-type ion-doped regions, located on both sides of the auxiliary gate along the first direction, forming the source and drain of the second MOS transistor, which is an NMOS transistor. The ratio of the area of ​​the floating gate on the first active region to the area of ​​the auxiliary gate on the second active region is 5-35:

1.

2. The storage unit as claimed in claim 1, characterized in that, The thickness ratio of the floating gate oxide on the first active region to the auxiliary gate oxide on the second active region is 1-5 :

1.

3. A one-time programmable non-volatile memory cell group, characterized in that, It includes four memory cells as described in any one of claims 1-2, arranged in a 2-row × 2-column array, with the substrates of all memory cells merged into one unit; The two memory cells in each row are mirror-symmetrical, and the first conductive well, the second conductive well, the first active region, the second active region, and the isolation region of the two memory cells in each row are each merged into one, and the three regions are arranged parallel to each other along the first direction. The two storage cells in each column are centrally symmetrical, and the two adjacent first active regions or the two adjacent second active regions in each column are also separated by an isolation region.

4. The storage cell group structure as described in claim 3, characterized in that, The four storage units in the group have the same composition and structure.

5. A one-time programmable non-volatile memory, characterized in that, It includes: At least one group of memory cells as described in claim 3 or 4 forms an array, wherein each group in the array is arranged in the same way, and the substrates of the memory cells of all groups are merged into one to form the substrate of the array. In the array, the first conductive well, the second conductive well, the first active region, the second active region, and the isolation region of all memory cells in each row are merged into one unit, and the active region and the isolation region are arranged parallel to each other along the first direction; In the array, each of the two adjacent first active regions of two adjacent memory cells in each column, or the two adjacent second active regions, is separated by an isolation region. Each column has one bit line and one common line, located on both sides of the column, and the bit line and common line are alternated in the array; the bit line and common line in each column are respectively connected to the drain and source of the first MOS transistor on the first active region of the memory cell in the column, or respectively connected to the source and drain of the first MOS transistor. Each row contains a word line that connects to the ion-doped regions on both sides of the auxiliary gate on the second active region of all memory cells in that row.

6. The non-volatile memory as described in claim 5, characterized in that, Each group in the array has the same composition and structure.

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