Method and circuit for implementing multi-bit register atomic operation, chip and electronic device

Abstract

The application discloses a method and circuit for realizing atomic operation of a multi-bit register, a chip and an electronic device.The multi-bit register comprises a write port, a set operation interface and a clear operation interface.The method comprises the following steps: writing data into the multi-bit register through the write port; and when it is necessary to modify the data in the multi-bit register, directly completing the data modification operation through the set operation interface or the clear operation interface once.The atomic access of the multi-bit register can be realized, and the normal operation of the system is avoided from being affected.

Description

Technical Field

[0001] This invention relates to the field of digital circuit technology, and more specifically to a method, circuit, chip, and electronic device for implementing atomic operations of multi-bit registers. Background Technology

[0002] Registers are small storage areas inside the CPU used to temporarily store data involved in calculations and the results of those calculations. The storage circuitry of a register consists of latches or flip-flops. Since one latch or flip-flop can store one bit of binary data, N latches or flip-flops can form an N-bit register. Functionally, registers are typically classified into general-purpose registers, special-purpose registers, and control registers.

[0003] General-purpose registers have a bit length equal to the machine word length, and can be 16 bits or 32 bits. Currently, in System-On-a-Chip (SoC) or integrated circuits, registers are mostly grouped into 32-bit sets. In existing technology, to avoid errors caused by contention for accessing registers in multi-core systems, which could invalidate previous operations, set-clear registers have been proposed. These registers implement set and clear operation interfaces. The set operation interface modifies the bits in the register, and the clear operation interface clears the bits in the register.

[0004] In existing technologies, set and clear operation interfaces are typically provided only for single-bit registers, while no corresponding operation interfaces are provided for multi-bit registers. This implementation method still cannot avoid errors introduced by multi-core contention for access. To address this, some products implement the above functions for multi-bit registers, that is, each bit in the multi-bit register adopts the same implementation scheme as the single-bit register. However, modifying multi-bit registers that provide set and clear operation interfaces not only complicates the register modification operation, but also introduces problems of varying degrees to the system due to the different meanings represented by the multi-bit registers. Summary of the Invention

[0005] This invention provides a method, circuit, chip, and electronic device for implementing atomic operations on multi-bit registers, so as to achieve atomic access to multi-bit registers and avoid affecting the normal operation of the system.

[0006] Therefore, the embodiments of the present invention provide the following technical solutions: On one hand, embodiments of the present invention provide a method for implementing atomic operations on a multi-bit register, wherein the multi-bit register includes a write port, a set operation interface, and a clear operation interface; the method includes: Data is written to the multi-bit register via the write port; When it is necessary to modify the data in the multi-bit register, the data modification operation can be completed in one step directly through the set operation interface or the clear operation interface.

[0007] Optionally, the step of directly completing the data modification operation through the set operation interface or the clear operation interface in one operation includes: If it is necessary to assign a non-zero value to the multi-bit register, then the non-zero target value is directly written to the multi-bit register through the set operation interface; If it is necessary to assign a value of 0 to the multi-bit register, a non-zero value can be written directly through the clear operation interface.

[0008] Optionally, the method further includes: A control signal is generated based on all the bits of data in the multi-bit register; A multiplexing signal is generated based on the control signal and the current operation signal. The operation signal includes: a write operation signal for controlling the write port, a set operation signal for controlling the set operation interface, and a clear operation signal for controlling the clear operation interface. The step of directly writing a non-zero target value to the multi-bit register through the set operation interface includes: Enable the set operation interface and transmit the non-zero target value to the data bus; The multiplexing signal controls the writing of the non-zero target value on the data bus into the multi-bit register. The step of directly writing a non-zero value through the clearing operation interface includes: Enable the zeroing operation interface and transmit a non-zero data to the data bus; The multiplexing signal controls the input of all-zero data values ​​to the multi-bit register.

[0009] On the other hand, embodiments of the present invention also provide a circuit for implementing atomic operations of a multi-bit register, the circuit comprising: a multi-bit register, the multi-bit register including a write port, a set operation interface, and a clear operation interface; The write operation module is used to output a write operation signal to control the write port to write data to the multi-bit register; The modification operation module is used to output a set operation signal or a clear operation signal when it is necessary to modify the data in the multi-bit register, so as to control the set operation interface or the clear operation interface to complete the data modification operation in one go.

[0010] Optionally, the modification operation module is specifically used to output the set operation signal when it is necessary to assign a non-zero value to the multi-bit register, so as to control the set operation interface to write a non-zero target value to the multi-bit register; and to output the set operation signal when it is necessary to assign a zero value to the multi-bit register, so as to control the clear operation interface to write a non-zero value to the multi-bit register.

[0011] Optionally, the circuit further includes: The control signal generation module is used to generate a selection control signal based on all bit data of the multi-bit register and the current operation signal. The operation signal includes: a write operation signal for controlling the write port, a set operation signal for controlling the set operation interface, and a clear operation signal for controlling the clear operation interface. The selection module is used to output the data on the data bus corresponding to each operation signal according to the selection control signal.

[0012] Optionally, the control signal generation module includes: a first OR gate, a first AND gate, and a second AND gate; The first OR gate takes the multi-channel data input signal of the multi-bit register as input and outputs a judgment signal. The first AND gate takes the set operation signal and the judgment signal as inputs and outputs a set selection signal; The second AND gate takes the clear operation signal and the judgment signal as inputs and outputs a clear selection signal; The selection module inputs the write operation signal, the set selection signal, and the clear operation signal; when the write operation signal is valid, it writes data to the multi-bit register through the write port; when the set selection signal is valid, it writes a non-zero target value to the multi-bit register through the set operation interface; when the clear selection signal is valid, it writes a non-zero value to the multi-bit register through the clear operation interface.

[0013] Optionally, the selection module includes: a third selector, a second selector, and a first selector connected in sequence; The control terminal of the third selector receives the write operation signal, and the first input terminal and the second input terminal of the third selector respectively receive the multi-channel data input signal of the multi-bit register and the multi-channel data output signal of the multi-bit register, and output the first data signal. The control terminal of the second selector receives the clear selection signal, and the first input terminal and the second input terminal of the second selector respectively receive the first data signal and the all-zero data value to be written for the clear operation, and output the second data signal. The control terminal of the first selector receives the set selection signal, the first input terminal and the second input terminal of the first selector receive the second data signal and the multi-channel data input signal of the multi-bit register respectively, and the output terminal is connected to the data input terminal of the multi-bit register.

[0014] Optionally, the second selector includes: a first inverter and a third AND gate; The first inverter receives the reset selection signal; One input of the third AND gate is connected to the output of the first inverter, the other input of the third AND gate receives the first data signal, and the output of the third AND gate outputs the second data signal.

[0015] Optionally, the selection module includes: a 3-to-1 selector, wherein the three control terminals of the 3-to-1 selector are respectively input to the write operation signal, the set selection signal, and the clear selection signal; the three input terminals of the 3-to-1 selector are respectively input to the multi-channel data input signal of the multi-bit register, the multi-channel data output signal of the multi-bit register, and the all-zero data value to be written for the clear operation; and the output terminal of the 3-to-1 selector is connected to the data input terminal of the multi-bit register.

[0016] Optionally, the selection module includes: a second OR gate, a 2-to-1 selector, a second inverter, and a fourth AND gate; The second OR gate receives the write operation signal and the set selection signal, respectively. The control terminal of the 2-to-1 selector is connected to the output terminal of the second OR gate. The first input terminal and the second input terminal of the 2-to-1 selector are respectively input to the multi-channel data input signal of the multi-bit register and the multi-channel data output signal of the multi-bit register. The reset selection signal is input to the second inverter; The two inputs of the fourth AND gate are connected to the output of the second inverter and the output of the 2-to-1 selector, respectively, and the output of the fourth AND gate is connected to the data input of the multi-bit register.

[0017] On the other hand, embodiments of the present invention also provide a chip, including the circuit described above for implementing atomic operations of multi-bit registers.

[0018] On the other hand, embodiments of the present invention also provide an electronic device, including the circuit described above for implementing atomic operations of multi-bit registers.

[0019] The method, circuit, chip, and electronic device for implementing atomic operations on multi-bit registers provided in this invention are designed for multi-bit registers with set and clear operation interfaces. When data in the multi-bit register needs to be modified, the data modification operation can be completed directly through the set or clear operation interface in one step. The modification of any one or more bits in the multi-bit register can be completed in one step, realizing true atomic operation. This effectively avoids errors introduced by multi-core contention access and does not introduce stability problems to the processor. Attached Figure Description

[0020] Figure 1 This is a flowchart illustrating a method for implementing atomic operations on multi-bit registers according to an embodiment of the present invention; Figure 2 This is a flowchart of the control method for the set operation interface and the clear operation interface in an embodiment of the present invention; Figure 3 This is a schematic block diagram of the circuit for implementing atomic operations on multi-bit registers according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the control principle for each operation in the circuit that implements atomic operations of a multi-bit register according to an embodiment of the present invention; Figure 5 It shows Figure 4 A schematic diagram of a specific structure of the middle part module and the control signal generation module; Figure 6 This is a schematic diagram of a specific structure of a circuit that implements atomic operations on a multi-bit register according to an embodiment of the present invention; Figure 7 yes Figure 6 A schematic diagram of a variant structure of the second selector in the circuit shown; Figure 8 This is another specific structural diagram of the circuit that implements atomic operations on multi-bit registers according to an embodiment of the present invention. Detailed Implementation

[0021] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0022] An atomic operation is an indivisible operation that is guaranteed to be executed and completed without being interrupted by another task or event; in other words, it is the smallest unit of execution. For a single-bit register, atomic operations are implemented by setting the set and clear operation interfaces.

[0023] Setting up set and clear operation interfaces for multi-bit registers, that is, using the same set and clear operations for each bit in a multi-bit register as for a single-bit register, typically has the following three implementation methods in existing technologies: (1) Perform the three-step operation of reading, modifying and writing through the standard interface.

[0024] Although multi-bit registers have set and clear operation interfaces, this three-step operation method cannot guarantee atomic operation, and therefore cannot avoid errors introduced by multi-core contention for access.

[0025] (2) First, perform the operation through the set operation interface, and then perform the operation through the clear operation interface.

[0026] For example, register y_reg[3:0] needs to be changed from 4'b0111 to 4'b1100. First, the register value is changed from 4'b0111 to 4'b1111 using the set operation interface; then, the register value is changed from 4'b1111 to 4'b1100 using the clear operation interface. If this multi-bit register value represents the processor's operating frequency, then the frequency corresponding to the intermediate value 4'b1111 will exceed the frequency allowed by the voltage corresponding to values ​​4'b0111 and 4'b1100, which will introduce stability problems to the processor.

[0027] (3) First, use the clear operation interface, and then use the set operation interface to perform the operation.

[0028] For example, register y_reg[3:0] needs to be changed from 4'b0111 to 4'b1100. First, the register value is changed from 4'b0111 to 4'b0100 using the clear operation interface; then, the register value is changed from 4'b0100 to 4'b1100 using the set operation interface. If this multi-bit register value represents the processor's operating voltage, then the voltage corresponding to the intermediate value 4'b0100 will be lower than the voltage allowed for the frequencies corresponding to values ​​4'b0111 and 4'b1100, which will also introduce stability problems to the processor.

[0029] Clearly, existing operations on multi-bit registers with set and clear operation interfaces are not only cumbersome, but also suffer from the aforementioned problems.

[0030] Therefore, embodiments of the present invention provide a method and circuit for implementing atomic operations on multi-bit registers. For multi-bit registers with set and clear operation interfaces, when it is necessary to modify the data in the multi-bit register, the data modification operation can be completed directly through the set or clear operation interface in one step, thus achieving true atomic operation.

[0031] like Figure 1 The diagram shows a flowchart of a method for implementing atomic operations on multi-bit registers according to an embodiment of the present invention, including the following steps: Step 101: Write data to the multi-bit register through the write port. The multi-bit register has a set operation interface and a clear operation interface.

[0032] Read and write operations for multi-bit registers with set and clear operation interfaces are the same as those for multi-bit registers without set and clear operation interfaces, i.e., they are performed through standard read and write interfaces, which will not be elaborated further.

[0033] Step 102: When it is necessary to modify the data in the multi-bit register, the data modification operation can be completed directly through the set operation interface or the clear operation interface in one step.

[0034] If a non-zero value needs to be assigned to the multi-bit register, the non-zero target value is directly written to the multi-bit register through the set operation interface. For example, if the multi-bit register y_reg[3:0] needs to be changed from 4'b0111 to 4'b1100, then 1100 is directly written to the register through the set operation interface, and the data stored in the register is modified to 1100.

[0035] If it is necessary to assign a value of 0 to the multi-bit register, that is, to clear the multi-bit register, a non-zero value is directly written through the clear operation interface. It should be noted that the specific value of the non-zero value written through the clear operation interface is not required, as long as any bit is 1.

[0036] like Figure 2 The diagram shown is a flowchart of the control method for the set operation interface and the clear operation interface in an embodiment of the present invention, including the following steps: Step 201: Generate control signals based on all the bit data of the multi-bit register.

[0037] Step 202: Generate a multiplexing signal based on the control signal and the current operation signal. The operation signal includes: a write operation signal for controlling the write port, a set operation signal for controlling the set operation interface, and a clear operation signal for controlling the clear operation interface.

[0038] Step 203: When a non-zero value needs to be assigned to the multi-bit register, enable the set operation interface and transmit the non-zero target value to the data bus. Then, control the writing of the non-zero target value on the data bus to the multi-bit register through the multiplexing signal.

[0039] Step 204: When it is necessary to assign a 0 value to the multi-bit register, enable the clear operation interface and transmit a non-zero data to the data bus. Control the input of all-zero data values ​​to the multi-bit register through the multiplexer signal.

[0040] It should be understood that, in the various embodiments of the present invention, the order of the above-mentioned process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0041] The method for implementing atomic operations on multi-bit registers provided in this invention targets multi-bit registers with set and clear operation interfaces. When it is necessary to modify the data in the multi-bit register, the data modification operation can be completed directly through the set or clear operation interface in one step. The modification of any one or more bits in the multi-bit register can be completed in one step, realizing true atomic operation. This effectively avoids errors introduced by multi-core contention access and does not introduce stability problems to the processor.

[0042] Accordingly, the present invention also provides a circuit for implementing atomic operations on multi-bit registers, such as... Figure 3 The diagram shown is a schematic diagram of this circuit.

[0043] The circuit includes a multi-bit register 301, which includes a write port, a set operation interface, and a clear operation interface.

[0044] The circuit also includes: a write operation module 302 and a modify operation module 303. Wherein: The write operation module 302 is used to output a write operation signal to control the write port to write data to the multi-bit register; The modification operation module 303 is used to output a set operation signal or a clear operation signal when it is necessary to modify the data in the multi-bit register, so as to control the set operation interface or the clear operation interface to complete the data modification operation in one step. Specifically, when it is necessary to assign a non-zero value to the multi-bit register 301, a set operation signal is output to control the set operation interface to write a non-zero target value to the multi-bit register; when it is necessary to assign a zero value to the multi-bit register 301, a clear operation signal is output to control the clear operation interface to write a non-zero value to the multi-bit register.

[0045] In practical applications, the operations of the write operation module 302 on the write port and the operations of the modification operation module 303 on the set operation interface and the clear operation interface can be controlled by corresponding signals.

[0046] like Figure 4 The diagram shown is a schematic diagram of the control principle of each operation in the circuit that implements atomic operations of a multi-bit register according to an embodiment of the present invention.

[0047] In this embodiment, the circuit further includes a control signal generation module 401 and a selection module 402. Wherein: The control signal generation module 401 is used to generate a selection control signal based on all bit data of the multi-bit register and the current operation signal. The operation signal includes: a write operation signal for controlling the write port, a set operation signal for controlling the set operation interface, and a clear operation signal for controlling the clear operation interface. The selection module 402 is used to output the data on the data bus corresponding to each operation signal according to the selection control signal.

[0048] It should be noted that, Figure 3 and Figure 4 The block diagram shown is only a schematic description of the principle of the present invention. In practical applications, the modules shown in the figure can be integrated into the same physical entity or can be independent physical entities. The embodiments of the present invention do not limit this.

[0049] The circuit and working process of implementing atomic operations on multi-bit registers according to the present invention will be described in further detail below through several specific examples.

[0050] Figure 5 The diagram shown is a specific structural schematic of a circuit that implements atomic operations on a multi-bit register according to an embodiment of the present invention.

[0051] In this embodiment, for clarity, the write operation module 302 and the modification operation module 303 described above are not shown in the figure; only the signals output by these two modules are shown: the write operation signal reg_wr, ​​the set interface operation signal reg_set, and the clear interface operation signal reg_clear. Additionally, Figure 5 PCLK and PRESETn are the clock signal and reset signal of the multi-bit register 301, respectively. The multi-data input signal of the multi-bit register 301 is reg_wdate[N:0], and the multi-data output signal of the multi-bit register 301 is y_reg [N:0].

[0052] In this embodiment, the control signal generation module includes: a first OR gate 410, a first AND gate 411, and a second AND gate 412. Wherein: The first OR gate 410 inputs the multi-channel data input signal reg_wdate[N:0] of the multi-bit register and outputs a judgment signal; The first AND gate 411 takes the set operation signal reg_set and the judgment signal as inputs, and outputs a set selection signal; The second AND gate 412 takes the clear operation signal reg_clear and the judgment signal as inputs and outputs a clear selection signal.

[0053] In this embodiment, the selection module 402 inputs the write operation signal reg_wr, ​​the set selection signal, and the clear operation signal; when the write operation signal is valid, data is written to the multi-bit register 301 through the write port; when the set selection signal is valid, a non-zero target value is written to the multi-bit register 301 through the set operation interface; when the clear selection signal is valid, a non-zero value is written to the multi-bit register 301 through the clear operation interface.

[0054] In practical applications, the selection module 402 can be implemented in multiple ways, as illustrated below.

[0055] For example, in a non-limiting embodiment, the selection module 402 can be implemented using a 3-to-1 selector. The three control terminals of the 3-to-1 selector are respectively input to the write operation signal reg_wr, ​​the set selection signal, and the clear selection signal; the three input terminals of the 3-to-1 selector are respectively input to the multi-bit register's multiple data input signal, the multi-bit register's multiple data output signal, and the all-zero data value N+1'b0 to be written for the clear operation (N+1 represents the number of bits in the multi-bit register, from 0 to N, and 'b0 represents the binary code representation of 0); the output terminal of the 3-to-1 selector is connected to the data input terminal of the multi-bit register.

[0056] Using this three-to-one selector, when all three control signals are invalid, the three-to-one selector outputs the multi-channel data output signal y_reg [N:0] of the multi-bit register 301, meaning the data in the multi-bit register 301 remains unchanged; when the write operation signal reg_wr or the set selection signal is valid, the multi-channel data input signal reg_wdate [N:0] of the multi-bit register is output, meaning data corresponding to the write interface or non-zero target data corresponding to the set operation interface is written to the multi-bit register 301; when the clear selection signal is valid, the all-zero data value N+1'b0 to be written for the clear operation is output. For example, in another non-limiting embodiment, the selection module 402 can be implemented by three two-to-one selectors, such as... Figure 6 As shown. The three 2-to-1 selectors are Figure 6The three selectors, namely the third selector 423, the second selector 422, and the first selector 421, are connected sequentially. The functions of these three 2-to-1 selectors are as follows: when the control input of the selector is 0, the selector outputs the value of the first input; when the control input of the selector is 1, the selector outputs the value of the second input. Wherein: The control terminal of the third selector 423 inputs a write operation signal reg_wr, ​​and the first and second input terminals respectively input the multi-channel data input signal reg_wdate[N:0] of the multi-bit register 301 and the multi-channel data output signal y_reg [N:0] of the multi-bit register 301, and output the first data signal; The control terminal of the second selector 422 receives the clear selection signal, the first input terminal and the second input terminal receive the first data signal and the all-zero data value to be written for the clear operation, respectively, and outputs the second data signal. The control terminal of the first selector 421 receives the set selection signal, the first input terminal and the second input terminal receive the second data signal and the multi-channel data input signal reg_wdate[N:0] of the multi-bit register respectively, and the output terminal is connected to the data input terminal of the multi-bit register 301.

[0057] The following is combined Figure 6 The working process of the circuit for implementing atomic operations of multi-bit registers according to the present invention is described in detail.

[0058] exist Figure 6 In the illustrated embodiment, OR gate 410 performs an OR operation on all bits of the multi-channel data input signal reg_wdate[n:0] of the multi-bit register 301 to determine whether the data in the write channel is zero. When the multi-channel data input signal reg_wdate[N:0] is equal to 0, the OR gate outputs 0; when the multi-channel data input signal reg_wdate[N:0] is not equal to 0, the OR gate outputs 1.

[0059] The first AND gate 411 is used to determine whether a non-zero value has been written through the set operation interface. When a non-zero value is written through the set operation interface, the output of the first AND gate 411 is 1; otherwise, the output of the first AND gate 411 is 0.

[0060] The second AND gate 412 is used to determine whether a non-zero value has been written through the clear operation interface. When a non-zero value is written through the clear operation interface, the second AND gate 412 outputs 1; otherwise, the second AND gate 412 outputs 0.

[0061] The first selector 421 writes a non-zero target value through the set operation interface, the first AND gate 411 outputs 1, the first selector 421 selects the multiplexed data input signal reg_wdate[N:0], and the multi-bit register 301 writes the value of the multiplexed data input signal reg_wdate[N:0]; otherwise, the first selector 421 selects the output of the second selector 422, and writes the output value of the second selector 422 into the multi-bit register 301.

[0062] Second selector 422: When a non-zero value is written through the clear operation interface, the output of the second AND gate 412 is 1, the second selector 422 selects the N+1'b0 value, and writes the all-zero value into the multi-bit register 301 through the first selector 421; otherwise, the second selector 422 selects the output of the third selector 423, and writes the output into the multi-bit register 301.

[0063] Third selector 423: When writing to multi-bit register 301 through the general write port, the write operation signal reg_wr is 1, the third selector 423 selects the multiplexed data input signal reg_wdate[N:0], and writes the value of the signal to multi-bit register 301 through the first selector 421 and the second selector 422; otherwise, the third selector 423 selects the Q value output by multi-bit register 301, and writes the value to multi-bit register 301, that is, keeps the data in multi-bit register 301 unchanged.

[0064] It should be noted that the three binary-to-one selectors mentioned above can also achieve the same function using other variant structures, such as... Figure 7 As shown, is Figure 6 A schematic diagram of a variant structure of the second selector in the circuit shown.

[0065] In this embodiment, the second selector 422 includes a first inverter 4221 and a third AND gate 4222. The input of the first inverter 4221 is ANDed with... Figure 6 The input terminal of the second AND gate 412 is connected to the input of the reset selection signal; one input terminal of the third AND gate 4222 is connected to the output terminal of the first inverter 4221, and the other input terminal of the third AND gate 4222 is connected to... Figure 6 The output of the third selector is connected to the input of the first data signal, and the output of the third AND gate 4222 is the output of the second selector 422, which outputs the second data signal.

[0066] Simultaneously refer to Figure 6 and Figure 7When a non-zero value is written through the clear operation interface, the first OR gate 410 outputs 1, the clear operation signal reg_clear is 1, the second AND gate 412 outputs 1, the first inverter 4221 outputs 0, and after performing an AND operation between the outputs of the third AND gate 4222 and the third selector 423, an N+1-bit all-zero value is generated and written to the multi-bit register 301, thereby achieving the clearing purpose. When a non-zero target value is written through the set operation interface, the first OR gate 410 outputs 1, the set operation signal reg_set is 1, the first AND gate 411 outputs a set selection signal, and the first selector 421 selects the multi-channel data input signal reg_wdate[N:0], writing the non-zero target value to the multi-bit register 301.

[0067] Reference Figure 8 , Figure 8 This is another specific structural diagram of the circuit that implements atomic operations on multi-bit registers according to an embodiment of the present invention.

[0068] In this embodiment, the selection module includes: a second OR gate 431, a 2-to-1 selector 432, a second inverter 433, and a fourth AND gate 434. Wherein: The second OR gate 431 is respectively input to the write operation signal reg_wr and the set selection signal output by the first AND gate 411; The control terminal of the 2-to-1 selector 432 is connected to the output terminal of the second OR gate 431. The first input terminal and the second input terminal of the 2-to-1 selector 432 respectively input the multi-channel data input signal reg_wdate[N:0] of the multi-bit register 301 and the multi-channel data output signal y_reg[N:0] of the multi-bit register 301. The second inverter 433 is input to the clear selection signal output by the second AND gate 412; The two inputs of the fourth AND gate 434 are connected to the output of the second inverter 433 and the output of the two-to-one selector 432, respectively, and the output of the fourth AND gate 434 is connected to the data input of the multi-bit register 301.

[0069] The following is combined Figure 8 The working process of the circuit in this embodiment will be explained in detail.

[0070] When writing to the multi-bit register 301 through the general-purpose write port, the write operation signal reg_wr is 1, the set operation signal reg_set and the clear operation signal reg_clear are 0, the output of the second AND gate 412 is 0, and the output of the second inverter 433 is 1. The 2-to-1 selector 432 selects the multiplexed data input signal reg_wdate[N:0] and outputs this signal to the fourth AND gate 434. The fourth AND gate 434 then writes the value of the multiplexed data input signal reg_wdate[N:0] into the multi-bit register 301.

[0071] When a non-zero target value is written through the set operation interface, the set operation signal reg_set is 1, the write operation signal reg_wr and the clear operation signal reg_clear are 0, the output of the second inverter 433 is 1, and after performing an AND operation with the output of the 2-to-1 selector 432 through the fourth AND gate 434, the output of the fourth AND gate 434 maintains the output value of the 2-to-1 selector 432, thereby achieving the purpose of writing a non-zero value when setting.

[0072] When a non-zero value is written through the clear operation interface, the output of the first OR gate 410 is 1, the clear operation signal reg_clear is 1, the write operation signal reg_wr and the set operation signal reg_set are 0, the output of the second inverter 433 is 0, and after performing an AND operation with the output of the 2-to-1 selector 432, an N+1-bit all-zero value is generated and written to the multi-bit register 301, thereby achieving the purpose of clearing.

[0073] The circuit for implementing atomic operations on multi-bit registers provided in this embodiment of the invention, for multi-bit registers with set operation interface and clear operation interface, when it is necessary to modify the data in the multi-bit register, the data modification operation can be completed directly through the set operation interface or the clear operation interface in one step. The modification of any one bit or multiple bits in the multi-bit register can be completed in one step, realizing true atomic operation, thereby effectively avoiding errors introduced by multi-core contention access and not introducing stability problems to the processor.

[0074] Using the solution of this invention, it is possible to easily and conveniently modify the data in a multi-bit register. The circuit structure is simple and the cost is low.

[0075] Accordingly, embodiments of the present invention also provide a chip, including the circuit described above for implementing atomic operations of multi-bit registers.

[0076] Accordingly, embodiments of the present invention also provide an electronic device, including the circuit described above for implementing atomic operations of a multi-bit register.

[0077] In practical implementation, the multiplier digital circuit mentioned above for in-memory computation can correspond to a chip in a network device, such as a SoC (System-On-a-Chip), a baseband chip, a chip module, etc.

[0078] In specific implementation, the modules / units included in the various devices and products described in the above embodiments can be software modules / units, hardware modules / units, or a combination of both.

[0079] For example, for various devices and products applied to or integrated into a chip, each module / unit can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a chip module, each module / unit can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The components can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, each of its components / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or in different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.

[0080] In the several embodiments provided by this invention, it should be understood that the disclosed methods, apparatuses, and systems can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for example, the division of units is merely a logical functional division, and other division methods may exist in actual implementation; for example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0081] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0082] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can be physically comprised separately, or two or more units can be integrated into one unit. The integrated unit described above can be implemented in hardware or in the form of hardware plus software functional units.

[0083] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for implementing atomic operations on a multi-bit register, wherein the multi-bit register includes a write port, a set operation interface, and a clear operation interface; characterized in that, The method includes: Data is written to the multi-bit register via the write port; When it is necessary to modify the data in the multi-bit register, the data modification operation can be completed directly through the set operation interface or the clear operation interface in one step, wherein: If a non-zero value needs to be assigned to the multi-bit register, the set operation interface is enabled, and the non-zero target value is transmitted to the data bus. The non-zero target value on the data bus is written to the multi-bit register by controlling the multiplexing signal. If it is necessary to assign a 0 value to the multi-bit register, the clear operation interface is enabled, and a non-zero data is transmitted to the data bus. The multiplexer signal controls the input of all-zero data values ​​to the multi-bit register.

2. The method according to claim 1, characterized in that, The method further includes: A control signal is generated based on all the bits of data in the multi-bit register; The multiplexing signal is generated based on the control signal and the current operation signal. The operation signal includes: a write operation signal for controlling the write port, a set operation signal for controlling the set operation interface, and a clear operation signal for controlling the clear operation interface.

3. A circuit for implementing atomic operations on a multi-bit register, characterized in that, The circuit includes a multi-bit register, which includes a write port, a set operation interface, and a clear operation interface. The write operation module is used to output a write operation signal to control the write port to write data to the multi-bit register; The modification operation module is used to output a set operation signal or a clear operation signal when it is necessary to modify the data in the multi-bit register, so as to control the set operation interface or the clear operation interface to complete the data modification operation in one step; when it is necessary to assign a non-zero value to the multi-bit register, it outputs the set operation signal to control the set operation interface to write a non-zero target value to the multi-bit register; when it is necessary to assign a zero value to the multi-bit register, it outputs the set operation signal to control the clear operation interface to write a non-zero value to the multi-bit register. The selection module is used to output the data on the data bus corresponding to each operation signal according to the selection control signal.

4. The circuit according to claim 3, characterized in that, The circuit also includes: The control signal generation module is used to generate the selection control signal based on all bit data of the multi-bit register and the current operation signal. The operation signal includes: a write operation signal for controlling the write port, a set operation signal for controlling the set operation interface, and a clear operation signal for controlling the clear operation interface.

5. The circuit according to claim 4, characterized in that, The control signal generation module includes: a first OR gate, a first AND gate, and a second AND gate; The first OR gate takes the multi-channel data input signal of the multi-bit register as input and outputs a judgment signal. The first AND gate takes the set operation signal and the judgment signal as inputs and outputs a set selection signal; The second AND gate takes the clear operation signal and the judgment signal as inputs and outputs a clear selection signal; The selection module inputs the write operation signal, the set selection signal, and the clear selection signal; when the write operation signal is valid, it writes data to the multi-bit register through the write port; when the set selection signal is valid, it writes a non-zero target value to the multi-bit register through the set operation interface; when the clear selection signal is valid, it writes a non-zero value to the multi-bit register through the clear operation interface.

6. The circuit according to claim 5, characterized in that, The selection module includes: a third selector, a second selector, and a first selector connected in sequence; The control terminal of the third selector receives the write operation signal, and the first input terminal and the second input terminal of the third selector respectively receive the multi-channel data input signal of the multi-bit register and the multi-channel data output signal of the multi-bit register, and output the first data signal. The control terminal of the second selector receives the clear selection signal, and the first input terminal and the second input terminal of the second selector respectively receive the first data signal and the all-zero data value to be written for the clear operation, and output the second data signal. The control terminal of the first selector receives the set selection signal, the first input terminal and the second input terminal of the first selector receive the second data signal and the multi-channel data input signal of the multi-bit register respectively, and the output terminal is connected to the data input terminal of the multi-bit register.

7. The circuit according to claim 6, characterized in that, The second selector includes: a first inverter and a third AND gate; The first inverter receives the reset selection signal; One input of the third AND gate is connected to the output of the first inverter, the other input of the third AND gate receives the first data signal, and the output of the third AND gate outputs the second data signal.

8. The circuit according to claim 5, characterized in that, The selection module includes a 3-to-1 selector, wherein the three control terminals of the 3-to-1 selector are respectively input to the write operation signal, the set selection signal, and the clear selection signal; the three input terminals of the 3-to-1 selector are respectively input to the multi-channel data input signal of the multi-bit register, the multi-channel data output signal of the multi-bit register, and the all-zero data value to be written for the clear operation; and the output terminal of the 3-to-1 selector is connected to the data input terminal of the multi-bit register.

9. The circuit according to claim 5, characterized in that, The selection module includes: a second OR gate, a 2-to-1 selector, a second inverter, and a fourth AND gate; The second OR gate receives the write operation signal and the set selection signal, respectively. The control terminal of the 2-to-1 selector is connected to the output terminal of the second OR gate. The first input terminal and the second input terminal of the 2-to-1 selector are respectively input to the multi-channel data input signal of the multi-bit register and the multi-channel data output signal of the multi-bit register. The reset selection signal is input to the second inverter; The two inputs of the fourth AND gate are connected to the output of the second inverter and the output of the 2-to-1 selector, respectively, and the output of the fourth AND gate is connected to the data input of the multi-bit register.

10. A chip, characterized in that, Includes the circuitry for implementing atomic operations of multi-bit registers as described in any one of claims 3 to 9.

11. An electronic device, characterized in that, Includes the circuitry for implementing atomic operations of multi-bit registers as described in any one of claims 3 to 9.

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