Expandable high-speed signal processing board VPX-FPGA-D690T

Abstract

The application relates to an extensible high-speed signal processing board VPX-FPGA-D690T, and belongs to the technical field of signal processing, in particular to an extensible high-speed signal processing board. The processing board is good in flexibility, has an SRIO port outside, can realize seamless interconnection with other SRIO interface supporting board cards, and facilitates high-speed data transmission between the boards; the board card defines an interface based on FPGA high-speed serial and source synchronous transmission on a VPX connector, facilitating construction of a stronger signal processing platform; the board has two connectors meeting the FMC+ standard, defines an interface based on FPGA high-speed serial and source synchronous transmission, and is used for realizing function expansion of the signal processing board.

Description

Technical Field

[0001] This invention relates to the scalable high-speed signal processing board VPX-FPGA-D690T, belonging to the field of signal processing technology, and specifically to a flexibly expandable high-speed signal processing board. Background Technology

[0002] High-speed signal processing boards are currently widely used in radar, military, aerospace, and other fields. The requirements for high-speed signal processing boards vary across these fields, and this demand continues to increase with technological advancements. Currently, the domestic market offers various types of high-speed signal processing boards, but most can only meet specific application needs, lacking flexibility and versatility. Summary of the Invention

[0003] The technical problem solved by this invention is to overcome the shortcomings of the prior art and propose a scalable high-speed signal processing board, VPX-FPGA-D690T. This signal processing board can flexibly realize high-speed real-time signal processing and multi-standard data interconnection, and is compatible with domestic and imported chips. This design aims to meet the needs of various fields and develop a high-performance signal processing board that is flexibly configurable, has strong expansion capabilities, strong versatility, and conforms to mainstream industry standards.

[0004] The technical solution of this invention is:

[0005] The scalable high-speed signal processing board VPX-FPGA-D690T includes three processing nodes, a configuration node, a crossbar interconnect chipset, and two extended FMC+ interfaces.

[0006] Connection relationship: The two FMC+ interfaces are connected to the first processing node and the second processing node respectively. High-speed data is received through the two FMC+ interfaces and transmitted to the FPGA in the first processing node and the second processing node. The FPGA in the first processing node and the second processing node completes the signal processing. The FPGA in the first processing node and the second processing node are both connected to 2GB DDRIII-SDRAM to buffer the received data. The DSP (model FT-M6678) in the third processing node is used to assist the FPGA in the first processing node and the second processing node in completing the signal processing.

[0007] The three processing nodes are interconnected via a high-speed standard bus between the nodes on the board.

[0008] The three processing nodes can also be interconnected with the boards via a high-speed standard bus through the interconnect chipset.

[0009] The configuration node is model FMQL45T900, and it has a gigabit Ethernet interface for remote information exchange and control.

[0010] The DSP chip in the third processing node has a gigabit Ethernet interface for remote information interaction and control.

[0011] The high-speed communication protocols of the scalable high-speed signal processing board VPX-FPGA-D690T mainly include: PCIe, SRIO, high-speed serial transmission, source synchronous transmission, and gigabit Ethernet.

[0012] The scalable high-speed signal processing board VPX-FPGA-D690T is in the openVPX 6U standard form factor.

[0013] The scalable high-speed signal processing board VPX-FPGA-D690T operates on an industrial control computer platform.

[0014] The three processing nodes are a first processing node, a second processing node, and a third processing node. The first processing node consists of a JFM7VX690T and 2GB of DDR3-SDRAM, the second processing node consists of a JFM7VX690T and 2GB of DDR3-SDRAM, and the third processing node consists of an FT-M6678 and 2GB of DDR3-SDRAM.

[0015] The configuration node consists of an FMQL45T900 and 2GB of DDR3-SDRAM;

[0016] The crossbar switch interconnect chipset includes a first interconnect chip and a second interconnect chip. The first interconnect chip is an SRIO switch with an NRS1800 model, and the second interconnect chip is a PCIe switch with an SM8619 model. The first interconnect chip serves as an SRIO bus switching device between processing nodes within and between boards, and the second interconnect chip serves as a PCIe bus switching device between processing nodes within and between boards.

[0017] The interconnection network of the nodes (including 3 processing nodes and 1 configuration node) can transmit data based on the interconnection mode of SRIO protocol, the interconnection mode based on PCIe protocol, the high-speed serial transmission mode based on FPGA, the LVDS source synchronous transmission mode based on FPGA, and the network mode based on Gigabit Ethernet.

[0018] The JFM7VX690T in the first processing node has four 4x SRIO interfaces connected to the first interconnect chip;

[0019] The JFM7VX690T in the second processing node has four 4x SRIO interfaces connected to the first interconnect chip;

[0020] The FT-M6678 in the third processing node has two SRIO interfaces connected to the JFM7VX690T in the first processing node;

[0021] The first interconnect chip of the scalable high-speed signal processing board VPX-FPGA-D690T has four 4xSRIO interfaces connected to the VPX connector to enable inter-board interconnection.

[0022] High-speed point-to-point data transmission can be achieved between any two nodes (including 3 processing nodes and 1 configuration node) through the first interconnect chip;

[0023] The JFM7VX690T in the first processing node has one PCIe interface connected to the second interconnect chip;

[0024] The JFM7VX690T in the second processing node has one PCIe interface connected to the second interconnect chip;

[0025] The FT-M6678 in the third processing node has one PCIe interface connected to the second interconnect chip;

[0026] The FMQL45T900 in the configuration processing node has one PCIe interface connected to the second interconnect chip;

[0027] The second interconnect chip has two PCIe interfaces that connect to the VPX connector to achieve inter-board interconnection;

[0028] High-speed point-to-point data transmission can be achieved between any two nodes (including 3 processing nodes and 1 configuration node) through a second interconnect chip;

[0029] The third processing node connects to the FPGA in the first processing node, the FPGA in the second processing node, and the FPGA in the configuration node through the EMIF synchronization interface, enabling high-speed data transmission between processing nodes within the board.

[0030] The first processing node and the second processing node exchange data via a high-speed serial protocol.

[0031] The first processing node connects to the VPX connector via a high-speed serial protocol to achieve inter-board interconnection.

[0032] The second processing node connects to the VPX connector via a high-speed serial protocol to achieve inter-board interconnection.

[0033] Data exchange between the first and second processing nodes is achieved via LVDS;

[0034] The first processing node connects to the VPX connector via LVDS to achieve inter-board interconnection;

[0035] The second processing node connects to the VPX connector via LVDS to achieve inter-board interconnection.

[0036] Beneficial effects

[0037] (1) This invention relates to the scalable high-speed signal processing board VPX-FPGA-D690T, which belongs to the field of signal processing technology, and specifically relates to a flexibly expandable high-speed signal processing board.

[0038] The processing board of this invention offers high flexibility. It features an external SRIO port, enabling seamless interconnection with other SRIO-enabled boards and facilitating high-speed data transmission between boards. The board defines interfaces for high-speed serial and source-synchronous transmission based on FPGA on its VPX connectors, facilitating the construction of more powerful signal processing platforms. The board also has two FMC+ compliant connectors, defining interfaces for high-speed serial and source-synchronous transmission based on FPGA, enabling functional expansion of the signal processing board.

[0039] (2) The processing board of the present invention has strong controllability. The SM8619 is a PCIe protocol switching chip, which enables the industrial control computer to identify each processing node in the signal processing board and monitor the operating status of the signal processing board in real time. The FMQL45T900 and FT-M6678 can both be used as gigabit Ethernet ports, which enable the industrial control computer to monitor the operating status of the signal processing platform in real time through the Ethernet port.

[0040] (3) This invention is a flexibly expandable high-speed signal processing board VPX-FPGA-D690T and a method for constructing various high-speed interconnect networks on the board. This invention addresses the problem that current high-speed signal processing boards on the domestic market generally only meet certain application needs, lacking flexibility and versatility. It designs this product and is compatible with domestic chips, achieving a 100% domestic production rate. The high-speed signal processing board is designed based on the openVPX6U standard. To maximize the board's processing performance within the limited area of ​​the circuit board, the board uses two high-performance domestic FPGAs and one high-performance domestic DSP as processing nodes, and one configuration FPGA as a configuration node. The board is designed with two FMC+ interfaces, connecting the two FPGA processing nodes respectively, providing strong expansion capabilities. Furthermore, the board's interconnect mode is flexible. Multiple high-speed serial interconnect paths and source-synchronous interconnect paths exist between the two processing FPGAs on the board and other processing nodes and connectors within the board, enabling high / low-speed data transmission within and between the boards. The DSP and each FPGA are interconnected via EMIF interfaces, allowing data transmission between the DSP and FPGA. The board includes one SRIO switch chip and one PCIe switch chip as the processing node interconnect chipset. Each processing node within the board is interconnected via the SRIO bus and the PCIe bus, and connects to other boards via VPX connectors. Data and command exchange within and between boards can be achieved through the SRIO / PCIe bus. The board can also exchange control information and monitor its operating status with an industrial control computer platform via a network port. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of the structural composition of the processing board of the present invention. Detailed Implementation

[0042] The following is a detailed description of this high-speed signal processing board with reference to the accompanying drawings.

[0043] This high-speed signal processing board is designed according to the openVPX 6U standard, and its structural block diagram is as follows: Figure 1 As shown, the board adopts a motherboard-daughterboard structure, with two internal FMC+ interfaces for connecting FMC / FMC+ daughter boards. Each of the two FMC+ connectors has a custom interface that connects to an FPGA (JFM7VX690T). Different functional daughter boards can be installed according to actual needs, such as using a signal acquisition daughter board for analog signal acquisition, a signal playback daughter board for analog signal playback, a fiber optic transmission daughter board to expand the board's transmission bandwidth, and a solid-state storage daughter board to expand storage capacity, etc.

[0044] To maximize signal processing capabilities within the limited area of ​​the signal processing board, two processing FPGA chips (JFM7VX690T), one DSP (FT-M6678) as a processing node, and one configuration FPGA (FMQL45T900) as a configuration node are placed on the motherboard. The board primarily uses the processing FPGA chip for signal processing, while the DSP chip acts as a coprocessor to assist the processing FPGA. The configuration FPGA is used to interact with the industrial control computer platform and control the nodes within the board based on this information.

[0045] The board contains multiple high-speed serial transmission paths for high-speed data transmission between the various processing chips within the board and for high-speed data transmission to external devices. There are four 4x high-speed serial ports interconnected between the two processing FPGA chips (JFM7VX690T) on the board, used for data transmission between the two FPGAs, with a line rate of up to 10.3125Gbps. Each FPGA has four 4x high-speed serial ports interconnected with the VPX connector, four 4x high-speed serial ports interconnected with the corresponding FMC+ interface, and two 4x high-speed serial ports interconnected with the corresponding optical module, used for high-speed data transmission and reception by each FPGA, with a line rate of up to 10.3125Gbps.

[0046] In addition to high-speed serial interconnects, the board also includes multiple source synchronous interconnect transmission paths. These are used for low-speed data transmission between the various processing chips on the board and between the board and external systems. There are 20 pairs of LVDS differential interconnects between the two processing FPGA chips (JFM7VX690T) on the board, used for data transmission between the two FPGAs, with a line rate of up to 1.25Gbps. Each FPGA has 20 pairs of LVDS differential interconnects with the VPX connector, 84 pairs of LVDS differential interconnects with the FMC+ port, and 10 pairs of LVDS differential interconnects with the onboard headers. All of these enable source synchronous interconnect transmission between the board and external systems, with a line rate of up to 1.25Gbps. Furthermore, the onboard DSP chip and each FPGA chip are interconnected via EMIF interfaces. The EMIF interface connected to the configuration FPGA chip has a 16-bit data bandwidth, and the EMIF interface connected to the processing FPGA chip has a 32-bit data bandwidth, supporting synchronous transmission mode. The DSP chip can transmit data with each FPGA through the EMIF interface.

[0047] The board supports multiple standard bus protocols, primarily SRIO and PCIe. It houses one SRIOSwitch chip (NRS1800) and one PCIe Switch chip (SM8619) for data interconnection. The SRIOSwitch chip has 12 4x SRIO bus ports with a maximum line rate of 5Gbps. Four of these ports are connected to each of the two processing FPGAs, and four more are connected to the VPX connector for interconnection with other boards. Additionally, the DSP chip has two fixed 4x SRIO ports, each connected to one of the two processing FPGAs. These connections form an SRIO interconnect network, enabling point-to-point data transmission between the board's processing nodes.

[0048] The on-board PCIe switch chip acts as the board's PCIe bus switching device. It connects to each of the two processing FPGAs via one 1x PCIe port, to the DSP chip via one 4x PCIe port, and to the configuration FPGA via one 1x PCIe port. The chip also connects to two 4x PCIe ports via a VPX connector for connecting to an industrial control computer platform. The industrial control computer platform identifies each processing node within the signal processing board through the PCIe bridge device, monitors the board's operating status in real time, and can also send commands to the configuration FPGA via the PCIe bus to control the functions of each processing node. Furthermore, both the on-board configuration node (FMQL45T900) and the DSP chip (FT-M6678) have Gigabit Ethernet ports, which can be connected to the front panel or VPX backplane to exchange control information with the industrial control computer platform.

[0049] Each processing node (FPGA, DSP) within the signal processing board is connected to 2GB of DDR3-SDRAM, which can be expanded to 4GB as needed, for caching high-speed data. Additionally, each processing node is connected to a FLASH chip, enabling automatic program loading for each FPGA and DSP chip upon power-up.

[0050] The signal processing board has multiple clock requirements for each processing node. This board provides the overall clock signal through an external reference clock or a crystal oscillator clock input + clock driver chip. The crystal oscillator clock frequencies are mainly 100MHz, 125MHz, and 156.25MHz. The various chips on the board have multiple power requirements. This board uses Shenzhen Guowei's SM4650, SM4644, and SM51200 power chips to power each chip. The board uses a health status monitoring sensor (LTM2990) to monitor the operating status of each chip on the board, including ambient temperature, operating voltage, and current. It can acquire board health information in real time and feed it back to the on-board configuration FPGA via the I2C bus. After the configuration FPGA summarizes the data, it outputs it to the industrial control computer platform via the network port.

Claims

1. The scalable high-speed signal processing board VPX-FPGA-D690T, characterized in that: The scalable high-speed signal processing board VPX-FPGA-D690T includes three processing nodes, a configuration node, a crossbar interconnect chipset, and two extended FMC+ interfaces; the two extended FMC+ interfaces are the first extended FMC+ interface and the second extended FMC+ interface; the three processing nodes are the first processing node, the second processing node, and the third processing node; the crossbar interconnect chipset includes the first interconnect chip and the second interconnect chip. The first FMC+ interface is connected to the first processing node; The second FMC+ interface is connected to the second processing node; High-speed data is received through the first FMC+ interface and transmitted to the FPGA in the first processing node. High-speed data is also received through the second FMC+ interface and transmitted to the FPGA in the second processing node. Signal processing is performed by the FPGAs in the first and second processing nodes. Both the FPGAs in the first and second processing nodes are connected to 2GB of DDRIII-SDRAM for buffering the received data. The three processing nodes are interconnected via a high-speed standard bus between the nodes on the board. The three processing nodes can also be interconnected with the boards via a high-speed standard bus through the interconnect chipset; The configuration node is model FMQL45T900, and it has a gigabit Ethernet interface for remote information exchange and control. The DSP chip in the third processing node has a gigabit Ethernet interface for remote information interaction and control. The first processing node consists of a JFM7VX690T and 2GB of DDR3-SDRAM, the second processing node consists of a JFM7VX690T and 2GB of DDR3-SDRAM, and the third processing node consists of an FT-M6678 and 2GB of DDR3-SDRAM. The configuration node consists of an FMQL45T900 and 2GB of DDR3-SDRAM; The first interconnect chip is an SRIO switch, model number NRS1800, and the second interconnect chip is a PCIe switch, model number SM8619. The first interconnect chip serves as an SRIO bus switching device between processing nodes within and between boards, and the second interconnect chip serves as a PCIe bus switching device between processing nodes within and between boards. The JFM7VX690T in the first processing node has four 4x SRIO interfaces connected to the first interconnect chip; The JFM7VX690T in the second processing node has four 4x SRIO interfaces connected to the first interconnect chip; The FT-M6678 in the third processing node has two SRIO interfaces connected to the JFM7VX690T in the first processing node; The first interconnect chip of the scalable high-speed signal processing board VPX-FPGA-D690T has four 4x SRIO interfaces connected to the VPX connector to enable inter-board interconnection; High-speed point-to-point data transmission can be achieved between any two nodes through the first interconnect chip; The JFM7VX690T in the first processing node has one PCIe interface connected to the second interconnect chip; The JFM7VX690T in the second processing node has one PCIe interface connected to the second interconnect chip; The FT-M6678 in the third processing node has one PCIe interface connected to the second interconnect chip; The FMQL45T900 in the configuration processing node has one PCIe interface connected to the second interconnect chip; The second interconnect chip has two PCIe interfaces that connect to the VPX connector to achieve inter-board interconnection; High-speed point-to-point data transmission can be achieved between any two nodes via a second interconnect chip; The third processing node connects to the FPGA in the first processing node, the FPGA in the second processing node, and the FPGA in the configuration node through the EMIF synchronization interface, enabling high-speed data transmission between processing nodes within the board. The first processing node and the second processing node exchange data via a high-speed serial protocol. The first processing node connects to the VPX connector via a high-speed serial protocol to achieve inter-board interconnection. The second processing node connects to the VPX connector via a high-speed serial protocol to achieve inter-board interconnection. Data exchange between the first and second processing nodes is achieved via LVDS; The first processing node connects to the VPX connector via LVDS to achieve inter-board interconnection; The second processing node connects to the VPX connector via LVDS to achieve inter-board interconnection.

2. The scalable high-speed signal processing board VPX-FPGA-D690T according to claim 1, characterized in that: The DSP in the third processing node assists the FPGA in the first and second processing nodes in completing signal processing.

3. The scalable high-speed signal processing board VPX-FPGA-D690T according to claim 2, characterized in that: The DSP in the third processing node is model FT-M6678.

4. The scalable high-speed signal processing board VPX-FPGA-D690T according to claim 1, characterized in that: The high-speed communication protocols of the scalable high-speed signal processing board VPX-FPGA-D690T mainly include: PCIe, SRIO, high-speed serial transmission, source synchronous transmission, and gigabit Ethernet. The scalable high-speed signal processing board VPX-FPGA-D690T is in the openVPX 6U standard form factor. The scalable high-speed signal processing board VPX-FPGA-D690T operates on an industrial control computer platform.

5. The scalable high-speed signal processing board VPX-FPGA-D690T according to claim 1, characterized in that: The interconnected network of each node can transmit data based on the SRIO protocol interconnection mode, the PCIe protocol interconnection mode, the FPGA-based high-speed serial transmission mode, the FPGA-based LVDS source synchronous transmission mode, and the Gigabit Ethernet network mode.

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