memory

Abstract

The present disclosure provides a memory device including a 3D data memory and a 3D reference memory. The reference memory is used to generate a reference signal for sensing data in the data memory. A conversion circuit converts a signal from a group of memory cells in the reference memory into the reference signal. The reference signal is applied to a sense amplifier to sense data stored in a selected memory cell in the data memory.

Description

Technical Field

[0001] This disclosure relates to circuit configurations for sensing data in memory integrated circuits, and more particularly to 3D nonvolatile memory integrated circuits. Background Technology

[0002] In high-density memories, such as RAMs, process, voltage, and temperature (PVT) conditions have varying impacts on the performance of memory cells across different devices and within individual devices. This issue is reflected in the design of sensing circuits. For example, some sense amplifier schemes involve generating a voltage from a selected memory cell and comparing that voltage to a reference voltage. The voltage generated from the selected memory cell can vary depending on the PVT conditions in different parts of the device and within individual devices. These variations extend the sensing margins between the data states required by the sensing circuit. When the sensing margins are high, high-voltage sensing circuits are needed for reliable operation. High-voltage sensing circuits may not be compatible with modern memory technologies or may be difficult to implement alongside them.

[0003] Furthermore, such variations in the reference voltage can help extend the sensing margin. For example, the reference voltage can be generated using a bandgap reference. However, bandgap reference circuits are affected by process and temperature variations, and these variations can differ from the behavior of memory cells. This problem with PVT variations also helps extend the sensing margin required for reliable operation.

[0004] The aim is to provide a technology that can improve the sensing margins in high-density memories, such as 3D flash memory.

[0005] Public content

[0006] A technique is described for a memory device comprising a data memory and a reference memory, wherein the reference memory is used to generate a reference signal for sensing data in the data memory. The reference signal can track the PVT conditions of memory cells in the data memory, thereby achieving better sensing boundaries for high-density memories including high-density 3D flash memory.

[0007] A memory device is described, comprising a data memory and a reference memory, having a conversion circuit that converts signals from a group of memory cells in the reference memory into a reference signal. The reference signal is applied to a sensing amplifier to sense data stored in selected memory cells in the data memory.

[0008] The data memory and reference memory may include a matching 3D memory structure, wherein signals from a group of memory cells in the reference memory are combined to track the PVT characteristics of the memory cells in the data memory.

[0009] Furthermore, a memory device is described, comprising a data memory and a reference memory, having a conversion circuit that converts signals from a first group of memory cells in the reference memory to generate a first reference signal, and converts signals from a second group of memory cells in the reference memory to generate a second reference signal. One of the first and second reference signals is selected based on a region in the data memory accessed for retrieval, and applied to a sensing amplifier to sense data stored in the selected memory cell in the data memory.

[0010] Various embodiments of the reference memory are described. In one example, the reference memory includes a plurality of memory cells, comprising passive memory cells and an active group of memory cells. The active group of memory cells is connected to a region reference bit line and to a reference word line in the reference memory. A conversion circuit combines signals from the region reference bit lines of the active group of memory cells to generate a reference signal.

[0011] The reference memory described herein may comprise a stacked structure with multiple layers, each layer containing a stack of horizontal word lines and a collection of vertical conductors in a separate layer of the stacked structure. Memory cells have horizontal channels between adjacent vertical conductors in the layer of horizontal word lines of the stack. Groups of memory cells are disposed in one layer of the multiple layers and are used to generate the reference signal as described above. The stack of horizontal word lines contains reference word lines for the group of memory cells. A reference word line driver applies a word line reference voltage to the reference word lines and applies a deselect voltage to other word lines in the reference memory. Vertical conductors for the memory cells in the group are connected to region reference bit lines that may cover the stack. Region reference bit lines are connected to conversion circuitry to generate reference signals.

[0012] In the described embodiment, a first group of memory cells in the reference memory is disposed on a word line layer of the lattice, and a second group of memory cells in the reference memory is disposed on a second word line layer of the lattice. In the described embodiment, a first group of memory cells in the reference memory is disposed on a layer of the lattice, and a second group of memory cells in the reference memory is disposed on another layer of the lattice.

[0013] An embodiment of the conversion circuit may include a summing node at which currents from memory cells in a group of memory cells in a reference memory are summed to produce a total current. The total current is applied to a current mirror circuit that mirrors the total current, thereby dividing the total current into target current levels for the reference current. The reference current may be applied to a current / voltage converter to generate a reference signal that serves as the input to a voltage comparator in a sense amplifier.

[0014] Further embodiments and advantages of the present disclosure will become apparent upon review of the following drawings, detailed description, and claims. Attached Figure Description

[0015] Figure 1 is a layout diagram of an integrated circuit device including a data memory and a reference memory.

[0016] Figure 2 is a plan view of the 3D memory structure used to implement the brick shown in Figure 1.

[0017] Figure 3 shows the cross-section of the guide pillars and layers in the XY plane of the 3D memory structure shown in Figure 2.

[0018] Figure 4 shows a cross-section along line A-A' as shown in Figure 3.

[0019] Figure 5 shows a cross-section along line B-B' as shown in Figure 3.

[0020] Figure 6 is a circuit diagram of part of the memory structure in the 3D memory structure shown in Figure 2.

[0021] Figure 7 is a schematic circuit diagram of the 3D memory structure shown in Figure 2.

[0022] Figure 8 is a perspective view of the 3D configuration of the 3D memory structure shown in Figure 2.

[0023] Figure 9 is a circuit diagram of the data memory and reference memory used in the device shown in Figure 1.

[0024] Figure 10A is a plan view of a 3D memory structure that can be used to implement a reference memory for a reference system as shown in Figure 1.

[0025] Figure 10B is a perspective view of the 3D configuration of the reference memory structure shown in Figure 10A.

[0026] Figure 11 is a perspective view of a sheet of memory structure as shown in Figure 10A, which includes a group of memory cells for generating reference signals.

[0027] Figure 12 is a schematic diagram of the reference memory shown in Figure 10A.

[0028] Figure 13 is a diagram illustrating the architecture of a memory device, which includes a data memory and a reference memory.

[0029] Figure 14 shows the sensing circuit of the memory device, which includes multiple sensing amplifiers.

[0030] Figures 15A and 15B show the read and access status of the data memory that can be distinguished in the reference system.

[0031] Figures 16A and 16B show a group of memory cells in a reference memory that can generate reference signals for the situations shown in Figures 15A and 15B.

[0032] Figures 17A, 17B, and 17C show the read and access status of the data storage device, which can be distinguished in the reference system.

[0033] Figures 18A and 18B show groups of memory cells in a reference memory that can generate reference signals for the cases in Figures 17A, 17B, and 17C.

[0034] Figure 19 is a perspective view of the slab structure of the memory structure shown in Figure 10A, which includes three groups of memory cells that generate reference signals.

[0035] Figure 20 is a perspective view of two layers of the memory structure shown in Figure 10A, which contains three groups of memory cells that generate reference signals.

[0036] Figure 21 shows the sensing circuit of a memory device that includes multiple sensing amplifiers and supports multiple read access scenarios.

[0037] Figure 22 is a simplified block diagram of an integrated circuit memory device containing two groups of reference cells in a reference memory.

[0038] Figure 23 is a simplified block diagram of an integrated circuit memory device containing three groups of reference cells in a reference memory.

[0039] Figure 24 is a flowchart that can be executed by control circuitry to program the threshold voltage of a memory cell in a reference memory.

[0040] Explanation of reference numerals in the attached figures

[0041] 0, 1: Plane

[0042] 101: Second Surrounding Area

[0043] 102: Reference System

[0044] 103. SA(1)~SA(K): Sensing amplifier circuit

[0045] 104: Compensation capacitor

[0046] 105, 1365, 1462, 2162: Input / output contacts

[0047] 108: First Surrounding Area

[0048] 110, 780, 880, 932, 1302, 1440: Global bit lines

[0049] 111, 130: Bricks

[0050] 121, 122, 123, 124, 125, 126, 127, 128: Columns

[0051] 210A, 210B, 210C, 210D, 210E, 210F, 210G, 210H, 210I, 701, 1010, 1020, 1030, 1300: Layers

[0052] 211, 212, 213, 214, 311, 702, 911, 1001, 1002, 1003, 1004: Horizontal letter lines

[0053] 215, 216, 217, 218, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1021, 1022, 102 3. 1024, 1025, 1026, 1027, 1028, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038: contacts

[0054] 219, 330, 331, 332, 333, 10111, 1110, 1111, 1112, 1113, 1120, 2010, 2011, 2012, 2013, 2020, 2021, 2022, 2023: Guide Posts

[0055] 219B, 219S, 320, 321, 912: Vertical conductors

[0056] 220, 1040: Bit-line transistor structure

[0057] 230, 801, 1051: Stacked structures

[0058] 231: Regional bit lines and source line conductors

[0059] 322: Data Storage Structure

[0060] 323: Semiconductor Channel Materials

[0061] 650, 741, 915, LSL(1), LSL(2): Regional source lines

[0062] 651, 721, 830, 913, LBL(1), LBL(2): Regional bit lines

[0063] 660, 960, 961, 962, 963, 971: Memory units

[0064] 720, 820, 930, 980, 1072, 1301: Bit line transistors

[0065] 740, 940, 990: Source-line transistors

[0066] 745: Grounding symbol

[0067] 760: Intermediate conductor

[0068] 810: Peripheral Circuit Area

[0069] 811, 2230, 2330: Word line decoders

[0070] 855, 860, 881, 1060, 1065, 1066: Pins

[0071] 900, 2200, 2300: Data storage devices

[0072] 910: Selected memory cell

[0073] 922, 1080: Reference level lines

[0074] 940, 990: Source Select Transistors

[0075] 942: Common source line

[0076] 950: Reference Memory

[0077] 951. WL(1), WL(2), WL(j-1), WL(j), WL (y, z), WL (y, z+1), WL (y+1, z), WL (y+1, z+1): word line

[0078] 953, 1052, 1055, LRBL: Regional reference bit lines

[0079] 970, 1258: Signage

[0080] 982: Common Reference Line

[0081] 983, 1280, 1350: Conversion circuits

[0082] 992: Common Reference Source Line

[0083] 998, 1268, 1410, 1433, 1450, 1451, 1452, 1453, 2140, 2150, 2151, 2152, 2153, A-A', B-B': Line

[0084] 999: Sensing Circuit

[0085] 1041: Source-line transistor structure

[0086] 1050, 1402: Groups

[0087] 1056: Regional Reference Source Line

[0088] 1058: Current Flow

[0089] 1071: Word line driver

[0090] 1090: Reference memory peripheral circuitry

[0091] 1100, 1900, 1910, 1911, 1912, 1913, 2000, 2001: Guide post area

[0092] 1102, 1104, 1902, 1904, 2002, 2004: Stepped contact structure

[0093] 1130, 1251, 1930A, 1930B, 1930C, 2030A, 2030B, 2030C, WL(A), WL(B), WL(C): Selected word lines

[0094] 1135, 1252, 1935, 2035: Unselected word lines

[0095] 1150, 1950A, 1950B, 1950C, 2050A, 2050B, 2050C: Location

[0096] 1220, 1312: Active layers

[0097] 1221, 1222: Floating laminates

[0098] 1250: Reference word line driver

[0099] 12511: Deselect drive

[0100] 1261, 1314: Reference bit line transistors

[0101] 1262: Reference-source line transistor

[0102] 1263: Global Reference Common Source Line

[0103] 1265: Global Reference Bitline

[0104] 1271: Unit

[0105] 1285, 2120, 2121, 2122, 2123, 2235, 2335: Sensing amplifiers

[0106] 1310: Reference Brick

[0107] 1311, 1313: Passive Layers

[0108] 1315: Summarize Node

[0109] 1351, 1352: PMOS transistors

[0110] 1353, 1354: NMOS transistors

[0111] 1355: Reference current I REF

[0112] 1356, 1431: Capacitors

[0113] 1361, 1441: Current / Voltage Converter

[0114] 1362: Voltage comparator

[0115] 1363, 1461, 2161: Output buffers

[0116] 1368, 1369: Nodes

[0117] 1370, 1404, 2110A, 2111B, 2112C: Switches

[0118] 1401, 2110, 2111, 2112: Modules

[0119] 1403: Current Mirror Circuit

[0120] 1410, 2140: Signal lines

[0121] 1420, 1421, 1422, 1423: Sensing modules

[0122] 1432: Transistor

[0123] 1434: Load Balancing Capacitor

[0124] 1435, I / V: Current / Voltage Converter

[0125] 1436, SA_K: Comparator

[0126] 2210, 2310: Controller

[0127] 2220, 2320: Bias voltage generator

[0128] 2251, 2351: First group

[0129] 2252, 2352: Second group

[0130] 2353: Third Group

[0131] 2410, 2420, 2430, 2440, 2450, 2460: Steps

[0132] Bank: Grouping

[0133] GBL_k: Global bit line

[0134] I REF I REF_A I REF_B I REF_C Current

[0135] VD, Vm, Vm(A), Vm(B), Vm(C), VR: Voltage

[0136] VR: Reference Signal

[0137] V READ Bias voltage

[0138] V REF V REF_A V REF_B V REF_C Reference voltage Detailed Implementation

[0139] Please refer to Figures 1 to 24 and compare them with the detailed description of the embodiments of the present disclosure.

[0140] Figure 1 is a layout diagram of an integrated circuit device including a data memory and a reference memory. In this example, the integrated circuit memory device in the layout has a data memory region having two planes, plane 0 and plane 1. Each plane includes an individual array of bricks (e.g., brick 111). In some embodiments, the bricks include a 3D multilayer structure, examples of which are described in more detail below.

[0141] Bricks are arranged in columns, such as columns 121 to 128 in plane 0. In each plane, rows of bricks are called banks, such as Bank K in plane 1. In this example, each bank contains redundant bricks for memory redundancy operations, such as Red. Brick 130. In this figure, each brick is labeled 16Mb, indicating that each brick contains a memory cell sufficient to store 16 Megabits of data. In this example, two planes, each containing 64 bricks, provide a memory with a capacity of 2 Gigabits, where each brick contains 16Mb of memory cells. Of course, other brick sizes and other plane sizes can be used. Embodiments of the memory device may, for example, have a capacity of approximately Terabits.

[0142] A first peripheral region 108 exists between plane 0 and plane 1, which contains peripheral circuitry supporting memory operations. Additionally, a second peripheral region 101 to the left of plane 0 and plane 1 also contains peripheral circuitry supporting memory operations.

[0143] As illustrated schematically, the first peripheral region 108 includes sensing circuitry comprising multiple sense amplifier (SA) circuits (e.g., SA circuitry 103) connected to individual rows in planes 0 and 1. A global bit line (GBL) 110, also referred to as a data bit line, shown above the rows in plane 0, includes bricks 111 and extends to the corresponding sense amplifier circuitry 103. Multiple global bit lines (not shown) may be implemented above each row of bricks, capable of sensing multiple side-by-side memory cells from a selected brick.

[0144] As shown in the figure, multiple sense amplifier circuits include sense amplifier circuits SA(1) to SA(K), each corresponding to a row in plane 0 and plane 1. Each sense amplifier circuit may include a sense amplifier for each global bit line in the row.

[0145] In this layout, the second peripheral region 101 includes other peripheral circuitry coupled to the input / output contact 105 and the reference system 102, the other peripheral circuitry including input / output drivers (not shown).

[0146] In some embodiments, reference system 102 includes a reference memory comprising a 3D multilayer structure that matches the bricks in the data memory. Reference system 102 generates one or more signals by biasing a group of memory cells. These one or more signals are converted into reference signals in a conversion circuit located in a first or second peripheral region, the reference signals being used as a reference for a sense amplifier circuit (e.g., SA circuit 103) sensing data in the data memory. The capacitance of the signal path from reference system 102 to the sense amplifier circuit may differ from the capacitance of the signal path from a selected brick in the data memory to the global bit line included in the sense amplifier circuit. Therefore, compensation capacitor 104 is included on the signal path of the reference signal. In one embodiment, for capacitance matching purposes, compensation capacitor 104 may include a virtual global bit line whose structure matches the structure of the global bit line. In embodiments where a group of sense amplifiers comprising sense amplifiers for a given plane shares a reference current generator, compensation capacitor 104 may be shared, and a virtual global bit line may be provided for compensation capacitor 104 in the given plane. In another embodiment, where individual reference current generators are provided for each row and each sense amplifier, the compensation capacitor 104 may be individually used for each row, and each row may have a virtual global bit line. Other capacitor structures of appropriate size for capacitor matching can save area, including MOS capacitors (MOS transistor structures having source and drain connected together at one node and gates forming another node to form capacitor terminals), metal-insulator-metal MIM capacitors (containing terminals formed in patterned conductor layers separated by interlayer dielectrics or intermetallic dielectrics), and various types of junction capacitors. In one example, the compensation capacitor 104 may include a MOS capacitor with a relatively thin gate dielectric, thereby achieving substantial area savings.

[0147] The embodiments of the technology described herein can be referenced to an integrated circuit memory having the layout shown in FIG1. ​​Of course, other layout configurations suitable for a particular embodiment may be utilized.

[0148] The sensing circuitry distinguishes high / low threshold voltage states in the data memory by comparing the reference cell current with the target cell current. Multiple memory cells in the reference memory can be connected together via conversion circuitry, for example, by connecting regional reference bit lines together to a common reference bit line, to average noise and improve sensing margins. Multiple memory cells in the reference memory can be configured for simultaneous programming, erasing, and reading. A threshold fine-tuning scheme can be used to program memory cells in the reference memory to approach the reference cell at a level higher than the target sensing current factor, and then this factor can be reduced using a current mirror circuit that stores PVT conditions in the reference memory or other conversion circuitry. Furthermore, the reference memory can use a smaller word line (WL) bias (e.g., 5.5V) during data memory reads, but the same global bit line bias as the array (e.g., 1.8V).

[0149] For reference memory, a small array area (X / Y: 20 micrometers to 30 micrometers) for process uniformity can be used to implement microarrays that use the same process technology to form data memory.

[0150] The reference system can be located in the peripheral area of ​​the memory device to maintain array uniformity of the data storage. On the other hand, the capacitive load of the memory cells used in the data memory can be much larger than the capacitive load of the memory cells used in the reference memory. To balance the capacitive load between the reference signal path and the data signal path, similar capacitive loads (e.g., MOS capacitors or MIM capacitors) can be added to the reference signal path.

[0151] More than one reference signal can be introduced to cover off-center cells (e.g., edge WL cells). Furthermore, to obtain sensing boundaries, different numbers of cells in different groups can be summed, or different reference voltages V can be used for different groups. REF .

[0152] Figure 1 illustrates an example of a memory, including a data memory comprising a 3D configuration of memory cells, each memory cell comprising one or more data memory rows. Each data memory row comprises a distinct set of global bit lines, the distinct set of global bit lines having at least one member and multiple distinct bricks. Each distinct brick in each data memory row comprises multiple region bit lines and multiple word lines coupled to the memory cells of the distinct brick, and bit line transistors are configured to connect the multiple region bit lines of the distinct brick to corresponding global bit lines in the distinct set of global bit lines for the data memory row. The memory also includes a reference memory comprising a 3D configuration of memory cells. The reference memory comprises multiple region reference bit lines and multiple word lines coupled to the memory cells of the reference memory, and bit line transistors are configured to connect the multiple region reference bit lines to reference bit lines for the reference memory. The memory includes conversion circuitry for converting signals from the reference bit lines into reference signals. The memory shown in Figure 1 includes one or more distinct sets of sense amplifiers. Each disjoint set is coupled to the disjoint set of the global bit lines of one or more data memory rows and coupled to a conversion circuit to sense data stored in a selected memory cell in the corresponding data memory row in response to a comparison of the memory array signal on the disjoint set of the global bit lines with a reference signal.

[0153] Figure 2 is a plan view of an example of a brick implemented by a 3D multilayer structure containing memory cells for data storage, which can be used in the device shown in Figure 1. The brick includes a stacked structure 230 and a bit-line transistor structure 220.

[0154] In this embodiment, the stack structure 230 includes multiple sheets 210A to 210I. Each sheet contains a set of horizontal word lines (e.g., 211, 212, 213, 214 for sheet 210A) in a particular layer of the stack. For simplicity, only four layers are shown. In this embodiment, each sheet contains multiple guide posts (e.g., 219) extending through the horizontal word lines of the sheets in the stack structure.

[0155] Each post includes an insulating filler having a vertical conductor 219S configured as a region source line and a vertical conductor 219B configured as a region bit line. Although not shown in the figures, the semiconductor channel material surrounding the insulating filler of the post provides a channel for a memory cell in a layer of horizontal word lines extending between the vertical conductors configured as region bit lines and the vertical conductors configured as region source lines. An unfolded illustration of the post is shown in Figures 3 through 5. The description of the 3D memory shown in Figure 2 is provided in co-owned U.S. Patent Application No. 17 / 170,542, filed February 8, 2021, entitled "CurvedcHANNEL MEMORY DEVICE," which is incorporated herein by reference as fully set forth herein.

[0156] Each layer comprises a set of vertical conductors configured for region bit lines and a set of vertical conductors configured for region source lines. In this example, each layer comprises two offset columns of pillars. Overlaying the stacked structure in the patterned conductor layers are multiple region bit line and source line conductors 231 (only a subset of the pillars in each layer is shown in the figure, but the region bit line and source line conductors cover all pillars used as memory). The region bit line conductors 231 in the set extend to the bit line transistor structure 220, which is connected to the global bit line via a bit line select transistor, the global bit line covering all the bricks in the row as discussed above. In this configuration, in each layer of the bricks, the region bit line conductor is connected to a vertical conductor configured as a region bit line conductor. Similarly, the source line conductors 231 in the set are connected to the source-side bias circuit via a source select transistor (not shown).

[0157] In this example, the horizontal word lines are connected to the corresponding word line drivers via contacts (e.g., contacts 215 to 218) in a stepped structure on each side of the stack-up structure.

[0158] Figure 3 is an unfolded view of the four posts 330, 331, 332, and 333 in the layered stack structure shown in Figure 2. A horizontal word line (WL) 311 surrounds posts 330 to 333 in the stack. Each post 330 to 333 includes an insulating filler filled with a semiconductor channel material (e.g., 323). A data storage structure (e.g., 322) surrounds the semiconductor channel material. The data storage structure may be a dielectric charge trapping structure comprising multiple dielectrics, including one or more layers configured as tunneling layers, one or more layers configured as charge trapping layers, and one or more layers configured as barrier layers.

[0159] Figure 4 shows a cross-section taken along line A-A' as shown in Figure 3. Figure 5 shows a cross-section taken along line B-B' as shown in Figure 3.

[0160] In Figure 4, a horizontal word line 311 is positioned on word line layer WL5. The post 333 includes an insulating core with vertical conductors 320 and 321 contacting semiconductor channel material 323 (not shown) to form the source / drain terminals for the memory cell in each word line layer. In Figure 5, the cross-section does not span the vertical conductors. It shows the insulating filler surrounded by semiconductor channel material 323. Furthermore, a data storage structure 322 is disposed between the semiconductor channel material and the word line.

[0161] Figure 6 is a circuit diagram of a portion of the memory structure in the 3D memory structure shown in Figure 2, illustrating a portion of two slab layers and two word line layers. Vertical conductors configured as region source lines (e.g., 650) and region bit lines (e.g., 651) extend vertically through the stacked structure. Memory cells (e.g., 660) extend between the vertical conductors configured as region source lines and the vertical conductors configured as region bit lines. The first slab layer, labeled "y", contains word lines WL(y, z) and WL(y, z+1). The second slab layer, labeled "y+1", contains word lines WL(y+1, z) and WL(y+1, z+1), where the word line layer is indicated by "z" and the slab position within the brick is indicated by "y". The position of individual region bit lines along columns in the slab layer will be indicated by "x" in the XYZ coordinate system. In this example, for each of the two layers, the region bit line LBL(1) for x = 1, the region bit line LBL(2) for x = 2, and the region source line LSL(1) and the region source line LSL(2) are described for the two stacks of the cell.

[0162] Figure 7 provides a perspective view of layer 701. Layer 701 comprises a stack of horizontal word lines 702. A collection of conductors configured as regional bit lines (e.g., 721) and a collection of conductors configured as regional source lines (e.g., 741) are disposed above this layer 701 and connected to corresponding vertical conductors. The collection of regional source lines is connected to source line transistors 740 to connect the regional source lines to a source-side bias circuit, indicated by ground symbol 745, which may include a common source line. In some embodiments, the source-side bias circuit may provide a voltage other than ground. The collection of regional bit lines is connected to a collection of bit line transistors 720. In this example, the collection of bit line transistors 720 connects the regional bit lines to corresponding global bit lines 780 via an intermediate conductor 760. Different regional bit lines in the layer may be biased on different layers depending on operation and thereby connected to independent global bit lines. In some embodiments, multiple region bit lines share a single global bit line and are connected one at a time to the corresponding region bit lines due to row decoding on the bit line transistors.

[0163] The embodiments shown in Figures 3 to 7 can implement NOR flash memory devices and AND flash memory devices, with separate region source lines and region bit lines for each stack of memory cells. Alternatively, the embodiments may include virtual grounded NOR flash memory devices and virtual AND flash memory devices, wherein vertical conductors may be shared between adjacent stacks of memory cells and configured to operate as both region bit lines (or region reference bit lines in reference memory) and region source lines (or region reference source lines in reference memory). Descriptions of the virtual ground NOR structure and the virtual AND structure are provided in U.S. Patent Application No. 17 / 170,542 (MXIC 2314-1), filed February 08, 2021, entitled "Curved Channel 3D Memory Device," and U.S. Patent Application No. 17 / 230,114 (MXIC2318-1), filed April 14, 2021, entitled "3D Virtual Ground Memory and Manufacture Methods for SAME," which are incorporated herein by reference as fully set forth herein.

[0164] This document describes embodiments of a memory, including a memory integrated circuit comprising a plurality of bricks arranged in a row and a row arranged in a plane. Each brick in the data memory includes: a plurality of layers, a plurality of vertical conductors, a data storage structure, and a semiconductor channel material. Each of the plurality of layers comprises a stack of alternating layers of insulating material and word line material, the layers of word line material being configured as word lines among a plurality of word lines. The plurality of vertical conductors are separated by insulating posts disposed through the stack and configured as region bit lines among a plurality of region bit lines. The data storage structure is disposed on the inner surface of the layers of word line material at the intersection of the insulating posts and the layers of word line material. The semiconductor channel material is located between the insulating posts and the data storage structure at the intersection of the layers of insulating posts and the layers of word line material, the semiconductor channel material forming a conductive path for the memory cell between source / drain terminals in adjacent vertical conductors. Furthermore, the memory includes: a reference array, a plurality of vertical conductors, a data storage structure, and a semiconductor channel material. The reference array comprises multiple reference layers, each of which includes a stack of alternating layers of insulating material and word line material, the word line material layers being configured as reference word lines among multiple reference word lines. Multiple vertical conductors are separated by insulating posts disposed through the stack and configured as multiple region reference bit lines. A data storage structure is disposed on the inner surface of the word line material layer at the intersection of the insulating posts and the word line material layer. Semiconductor channel material is located between the insulating posts and the data storage structure at the intersection of the insulating posts and the word line material layer, forming a conductive path for the memory cell between the source / drain terminals in adjacent vertical conductors.

[0165] This document describes embodiments of a memory comprising a memory integrated circuit including a plurality of bricks arranged in a row and a row arranged in a plane. Each brick in the data memory includes a plurality of layers, and each of the plurality of layers includes alternating layers of insulating material and word line material and a stack of a plurality of vertical posts passing through the alternating layers. Some or all of the layers of word line material are configured as word lines among a plurality of word lines. Each of the plurality of vertical posts includes a first vertical conductor, a second conductive post, a first vertical conductor among the plurality of posts, a second vertical conductor among the plurality of vertical posts, a data storage structure, and a semiconductor channel material. The second conductive post is separated from the first conductive post by an insulator. The first vertical conductor among the plurality of posts is configured as a region bit line among a plurality of region reference bit lines. The second vertical conductor among the plurality of vertical posts is configured as a region source line. The data storage structure is disposed on the inner surface of the layer of word line material at the intersection of the vertical post and the layer of word line material. The semiconductor channel material is located between the insulator and the data storage structure at the intersection of the vertical post and word line material layers. The semiconductor channel material forms the conductive path of the memory cell between the source / drain terminals in the first vertical conductor and the second vertical conductor in the vertical post. The reference array also includes multiple reference layers, each of which comprises alternating layers of insulating material and word line material and a stack of multiple vertical pillars passing through the alternating layers. One or more of the word line material layers are configured as reference word lines among multiple reference word lines. Each of the multiple vertical pillars includes a first vertical conductor, a second conductive pillar, a first vertical conductor among the multiple pillars, a second vertical conductor among the multiple vertical pillars, a data storage structure, and a semiconductor channel material. The second conductive pillar is separated from the first conductive pillar by an insulator. The first vertical conductor among the multiple pillars is configured as a region reference bit line among multiple region reference bit lines. The second vertical conductor among the multiple vertical pillars is configured as a region source line. The data storage structure is disposed on the inner surface of the word line material layer at the intersection of the vertical pillar and the word line material layer. The semiconductor channel material is located between the insulator and the data storage structure at the intersection of the vertical pillar and the word line material layer, and the semiconductor channel material forms a conductive path for the memory cell between the source / drain terminals of the first vertical conductor and the second vertical conductor in the vertical pillar.

[0166] Figure 8 shows a 3D configuration of the region bit lines 830 and the global bit lines 880 above the stack structure 801 of bricks in different patterned conductor layers. In this figure, the region bit lines 830 are configured in the patterned conductor layers covering the stack structure. The global bit lines 880 are configured in the patterned conductor layers covering the region bit lines 830. The spacing of the global bit lines 880 in the x-direction can be larger than that of the region bit lines. Thus, for example, a group of four region bit lines 830 can share a single global bit line. Bit line transistors operate to select the current region bit line for a specific addressed cell from the group of region bit lines. Vertical conductors (not shown) pass through the stack structure and are configured to connect to the corresponding region bit lines 830 as discussed above. The region bit lines 830 extend into the region of the stack structure adjacent to the bricks and are connected to the bit line transistors 820 on the substrate via pins 855 or other interlayer connections. Bit line transistors connect the region bit lines of the selected brick to global bit lines (e.g., GBL 880) via pins 860 or other interlayer connections. Global bit lines 880 extend across the brick to a sense amplifier in a peripheral circuitry area 810 for row arrangement and are connected via pins 881 or other interlayer connection structures. In this example, the word line decoder 811 is positioned under the stack-up structure using techniques such as under-array CMOS.

[0167] Figure 9 is a circuit diagram of a memory device (e.g., the memory device of Figure 1) including a data memory 900 and a reference memory 950. The data memory 900 is shown in the schematic diagram of Figure 6. The data memory 900 includes a source line select transistor (SLT) 940 that connects a region source line to a common source line (CSL) 942. Additionally, the data memory 900 includes a bit line transistor 930 that connects a selected region bit line (e.g., 913) to a global bit line (GBL) 932. The bit line transistor 930 decodes selected region bit lines marked with a "checkmark," and unselected region bit lines are marked with an "X" to select one region bit line at a time. A bias configuration for a read operation on the selected memory cell 910 is shown. The selected memory cell 910 is disposed on a horizontal word line 911 and a region bit line 913 connected to the selected memory cell 910 via a vertical conductor 912. In this embodiment, the source line transistor 940 is also decoded to select the regional source line 915 while not connecting other regional source lines. The word line 951 receives a bias voltage VREAD, the regional source line 915 connected to the common source line 942 receives a reference voltage of 0V, and the regional bit line 913 is connected to the global bit line 932 via the bit line transistor 930. The global bit line 932 is biased to the bit line read voltage in the sensing circuit 999.

[0168] Reference memory 950 has the same schematic structure. Reference memory 950 includes a source line select transistor (SLT) 990 that connects the regional reference source line to the common reference source line 992. Furthermore, reference memory 950 includes a bit line transistor (BLT) 980 that connects the selected regional reference bit line (e.g., 953) to the reference bit line (RBL) 982.

[0169] The reference memory is configured such that its PVT characteristics match those of the data memory. Therefore, the reference memory may have the same three-dimensional configuration as the data memory and may be manufactured using the same manufacturing process. In some embodiments, the memory cells in the reference memory have the same dimensions as the memory cells in the data memory. In some embodiments, the memory cells in the reference memory are manufactured using the same manufacturing process as the memory cells in the data memory and have the same dimensions as the memory cells in the data memory.

[0170] In this example, a reference memory 950 is biased to select a group of memory cells, which is used to generate a reference signal on line 998 via a sensing circuit 999. During a read operation, the horizontal word line 951 receives the reference voltage V. REF Reference voltage V REF It can be different from the read voltage V applied to the data storage. READ Unselected word lines in the same layer and unselected word lines in an unselected layer can be biased to a common deselect voltage, such as ground.

[0171] Memory cells 960, 961, 962, and 963 on a region reference bit line (e.g., 953) are coupled to bit line transistors 980, all of which are turned on to couple the group of region reference bit lines for all memory cells 960 to 963 in the group to a common reference bit line 982. Furthermore, the region reference source lines of memory cells 960, 961, 962, and 963 are coupled to source line transistors 990, all of which are turned on to couple the group of region reference source lines to a common source line (CSL) 992. During a read operation, the common reference bit line 982 and the common reference source line 992 can be biased to the same voltage as the global bit lines in the data memory. In this embodiment, the current of the regional reference bit line is summed at the summing node of the bit line transistor 980 and applied to the reference bit line 982, which is connected to other parts of the conversion circuit 983. This summing node can be considered part of the conversion circuit. The summed current is converted into a reference signal on line 998 in the conversion circuit 983 and applied to the sensing circuit 999. The reference signal on line 998 can be compared with the signal on the global bit line 932 in the sensing circuit to indicate the data in the selected memory cell stored in the data memory 900.

[0172] In an unselected layer of reference memory 950, the vertical conductor can be disconnected from the region reference bit line, as shown at reference 970, disconnecting memory cell 971 from region reference bit line 953. This can be statically achieved by omitting the vertical connection between the vertical conductor in the stack structure and the overlay patterned metal layer in which the region bit line is disposed. Furthermore, this can be achieved by omitting the region reference bit line from the stack structure, which does not contain a group of memory cells to be utilized.

[0173] In this example, four memory cell groups in a statically selected layer of a statically selected slab of the reference memory are utilized to generate a reference signal for any memory cell in the memory array. The number of memory cells in the groups can be varied to suit a particular embodiment, but it can be found that four memory cell groups provide good characteristics for the reference signal to be used for sensing all or most of the memory cells on the data memory in a 3D configuration.

[0174] Figure 10A is a plan view of an example 3D configuration of the memory cells of the reference memory, which can be used to utilize the bricks in the device shown in Figure 1 (the bricks in Figure 2). Figure 10B is a perspective view of a 3D configuration of the reference memory structure shown in Figure 10A. The reference memory includes a stacked structure comprising three layers 1010, 1020, and 1030, as in this example, and a bit line transistor structure 1040. The reference memory structure shown in Figure 10B can be configured as described above relative to Figure 8. Furthermore, it includes a source line transistor structure. The source line transistor structure can be disposed on the same side as the bit line transistor structure 1040, or on the opposite side as shown.

[0175] Each layer 1010, layer 1020, and layer 1030 contains a stack of horizontal word lines. For example, layer 1020 contains horizontal word lines 1001, 1002, 1003, and 1004 in four corresponding word line layers. The number of word line layers can be the same as the number of word line layers implemented in the data memory.

[0176] Each layer 1010, 1020, and 1030 includes a plurality of posts (e.g., post 10111) extending through the stacked structure of the layer. As shown in the structure of Figure 2, each post includes a vertical conductor configured as a region source line and a vertical conductor configured as a region bit line. A semiconductor channel material surrounds the insulating filler of the post to provide a channel for memory cells in the layer of horizontal word lines, and extends between the vertical conductor configured as a region bit line and the vertical conductor configured as a region source line. The reference memory can be implemented in the same manner as the data memory discussed above.

[0177] In a data memory, for example, each layer contains two offset columns of pillars. The stacked structure covering the patterned conductor layer consists of multiple region reference bit lines (e.g., 1055) and region reference source lines (e.g., 1056). The region reference bit lines extend to bit line transistor structure 1040 for connection to the switching circuitry described above. The region reference source lines extend to source line transistor structure 1041 for connection to a source-side bias circuitry that may include a common source line.

[0178] In the reference memory, a reference signal is generated using a group of memory cells 1050. In this example, the group of memory cells 1050 is positioned in a layer 1020 on a horizontal word line 1002. The group of memory cells 1050 is used to generate the reference signal and can be a statically selected group, which is automatically biased when a group is selected as a reference cell. The group can be statically selected by connecting an unselected word line to a deselect bias voltage (e.g., ground) using its contacts. In this example, contacts 1021, 1022, and 1024 (and optionally contacts 1028, 1026, and 1025) in layer 1020 are connected to the deselect bias voltage. Contact 1027 (and optionally contact 1023) is connected to a reference word line voltage driver to receive voltage V during read operations for the data storage. REF .

[0179] The current flow through the memory cells is shown in Figure 10A. The current flow 1058 of the reference memory cell in group 1050 flows along the region reference bit line 1055 to the memory cell of the layer of word line 1002, across the memory cell, to the vertical conductor configured as a region source line, and to the region reference source line 1056. This current flows along the region reference source line 1056 to the source line transistor structure 1041. In this case, there are four pillars in group 1050, and the currents from the four memory cells on the layer of word line 1002 are summed in the bit line structure as described above.

[0180] In the unselected layers 1010 and 1030 of this example, the vertical conductors in the posts are omitted from the vertical connections between the covered area reference source line and the area reference bit line. Similarly, the word line driver circuitry that applies a bias voltage to the selected layer 1020 can disconnect from contacts 1031 to 1034 and contacts 1035 to 1038 in layer 1030, and can disconnect from contacts 1011 to 1014 and contacts 1015 to 1018 in layer 1010. Other techniques for disconnecting the unselected layer connections can also be used.

[0181] In this example, there are three slabs in the reference memory stack-up structure. The first and third slabs are dummy slabs disconnected from the circuitry used to generate the reference signal. Slab 1020 (an active slab) is positioned between the first and third slabs. By positioning the active slab 1020 between the dummy slabs, the PVT characteristics of the active slab can be matched to the PVT characteristics of the data memory over a wider range of conditions.

[0182] In some embodiments, more than three slabs may exist in the reference memory stack-up. For example, in some embodiments, five slabs may exist.

[0183] In Figure 10B, a region reference bit line 1052 is disposed in a patterned conductor layer covering the stacked structure. A reference bit line 1080 is disposed in the patterned conductor layer covering the region reference bit line 1052. Bit line transistors operate to connect a group of region reference bit lines 1052 for a group of memory cells to reference bit line 1080. Vertical conductors (not shown) are disposed through the stacked structure and connected to the corresponding region reference bit lines 1052 as discussed above. The region reference bit line 1052 extends to a region adjacent to the stacked structure 1051 and is connected to a bit line transistor 1072 on the substrate via a pin 1065 or other interlayer connector. The bit line transistor 1072 connects the region reference bit line to the reference bit line 1080 of the switching circuit via a pin 1060 or other interlayer connector. The reference bit line 1080 extends across the stacked structure in this example to a region on a device containing other components of the switching circuit. This region may be adjacent to a sense amplifier circuit for data storage. Furthermore, reference bit line 1080 is connected via pin 1066 to reference memory peripheral circuitry 1090 on the substrate. Reference memory peripheral circuitry 1090 includes control circuitry and bias circuitry for programming and verification operations, which are used to set threshold states of memory cells in the reference memory and are applied during data storage read operations. In some embodiments, threshold voltage fine-tuning operations for the reference memory can be controlled by wafer sorting tools in a manufacturing plant. The control and bias circuitry can perform the process described below with reference to FIG24 to set and fine-tune the threshold voltages of memory cells in the reference memory.

[0184] Some or all of the word line drivers (XDEC) 1071 used for the reference memory can be configured under a stacked structure using techniques such as under-array CMOS.

[0185] In the embodiment of FIG10B, the reference memory stack structure matches the brick structure in the data memory relative to the configuration of the bit line transistors and word line drivers. In some embodiments, other configurations for these components may be used.

[0186] Figure 11 is a perspective view of a slice in a reference stack for a reference memory. The slice includes stepped contact structures 1102 and 1104 on opposite sides, and a post region 1100. For the purposes of this figure, horizontal word lines are not shown in the post region. The slice includes multiple posts (e.g., post 1120) arranged in two offset columns as described with reference to Figure 10A. Groups of memory cells (in position 1150) on posts 1110, 1111, 1112, and 1113 of the selected word line 1130 are configured to generate reference signals. Posts 1110, 1111, 1112, and 1113 are connected to individual region reference bit lines LRBL, while other posts in the slice are not connected to the region reference bit lines in this example. Region reference source lines are not shown in the figure.

[0187] The selected word line 1130 is connected to the applied voltage V REF The word line driver or other bias circuitry. Unselected word lines (e.g., 1135) are connected to a word line driver or other bias circuitry that applies a deselection voltage (e.g., ground). In this example, all word lines except the selected word line 1130 are unselected word lines, and a group of cells of the selected word lines is used to generate a reference signal.

[0188] Figure 12 is a circuit diagram of a reference memory (the reference memory of Figures 10A and 11). The reference memory includes an active chip layer 1220 and two floating chip layers 1221 and 1222 disposed on opposite sides of the active chip layer 1220. Each chip layer contains an array of memory cells in an xz plane, where x is the word line direction and z is the vertical direction. The floating chip layers are not connected to the region reference bit lines or region reference source lines shown in this diagram. In some embodiments, the floating chip layers may be biased by a deselection voltage of the horizontal word line.

[0189] The reference word line driver 1250 will use the reference voltage V REFA selected word line 1251 is applied to the active layer 1220. A deselect driver 12511 applies a deselect voltage to an unselected word line (e.g., 1252) of the active layer 1220. Region reference bit lines and region reference source lines of the reference memory are connected to corresponding vertical conductors in the active layer 1220 at location 1258. Floating or passive layers are not connected to region reference bit lines and region reference source lines. In this example, the group of memory cells containing memory cells 1271 used to generate the reference signal comprises four cells, and therefore four region reference bit lines and four region reference source lines exist. The region reference bit lines are connected to a reference bit line transistor RBLT(X4) 1261, which connects them together to a global reference bit line 1265 in a switching circuit 1280 that generates a reference signal in response to the combined current of the region reference bit lines of the selected group. The regional reference source line is connected to the reference source line transistor RSLT(X4) 1262, which together connects it to the global reference common source line 1263.

[0190] A reference signal is applied to the output of the conversion circuit 1280 on line 1268 to the sense amplifier 1285.

[0191] Figure 13 illustrates a memory device (e.g., a chip layer 1300 containing data) and bit line transistors 1301. The chip layer 1300 and bit line transistors 1301 connect selected region bit lines (not shown) to global bit lines 1302. The global bit lines are connected to a current / voltage converter 1361 to generate a voltage VD at node 1369 on the input of a voltage comparator 1362. The current / voltage converter 1361 can be implemented in various circuits containing, for example, resistors or transistors. Voltage VD represents the current in the global bit lines from the selected memory cell during a read operation, thereby representing the data stored in the selected memory cell.

[0192] Furthermore, the memory device includes a reference memory, such as a reference brick 1310. The reference brick includes an active slab layer 1312 comprising a group of reference cells and passive slab layers 1311 and 1313 on opposite sides of the active slab layer 1312. The passive slab layers are floating or biased in a deselected state. The reference brick 1310 includes a reference bit line transistor 1314 connecting a region reference bit line to a summing node 1315 in the switching circuit 1350.

[0193] The conversion circuit 1350 includes a current mirror circuit that sums the currents (M*I) from the memory cell group in the active layer 1312. refConverted to reference current I ref The aforementioned current mirror circuit includes one or more PMOS transistors 1351 having a relative effective channel width M = 4. The drain of transistor 1351 is connected to summing node 1315. The source of transistor 1351 is connected to VDD (not shown). The gate of transistor 1351 is connected to its drain. The aforementioned current mirror circuit also includes one or more PMOS transistors 1352 having a relative effective channel width M = 1. The drain of transistor 1352 is connected to the drain of NMOS transistor 1353. The source of transistor 1352 is connected to VDD (not shown). The gate of transistor 1352 is connected to the gate of transistor 1351. Transistor 1353 has a source connected to ground and a gate connected to its drain. In summary, transistors 1352 and 1353 mirror the current in transistor 1351, the current being divided in magnitude by the ratio of the relative effective transistor widths of transistors 1351 and 1352.

[0194] The gate of NMOS transistor 1353 is used as a current mirror gate reference, and a voltage Vm is provided at the gate of NMOS transistor 1354 to generate a reference current I. REF 1355. Switch 1370 is positioned between transistors 1353 and 1354 as shown to connect and disconnect reference brick 1310.

[0195] In this embodiment, a reference current I is applied. REF A current / voltage converter 1361 is used to generate a reference signal VR at node 1368 at the input of the voltage comparator 1362. The current / voltage converter 1361 is implemented in various circuits containing, for example, resistors or transistors. The reference signal from the memory cell group is obtained from the voltage Vm and reference current I in this circuit. REF And voltage VR implementation.

[0196] The capacitance of the data path from the data memory to the comparator can be significantly different from the capacitance of the signal path from the reference memory to the comparator. In this embodiment, capacitor 1356 is provided in the signal path from the reference memory to the comparator 1362. Capacitor 1356 can be implemented as described above with reference to the compensation capacitor 104 of FIG1. ​​In one example, capacitor 1356 is a MOS capacitor, comprising a MOS transistor whose source and drain are connected together as one terminal and whose gate is another terminal. Alternatively, a metal-insulator-metal (MIM) capacitor or other capacitor structure can be used. In some embodiments, capacitor 1356 may include a virtual global bit line. In some embodiments, capacitor 1356 may include a virtual global bit line in conjunction with a trimmer capacitor. Capacitor 1356 has capacitance that compensates for the different capacitances on the reference signal path and the data signal path.

[0197] The output of comparator 1362 is a data signal, which is applied to a data path circuit, which in this simplified example includes an output buffer 1363 connected to an input / output contact 1365 of a memory device.

[0198] Figure 14 illustrates an embodiment in which a reference memory is used to generate a current mirror reference voltage Vm, which is distributed to a plurality of sense amplifiers, such as for a row of memory cells in the layout of Figure 1 or for all sense amplifiers in a planar or multi-planar sense circuit.

[0199] In Figure 14, module 1401 of the reference system includes a group 1402 of memory cells from the reference memory, which is coupled to a summing node and a current mirror circuit 1403. Referring to Figure 13, the current mirror circuit 1403 generates an output voltage Vm as discussed with reference to Figure 13. A switch 1404 may be provided in the circuit to connect or disconnect this module 1401 from the sensing circuit.

[0200] A voltage Vm is applied to signal line 1410 to multiple sensing modules 1420, 1421, 1422, and 1423. The sensing amplifiers in this embodiment may all have the same implementation. Therefore, taking sensing module 1420 as an example, sensing module 1420 includes a capacitor 1431 connected to signal line 1410 and the gate of transistor 1432. Capacitor 1431 is operable to stabilize the voltage Vm on signal line 1410. Transistor 1432 mirrors the current I from module 1401. REF To generate a current I on line 1433 in sensing module 1420 REFA load balancing capacitor 1434, used to compensate for the load difference between the reference memory and the data memory, is connected to line 1433. Line 1433 is connected to a current / voltage converter 1435, which applies a voltage VR as an input to comparator 1436. A sensing module 1420 is connected to a global bit line 1440 (e.g., GLB_1). The global bit line 1440 is connected to a current / voltage converter 1441, which applies a voltage VD to the input of comparator 1436. The output of comparator 1436 is a data signal connected to line 1450 of output buffer 1461. Output buffer 1461 drives the data signal at I / O contacts 1462 of the integrated circuit memory device.

[0201] Sensing module 1421 generates a data signal on line 1451. Sensing module 1422 generates a data signal on line 1452. Sensing module 1423 generates a data signal on line 1453. Lines 1451, 1452, and 1453 are also connected to output buffer 1461.

[0202] In the embodiments of Figures 13 and 14, a single group of memory cells in the reference memory is used to generate a reference signal, which can be applied to sense any memory cell in the data memory.

[0203] In some high-density memories that include memory (such as the memory described above), the PVT conditions of memory cells in different parts of the data memory may differ. Embodiments of the reference system described herein are designed to compensate for these differences.

[0204] For example, Figure 15A shows read operation case A in the data memory of the memory cells in the core of the array, where the core of the array includes memory cells on the intermediate layer of the stack. A read from the intermediate layer memory cell on word line WL(j-1) via word line WL(2) can be considered as read case A, which addresses the memory cell at the bottom layer of the stack on word line WL(1). Figure 15B shows read operation case B in the data memory of the memory cells on word line WL(j) in the top layer of the array. The PVT conditions of case A can be significantly different from those of case B. Therefore, the reference voltage to be used to sense the memory cells in both cases can be fine-tuned as described herein.

[0205] One method for fine-tuning the reference voltage is to define a group of memory cells in a reference memory used to generate the reference voltage. Therefore, Figure 16A shows a group of memory cells in a reference memory that can be used in combination to generate the reference signal in case A. In Figure 16A, the group of memory cells includes those connected to the receiving reference voltage V. REF_AThe four members of the common word line generate the current I of the four region reference bit lines. REF_A The four region reference bit lines are coupled in an aggregation node in the conversion circuit as described above to generate a reference voltage V for case A. REF_A .

[0206] Figure 16B shows a group of memory cells in a reference memory that can be used in combination to generate the reference signal for case B. In Figure 16B, the group of memory cells includes six members at the top layer of the reference memory connected to word lines that receive the reference voltage V. REF_B To generate current I in six region reference bit lines REF_B The six region reference bit lines are coupled in an aggregation node in the conversion circuit as described above to generate a reference voltage V for case B. REF_B .

[0207] The circuit in Case B may include a current mirror circuit that divides the combined current from the reference memory into six segments, thereby reflecting the usage of the six memory cells in the memory cell group. In some embodiments, the memory cell group for Case A is disposed in one layer of the reference memory, and the memory cell group for Case B is disposed in a different layer of the reference memory, with reference bit lines in the same or different regions. In other embodiments, the memory cell groups for Case A and Case B may be disposed in the same layer of the reference memory with reference bit lines in the same or different regions.

[0208] In large, high-density memories, more than two scenarios may exist. For example, Figures 17A, 17B, and 17C illustrate embodiments with three scenarios. Scenario A, shown in Figure 17A, involves access to the edge word line WL(1) at the bottom of the word line stack. Scenario B, shown in Figure 17B, involves access to intermediate word lines WL(2) through WL(j-1). Scenario C, shown in Figure 17C, involves access to the edge word line WL(j) at the top of the word line stack. The reference system may include three different groups of reference memories with memory cells, each group for one of scenarios A, B, and C.

[0209] Figures 18A and 18B illustrate another embodiment, in which access to the data storage is divided into two cases. Figure 18A shows case A, in which access to the edge word line WL(1) at the bottom of the stack and access to the edge word line WL(j) at the top of the stack both correspond to case A. Figure 18B shows case B, in which access to the middle word line WL(2) to the middle word line WL(j-1) of the word line layer is considered case B.

[0210] Figure 19 is a perspective view of a slice in a reference memory for illustrating scenarios A, B, and C. The slice includes stepped contact structures 1902 and 1904 on opposite sides, and a guide post area 1900. For the purposes of this figure, horizontal word lines are not shown in the guide post area. The slice includes multiple guide posts arranged in two offset columns as described with reference to Figure 10A. Three groups of memory cells (in positions 1950A, 1950B, and 1950C) on guide posts 1910, 1911, 1912, and 1913 of the slice for three distinct selected word lines WL(A) 1930A, WL(B) 1930B, and WL(C) 1930C are configured to generate reference signals for individual scenarios. Leads 1910, 1911, 1912, and 1913 are connected to the individual region reference bit line LRBL, while other leads in the layer are not connected to the region reference bit line in this example. The region reference source line is not shown in this figure.

[0211] Selected word line 1930A, selected word line 1930B, and selected word line 1930C are connected to the applied voltage V. REF_A Voltage V REF_B and voltage V REF_C Connect to the word line driver or other bias circuitry corresponding to the word line. Unselected word lines (e.g., 1935) are connected to the word line driver or other bias circuitry that applies a deselection voltage (e.g., ground).

[0212] Figure 20 is a perspective view of two active dies in a reference memory used to illustrate embodiments A, B, and C. In embodiments such as Figure 20, more than one active die is used, and these active dies can be separated from passive dies in the reference memory stack structure described above. In other embodiments, the two active dies shown may be adjacent dies. One or more passive dies may also exist between the active dies. Furthermore, in some embodiments, the active dies may be disposed in separate reference memory stack structures.

[0213] The active layers shown in FIG20 each include stepped contact structures (e.g., 2002 and 2004) at opposite ends and individual post regions 2000 and 2001. For the purposes of this figure, horizontal word lines are not shown in the post regions. Each layer includes multiple posts arranged in two offset columns as described with reference to FIG10A. A first group of memory cells in position 2050A in the post region 2000 of the first layer on the post 2010, post 2020, post 2012, and post 2013 of the selected word line 2030A of the bottom of the stack is configured to generate a reference signal for case A. Posts 2010, 2011, 2012, and 2013 are connected to the individual region reference bit lines LRBL of the LBRL group (A), while the other posts in the first layer are not connected to the region reference bit lines in this example. Region reference source lines are not shown in this figure.

[0214] On pillars 2020, 2021, 2022, and 2023 of two distinct selected word lines 2030B and 2030C, a second group of memory cells at position 2050B in the pillar region 2001 of the second layer and a third group of memory cells at position 2050C in the pillar region 2001 of the second layer are configured to generate reference signals for cases B and C. Pillars 2020, 2021, 2022, and 2023 are connected to the individual region reference bit lines LRBL of the LBRL group (B, C), while other pillars in the second layer are not connected to the region reference bit lines in this example. The region reference source lines are not shown in this figure. In other embodiments, the labels of the region reference bit lines and the labels of the memory cells may vary with reference to the cases described in Figures 16A and 16B.

[0215] Connect the selected word line 2030A, the selected word line 2030B, and the selected word line 2030C to the applied voltage V. REF_A Voltage V REF_B and voltage V REF_C Connect the word line driver or other bias circuitry to the corresponding word line. Connect the unselected word line (e.g., 2035) to the word line driver or other bias circuitry that applies a deselection voltage (e.g., ground).

[0216] Region reference bit line groups LRBL group (A) and LRBL group (B, C) can be respectively connected to a conversion circuit, which is enabled when the data memory accesses the mapping for individual cases. Alternatively, region reference bit line groups LRBL group (A) and LRBL group (B, C) can share a connection to the conversion circuit. Furthermore, in other embodiments, as shown with reference to FIG21, the conversion circuit may be configured with a separate current mirror circuit.

[0217] Figure 21 illustrates an embodiment of accessing different areas of a data memory, wherein the reference memory comprises three modules 2110, 2111, and 2112 for reference cells that generate multiple current mirror reference signal voltages Vm(A), Vm(B), and Vm(C) for cases A, B, and C, respectively. One of the reference signals is selected and assigned to multiple sense amplifiers, for example, for a row of memory cells in the layout shown in Figure 1, or for all sense amplifiers in a planar or multi-planar sense circuit.

[0218] In Figure 21, module 2110 of the reference system includes a first group of memory cells from the reference memory, the first group being coupled to a summing node and a current mirror circuit. The current mirror circuit generates an output voltage Vm (A) as shown with reference to Figure 13. A switch 2110A can be configured in the circuit to connect or disconnect this module 2110 from the sensing circuit.

[0219] The reference system module 2111 includes a second group of memory cells from the reference memory, the second group being coupled to a summing node and a current mirror circuit. The current mirror circuit, as previously described, generates an output voltage Vm(B). A switch 2111B may be provided in the circuit to connect or disconnect this module 2111 from the sensing circuit.

[0220] Module 2112 of the reference system includes a third group of memory cells from the reference memory, the third group being coupled to a summing node and a current mirror circuit. The current mirror circuit generates an output voltage Vm(B) as previously described. A switch 2112C may be provided in the circuit to connect or disconnect this module 2112 from the sensing circuit.

[0221] The first, second, and third groups of memory cells in the reference memory may be disposed on a single layer or multiple layers as described above. The first, second, and third groups of memory cells in the reference memory may also be disposed on a single set or multiple sets of region reference bit lines as described above. The first, second, and third groups of memory cells in the reference memory may contain the same number of reference memory cells, or may contain different numbers of reference memory cells, as described above.

[0222] For example, switches 2110A, 2111B, and 2112C are controlled by a read state machine, which can determine the area of ​​data memory being accessed based on, for example, a word line label or other address in the data memory. Based on the area being accessed, the state machine or other control circuitry determines which reference memory module will be connected to the sensing circuitry for the data memory, thereby closing the corresponding switch when the access to the data memory matches the area configured therein.

[0223] A selected signal Vm(A), signal Vm(B), and signal Vm(C) are applied to a plurality of sense amplifiers 2120, 2121, 2122, and 2123 on line 2140. The sense amplifiers in this embodiment all have the same implementation as described in FIG14. Therefore, sense amplifier 2120 includes a capacitor connected to signal line 2140 and a capacitor connected to the gate of a current mirror transistor. The transistor mirrors the current I from the selected module. REF_A Current I REF_B or current I REF_C To generate current I in the sensing amplifier 2120 REF A load balancing capacitor, used to compensate for the load difference between the reference memory and the data memory, is connected to the data path. Current is applied to a current-to-voltage converter, which applies a voltage as the input to comparator SA_K. A sense amplifier 2120 is connected to a global bit line (e.g., GBL_k). The global bit line is also connected to a current-to-voltage converter, which applies a voltage VD at the input of comparator SA_K. The output of comparator SA_K is the data signal on line 2150, which is connected to output buffer 2161. Output buffer 2161 drives the data signal at I / O contacts 2162 of the integrated circuit memory device.

[0224] Sensing amplifier 2121 generates a data signal on line 2151. Sensing amplifier 2120 generates a data signal on line 2152. Sensing amplifier 2123 generates a data signal on line 2153. Lines 2151, 2152, and 2153 are also connected to output buffer 2161.

[0225] Figure 22 is a simplified block diagram of a memory device implemented on a single integrated circuit, the memory device using a first group 2251 (REF A) of reference memory cells for case A and a second group 2252 (REF B) of reference memory cells for case B. The memory includes a data memory 2200 with peripheral circuitry, including a word line decoder 2230 driving selected word lines in the data memory and a sense amplifier SA 2235 sensing data on unselected word lines in the data memory. The memory device includes a controller 2210 and a bias voltage generator 2220, the bias voltage generator 2220 including a state machine or other circuitry for performing read, program, erase, and other operations on the data memory. Furthermore, the controller 2210 and the bias voltage generator 2220 are coupled to a reference memory system comprising the first group 2251 and the second group 2252 of reference memory cells. During operation, the controller 2210 determines the area in the data memory being accessed by the current read operation and enables one of the first group 2251 and the second group 2252 for the purpose of generating a reference signal to be used by the sense amplifier 2235.

[0226] As described above, a region in the data memory corresponding to case A may contain memory cells located on, for example, the top word line, the bottom word line, or the edge word line of both the top and bottom word lines. A region in the data memory corresponding to case B may contain all other memory cells on the intermediate layer of the word lines.

[0227] For example, case A can be extended to include accessing both bottom layers of the word line instead of just one bottom layer.

[0228] Furthermore, Case A and Case B can be applied to different groups of bricks in a large-scale memory as shown in Figure 1. For example, Case A can be applied to the edge bricks surrounding the perimeter of the brick array, while Case B can be applied to the inner bricks. Generally, Case A and Case B can be designed according to the specific implementation of the data memory to be contained in areas with relatively similar PVT conditions, so that it can be effectively sensed using a single group of memory cells in the reference memory.

[0229] Figure 23 is a simplified block diagram of a memory device implemented on a single integrated circuit chip or a multi-chip module, the memory device utilizing a first group 2351 (REF A) of reference memory cells for case A, a second group 2352 (REF B) of reference memory cells for case B, or a third group 2353 (REFC) of reference memory cells for case C. The technology can be extended to any number of reference memory cell groups.

[0230] The memory includes a data memory 2300 with peripheral circuitry, including a word line decoder 2330 that drives selected word lines in the data memory and a sense amplifier SA 2335 that senses data on unselected word lines in the data memory. The memory device includes a controller 2310 and a bias voltage generator 2320, which includes a state machine or other circuitry for performing read, program, erase, and other operations on the data memory. Furthermore, the controller 2310 and the bias voltage generator 2320 are coupled to a reference memory system comprising a first group 2351 and a second group 2352 of reference memory cells. In operation, the controller 2310 determines a region in the data memory being accessed by the current read operation and enables one of the first group 2351 and the second group 2352 for the purpose of generating a reference signal to be used by the sense amplifier 2335.

[0231] As mentioned above in Figures 10A and 10B, the memory device may include programming and verification circuitry (e.g., in peripheral circuitry 1090) for a reference memory. The programming and verification circuitry can be used to fine-tune the threshold values ​​of memory cells in the reference memory so that they operate within a desired target. For example, the designer can specify a current I... REF The target value is set. This value can be, for example, 10µA. Programming and verification circuitry can be connected to the reference bit line and executed to establish a combined value for a group (containing multiple reference memory cells) of reference memory cells to be applied, such that the combined current of the reference bit line equals the target value multiplied by the number of reference memory cells. In an embodiment containing four reference memory cells, where the target value is 10µA, the threshold of the reference memory cells in the group is fine-tuned to establish a combined current of 40µA. Unused memory cells in the reference memory can be programmed to a high threshold so that they are not conductive during operation.

[0232] Figure 24 is a simplified flowchart of a control algorithm that can be executed by a controller and bias circuitry associated with the reference memory. In some embodiments, this algorithm may be executed periodically in the field as needed to restore the conditions of the reference memory. In other embodiments, this algorithm may be executed only once during manufacturing, or after the device has been deployed in the field.

[0233] In this example, the algorithm begins (2410) by applying a "dumb" programming loop to an unselected word line commonly connected by word line drivers. A non-intelligent programming loop may simply involve applying a single high-voltage programming pulse sufficient to increase the threshold to a high threshold state. The algorithm then applies a programming algorithm to a selected word line for a memory cell in group A, the memory cell being positioned on a word line (A) that can be used to fine-tune the magnitude of the combined output current. For example, an incremental step pulse program (ISPP) algorithm can be used to fine-tune the threshold voltage of the memory cell in the group on the word line WL (A) to be used for case A. This involves applying a pulse (2420) and then verifying that the magnitude of the combined output current meets a condition (2430). The verification operation may utilize a bandgap reference circuit in an on-chip bias voltage generator to provide a reference signal, which is compared to fine-tune the threshold of the memory cell in the reference memory. If the verification fails, the algorithm returns to step 2420 to apply another pulse that can be incremented even higher. If, at step 2430, the group to be used for case A passes verification, the controller continues to apply the programming algorithm to the selected word line for group B. This involves applying a pulse (2440) to word line WL(B) to verify whether the current generated by the group of memory cells to be used for case B meets the condition (2450). If, at step 2450, the group for case B fails verification, the algorithm returns to step 2440 to apply the next pulse. If, at step 2450, the group for case B passes verification, the training algorithm ends (2460).

[0234] This reference memory programming operation can be performed under the control of logic in a wafer sorting machine at the manufacturing plant or in on-chip control circuitry. Essentially, an amplified sense containing an output latch can be deployed connected to the bit lines of a selected region in the reference memory. The logic may include sequences, such as:

[0235] 1) Enter a program code (e.g., "1") at the latch as a flag.

[0236] 2) ISPP programming (first pulse, initial bias voltage from the control circuit)

[0237] 3) If the programming verification (PV) step detects that cell Vt < reference Vt, the latch's program code is maintained.

[0238] 4) ISPP programming (second pulse, higher WL bias provided by the control circuit)

[0239] 5) If the programming verification (PV) step detects that cell Vt < reference Vt, the latch's program code is maintained.

[0240] …

[0241] 6) ISPP programming (nth pulse, Vg0 + (n-1) * Vstep)

[0242] 7) If the programming verification (PV) step detects that cell Vt > reference Vt, the latch's program code is changed. Therefore, the control circuit will prevent the Vt fine-tuning algorithm.

[0243] Embodiments of the reference system technology described herein have been applied to NOR and AND structure memory devices that utilize dielectric charge trapping storage elements. The reference system technology described herein can also be applied to other types of memory structures and to storage elements of other storage types.

[0244] Although this disclosure is made with reference to the preferred embodiments and examples detailed above, it should be understood that these examples are intended to be illustrative rather than restrictive. Modifications and combinations will readily occur to those skilled in the art, and such modifications and combinations will be within the spirit of this disclosure and the scope of the following claims.

Claims

1. A memory, comprising: Data storage, comprising multiple memory cells with multiple bit lines; Reference memory, comprising multiple memory units; A conversion circuit is used to convert a signal from a group of memory cells into a reference signal, the group of memory cells including multiple members of the plurality of memory cells within the reference memory; as well as A sensing amplifier, connected to the conversion circuit and one bit line of the plurality of bit lines in the data memory, is used to sense data stored in a selected memory cell in the data memory, the data being in response to a comparison of a data signal from the selected memory cell and a reference signal; The reference memory includes a stack of horizontal word lines and a collection of vertical conductors, the stack of horizontal word lines being in individual layers of the stack, and the memory cells in the reference memory having horizontal channels between adjacent vertical conductors on the layers of the horizontal word lines in the stack. The memory cell group is disposed on a plurality of region reference bit lines, which are disposed in a patterned conductor layer covering the stack and include the vertical conductors extending to the region reference transistor regions.

2. The memory according to claim 1, wherein the plurality of region reference bit lines are connected together for programming operations of the reference memory.

3. The memory of claim 1, wherein the set of vertical conductors includes the vertical conductors extending to a region reference source line and the vertical conductors extending to a region reference bit line, and the reference memory includes a reference bit line transistor connected to the region reference bit line in the group of memory cells within the switching circuit.

4. The memory according to claim 1, wherein the stack is disposed above the circuit layer of the substrate, and the reference bit line transistor is disposed in a reference bit line transistor region on the circuit layer adjacent to the stack.

5. The memory of claim 1, wherein the conversion circuitry includes a current mirror circuit and a current / voltage converter, the current mirror circuitry generating a reference current corresponding to the combined current from the group of memory cells.

6. The memory of claim 1, wherein the memory cells in the group of memory cells are disposed on a reference word line, and includes a reference word line driver to apply a word line reference voltage to the reference word line and to apply a deselect voltage to other word lines in the reference memory.

7. The memory of claim 1, wherein the reference memory comprises a stacked structure comprising a plurality of lattice layers, each lattice layer comprising a stack of horizontal word lines and a collection of vertical conductors, the stack of horizontal word lines being in a particular layer of the stack, the memory cells in the reference memory having horizontal channels between adjacent vertical conductors on the layer of the horizontal word lines in the stack, and wherein a group of memory cells is disposed on one of the plurality of lattice layers, the stack of horizontal word lines including reference word lines for the group of memory cells, and the memory cells in the group of memory cells including reference word line drivers to apply a word line reference voltage to the reference word line and to apply a deselect voltage to other word lines in the reference memory.

8. The memory of claim 1, wherein the reference memory comprises a stacked structure comprising a plurality of layers, each layer comprising a stack of horizontal word lines and a set of vertical conductors, the stack of horizontal word lines having a horizontal channel between the memory cells in the reference memory, the horizontal channel being between adjacent vertical conductors on the layer of the horizontal word lines in the stack, and wherein at least one layer of the plurality of layers has the memory cell group, and at least one other layer of the plurality of layers is disconnected from the switching circuit.

9. A memory, comprising: Data storage, comprising multiple memory cells with multiple bit lines; A reference memory includes multiple memory cells, the reference memory including passive memory cells and active memory cell groups, the active memory cell groups being connected to region reference bit lines and reference word lines; A conversion circuit is used to convert signals from the region reference bit lines in the active memory cell group into reference signals; And a sensing amplifier, a bit line connected to the conversion circuit and the plurality of bit lines in the data memory, for sensing data stored in a selected memory cell in the data memory, the data being in response to a comparison of a data signal from the selected memory cell and a reference signal; The reference memory includes multiple layers, each layer including a stack of horizontal word lines and a set of vertical conductors, the stack of horizontal word lines being in individual layers of the stack, the memory cells in the reference memory having horizontal channels between adjacent vertical conductors on the layers of the horizontal word lines in the stack, and the memory cell groups being disposed in the first layer, and memory cells having vertical conductors in other layers not connected to region reference bit lines.

10. The memory of claim 9, further comprising a word line driver connected to the reference word line to apply a word line reference voltage and connected to other word lines of the reference memory to apply a deselect voltage.

11. The memory of claim 9, wherein the conversion circuit includes a summing node and a current mirror circuit, the summing node summing currents from the region reference bit line to generate a merged current, and the current mirror circuit converting the merged current into a reference current having a reduced magnitude.

12. The memory of claim 11, wherein the conversion circuitry includes a current / voltage converter to convert the reference current into a reference voltage and to apply the reference voltage to the sensing amplifier.

13. The memory of claim 9, comprising control circuitry to program the passive memory cells to a first threshold state and to program the group of active memory cells to a second threshold state below the first threshold state.

14. The memory of claim 13, wherein the control circuit applies an incremental step pulse programming operation to the memory cell group to set the second threshold state.

15. The memory of claim 9, further comprising control circuitry for programming the active memory cells using an incremental step pulse programming operation.

16. The memory of claim 9, wherein the reference memory comprises a stacked structure comprising a plurality of lattice layers, each lattice layer comprising a stack of horizontal word lines and a collection of vertical conductors, the stack of horizontal word lines being disposed on a separate layer of the stack, the memory cells in the reference memory having horizontal channels between adjacent vertical conductors on the layer of the horizontal word lines in the stack, and wherein a group of memory cells is disposed on a lattice layer of the plurality of lattice layers, the stack of horizontal word lines including reference word lines for the group of memory cells, and the reference memory including a reference word line driver to apply word line voltages to the reference word lines and to apply deselect voltages to other word lines of the reference memory.

17. The memory of claim 9, wherein the reference memory comprises a stacked structure comprising a plurality of slabs, each slab comprising a stack of horizontal word lines and a set of vertical conductors, the stack of horizontal word lines being in a particular layer of the stack, the memory cells in the reference memory having horizontal channels between adjacent vertical conductors on the layer of the horizontal word lines in the stack, and wherein a group of memory cells is disposed on a slab of the plurality of slabs, the stack of horizontal word lines including the reference word lines for the group of memory cells, and wherein at least one slab of the plurality of slabs has the group of memory cells, and at least one other slab of the plurality of slabs is disconnected from the switching circuit.

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