Power behavior detection in memory devices

Abstract

This disclosure relates to power behavior detection in a memory device. A method includes: receiving signaling by a processing means instructing a power cycle PC to a memory device MD, the signaling having a first signal indicating a power-on operation and a second signal indicating a power-off operation; and determining an average power-on time APOT of the MD based at least in part on the number of power cycles (n) to the MD within a predetermined time interval PTI and the amount of time between the reception of the first and second signals for each PC within the PTI. The sum of each of the amounts of time between the reception of the first and second signals within the PTI provides a total power-on time (T) to the MD, and the APOT is equal to T / n. When the APOT is less than (<) a threshold APOT value, a frequency for performing a media scan operation is determined, and a media scan operation involving the MD is performed at the determined frequency.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically to power behavior detection in memory devices. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, the host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] One aspect of this disclosure relates to a method for detecting power behavior in a memory device, the method comprising: receiving, by a processing device, signaling an indication of a power cycle to the memory device; determining, within a predetermined time interval, an average on-time (APOT) of the memory device based on the signaling an indication of a power cycle to the memory device; determining whether a criterion for the APOT is met; in response to determining that the criterion for the APOT is met, determining a frequency for performing a media scan operation relating to the memory device; and performing the media scan operation relating to the memory device at the determined frequency.

[0004] Another aspect of this disclosure relates to an apparatus for power behavior detection in a memory device, the apparatus comprising: a memory device; and a power behavior detector coupled to the memory device, wherein the power behavior detector will: receive a signal indicating a power cycle to the memory device; determine a total on-time (T) to the memory device from a number (n) of power cycles within a predetermined time interval; determine an average on-time (APOT) of the memory device, wherein APOT is equal to T / n; determine whether a criterion for the APOT is met; in response to determining that the criterion for the APOT is met, determine a frequency for performing a media scan operation involving the memory device; and perform the media scan operation involving the memory device at the determined frequency.

[0005] Another aspect of this disclosure relates to a non-transitory computer-readable storage medium for power behavior detection in a memory device, comprising instructions that, when executed by a processing device, cause the processing device to: receive signaling indicating a power cycle to the memory device, wherein the signaling includes a first signal indicating a power-on operation of the memory device and a second signal following the first signal indicating a power-off operation of the memory device; determine, at least in part, an average power-on time (APOT) of the memory device based on: the number of power cycles (n) to the memory device within a predetermined time interval; and, for each power cycle within the predetermined time interval, the amount of time between the reception of the first signal and the second signal, wherein: the sum of each of the amounts of time between the reception of the first signal and the second signal within the predetermined time interval provides a total power-on time (T) to the memory device, and the APOT is equal to T / n; determine whether a criterion for the APOT is met; in response to determining that the criterion for the APOT is met, determine a frequency for performing a media scan operation involving the memory device; and perform the media scan operation involving the memory device at the determined frequency. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof.

[0007] Figure 1 Examples of computing systems including a memory subsystem are shown according to some embodiments of the present disclosure.

[0008] Figure 2 This is a flowchart corresponding to a method for power behavior detection in a memory device, based on some embodiments of the present disclosure.

[0009] Figure 3 This is a flowchart corresponding to power behavior detection in a memory device according to some embodiments of the present disclosure.

[0010] Figure 4 This is a block diagram of an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0011] This disclosure relates to power behavior detection in a memory device, and more specifically to power behavior detection including a power behavior detector component. The memory subsystem can be a storage system, a storage device, a memory module, or a combination thereof. Examples of memory subsystems include storage systems such as solid-state drives (SSDs). The following description... Figure 1(And others) Examples describing storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components (e.g., a memory device for storing data). The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0012] Memory devices can be non-volatile memory devices. An example of a non-volatile memory device is a NAND flash memory device (also known as flash memory). The following section combines... Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. Planes may be grouped into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Hereinafter, a block refers to a unit of a memory device used to store data and may contain groups of memory cells, groups of word lines, word lines, or individual memory cells. For some memory devices, a block (also referred to below as a “memory block”) is the smallest erasable area. Pages cannot be erased individually; only the entire block can be erased.

[0013] Each memory device may contain one or more arrays of memory cells. Depending on the cell type, a cell may store one or more bits of binary information and has various logical states related to the number of bits being stored. Logical states may be represented by binary values ​​(e.g., "0" and "1") or combinations of these values. Various types of cells exist, such as single-level cell (SLC), multi-level cell (MLC), three-level cell (TLC), and four-level cell (QLC). For example, an SLC may store one bit of information and have two logical states.

[0014] Some NAND memory devices employ a floating gate architecture, where memory access is controlled based on a relative voltage change between the bit line and the word line. Other examples of NAND memory devices may employ an alternative gate architecture that may include a word line layout, which allows for the trapping of charges corresponding to data values ​​within the memory cell based on the properties of the materials used to construct the word lines.

[0015] The memory devices described above are found in many of today's battery-powered mobile devices. Because these mobile devices have limited battery life, power-saving techniques to extend battery life have become a significant concern. For example, to extend battery life, some mobile host chipsets remove power to the non-volatile memory devices in these devices after only a few seconds of user inactivity. This can result in thousands of power-on and power-off operations (i.e., power cycling) of the non-volatile memory devices throughout the day. These power cycles typically occur via the output stage logic supply voltage (VCCQ) pin, or "input / output (I / O) power pin," which supplies power to, for example, NAND memory devices; however, power from the device power supply (VCC) pin to other non-volatile memory devices is maintained. Maintaining power through the VCC pin allows the system clock for these other non-volatile memory devices to be maintained. For example, in the case of Universal Flash Memory (UFS), the UFS controller, which has its system clock, is powered via the VCC pin, but power to the VCCQ pin of the NAND memory device can undergo power cycling. However, mobile host chipsets now perform power cycles involving both the VCCQ and VCC pins to extend battery life, meaning that the system clock, for example, that of the UFS controller is reset at each power cycle. Therefore, tracking the correct timing in the UFS across other memory devices becomes more difficult.

[0016] The difficulty in tracking the correct timing in memory devices (e.g., UFS) can lead to problems with system maintenance algorithms. Until recently, maintenance algorithms in memory devices relied on an uninterrupted power supply to the VCC pin when the mobile device was powered on. These algorithms used scheduled media scans, spread over predetermined time periods (e.g., 30 days), to check data integrity in the memory device. This remains true for many memory devices; however, memory devices undergoing thousands of power cycles per day to extend their battery life are now or will soon be used in mobile devices. For these devices, the system clock resets and no media scan occurs when power is disconnected. Both issues can derail memory device maintenance schedules. Therefore, being able to distinguish whether a memory device in a mobile device is undergoing a high number of power cycles (e.g., thousands per day) is an important consideration for ensuring proper system maintenance of the mobile device.

[0017] This disclosure addresses the above and other deficiencies by detecting whether a memory device in a mobile device is performing frequent power cycles (e.g., thousands of power cycles per day) or relatively few power cycles per day (e.g., several power cycles per day). To this end, this disclosure tracks the total power-on time (T) and the number of power cycles (n) occurring to the memory device within a predetermined time interval. As discussed more fully herein, the total power-on time and the number of power cycles within the predetermined time interval are used to calculate the average power-on time (APOT) of the memory device. APOT is used to determine whether criteria for APOT are met. In response to determining whether criteria for APOT are met, the frequency of performing media scan operations involving the memory device is determined and executed.

[0018] Figure 1 Example computing system 100 including memory subsystem 110 according to some embodiments of the present disclosure is shown. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or combinations of such devices.

[0019] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0020] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, server, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing devices.

[0021] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1An example of a host system 120 coupled to a memory subsystem 110 is shown. As used herein, “coupled to…” or “coupled with…” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0022] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an SSD controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110 to, for example, write data to memory subsystem 110 and read data from memory subsystem 110.

[0023] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include (but are not limited to) Serial Advanced Technology Attachment (SATA) interface, Peripheral Component Interconnect High Speed ​​(PCIe) interface, Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Dual Data Rate (DDR) memory bus, Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Dual Data Rate (DDR)), Open NAND Flash Interface (ONFI), Dual Data Rate (DDR), Low Power Dual Data Rate (LPDDR), or any other interface. The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via PCIe interface, host system 120 can further utilize NVM Express (NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data and other signals between the memory subsystem 110 and the host system 120. Figure 1 Memory subsystem 110 is shown as an example. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0024] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be (but are not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0025] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. The crosspoint array of non-volatile memory can perform bit storage based on changes in volume resistance in conjunction with a stackable cross-grid data access array. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0026] Each of the memory devices 130 and 140 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0027] Although non-volatile memory components such as three-dimensional cross-point arrays of non-volatile memory cells and NAND-type memories (e.g., 2D NAND, 3D NAND) are described, memory device 130 may be based on any other type of non-volatile memory or storage device, such as read-only memory (ROM), phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0028] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-decoded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0029] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0030] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure is shown to include a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0031] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to enable desired access to memory devices 130 and / or 140. The memory subsystem controller 115 may handle other operations, such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses, physical media locations, etc.) associated with memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communication with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access memory devices 130 and / or 140, and translate responses associated with memory devices 130 and / or 140 into information for the host system 120.

[0032] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., a row decoder and a column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access memory device 130 and / or memory device 140.

[0033] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0034] The memory subsystem 110 may include a power behavior detector component 113. Although Figure 1For the sake of clarity, these are not shown in the diagram, but the power behavior detector assembly 113 may include various circuitry to receive signaling indicating power cycles to the memory device, and to determine the average power-on time (APOT) of the memory device based on the number (n) of power cycles to the memory device and the total power-on time (T) to the memory device, wherein APOT (equal to T / n) is used to determine the frequency at which media scan operations involving the memory device are performed. In some embodiments, the power behavior detector assembly 113 may include dedicated circuitry in the form of an ASIC, FPGA, state machine, and / or other logic circuitry, which may allow the power behavior detector assembly 113 to orchestrate and / or perform operations to detect what type of memory device 130 and / or memory device 140 is present in the mobile device: a type with frequent power cycles (e.g., thousands of power cycles per day), or a type with relatively few power cycles per day (e.g., several power cycles per day).

[0035] As used herein, “power cycling” is defined as cutting off power supplied to memory device 130 and / or memory device 140 via at least VCC (power-off operation) and then turning it back on (power-on operation).

[0036] In some embodiments, the memory subsystem controller 115 includes at least a portion of the power behavior detector component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the power behavior detector component 113 is part of the host system 110, an application, or an operating system.

[0037] In a non-limiting example, a device (e.g., computing system 100) may include a power behavior detector assembly 113. The power behavior detector assembly 113 may reside on a memory subsystem 110. As used herein, the term "resides on" means that something is physically located on a particular component. For example, "resides on memory subsystem 110" means that the hardware circuitry including the power behavior detector assembly 113 is physically located on memory subsystem 110. The term "resides on" may be used interchangeably herein with other terms such as "deployed on" or "located on".

[0038] The power behavior detector assembly 113 can be configured to detect signaling including a first signal indicating a power-on operation of the memory device 130 and / or the memory device 140, and a second signal following the first signal indicating a power-off operation of the memory device 130 and / or the memory device 140. As described above, the memory device 130 and / or the memory device 140 can be a memory die or a memory package forming at least a portion of the memory device 130 and / or the memory device 140.

[0039] The power behavior detector component 113 is further configured to determine the average on-time (APOT) of the memory device 130 and / or the memory device 140 based at least in part on the number (n) of power cycles to the memory device 130 and / or the memory device 140 within a predetermined time interval and the amount of time between the reception of the first signal and the second signal for each power cycle within the predetermined time interval. The power behavior detector component 113 is configured to use the amount of time between the reception of the first signal and the second signal to determine the sum of each of the amounts of time between the reception of the first signal and the second signal within the predetermined time interval, wherein the sum provides the total on-time (T) to the memory device during the predetermined time interval.

[0040] The power behavior detector component 113 is further configured to determine APOT, which is equal to T / n. The power behavior detector component 113 also determines whether a criterion for APOT is met. For example, one way to determine whether a criterion for APOT is met is to determine whether APOT is less than (<) a threshold APOT value. As discussed herein, determining that APOT is less than the threshold APOT value indicates that memory device 130 and / or memory device 140 is performing frequent power cycling (e.g., thousands of power cycles per day).

[0041] In response to determining the criteria for achieving APOT (e.g., whether APOT is less than (<) a threshold APOT value), the power behavior detector component 113 determines the frequency at which a media scan operation involving the memory device is performed. In determining the frequency of performing the media scan operation involving the memory device, the power behavior detector component 113 is configured to determine the fraction of the set of memory cells of the memory device to undergo a media scan operation within a predetermined time interval (T) to achieve a complete media scan of the set of memory cells within a media scan cycle. For various embodiments, the predetermined time interval is less than the total time of the media scan cycle.

[0042] The power behavior detector component 113 is further configured to divide a fraction of the set of memory cells of the memory device undergoing a media scan operation by at least a portion of the number of power cycles (n) experienced by the processing device (e.g., processor 117) within a predetermined time interval to give the frequency of media scan operations per predetermined time interval. For various embodiments, the frequency of media scan operations is less than the number of power cycles (n) experienced by the processing device (e.g., processor 117) within the predetermined time interval.

[0043] Using a determined frequency, the power behavior detector assembly 113 performs or assists in performing a media scan operation involving the memory device. In various embodiments, the memory device undergoing the media scan operation, such as memory device 130 and / or memory device 140, may comprise sets of memory cells, which may be a portion of one or more blocks, stripes, dies, and / or word lines of the memory device. In various embodiments, the power behavior detector assembly 113 may perform a complete media scan of the memory device within a media scan cycle. Therefore, when the memory device comprises multiple sets of memory cells, each set of memory cells undergoes a complete media scan within a media scan cycle.

[0044] Figure 2 This is a flowchart corresponding to a method 250 for power behavior detection in a memory device according to some embodiments of this disclosure. Method 250 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 250 is performed by… Figure 1 The power behavior detector component 113 performs the operation. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0045] At operation 252, a signal indicative of a power cycle to the memory device may be received by the processing apparatus as provided herein. Each of the signals indicative of a power cycle includes a first signal indicative of a power-on operation of the memory device, and a subsequent signal indicative of the memory device (e.g., as described herein). Figure 1 A second signal indicating the power-off operation of memory device 130 and / or memory device 140 shown in the diagram. In some embodiments, a signal indicating power cycling to the memory device is, for example, a second signal indicating the power cycle to the memory device. Figure 1The power behavior detector component 113 and other memory subsystems shown in the figure monitor and receive power behavior detectors.

[0046] At operation 254, the processing device may be used to determine the average power-on time (APOT) of the memory device. APOT may be determined at least in part based on the number of power cycles (n) to the memory device within a predetermined time interval and the total power-on time (T). The value of the predetermined time interval may be determined based on several factors, including the size of the memory to be subjected to the media scan operation, the media scan cycle during which the media scan operation completes a full scan of the memory, and / or a predetermined value of the predetermined time interval derived from averages and / or mean values ​​used in similar or identical computing systems. Preferably, the predetermined time interval has a value of approximately twenty-four (24) hours.

[0047] The total power-on time (T) can be determined using each power cycle within a predetermined time interval. At operation 254, the amount of time between the reception of the first signal and the second signal is determined, wherein the sum of each of the amounts of time between the reception of the first signal and the second signal within the predetermined time interval provides the total power-on time (T) to the memory device. As mentioned herein, APOT equals T / n.

[0048] At operation 256, a determination can be made regarding whether APOT meets a certain criterion. For example, a determination can be made regarding whether the APOT determined in operation 254 is less than (<) a threshold APOT value. The value of the threshold APOT value can be determined based on several factors, which may include the size of the memory to be subjected to the media scan operation, the media scan cycle during which the media scan operation completes a full scan of the memory, and / or a predetermined value of a predetermined time interval derived from the average and / or mean used in similar or identical computing systems. In some embodiments, the threshold APOT value has a value of ten (10) hours / power cycles or less.

[0049] For various embodiments, the media scan cycle is the time required to complete a full scan of the memory. The time required to complete a full scan of the memory can depend on several factors, including the size of the memory to be subjected to the media scan operation, the media scan cycle during which the media scan operation completes the full scan of the memory, and / or a predetermined value of the time required to complete the full scan of the memory derived from averages and / or mean values ​​used in similar or identical computing systems. For various embodiments, the media scan cycle has values ​​from several days (e.g., 3 days) to several months (e.g., 90 days). Preferably, the media scan cycle has a value of about thirty (30) days.

[0050] At operation 258, in response to determining the criteria for implementing APOT (e.g., when APOT is less than (<) a threshold APOT value), a determination is made of the frequency at which media scan operations involving the memory device are performed. The determination of the frequency of performing media scan operations may include several aspects. These include determining a fraction of the set of memory cells of the memory device to undergo media scan operations within a predetermined time interval (T) to achieve a complete media scan of the set of memory cells within a media scan cycle. The fraction of the set of memory cells of the memory device to undergo media scan operations is used in a division operation together with at least a portion of the number of power cycles (n) experienced by the processing device within the predetermined time interval to give the frequency number of media scan operations per predetermined time interval. For various embodiments, the frequency number of media scan operations may (e.g., indeed) be less than the number of power cycles (n) experienced by the processing device within the predetermined time interval. For various embodiments, the predetermined time interval may be less than the total time of the media scan cycle.

[0051] At operation 260, a media scan operation involving the memory device can be performed at a determined frequency. For various embodiments, the determined frequency of the media scan operation presupposes a complete media scan of the memory device within a media scan cycle. Therefore, in the case where the memory device comprises multiple sets of memory cells, each set of memory cells undergoes a complete media scan within a media scan cycle. Figure 3 The flowchart and explanations of these operations are provided below.

[0052] Figure 3 This is a flowchart 362 corresponding to a memory subsystem power behavior detector according to some embodiments of the present disclosure. At operation 364, signals indicating power cycles to the memory device are received. Each power cycle includes a first signal 366 indicating a power-on operation of the memory device, and a second signal 368 following the first signal 366 indicating a power-off operation of the memory device. As discussed herein, at operation 364, the number of power cycles (n) to the memory device and the total power-on time (T) are determined within a predetermined time interval using the first signal 366 and the second signal 368. In some embodiments, by, for example... Figure 1 The power behavior detector component 113 shown in the diagram monitors and receives signals indicating power cycling to the memory device, as previously discussed.

[0053] At operation 370, the processing device determines the APOT of the memory device based on the number of power cycles (n) to the memory device within a predetermined time interval and the total power-on time (T), where APOT is equal to T / n.

[0054] At operation 372, a determination is made as to whether the criterion for APOT has been met. As previously discussed, one example of this determination is whether APOT is less than, greater than, or equal to a threshold APOT value. Continuing with this example, when the APOT value is greater than or equal to (>) the threshold APOT value (i.e., "No," the criterion for APOT has not been met), the memory subsystem power behavior detector returns to operation 364 via 374, and the processing device continues to receive signals indicating the power cycle of the memory device for a predetermined time interval following the predetermined time interval used in the determination of APOT at operation 370.

[0055] When the APOT value is less than (<) the threshold APOT value (i.e., "yes", the criterion for APOT is implemented), the memory subsystem power behavior detector proceeds to operation 376. At operation 376, the frequency of performing media scan operations involving the memory device is determined. For various embodiments, in order to determine the frequency of performing media scan operations involving the memory device, a fraction of the set of memory cells of the memory device to undergo media scan operations within a predetermined time interval (T) is determined, wherein the use of this frequency facilitates a complete media scan of the set of memory cells within a media scan cycle.

[0056] With the aid of examples, for the operations discussed so far, let's assume a computing system (e.g., Figure 1 A memory device with a capacity of 90 gigabytes (GB) has been assigned a predetermined time interval of 24 hours. To achieve a complete scan of the 90GB memory cell set, a threshold APOT value of 0.1 hours / cycle and a media scan cycle of thirty (30) days are set. For this given computing system, operation 364 determines that the total power-on time (T) for the current instance memory device is four (4) hours and the number of power cycles (n) for the current instance is one hundred (100). These values ​​give an APOT value of 0.04 hours / power cycle at operation 370. Operation 372 determines an APOT achievement criterion (e.g., an APOT value less than the threshold APOT value), and thus proceeds to operation 376 to determine the frequency at which the media scan operation is performed.

[0057] At operation 376, a fraction of the 90GB set of memory cells to undergo media scan operations within a predetermined time interval total power-on time (T) is determined. For the parameters of the computing system in the previous paragraph, this fraction of the 90GB set of memory cells can be approximately a 3GB subset of memory cells, which can be provided as the set of memory cells of the memory device to undergo media scan operations within a predetermined time interval total power-on time (T). That is, in this illustrative example, approximately 90GB of memory cells can be scanned over 30 days, meaning that approximately a 3GB subset of the memory device should be scanned each day. Also at operation 376, the frequency of performing media scan operations involving the memory device is determined, wherein each of the fractions of approximately 3GB subsets of memory cells of the memory device is scheduled to be completed within four (4) hours of total power-on time (T) on each day of the media scan cycle (e.g., 30 days).

[0058] For various embodiments, operation 376 uses both a fraction of the set of memory cells of the memory device undergoing media scan operations and at least a portion of the number of power cycles (n) experienced by the processing device within a predetermined time interval to give the frequency of media scan operations per predetermined time interval. For example, the fraction of the set of memory cells of the memory device undergoing media scan operations may be divided by at least a portion of the number of power cycles (n) experienced by the processing device within a predetermined time interval to give the frequency of media scan operations per predetermined time interval. For a given example, the fraction of the set of memory cells of the memory device undergoing media scan operations within a total power-on time (T) of four hours in a given predetermined time interval of 24 hours is approximately 3GB. Within the total power-on time (T) of four hours, there are n power cycles (e.g., 100 power cycles) that divide the time during which media scans can occur. In a given example, four hours divided by 100 power cycles gives the frequency of media scan operations as 25 media scan operations per hour of the total power-on time (T).

[0059] In an alternative embodiment, the media scan rate of a given computing system (e.g., GB / min) can be used to determine the frequency of performing media scan operations. For example, given a media scan rate of 0.02 GB / min and a total power-on time (T) of four hours for a given predetermined time interval of 24 hours in which a 3 GB scan is completed, the frequency of performing media scan operations during the total power-on time (T) would be approximately 0.625 scans / min. Other techniques are possible for determining the frequency of performing media scan operations.

[0060] In various embodiments, the given number of media scan operations during the total power-on time (T) within a predetermined time interval can be uniformly distributed over the given predetermined time interval. In alternative embodiments, the number of media scan operations can be less than the number of power cycles (n) experienced by the processing device within the predetermined time interval. This embodiment thus allows for a non-uniform distribution of the given number of media scan operations during the total power-on time (T) within the predetermined time interval (e.g., preload media scan events).

[0061] At operation 378, a media scan operation can be performed at the frequency determined in operation 376 for each predetermined time interval in order to achieve a complete media scan of the memory cell set within the media scan cycle.

[0062] Figure 4 This is a block diagram of an example computer system 400 in which embodiments of this disclosure may operate. For example, Figure 4 An example machine of computer system 400 is shown, within which an instruction set executable for causing the machine to perform any one or more of the methods discussed herein is available. In some embodiments, computer system 400 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1 (Operation of the power behavior detector component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment within the capacity of a server or client machine in a client-server network environment.

[0063] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should be understood to include any set of machines that individually or jointly execute a set (or sets of sets) of instructions to perform any or more of the methods discussed herein.

[0064] The example computer system 400 includes a processing device 402, a main memory 404 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 406 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 418, which communicate with each other via a bus 430.

[0065] Processing device 402 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 402 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 402 is configured to execute instructions 426 for performing the operations and steps discussed herein. Computer system 400 may further include network interface device 408 for communication on network 420.

[0066] Data storage system 418 may include machine-readable storage medium 424 (also referred to as computer-readable medium) on which one or more instruction sets 426 or software embodying any one or more methods or functions described herein are stored. Instructions 426 may also reside wholly or at least partially within main memory 404 and / or processing device 402 during execution by computer system 400, which also constitute machine-readable storage media. Machine-readable storage medium 424, data storage system 418, and / or main memory 404 may correspond to... Figure 1 The memory subsystem 110.

[0067] In one embodiment, instruction 426 includes implementing a power behavior detector component (e.g., Figure 1 The power behavior detector component 113) contains functional instructions. While machine-readable storage medium 424 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be understood to include a single medium or multiple media storing the one or more sets of instructions. The term "machine-readable storage medium" should also be understood to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. The term "machine-readable storage medium" should be accordingly understood to include (but is not limited to) solid-state memory, optical media, and magnetic media.

[0068] In a non-limiting example, instruction 426 may be an instruction that, when executed by processing device 402, causes processing device to receive signaling instructing a power cycle to a memory device, said signaling including a first signal instructing the memory device to power on, and an instruction following the first signal instructing the memory device (e.g., herein, ...). Figure 1 The processing device 402 may further execute instructions to determine the average power-on time (APOT) of the memory device based at least in part on the number of power cycles (n) of the memory device within a predetermined time interval and / or the amount of time between the reception of the first and second signals for each power cycle within the predetermined time interval. The processing device 402 may further execute instructions to determine whether a criterion for APOT is met, and in response to determining that the criterion for APOT is met, determine the frequency at which a media scan operation involving the memory device is performed. By way of example, the processing device 402 may execute instructions to determine whether APOT is less than (<) a threshold APOT value, and in response to determining that APOT is less than (<) a threshold APOT value, determine the frequency at which a media scan operation involving the memory device is performed. The processing device 402 may further execute instructions to perform a media scan operation involving the memory device at the determined frequency. In some embodiments, the sum of each of the amounts of time between the reception of the first and second signals within the predetermined time interval is provided to the total power-on time (T) of the memory device, and APOT is equal to T / n, as described above.

[0069] Some parts of the previously described descriptions have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. An algorithm here and generally is considered a self-consistent sequence of operations that produce the desired result. An operation is an operation that requires physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Primarily for reasons of common use, it has proven convenient to sometimes refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc.

[0070] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure may relate to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0071] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for a particular purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0072] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the teachings and procedures herein, or it may prove convenient to construct more specialized devices to implement the methods. The structures of various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure described herein can be implemented using various programming languages.

[0073] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable for programming a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0074] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A method for detecting power behavior in a memory device, comprising: The processing unit (113, 117, 402) receives a signal instructing the memory device (130, 140) to perform a power cycle. The average power-on time (APOT) of the memory devices (130, 140) is determined based on the signaling indicating the power cycle to the memory devices (130, 140) within a predetermined time interval; Determine whether the APOT value is less than the threshold APOT value; In response to determining that the APOT is less than the threshold APOT value, a frequency for performing a media scan operation involving the memory devices (130, 140) is determined; as well as The media scan operation involving the memory devices (130, 140) is performed at the determined frequency.

2. The method of claim 1, wherein determining the APOT of the memory device comprises: Determine the number of power cycles (n) to the memory device within the predetermined time interval; and For each power cycle of the number of power cycles (n) during the predetermined time interval, determine the amount of time between receiving a first signal indicating a power-on operation of the memory device and a second signal indicating a power-off operation of the memory device following the first signal, wherein: The sum of the time between the reception of the first signal and the second signal for each power cycle of the number of power cycles (n) during the predetermined time interval is provided to the memory device as the total power-on time (T), where APOT is equal to T / n.

3. The method of claim 2, wherein determining the frequency for performing the media scanning operation comprises: Determine the fraction of the memory cell set of the memory device to undergo media scan operation within the total power-on time (T) of the predetermined time interval to achieve a complete media scan of the memory cell set within the media scan cycle; and The fraction of the set of memory cells of the memory device to undergo a media scan operation is divided by at least a portion of the number of power cycles (n) experienced by the processing device within the predetermined time interval to give the frequency of media scan operations per predetermined time interval.

4. The method of claim 3, wherein the number of frequencies of the media scanning operation is less than the number of power cycles (n) experienced by the processing device within the predetermined time interval.

5. The method of claim 3, wherein the memory device comprises a plurality of memory cell sets, and each of the plurality of memory cell sets undergoes the complete media scan during the media scan cycle.

6. The method according to claim 3, wherein the predetermined time interval is less than the total time of the medium scanning cycle.

7. The method according to claim 1, wherein the predetermined time interval is twenty-four hours.

8. The method of claim 1, wherein the threshold APOT value has a value of ten hours / power cycle or less.

9. An apparatus for detecting power behavior in a memory device, comprising: Memory devices (130, 140); as well as A power behavior detector (113) coupled to the memory devices (130, 140), wherein the power behavior detector (113) will: Receive a signal indicating a power cycle to the memory devices (130, 140); The total power-on time (T) of the memory devices (130, 140) is determined from the number of power cycles (n) within a predetermined time interval; Determine the average power-on time APOT of the memory devices (130, 140), where APOT is equal to T / n; Determine whether the APOT value is less than the threshold APOT value; In response to determining that the APOT is less than the threshold APOT value, a frequency for performing a media scan operation involving the memory devices (130, 140) is determined; as well as The media scan operation involving the memory devices (130, 140) is performed at the determined frequency.

10. The device of claim 9, wherein each signal indicating a power cycle of the memory device comprises an amount of time between the reception of a first signal indicating a power-on operation of the memory device and a second signal indicating a power-off operation of the memory device following the first signal, wherein the sum of the amounts of time between the reception of the first signal and the second signal for each power cycle of the number (n) of power cycles within the predetermined time interval provides the total power-on time (T) of the memory device.

11. The device of claim 9, further comprising a processing means, wherein, during the determination of the frequency, the power behavior detector determines a fraction of the set of memory cells of the memory device to undergo a media scan operation within the total power-on time (T) of the predetermined time interval to achieve a complete media scan of the set of memory cells within the media scan cycle; and The fraction of the set of memory cells of the memory device to undergo a media scan operation is divided by at least a portion of the number of power cycles (n) experienced by the processing device within the predetermined time interval to give the frequency of media scan operations per predetermined time interval.

12. The apparatus of claim 11, wherein the frequency of the media scanning operation is less than the number of power cycles (n) experienced by the processing device within the predetermined time interval.

13. The device of claim 11, wherein the memory device comprises a plurality of memory cell sets, and each of the plurality of memory cell sets undergoes a complete media scan during the media scan cycle.

14. The device of claim 11, wherein the predetermined time interval is less than the total time of the media scanning cycle.

15. The device of claim 9, wherein the memory device is a general-purpose flash memory device.

16. A non-transitory computer-readable storage medium (424) for power behavior detection in a memory device, comprising instructions (426) that, when executed by a processing device (113, 117), cause the processing device (113, 117) to: Receive signaling instructing a power cycle to a memory device (130, 140), wherein the signaling includes a first signal instructing a power-on operation of the memory device (130, 140), and a second signal following the first signal instructing a power-off operation of the memory device (130, 140). The average power-on time (APOT) of the memory devices (130, 140) is determined at least in part based on the following: The number of power cycles (n) to the memory devices (130, 140) within a predetermined time interval; and For each power cycle within the predetermined time interval, the amount of time between the reception of the first signal and the second signal, wherein: The sum of each of the time amounts between the reception of the first signal and the second signal within the predetermined time interval provides the total power-on time (T) to the memory device (130, 140), and The APOT is equal to T / n; Determine whether the APOT value is less than the threshold APOT value; In response to determining that the APOT is less than the threshold APOT value, a frequency for performing a media scan operation involving the memory devices (130, 140) is determined; as well as The media scan operation involving the memory devices (130, 140) is performed at the determined frequency.

17. The non-transitory computer-readable storage medium of claim 16, further comprising instructions that, when executed by the processing means, cause the processing means to: Determine the fraction of the memory cell set of the memory device to undergo media scan operation within the total power-on time (T) of the predetermined time interval to achieve a complete media scan of the memory cell set within the media scan cycle; and An operation is performed to divide the fraction of the set of memory cells of the memory device to undergo a media scan operation by at least a portion of the number of power cycles (n) experienced by the processing device within the predetermined time interval to give the frequency of media scan operations per predetermined time interval.

18. The non-transitory computer-readable storage medium of claim 17, further comprising instructions that, when executed by the processing means, cause the processing means to control the number of frequencies of the medium scanning operation such that the frequency of the medium scanning operation is less than the number (n) of power cycles experienced by the processing means within the predetermined time interval.

19. The non-transitory computer-readable storage medium of claim 17, further comprising instructions that, when executed by the processing means, cause the processing means to cause each memory cell set of the memory device to undergo a complete media scan during the media scan cycle.

20. The non-transitory computer-readable storage medium of claim 17, further comprising instructions that, when executed by the processing means, cause the processing means to set the predetermined time interval such that the predetermined time interval is less than the total time of the medium scan cycle.

Images