Capacitor and method of manufacturing a capacitor

Abstract

The present disclosure provides a capacitor and a preparation method of the capacitor. The capacitor comprises a first electrode, a dielectric layer and a second electrode, the dielectric layer is located between the first electrode and the second electrode; the capacitor further comprises: a first charge trapping layer located between the first electrode and the dielectric layer, the energy band gap of the first charge trapping layer is smaller than the energy band gap of the dielectric layer; a first barrier layer located between the first charge trapping layer and the first electrode, the energy band gap of the first barrier layer is greater than the energy band gap of the dielectric layer. Through the first charge trapping layer and the first barrier layer, the charge transition of the dielectric layer to the first electrode can be effectively prevented, thereby reducing the leakage current and improving the performance of the capacitor. Therefore, the capacitor and the preparation method of the capacitor provided by the present disclosure can reduce the leakage current of the capacitor and improve the performance of the capacitor.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a capacitor and a method for manufacturing the capacitor. Background Technology

[0002] Capacitors are important components in Dynamic Random Access Memory (DRAM), and their performance affects the storage performance of DRAM devices.

[0003] In related technologies, a capacitor may include a lower electrode, a dielectric layer, and an upper electrode, with the dielectric layer located between the lower and upper electrodes. The capacitance of a capacitor is directly proportional to the surface area of ​​the electrodes and the dielectric constant of the dielectric layer, and inversely proportional to the thickness of the dielectric layer. The capacitance can be increased by increasing the surface area of ​​the electrodes, using a high-dielectric-constant material to form the dielectric layer, or decreasing the thickness of the dielectric layer.

[0004] However, the performance of the aforementioned capacitors needs improvement. Summary of the Invention

[0005] This disclosure provides a capacitor and a method for manufacturing the capacitor, which can reduce the leakage current of the capacitor and improve its performance.

[0006] The embodiments disclosed herein provide the following technical solutions:

[0007] A first aspect of this disclosure provides a capacitor, including: a first electrode, a dielectric layer, and a second electrode, the dielectric layer being located between the first electrode and the second electrode; the capacitor further includes: a first charge trapping layer located between the first electrode and the dielectric layer, the band gap of the first charge trapping layer being smaller than the band gap of the dielectric layer; and a first blocking layer located between the first charge trapping layer and the first electrode, the band gap of the first blocking layer being larger than the band gap of the dielectric layer.

[0008] In one possible implementation, the capacitor further includes: a second charge trapping layer located between the second electrode and the dielectric layer, wherein the band gap of the second charge trapping layer is smaller than the band gap of the dielectric layer; and a second blocking layer located between the second charge trapping layer and the second electrode, wherein the band gap of the second blocking layer is larger than the band gap of the dielectric layer.

[0009] In one possible implementation, the band gap of the dielectric layer is 4eV-6eV.

[0010] In one possible implementation, the material of the dielectric layer includes at least one of hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, tantalum oxide, and niobium oxide.

[0011] In one possible implementation, the band gap of the first charge trapping layer and / or the second charge trapping layer is 2eV-4eV; and / or, the band gap of the first blocking layer and / or the second blocking layer is 8eV-10eV.

[0012] In one possible implementation, the first barrier layer and / or the second barrier layer comprise a silicon oxide material.

[0013] In one possible implementation, the first charge trapping layer and / or the second charge trapping layer comprise undoped silicon carbide material.

[0014] In one possible implementation, the first electrode and / or the second electrode comprise a metal or a metal compound.

[0015] In one possible implementation, the first electrode and / or the second electrode comprise carbon-containing and germanium-containing semiconductor materials.

[0016] In one possible implementation, the semiconductor material is a P-type doped semiconductor material.

[0017] In one possible implementation, it also includes metallic materials, semiconductor materials, and metallic materials formed into alloy materials.

[0018] In one possible implementation, a conductive support layer is further included between the first electrode and the first barrier layer, the conductive support layer comprising a carbon-containing alloy material.

[0019] In one possible implementation, the first electrode is the bottom electrode in the capacitor, and the bottom electrode has a cylindrical and / or columnar shape.

[0020] A second aspect of this disclosure provides a method for manufacturing a capacitor, comprising:

[0021] A first electrode is formed; a first barrier layer is formed on the first electrode; a first charge trapping layer is formed on the first barrier layer; a dielectric layer is formed on the first charge trapping layer; a second electrode is formed on the dielectric layer; wherein the band gap of the first charge trapping layer is smaller than the band gap of the dielectric layer, and the band gap of the first barrier layer is larger than the band gap of the dielectric layer.

[0022] The capacitor fabrication method provided in this disclosure can be used to fabricate a capacitor. The capacitor can form a first electrode, a dielectric layer, and a second electrode, with the dielectric layer located between the first and second electrodes. The capacitor also forms a first charge-trapping layer, located between the first electrode and the dielectric layer, with a band gap smaller than that of the dielectric layer. The first charge-trapping layer can trap charges in the dielectric layer. A first barrier layer is also formed between the first charge-trapping layer and the first electrode, with a band gap larger than that of the dielectric layer. The first barrier layer can prevent charges trapped in the first charge-trapping layer from transitioning to the first electrode. Thus, the first charge-trapping layer and the first barrier layer effectively prevent charges in the dielectric layer from transitioning to the first electrode, thereby reducing leakage current and improving the performance of the capacitor.

[0023] In one possible implementation, between forming the dielectric layer and forming the second electrode, the method further includes: forming a second charge trapping layer, the second charge trapping layer being located on the dielectric layer; and forming a second barrier layer, the second barrier layer being located on the second charge trapping layer; wherein the band gap of the second charge trapping layer is smaller than the band gap of the dielectric layer, and the band gap of the second barrier layer is larger than the band gap of the dielectric layer.

[0024] The second charge trapping layer and the second barrier layer can effectively prevent charge from jumping from the dielectric layer to the second electrode, thereby reducing leakage current and improving capacitor performance.

[0025] The structure of this disclosure, as well as its other inventive objectives and beneficial effects, will become more apparent from the description of the preferred embodiments taken in conjunction with the accompanying drawings. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the structure of a capacitor provided in an embodiment of this disclosure;

[0028] Figure 2 A schematic diagram of the structure provided in this disclosure showing that the charge of the dielectric layer is captured by the charge trapping layer;

[0029] Figure 3 This is a schematic diagram of the semiconductor structure provided in the embodiments of this disclosure;

[0030] Figure 4 This is another schematic diagram of the semiconductor structure provided in the embodiments of this disclosure;

[0031] Figure 5 A schematic flowchart illustrating the method for manufacturing a capacitor according to an embodiment of this disclosure;

[0032] Figure 6 This is a schematic diagram of the structure for forming the first electrode provided in an embodiment of the present disclosure;

[0033] Figure 7 This is a schematic diagram of the structure for forming the first barrier layer provided in an embodiment of the present disclosure;

[0034] Figure 8 This is a schematic diagram of the structure for forming the first charge trapping layer provided in an embodiment of the present disclosure;

[0035] Figure 9 This is a schematic diagram of the structure for forming a dielectric layer provided in an embodiment of the present disclosure;

[0036] Figure 10 This is a schematic diagram of the structure for forming the second charge trapping layer provided in an embodiment of the present disclosure;

[0037] Figure 11 This is a schematic diagram of the structure for forming the second barrier layer provided in an embodiment of the present disclosure;

[0038] Figure 12 This is a schematic diagram of the structure of a silicon-germanium layer doped with carbon provided in an embodiment of this disclosure;

[0039] Figure 13 This is a schematic diagram of the structure for forming a metallic material layer provided in an embodiment of this disclosure;

[0040] Figure 14 This is a schematic diagram of the structure for forming a silicon-germanium-carbon alloy layer provided in an embodiment of this disclosure;

[0041] Figure 15 A schematic diagram of the structure of the substrate provided in the embodiments of this disclosure;

[0042] Figure 16 A schematic diagram of a structure in which an isolation layer, a sacrificial layer and a support layer are sequentially formed, provided in an embodiment of this disclosure;

[0043] Figure 17 This is a schematic diagram of the structure for forming a capacitor hole provided in an embodiment of this disclosure;

[0044] Figure 18 This is a schematic diagram of the structure of the first electrode forming a columnar shape provided in an embodiment of the present disclosure;

[0045] Figure 19 This is a schematic diagram of the structure for removing the sacrificial layer provided in an embodiment of the present disclosure;

[0046] Figure 20This is a schematic diagram of the structure for forming a conductive support layer provided in an embodiment of the present disclosure;

[0047] Figure 21 This is another structural schematic diagram of the formation of the first barrier layer provided in an embodiment of the present disclosure;

[0048] Figure 22 This is another structural schematic diagram of the formation of the first charge trapping layer provided in an embodiment of the present disclosure;

[0049] Figure 23 This is another structural schematic diagram of the formation of the dielectric layer provided in an embodiment of the present disclosure;

[0050] Figure 24 This is another structural schematic diagram of forming a second charge trapping layer provided by an embodiment of the present disclosure;

[0051] Figure 25 This is another structural schematic diagram of the formation of the second barrier layer provided in an embodiment of the present disclosure.

[0052] Explanation of reference numerals in the attached figures:

[0053] 100: Semiconductor structure; 101: Capacitor;

[0054] 111: First electrode; 112: Second electrode;

[0055] 1121: Silicon-germanium layer; 1122: Silicon-germanium-carbon layer;

[0056] 1123: Metallic material layer; 1124: Silicon-germanium-carbon alloy layer;

[0057] 113: Conductive support layer; 120: Dielectric layer;

[0058] 130: Charge trapping layer; 131: First charge trapping layer;

[0059] 132: Second charge trapping layer; 140: Barrier layer;

[0060] 141: First barrier layer; 142: Second barrier layer;

[0061] 150: Substrate; 151: Substrate;

[0062] 152: Interlayer dielectric layer; 153: Contact element;

[0063] 161: Isolation layer; 162: Sacrifice layer;

[0064] 163: Support layer; 164: Capacitor via;

[0065] 170: Electric charge. Detailed Implementation

[0066] This disclosure provides a capacitor and a method for fabricating a capacitor. The capacitor may include a first electrode, a dielectric layer, and a second electrode, with the dielectric layer located between the first and second electrodes. The capacitor also includes a first charge-trapping layer located between the first electrode and the dielectric layer, the first charge-trapping layer having a smaller band gap than the dielectric layer. The first charge-trapping layer can trap charge in the dielectric layer. A first barrier layer is further disposed between the first charge-trapping layer and the first electrode, the first barrier layer having a larger band gap than the dielectric layer. The first barrier layer can prevent the charge trapped in the first charge-trapping layer from transitioning to the first electrode. Thus, the first charge-trapping layer and the first barrier layer effectively prevent charge transition from the dielectric layer to the first electrode, thereby improving leakage in the dielectric layer, preventing phenomena such as electron tunneling, reducing leakage current, and improving the performance of the capacitor.

[0067] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0068] The following will combine Figures 1-25 The capacitor 101 provided in the embodiments of this disclosure will be described.

[0069] The capacitor 101 provided in this disclosure can be applied to a semiconductor structure 100. The semiconductor structure 100 includes, but is not limited to, a memory device or a non-memory device. Memory devices may include, for example, Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), flash memory, Electrically Erasable Programmable Read-Only Memory (EEPROM), Phase Change Random Access Memory (PRAM), or Magnetoresistive Random Access Memory (MRAM). Non-memory devices may be logic devices (e.g., microprocessors, digital signal processors, or microcontrollers) or similar devices. This disclosure uses a DRAM memory device as an example for illustration.

[0070] like Figure 1 As shown, capacitor 101 may include electrodes, which may include a first electrode 111 and a second electrode 112, with a dielectric layer 120 disposed between the first electrode 111 and the second electrode 112.

[0071] In this embodiment, one of the first electrode 111 and the second electrode 112 is the bottom electrode, and the other electrode is the top electrode. This disclosure uses the example of the first electrode 111 being the bottom electrode of the capacitor 101 and the second electrode 112 being the top electrode of the capacitor 101 for illustration.

[0072] The first electrode 111 may include any one or more of metals, metal compounds, and semiconductor materials. The first electrode 111 may be a single-layer structure, or it may be a multi-layer stacked structure. The second electrode 112 may include any one or more of metals, metal compounds, and semiconductor materials. The second electrode 112 may be a single-layer structure, or it may be a multi-layer stacked structure. The materials of the first electrode 111 and the second electrode 112 may be the same or different.

[0073] The material of the first electrode 111 provided in the embodiments of this disclosure will be described below.

[0074] In some examples, the first electrode 111 may include a metal, for example, the metal may be any one or more of tantalum, titanium, nickel, cobalt, platinum, tungsten, ruthenium, iridium, etc.

[0075] In other examples, the first electrode 111 may include a metal compound, which may include at least one of a metal nitride and a metal oxide. For example, the metal compound may be any one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), ruthenium oxide, iridium oxide, etc.

[0076] In other examples, the first electrode 111 may include a semiconductor material, which may be at least one of silicon and germanium. This disclosure describes embodiments using silicon or silicon-germanium as examples of semiconductor materials. The semiconductor material may be a carbon-containing semiconductor material, where carbon atoms combine with silicon or silicon-germanium (SiGe) to form silicon-carbon (SiC) or silicon-germanium-carbon (SiGeC). Taking silicon-germanium-carbon (SiGeC) as an example, the smaller size of carbon atoms results in smaller grains in silicon-germanium-carbon (SiGeC) compared to silicon-germanium (SiGe), leading to lower roughness, better flatness, higher adhesion, and stronger pore-filling ability. Furthermore, the higher hardness of carbon results in greater hardness in silicon-germanium-carbon (SiGeC) compared to silicon-germanium (SiGe), resulting in better support and reducing or preventing bending and collapse of the first electrode 111.

[0077] The semiconductor material can be a P-type doped semiconductor material. For example, boron can be doped into the semiconductor material. When using P-type polycrystalline silicon, such as boron-doped SiGe, as the electrode of the capacitor, the capacitor 101 structure provided in this embodiment can effectively improve the problems of depletion under reverse bias at low boron concentration and boron penetration at high concentration. In this embodiment, the electrode is doped with carbon, which strengthens the bond between silicon-germanium-carbon and boron (SiGeC-B), making it less likely for boron to detach from the first electrode 111 and enter the dielectric layer 120 after the thermal process, thus preventing unnecessary charge trapping problems. Furthermore, when operating the DRAM device containing the capacitor 101, the top electrode of this embodiment will not form a reverse bias, thus preventing undesirable depletion effects.

[0078] In other embodiments, the semiconductor material can be an N-type doped semiconductor material. For example, arsenic or phosphorus can be doped into the semiconductor material. When other film layers contain boron, the semiconductor material provided in this disclosure embodiment can also effectively prevent the diffusion of boron. In the semiconductor manufacturing process, some of the gases used contain hydrogen, resulting in hydrogen being present in the first electrode 111. Carbon can strengthen the bonding between the semiconductor material and hydrogen, thereby reducing hydrogen transitions in the capacitor 101 and improving the performance of the capacitor 101.

[0079] In other examples, the first electrode 111 may comprise an alloy of semiconductor and metallic materials. The semiconductor material may be at least one of silicon and silicon-germanium, and may contain carbon; the principle of this has already been explained and will not be repeated here. The metallic material may be any one or more of tantalum, titanium, nickel, cobalt, platinum, tungsten, ruthenium, iridium, etc. The addition of metallic materials to the semiconductor material increases its conductivity, resulting in lower resistance for the first electrode 111. Furthermore, the metallic material can mitigate the depletion effect of the semiconductor material, thereby improving the performance of the capacitor 101. For example, the alloy material may be a SiC-Ti alloy, a SiC-Ni alloy, a SiGeC-Ni alloy, a SiGeC-Ti alloy, etc.

[0080] The second electrode 112 can be formed using any one or more of the materials of the first electrode 111 in the above examples. Its principle is similar to that of the first electrode 111, and will not be described again.

[0081] The following describes the media layer 120 provided in this disclosure.

[0082] The dielectric layer 120 can be a single-layer structure, or it can be a multi-layer stacked structure. The dielectric layer 120 can include a material with a high dielectric constant, such as any one or more of hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), and strontium titanium oxide (SrTiO3).

[0083] For example, the band gap of the dielectric layer 120 can be in the range of 4eV-6eV. The larger the dielectric constant of the dielectric layer 120, the larger the capacitance value. However, the larger the dielectric constant, the easier it is to cause leakage current. The band gap of the dielectric layer 120 can be in the range of 4eV-6eV. For example, the band gap of the dielectric layer 120 can be 4eV, 4.5eV, 5eV, 5.5eV, 6eV or any value between 4eV and 6eV.

[0084] The charge trapping layer 130 and the blocking layer 140 provided in this disclosure will be described below.

[0085] like Figure 1 As shown, capacitor 101 may further include a charge trapping layer 130, the band gap of which may be smaller than that of dielectric layer 120, and the charge trapping layer 130 may trap charge 170 in dielectric layer 120. Figure 2 ).

[0086] For example, the band gap of the charge trapping layer 130 can be in the range of 2 eV-4 eV, thereby avoiding the charge trapping layer 130 being too low and thus being broken down; and also avoiding the charge trapping layer 130 being too high and thus affecting its trapping performance. For example, the band gap of the charge trapping layer 130 can be 2 eV, 2.5 eV, 3 eV, 3.2 eV, 3.5 eV, 4 eV, or any value between 2 eV and 4 eV. Taking the charge trapping layer 130 as an example, which includes undoped silicon carbide material, silicon carbide has a band gap of 3.2 eV, which is relatively small and can effectively trap the charge 170 in the dielectric layer 120. Figure 2 ).

[0087] Additionally, capacitor 101 may also include a barrier layer 140 located on the side of charge trapping layer 130 away from dielectric layer 120. The band gap of barrier layer 140 may be larger than the band gap of dielectric layer 120. Barrier layer 140 may prevent charge 170 trapped in charge trapping layer 130 from transitioning to the electrodes (first electrode 111 and / or second electrode 112).

[0088] Herein, the charges 170 may be positive charge ions and / or negative charge ions. As Figure 2 shown, the band gap of the charge trapping layer 130 is H1, the band gap of the dielectric layer 120 is H2, and the band gap of the blocking layer 140 is H3, where H1<H2<H3. The charges 170 can enter the charge trapping layer 130 from the dielectric layer 120 and be trapped by the charge trapping layer 130, and the charges 170 are blocked by the blocking layer 140 and cannot jump into the electrode.

[0089] Exemplarily, the range of the band gap of the blocking layer 140 may be 8eV-10eV, so that the band gap of the blocking layer 140 can be prevented from being too low to avoid affecting the blocking effect of the blocking layer 140; and the band gap of the blocking layer 140 can also be prevented from being too high, so as to avoid greatly affecting the selectivity of the material for the blocking layer 140. For example, the band gap of the blocking layer 140 may be 8eV, 8.5eV, 9eV, 9.5eV, 10eV, or any value between 8eV and 10eV. Taking the blocking layer 140 including a silicon oxide material as an example, silicon oxide has a band gap of 9eV, which is a relatively large band gap and can effectively block the charges 170 in the charge trapping layer 130 from jumping into the electrode.

[0090] By providing both the charge trapping layer 130 and the blocking layer 140 between the dielectric layer 120 and the electrode, the charges 170 in the dielectric layer 120 can be effectively prevented from jumping into the first electrode 111 and / or the second electrode 112, thereby reducing the leakage current and improving the performance of the capacitor 101.

[0091] In some examples, as Figure 1 shown, the charge trapping layer 130 may include a first charge trapping layer 131, and the blocking layer 140 may include a first blocking layer 141. The first charge trapping layer 131 is located between the first electrode 111 and the dielectric layer 120, and the first blocking layer 141 is located between the first charge trapping layer 131 and the first electrode 111. In this way, by providing both the first charge trapping layer 131 and the first blocking layer 141 between the dielectric layer 120 and the first electrode 111, the charges 170 in the dielectric layer 120 can be effectively prevented from jumping into the first electrode 111, thereby reducing the leakage current and improving the performance of the capacitor 101.

[0092] With further reference to Figure 1In other examples, the charge trapping layer 130 may include a second charge trapping layer 132, and the blocking layer 140 may include a second blocking layer 142. The second charge trapping layer 132 is located between the second electrode 112 and the dielectric layer 120, and the second blocking layer 142 is located between the second charge trapping layer 132 and the second electrode 112. Thus, by simultaneously providing the second charge trapping layer 132 and the second blocking layer 142 between the dielectric layer 120 and the second electrode 112, the charge 170 in the dielectric layer 120 can be effectively prevented from transitioning to the second electrode 112, thereby reducing leakage current and improving the performance of the capacitor 101.

[0093] The material, thickness, band gap, and other parameters of the first barrier layer 141 and the second barrier layer 142 may be the same or different. The material, thickness, band gap, and other parameters of the first charge trapping layer 131 and the second charge trapping layer 132 may be the same or different.

[0094] In some embodiments, such as Figure 1 As shown, a conductive support layer 113 may also be provided between the first electrode 111 and the first barrier layer 141. The conductive support layer 113 can provide good support and adhesion for the capacitor 101, thereby reducing or preventing bending and collapse of the capacitor 101. The conductive support layer 113 may include a carbon-containing alloy material. For example, the conductive support layer 113 may be a silicon-carbon alloy formed from silicon-carbon (SiC) and any one or more of tantalum, titanium, nickel, cobalt, platinum, tungsten, ruthenium, iridium, etc.

[0095] The semiconductor structure 100 provided in the embodiments of this disclosure will be described below.

[0096] like Figure 3 and Figure 4 As shown, the semiconductor structure 100 may include a substrate 150, and a capacitor 101 may be located on the substrate 150. The substrate 150 may include a substrate 151, which may be made of monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium compound, etc. The substrate 151 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The substrate 151 may provide a supporting foundation for other structural layers on the substrate 151.

[0097] The substrate 150 may include an interlayer dielectric layer 152, which may be located between the substrate 151 and the capacitor 101. The interlayer dielectric layer 152 has a plurality of contacts 153 spaced apart along its extension direction, and the contacts 153 penetrate the interlayer dielectric layer 152 along its thickness direction. The capacitor 101 may include a plurality of first electrodes 111, which are spaced apart along the extension direction of the interlayer dielectric layer 152. One contact 153 corresponds to one first electrode 111, and the contact 153 contacts both the substrate 151 and the first electrode 111. An isolation layer 161 may be disposed on the interlayer dielectric layer 152, which can isolate the substrate 150 and the structural layers on the substrate 150.

[0098] like Figure 3 As shown, the semiconductor structure 100 may further include at least one support layer 163 for supporting the capacitor 101. When there are multiple support layers 163, the multiple support layers 163 are spaced apart along the thickness direction of the substrate 151. For example, the multiple support layers 163 may include a first support layer located at the end of the first electrode 111 away from the substrate 151, a second support layer located at the end of the first electrode 111 near the substrate 151, and a third support layer located between the first support layer and the second support layer. Figure 3 Only the first support layer is shown in the image.

[0099] like Figure 3 As shown, the first electrode 111 can be a columnar electrode. A conductive support layer 113 is disposed on the outer surface of the columnar electrode, the exposed outer surface of the isolation layer 161 and the support layer 163. A first barrier layer 141 is disposed on the side of the conductive support layer 113 away from the columnar electrode, the isolation layer 161 and the support layer 163. A first charge trapping layer 131 is disposed on the side of the first barrier layer 141 away from the conductive support layer 113. A dielectric layer 120 is disposed on the side of the first charge trapping layer 131 away from the conductive support layer 113. A second charge trapping layer 132 is disposed on the side of the dielectric layer 120 away from the conductive support layer 113. A second barrier layer 142 is disposed on the side of the second charge trapping layer 132 away from the conductive support layer 113. A second electrode 112 is disposed on the side of the second barrier layer 142 away from the conductive support layer 113.

[0100] like Figure 4As shown, the first electrode 111 can be a cylindrical electrode. Conductive support layers 113 are provided on the exposed outer surfaces of the isolation layer 161 and the support layer 163, as well as on the inner and outer surfaces of the cylindrical electrode. This allows full utilization of both the inner and outer surfaces of the cylindrical electrode, resulting in a larger electrode area for the capacitor 101 and thus increasing its capacitance. A first barrier layer 141 is provided on the side of the conductive support layer 113 away from the cylindrical electrode, the isolation layer 161, and the support layer 163. A first charge trapping layer 131 is provided on the side of the first barrier layer 141 away from the conductive support layer 113. A dielectric layer 120 is provided on the side of the first charge trapping layer 131 away from the conductive support layer 113. A second charge trapping layer 132 is provided on the side of the dielectric layer 120 away from the conductive support layer 113. A second barrier layer 142 is provided on the side of the second barrier layer 142 away from the conductive support layer 113. A second electrode 112 is provided on the side of the second barrier layer 142 away from the conductive support layer 113.

[0101] In the semiconductor structure 100, the plurality of first electrodes 111 can all be columnar electrodes or cylindrical electrodes, or some of the first electrodes 111 can be columnar electrodes and other parts of the first electrodes 111 can be cylindrical electrodes.

[0102] The following describes the method for preparing the capacitor 101 provided in the embodiments of this disclosure.

[0103] The method for preparing the capacitor 101 provided in this disclosure can be used to prepare the capacitor 101 in the above embodiments. Figure 5 As shown, the method for manufacturing the capacitor 101 may include:

[0104] S110: Form the first electrode.

[0105] like Figure 6 As shown, firstly, a first electrode 111 is formed. The first electrode 111 can be formed using sputtering or deposition processes (e.g., atomic layer deposition, chemical vapor deposition, or physical vapor deposition), and the first electrode 111 is, for example, tungsten W.

[0106] S120: Form a first barrier layer, which is located on the first electrode.

[0107] like Figure 7As shown, before forming the first barrier layer 141 on the first electrode 111, a conductive support layer 113 can be formed first, and then the first barrier layer 141 can be formed on the conductive support layer 113. The conductive support layer 113 may include a carbon-containing alloy material, such as SiC-Ti, formed by growing SiC in a furnace tube, followed by growing Ti through processes such as PVD or CVD, and then forming SiC-Ti through a temperature process. The first barrier layer 141 may include SiO2, formed through an ALD process.

[0108] S130: Form a first charge trapping layer, which is located on the first barrier layer.

[0109] like Figure 8 As shown, a first charge trapping layer 131 is formed on the first barrier layer 141. Thus, by simultaneously providing the first charge trapping layer 131 and the first barrier layer 141 between the dielectric layer 120 and the first electrode 111, the charge 170 in the dielectric layer 120 can be effectively prevented from transitioning to the first electrode 111, thereby reducing leakage current and improving the performance of the capacitor 101. The first charge trapping layer 131 can be, for example, undoped SiC. In this embodiment, undoped SiC and SiO2 are used as the first charge trapping layer 131 and the first barrier layer 141, respectively, to improve the performance of the subsequently formed dielectric layer 120.

[0110] S140: Form a dielectric layer, which is located on the first charge trapping layer.

[0111] like Figure 9 As shown, a dielectric layer 120 is formed on the first charge trapping layer 131, and the dielectric layer 120 may include a material with a high dielectric constant.

[0112] S150: Form a second electrode, which is located on the dielectric layer.

[0113] like Figure 10 and Figure 11 As shown, after forming the dielectric layer 120 and before forming the second electrode 112, the process may include forming a second charge trapping layer 132 on the dielectric layer 120 and forming a second barrier layer 142 on the second charge trapping layer 132. By simultaneously providing the second charge trapping layer 132 and the second barrier layer 142 between the dielectric layer 120 and the second electrode 112, the charge 170 in the dielectric layer 120 can be effectively prevented from transitioning to the second electrode 112, thereby reducing leakage current and improving the performance of the capacitor 101. The second charge trapping layer 132 and the second barrier layer 142 may have the same structure as the first charge trapping layer 131 and the first barrier layer 141.

[0114] Continue to refer to Figure 11After the second barrier layer 142 is formed, the dielectric layer 120 can be subjected to thermal annealing. The temperature range of the thermal annealing of the dielectric layer 120 can be 400℃-950℃, for example, the temperature of the thermal annealing can be 450℃, 650℃, or 700℃.

[0115] like Figure 1 As shown, after thermal annealing the dielectric layer 120, a second electrode 112 is formed on the second barrier layer 142.

[0116] In embodiments where the second electrode 112 is a P-type doped carbon-containing semiconductor material, forming the second electrode 112 may include: Figure 12 and Figure 13 As shown, a semiconductor material layer of silicon-germanium or silicon is first formed. For example, a silicon-germanium layer 1121 (or a silicon layer) can be formed first in a furnace tube. Then, the semiconductor material layer is doped to form a P-type silicon-germanium-carbon layer 1122 (or a silicon-carbon layer). The doping method can be plasma doping, ion implantation, etc.

[0117] In embodiments where the second electrode 112 is an alloy material comprising a p-type doped carbon-containing semiconductor material and a metallic material, forming the second electrode 112 may include: such as Figure 13 As shown, a silicon-germanium-carbon layer 1122 (or a silicon-carbon layer) is formed; the principle of this process has already been explained and will not be repeated here. Subsequently, a metal material layer 1123 is formed on the silicon-germanium-carbon layer 1122 (or the silicon-carbon layer). Figure 14 As shown, the silicon-germanium-carbon layer 1122 (or silicon-carbon layer) and the metal material layer 1123 are heat-treated to form a silicon-germanium-carbon alloy layer 1124 (or silicon-carbon alloy layer). The heat treatment may include hot annealing. Taking the formation of the silicon-germanium-carbon alloy layer 1124 as an example, the temperature range of the hot annealing treatment can be 400℃-900℃, and the time range of the hot annealing treatment can be 1min-20min, thus minimizing the impact on other structural layers while forming the alloy layer. For example, the temperature of the hot annealing treatment can be 400℃, 500℃, 600℃, 700℃, 800℃, 900℃, or any temperature between 400℃ and 900℃. The time of the hot annealing treatment can be 1min, 2min, 5min, 10min, 15min, 20min, or any time between 1min and 20min.

[0118] The following description uses a first electrode 111 provided in the embodiments of this disclosure as an example of a columnar electrode.

[0119] S110: Form the first electrode.

[0120] like Figure 15As shown, a substrate 150 may be provided before forming the first electrode 111, and then the first electrode 111 may be formed on the substrate 150. The substrate 150 may include a substrate 151 and an interlayer dielectric layer 152 formed on the substrate 151. The interlayer dielectric layer 152 includes a plurality of spaced contacts 153.

[0121] like Figure 16 As shown, forming the first electrode 111 may include sequentially stacking an isolation layer 161, a sacrificial layer 162, and a support layer 163 on a substrate 150. The sacrificial layer 162 is to be removed in a subsequent process, forming a space for accommodating the capacitor 101 after removal. The sacrificial layer 162 and the support layer 163 are made of different materials. The material of the sacrificial layer 162 may include any one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride, while the material of the support layer 163 may include any one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride. For example, the material of the support layer 163 may be silicon nitride, and the material of the sacrificial layer 162 may be silicon oxide.

[0122] like Figure 17 As shown, a patterned support layer 163, sacrificial layer 162, and isolation layer 161 are used to form a capacitor hole 164 that penetrates the support layer 163, sacrificial layer 162, and isolation layer 161, exposing a portion of the substrate 150. Multiple capacitor holes 164 may be included, and these holes are spaced apart along the extending direction of the substrate 150. The orthographic projection of the capacitor hole 164 onto the substrate 150 overlaps the orthographic projection of the contact 153 onto the substrate 150. Figure 18 As shown, a first electrode 111 is filled into the capacitor hole 164. The first electrode 111 can completely fill the capacitor hole 164 to form a columnar electrode.

[0123] like Figure 19 As shown, a portion of the support layer 163 is removed to expose a portion of the sacrificial layer 162. The sacrificial layer 162 is then completely removed using wet etching to expose the outer surface of the first electrode 111, facilitating the formation of other structural layers on the outer surface of the first electrode 111. Additionally, removing the sacrificial layer 162 also exposes the outer surfaces of the support layer 163 and the isolation layer 161.

[0124] like Figure 20 As shown, a conductive support layer 113 is formed on the first electrode 111. The conductive support layer 113 can cover the outer surface of the columnar electrode, the isolation layer 161, and the outer surface of the support layer 163.

[0125] It is understandable that in embodiments where the first electrode 111 is a cylindrical electrode, such as Figure 4As shown, the first electrode 111 covers the surface of the substrate 150 at the bottom of the capacitor hole 164 and the sidewall of the capacitor hole 164. The conductive support layer 113 covers the inner and outer surfaces of the cylindrical electrode, the outer surface of the insulating layer 161 and the support layer 163. Its principle is similar to that of the first electrode 111 being a columnar electrode, and will not be described again.

[0126] S120: Form a first barrier layer, which is located on the first electrode.

[0127] like Figure 21 As shown, a first barrier layer 141 is formed on the conductive support layer 113. The first barrier layer 141 is located on the side of the conductive support layer 113 away from the first electrode 111, the isolation layer 161 and the support layer 163.

[0128] S130: Form a first charge trapping layer, which is located on the first barrier layer.

[0129] like Figure 22 As shown, a first charge trapping layer 131 is formed on the first barrier layer 141, and the first charge trapping layer 131 is located on the side of the first barrier layer 141 away from the conductive support layer 113.

[0130] S140: Form a dielectric layer, which is located on the first charge trapping layer.

[0131] like Figure 23 As shown, a dielectric layer 120 is formed on the first charge trapping layer 131, and the dielectric layer 120 is located on the side of the first charge trapping layer 131 opposite to the conductive support layer 113.

[0132] like Figure 24 and Figure 25 As shown, a second charge trapping layer 132 and a second barrier layer 142 are then formed sequentially on the dielectric layer 120. The second charge trapping layer 132 is located on the side of the dielectric layer 120 away from the conductive support layer 113, and the second barrier layer 142 is located on the side of the second charge trapping layer 132 away from the conductive support layer 113.

[0133] S150: Form a second electrode, which is located on the dielectric layer.

[0134] like Figure 3 As shown, a second electrode 112 is formed on the second barrier layer 142, and the second electrode 112 is located on the side of the second barrier layer 142 away from the conductive support layer 113.

[0135] It should be noted that the numerical values ​​and ranges involved in the embodiments of this disclosure are approximate values. Due to the influence of the manufacturing process, there may be a certain range of errors, which can be considered negligible by those skilled in the art.

[0136] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A capacitor, characterized in that, include: The capacitor comprises a first electrode, a dielectric layer, and a second electrode, wherein the dielectric layer is located between the first electrode and the second electrode, and the band gap of the dielectric layer is 4eV-6eV; the capacitor further comprises: A first charge trapping layer is located between the first electrode and the dielectric layer, and the band gap of the first charge trapping layer is smaller than that of the dielectric layer; the first charge trapping layer comprises undoped silicon carbide material; A first barrier layer is located between the first charge trapping layer and the first electrode, and the band gap of the first barrier layer is larger than the band gap of the dielectric layer. Wherein, the band gap of the first charge trapping layer is 2eV-4eV; and / or, The band gap of the first barrier layer is 8eV-10eV.

2. The capacitor according to claim 1, characterized in that, The capacitor further includes: a second charge trapping layer located between the second electrode and the dielectric layer, wherein the band gap of the second charge trapping layer is smaller than the band gap of the dielectric layer; A second barrier layer is located between the second charge trapping layer and the second electrode, and the band gap of the second barrier layer is larger than the band gap of the dielectric layer.

3. The capacitor according to claim 1 or 2, characterized in that, The material of the dielectric layer includes at least one of hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, tantalum oxide, and niobium oxide.

4. The capacitor according to claim 2, characterized in that, The band gap of the second charge trapping layer is 2eV-4eV; and / or, The band gap of the second barrier layer is 8eV-10eV.

5. The capacitor according to claim 2, characterized in that, The first barrier layer and / or the second barrier layer comprise silicon oxide material.

6. The capacitor according to claim 2, characterized in that, The second charge trapping layer comprises undoped silicon carbide material.

7. The capacitor according to claim 1 or 2, characterized in that, The first electrode and / or the second electrode comprise a metal or a metal compound.

8. The capacitor according to claim 1 or 2, characterized in that, The first electrode and / or the second electrode comprise carbon-containing and germanium-containing semiconductor materials.

9. The capacitor according to claim 8, characterized in that, The semiconductor material is a P-type doped semiconductor material.

10. The capacitor according to claim 8, characterized in that, The first electrode and / or the second electrode having the semiconductor material further include a metallic material, wherein the semiconductor material and the metallic material are formed as an alloy.

11. The capacitor according to any one of claims 1 or 2, characterized in that, A conductive support layer is further included between the first electrode and the first barrier layer, and the conductive support layer comprises a carbon-containing alloy material.

12. The capacitor according to claim 1 or 2, characterized in that, The first electrode is the bottom electrode in the capacitor, and the bottom electrode has a cylindrical and / or columnar shape.

13. A method for manufacturing a capacitor, characterized in that, include: Form the first electrode; A first barrier layer is formed, and the first barrier layer is located on the first electrode; A first charge trapping layer is formed, which is located on the first barrier layer; A dielectric layer is formed on the first charge trapping layer, and the band gap of the dielectric layer is 4eV-6eV; a second electrode is formed on the dielectric layer. Wherein, the band gap of the first charge trapping layer is smaller than the band gap of the dielectric layer, and the band gap of the first blocking layer is larger than the band gap of the dielectric layer; the first charge trapping layer comprises undoped silicon carbide material; The band gap of the first charge trapping layer is 2eV-4eV; and / or the band gap of the first blocking layer is 8eV-10eV.

14. The method for preparing a capacitor according to claim 13, characterized in that, Between forming the dielectric layer and forming the second electrode, the method further includes: A second charge trapping layer is formed on the dielectric layer; a second barrier layer is formed on the second charge trapping layer; wherein the band gap of the second charge trapping layer is smaller than the band gap of the dielectric layer, and the band gap of the second barrier layer is larger than the band gap of the dielectric layer.

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