A photosensitive transistor, an array substrate and a display panel

Abstract

Embodiments of the present application provide a photosensitive transistor, an array substrate and a display panel, the photosensitive transistor comprising a first active layer, a first electrode, a second electrode, a first sub-gate and a second sub-gate, the first electrode being electrically connected with a first end of the first active layer, the second electrode being electrically connected with a second end of the first active layer; in a direction perpendicular to a plane in which the first active layer is located, the first sub-gate overlaps the first active layer and is located on a side of the first active layer away from the first electrode and the second electrode, the second sub-gate overlaps the first active layer and does not overlap the first sub-gate, and is located between the first active layer and the first electrode and the second electrode. Embodiments of the present application provide a photosensitive transistor, an array substrate and a display panel, so as to improve the photosensitive effect of the photosensitive transistor, reduce the threshold voltage offset of the photosensitive transistor, and improve the stability of the fingerprint identification circuit.

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to a photosensitive transistor, an array substrate, and a display panel. Background Technology

[0002] Because fingerprints are unique to each individual, they are innate. With technological advancements, various display devices with fingerprint recognition capabilities have emerged on the market, such as mobile phones, tablets, and smart wearable devices. This allows users to simply touch the display device with their finger before operating it; the fingerprint sensor identifies the fingerprint information, simplifying the authorization verification process.

[0003] The fingerprint recognition circuit is the circuit in the display panel used to realize fingerprint recognition. The threshold voltage of the photosensitive transistor in the fingerprint recognition circuit is prone to fluctuation under different light intensities, which affects the stability of the fingerprint recognition circuit. Summary of the Invention

[0004] This invention provides a photosensitive transistor, an array substrate, and a display panel to improve the photosensitivity of the photosensitive transistor, reduce the threshold voltage offset of the photosensitive transistor, and improve the stability of the fingerprint recognition circuit.

[0005] In a first aspect, embodiments of the present invention provide a photosensitive transistor, including a first active layer, a first electrode, a second electrode, a first sub-gate and a second sub-gate, wherein the first electrode is electrically connected to a first end of the first active layer and the second electrode is electrically connected to a second end of the first active layer.

[0006] In a direction perpendicular to the plane of the first active layer, the first sub-gate overlaps with the first active layer and is located on the side of the first active layer away from the first electrode and the second electrode. The second sub-gate overlaps with the first active layer but does not overlap with the first sub-gate and is located between the first active layer and the first electrode and the second electrode.

[0007] Optionally, it also includes an auxiliary electrode, which is electrically connected to the first sub-gate.

[0008] The second electrode is electrically connected to the second sub-gate.

[0009] In a second aspect, embodiments of the present invention provide an array substrate, comprising:

[0010] Substrate;

[0011] Sub-pixels are located on one side of the substrate;

[0012] A fingerprint recognition circuit, located on one side of the substrate, includes the photosensitive transistor described in the first aspect.

[0013] Optionally, it also includes a pixel driving circuit, the pixel driving circuit including a thin-film transistor;

[0014] The thin-film transistor includes a second active layer, a second gate, a third electrode, and a fourth electrode. The third electrode is electrically connected to a first end of the second active layer, and the fourth electrode is electrically connected to a second end of the second active layer. The second active layer is located between the third electrode and the fourth electrode and the substrate. In a direction perpendicular to the plane of the substrate, the second gate overlaps with the second active layer.

[0015] The second gate is on the same layer as either the first sub-gate or the second sub-gate.

[0016] Optionally, the second gate is on the same layer as the first sub-gate;

[0017] The second gate is located between the second active layer and the substrate, or the second gate is located between the third electrode and the fourth electrode and the second active layer.

[0018] Optionally, the third electrode and the fourth electrode are on the same layer as the second sub-gate.

[0019] Optionally, the second gate is located between the second active layer and the substrate, and the first active layer and the second active layer are on the same layer.

[0020] Optionally, the second gate and the second sub-gate are on the same layer;

[0021] The second gate is located between the third electrode and the fourth electrode and the second active layer.

[0022] Optionally, the first electrode, the second electrode, the third electrode, and the fourth electrode are in the same layer.

[0023] Optionally, the first active layer and the second active layer are on the same layer.

[0024] Optionally, the first active layer and the second active layer are made of the same material.

[0025] Thirdly, embodiments of the present invention also provide a display panel, including the array substrate described in the second aspect.

[0026] This invention provides a photosensitive transistor, including a first sub-gate and a second sub-gate. The first and second sub-gates are located on opposite sides of a first active layer, and overlap with different regions of the first active layer, effectively forming a transistor combining a bottom-gate structure and a top-gate structure. When light is projected onto the photosensitive transistor, since the first sub-gate is located on the back side of the first active layer, it does not block the light. The light is projected onto the first active layer above the first sub-gate, increasing the leakage current of the photosensitive transistor and improving its photosensitivity. When light is projected onto the photosensitive transistor, since the second sub-gate is located on the front side of the first active layer, it prevents light from being projected onto the first active layer below it. The shift in the threshold voltage of the top-gate structure formed by the second sub-gate reduces the threshold voltage shift of the photosensitive transistor, suppresses fluctuations in the threshold voltage of the photosensitive transistor under different light intensities, and improves the stability of the fingerprint recognition circuit. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the structure of a photosensitive transistor provided in an embodiment of the present invention;

[0028] Figure 2 This is a schematic diagram of another photosensitive transistor provided in an embodiment of the present invention;

[0029] Figure 3 This is a top view of an array substrate provided in an embodiment of the present invention;

[0030] Figure 4 For along Figure 3 A schematic diagram of the cross-sectional structure of AA';

[0031] Figure 5 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention;

[0032] Figure 6 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention;

[0033] Figure 7 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention;

[0034] Figure 8 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention;

[0035] Figure 9 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention;

[0036] Figure 10 This is a schematic diagram of the circuit structure of a fingerprint recognition circuit provided in an embodiment of the present invention;

[0037] Figure 11 This is a cross-sectional structural diagram of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0038] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0039] Figure 1 This is a schematic diagram of a photosensitive transistor provided in an embodiment of the present invention, with reference to... Figure 1 The photosensitive transistor 10 includes a first active layer 11, a first electrode 12, a second electrode 13, a first sub-gate 14, and a second sub-gate 15. The first electrode 12 is electrically connected to a first end of the first active layer 11, and the second electrode 13 is electrically connected to a second end of the first active layer 11. The first active layer 11 may include at least one of monocrystalline silicon, polycrystalline silicon, or a metal oxide. The metal oxide may be, for example, indium gallium zinc oxide (IGZO). Perpendicular to the plane of the first active layer 11, the first sub-gate 14 overlaps with the first active layer 11 and is located on the side of the first active layer 11 away from the first electrode 12 and the second electrode 13. The second sub-gate 15 overlaps with the first active layer 11 but does not overlap with the first sub-gate 14, and is located between the first active layer 11 and the first electrode 12 and the second electrode 13. The first sub-gate 14 and the second sub-gate 15 are located on opposite sides of the first active layer 11.

[0040] This invention provides a photosensitive transistor 10, including a first sub-gate 14 and a second sub-gate 15. The first sub-gate 14 and the second sub-gate 15 are respectively located on opposite sides of a first active layer 11, and the first sub-gate 14 and the second sub-gate 15 overlap with different regions of the first active layer 11, equivalent to forming a transistor combining a bottom gate structure and a top gate structure. Light (such as...) Figure 1When light is projected onto the photosensitive transistor 10 (as indicated by the middle arrow), since the first sub-gate 14 is located on the back of the first active layer 11, it does not block the light. The light is projected onto the first active layer 11 above the first sub-gate 14, increasing the leakage current of the photosensitive transistor 10 and improving its photosensitivity. When light is projected onto the photosensitive transistor 10, since the second sub-gate 15 is located on the front of the first active layer 11, the second sub-gate 15 prevents light from being projected onto the first active layer 11 below it. The shift in the threshold voltage of the top gate structure formed by the second sub-gate 15 can reduce the threshold voltage shift of the photosensitive transistor 10, suppress fluctuations in the threshold voltage of the photosensitive transistor 10 under different light intensities, and improve the stability of the fingerprint recognition circuit.

[0041] For example, the first electrode 12 and the second electrode 13 are located in the same film layer, and the first electrode 12 and the second electrode 13 are made of the same material and formed in the same patterning process. The first electrode 12 can be the source electrode and the second electrode 13 can be the drain electrode; or, the first electrode 12 can be the drain electrode and the second electrode 13 can be the source electrode.

[0042] It is understandable that the first sub-gate 14 and the second sub-gate 15 jointly control the channel conductivity of the first active layer 11, that is, the first sub-gate 14 and the second sub-gate 15 jointly control the on / off state of the first electrode 12 and the second electrode 13. Therefore, the same electrical signal can be provided to the first sub-gate 14 and the second sub-gate 15. Furthermore, in some fingerprint recognition circuits, it is necessary to provide the same electrical signal to the second electrode 13, the first sub-gate 14, and the second sub-gate 15 of the photosensitive transistor 10. It should be noted that in other fingerprint recognition circuits, different electrical signals can also be provided to the second electrode 13 and the first sub-gate 14 of the photosensitive transistor 10.

[0043] Figure 2 This is a schematic diagram of another photosensitive transistor structure provided in an embodiment of the present invention. The photosensitive transistor 10 further includes an auxiliary electrode 16, which is electrically connected to a first sub-gate 14, and a second electrode 13 is electrically connected to a second sub-gate 15. In this embodiment of the present invention, by setting the auxiliary electrode 16 to be electrically connected to the first sub-gate 14 and the second electrode 13 to be electrically connected to the second sub-gate 15, it is convenient to provide the same electrical signal to the second electrode 13, the first sub-gate 14, and the second sub-gate 15 of the photosensitive transistor 10. Further, in this embodiment of the present invention, the function of setting the auxiliary electrode 16 is to lead the first sub-gate 14 to the same film layer as the second electrode 13, so as to apply the same electrical signal to the second electrode 13 and the auxiliary electrode 16, or to facilitate the electrical connection between the second electrode 13 and the auxiliary electrode 16.

[0044] Figure 3 This is a top view of an array substrate provided in an embodiment of the present invention. Figure 4 For along Figure 3 Schematic diagram of the cross-sectional structure of AA' (see reference). Figure 3 and Figure 4 The array substrate includes a substrate 51, sub-pixels 21, and a fingerprint recognition circuit 22. The sub-pixels 21 are located on one side of the substrate 51. The sub-pixels 21 are light-emitting display units formed after the display panel is constructed. The fingerprint recognition circuit 22 is located on one side of the substrate 51 and includes the photosensitive transistor 10 described in the above embodiment. In this embodiment of the invention, since the array substrate includes the photosensitive transistor 10 described in the above embodiment, it has the beneficial effects of the photosensitive transistor 10, namely, improving the photosensitivity of the photosensitive transistor 10 and reducing the threshold voltage offset of the photosensitive transistor 10, thereby improving the stability of the fingerprint recognition circuit. It should be noted that... Figure 4 Including, for example Figure 2 The photosensitive transistor 10 shown is not limited to this. Figure 4 It can also include, for example Figure 1 The photosensitive transistor 10 is shown.

[0045] Optionally, refer to Figure 3 and Figure 4 The array substrate also includes a pixel driving circuit located on one side of the substrate 51, used to drive the sub-pixels 21 to emit light. The pixel driving circuit includes a thin-film transistor 30. The thin-film transistor 30 includes a second active layer 34, a second gate 31, a third electrode 32, and a fourth electrode 33. The third electrode 32 is electrically connected to a first end of the second active layer 34, and the fourth electrode 33 is electrically connected to a second end of the second active layer 34. The second active layer 34 is located between the third electrode 32, the fourth electrode 33, and the substrate 51. The second gate 31 overlaps with the second active layer 34 in a direction perpendicular to the plane of the substrate 51. The second gate 31 is on the same layer as the first sub-gate 14. In this embodiment of the invention, the second gate 31 and the first sub-gate 14 are on the same layer, thus eliminating the need to add a new film layer for the first sub-gate 14 and reducing the thickness of the array substrate. Since the second gate 31 and the first sub-gate 14 are on the same layer, the second gate 31 and the first sub-gate 14 can be formed using the same material in the same patterning process, saving process steps. It should be noted that, in one embodiment, the pixel driving circuit and the fingerprint recognition circuit 22 can together form a complete pixel circuit. A pixel circuit can be set in the area where one sub-pixel 21 is located or in the area where multiple sub-pixels 21 are located to realize display and fingerprint recognition functions.

[0046] Optionally, refer to Figure 4 The second gate 31 is on the same layer as the first sub-gate 14, and the second gate 31 is located between the third electrode 32 and the fourth electrode 33 and the second active layer 34. In this embodiment of the invention, the thin-film transistor 30 is a top-gate thin-film transistor, and the second gate 31 is on the same layer as the first sub-gate 14.

[0047] For example, refer to Figure 4 The pixel driving circuit also includes a storage capacitor 40, which includes a first electrode 41 and a second electrode 42. The first electrode 41 and the second electrode 42 overlap in a direction perpendicular to the substrate 51. The first electrode 41 is on the same layer as the second active layer 34 and can be made of the same material as the second active layer 34. The second electrode 42 is on the same layer as the second gate 31 and can be made of the same material as the second gate 31.

[0048] For example, refer to Figure 4 The third electrode 32 can be the source of the thin-film transistor 30, and the fourth electrode 33 can be the drain of the thin-film transistor 30. Alternatively, the third electrode 32 can be the drain of the thin-film transistor 30, and the fourth electrode 33 can be the source of the thin-film transistor 30.

[0049] Optionally, refer to Figure 4 The second gate 31 is on the same layer as the first sub-gate 14, and the third electrode 32 and the fourth electrode 33 are on the same layer as the second sub-gate 15. In this embodiment of the invention, the third electrode 32 and the fourth electrode 33 are on the same layer as the second sub-gate 15, thus eliminating the need to add a new film layer for the second sub-gate 15 and reducing the thickness of the array substrate. Since the third electrode 32 and the fourth electrode 33 are on the same layer as the second sub-gate 15, they can be formed using the same material in the same patterning process, saving on process steps.

[0050] By way of example, the array substrate may also include multiple insulating film layers. (Continue to refer to...) Figure 4 The array substrate includes a buffer layer 52, a first sub-gate insulating layer 53, a second sub-gate insulating layer 54, a first sub-spacer layer 55, a second sub-spacer layer 56, a first passivation layer 57, a second passivation layer 58, and a planarization layer 59, which are stacked sequentially. The buffer layer 52 is located between the substrate 51 and the thin-film transistor 30. The first sub-gate insulating layer 53 and the second sub-gate insulating layer 54 are both located between the second active layer 34 and the second gate 31. The first sub-spacer layer 55 and the second sub-spacer layer 56 are both located between the second gate 31 and the third electrode 32, with the third electrode 32 and the fourth electrode 33 on the same layer. The first passivation layer 57 is located between the third electrode 32 and the first electrode 12, with the first electrode 12 and the second electrode 13 on the same layer. The second passivation layer 58 is located between the first electrode 12 and the planarization layer 59. The planarization layer 59 is located between the sub-pixel 21 and the thin-film transistor 30; specifically, the planarization layer 59 is located between the sub-pixel 21 and the first electrode 12.

[0051] Figure 5 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention, with reference to... Figure 5The second gate 31 is on the same layer as the first sub-gate 14, and the first electrode 12, second electrode 13, third electrode 32, and fourth electrode 33 are on the same layer. In this embodiment of the invention, the first electrode 12, second electrode 13, third electrode 32, and fourth electrode 33 are on the same layer, thus eliminating the need to add new film layers for the first electrode 12 and second electrode 13, reducing the thickness of the array substrate. Since the first electrode 12, second electrode 13, third electrode 32, and fourth electrode 33 are on the same layer, they can be formed using the same material in the same patterning process, saving on process steps. Furthermore, in various embodiments, the auxiliary electrode 16, the first electrode 12, and the second electrode 13 are all located in the same film layer, that is, they are all disposed on the same layer.

[0052] For example, refer to Figure 5 The first sub-spacer layer 55 is located between the first sub-gate 14 and the first active layer 11. The second sub-spacer layer 56 is located between the first active layer 11 and the second sub-gate 15. The array substrate may also include a first insulating layer 510, which is located between the second sub-spacer layer 56 and the first passivation layer 57, and between the second sub-gate 15 and the first electrode 12.

[0053] Figure 6 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention, with reference to... Figure 6 The second gate 31 is on the same layer as the first sub-gate 14, and the second gate 31 is located between the second active layer 34 and the substrate 51. In this embodiment of the invention, the thin-film transistor 30 is a bottom-gate thin-film transistor, and the second gate 31 is on the same layer as the first sub-gate 14.

[0054] For example, refer to Figure 6 The third electrode 32, the fourth electrode 33, and the second sub-gate 15 are on the same layer. In this embodiment of the invention, the third electrode 32, the fourth electrode 33, and the second sub-gate 15 are on the same layer, thus eliminating the need to add a new film layer for the second sub-gate 15 and reducing the thickness of the array substrate. Since the third electrode 32, the fourth electrode 33, and the second sub-gate 15 are on the same layer, they can be formed using the same material in the same patterning process, saving on process steps.

[0055] Figure 7 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention, with reference to... Figure 7The second gate 31 is on the same layer as the first sub-gate 14, and is located between the second active layer 34 and the substrate 51. The first electrode 12, the second electrode 13, the third electrode 32, and the fourth electrode 33 are on the same layer. In this embodiment of the invention, the first electrode 12, the second electrode 13, the third electrode 32, and the fourth electrode 33 are on the same layer, thus eliminating the need to add new film layers for the first electrode 12 and the second electrode 13, reducing the thickness of the array substrate. The first electrode 12, the second electrode 13, the third electrode 32, and the fourth electrode 33 are on the same layer, and can be formed using the same material in the same patterning process, saving process steps.

[0056] For example, refer to Figure 7 The first sub-spacer layer 55 is located between the first active layer 11 and the second sub-gate 15. The second sub-spacer layer 56 is located between the second sub-gate 15 and the first electrode 12. The first electrode 12, the second electrode 13, the third electrode 32, and the fourth electrode 33 are on the same layer, so only one passivation layer needs to be provided for the first electrode 12, the second electrode 13, the third electrode 32, and the fourth electrode 33, that is, only the first passivation layer 57 needs to be provided, and the second passivation layer 58 does not need to be provided, thereby reducing the thickness of the array substrate.

[0057] Optionally, refer to Figure 6 or Figure 7 In any of the arrays, the second gate 31 is located between the second active layer 34 and the substrate 51, and the first active layer 11 and the second active layer 34 are on the same layer. In this embodiment of the invention, the first active layer 11 and the second active layer 34 are on the same layer, thereby eliminating the need to add a new film layer to the first active layer 11 and reducing the thickness of the array substrate.

[0058] Furthermore, the first active layer 11 and the second active layer 34 are made of the same material, thus allowing them to be formed in the same patterning process using the same material, saving on process steps. Exemplarily, both the first active layer 11 and the second active layer 34 comprise polycrystalline silicon, monocrystalline silicon, or metal oxides. The metal oxide may include, for example, indium gallium zinc oxide (IGZO). Metal oxides have high carrier mobility, which can reduce the size of the photosensitive transistor 10, lower costs, and reduce the space occupied in the display area, thereby improving the resolution of the display panel. In other embodiments, the first active layer 11 and the second active layer 34 may also be made of different materials; this embodiment of the invention does not limit this.

[0059] Figure 8 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention, with reference to... Figure 8Since the second gate 31 and the second sub-gate 15 are on the same layer, there is no need to add a new film layer for the second sub-gate 15, thus reducing the thickness of the array substrate. Because the second gate 31 and the second sub-gate 15 are on the same layer, they can be formed using the same material in the same patterning process, saving on process steps.

[0060] For example, refer to Figure 8 The second gate 31 is on the same layer as the second sub-gate 15. The first electrode 12, the second electrode 13, the third electrode 32 and the fourth electrode 33 are on the same layer, so only one passivation layer needs to be provided for the first electrode 12, the second electrode 13, the third electrode 32 and the fourth electrode 33, that is, only the first passivation layer 57 needs to be provided, and the second passivation layer 58 does not need to be provided, thereby reducing the thickness of the array substrate.

[0061] For example, refer to Figure 8 The first sub-gate 14 is on the same layer as the second active layer 34, thus eliminating the need for adding a new film layer to the first sub-gate 14 and reducing the thickness of the array substrate. The first sub-gate insulating layer 53 is located between the first sub-gate 14 and the first active layer 11. The second sub-gate insulating layer 54 is located between the first active layer 11 and the second sub-gate 15.

[0062] Optionally, refer to Figure 8 The second gate 31 is on the same layer as the second sub-gate 15, and the second gate 31 is located between the third electrode 32 and the fourth electrode 33 and the second active layer 34. The thin-film transistor 30 is a top-gate thin-film transistor, with the second gate 31 and the second sub-gate 15 on the same layer.

[0063] Figure 9 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention, with reference to... Figure 9 The second gate 31 and the second sub-gate 15 are on the same layer, and the first active layer 11 and the second active layer 34 are on the same layer. In this embodiment of the invention, the first active layer 11 and the second active layer 34 are on the same layer, so there is no need to add a new film layer to the first active layer 11, thus reducing the thickness of the array substrate.

[0064] Furthermore, the first active layer 11 and the second active layer 34 can also be made of the same material.

[0065] For example, refer to Figure 9 The array substrate may also include a second insulating layer 511, which is located between the buffer layer 52 and the first sub-gate insulating layer 53, and between the first sub-gate 14 and the first active layer 11.

[0066] For example, continue to refer to Figure 3The array substrate includes a display area AA, in which multiple sub-pixels 21 are arranged in an array along a first direction and a second direction. Multiple fingerprint recognition circuits 22 are located in the display area AA and are arranged in an array. In other embodiments, the array substrate may further include a non-display area located around the display area AA, and the fingerprint recognition circuits 22 may also be disposed in the non-display area.

[0067] Figure 10 This is a schematic diagram of the circuit structure of a fingerprint recognition circuit provided in an embodiment of the present invention, with reference to... Figure 10 The gate (including the first sub-gate 14 and the second sub-gate 15) of the photosensitive transistor 10 is electrically connected to the source (i.e., the second electrode 13). Specifically, the auxiliary electrode 16 is electrically connected to the first sub-gate 14, and the second electrode 13 is electrically connected to the second sub-gate 15. The second electrode 13 of the photosensitive transistor 10 is electrically connected to the first voltage terminal VSS. The first voltage terminal VSS provides the same electrical signal to the second electrode 13, the first sub-gate 14, and the second sub-gate 15 of the photosensitive transistor 10. The first electrode 12 of the photosensitive transistor 10 is connected to the sensing node N1. The fingerprint recognition circuit also includes a first transistor M1, a second transistor M2, a third transistor M3, and a storage capacitor C. The gate of the first transistor M1 is coupled to the reset port reset to receive a reset control signal. The first electrode of the first transistor M1 is coupled to the second voltage terminal VDD, and the second electrode of the first transistor M1 is coupled to the sensing node N1. The gate of the second transistor M2 is coupled to the sensing node N1, and the first electrode of the second transistor M2 is coupled to the second voltage terminal VDD. The gate of the third transistor M3 is coupled to the output control terminal select, and the first terminal of the third transistor M3 is coupled to the second terminal of the second transistor M2. The first plate of the storage capacitor C is coupled to the sensing node N1, and the second plate of the storage capacitor C is coupled to the first voltage terminal VSS. During the reset phase, the first transistor M1 is turned on, that is, the reset control signal controls the first transistor M1 to be a conductor, so that a positive power supply voltage is applied to the sensing node N1 from the second voltage terminal VDD. This causes the sensing node N1 to reset in response to the positive power supply voltage. During the sensing phase, the reset port reset controls the first transistor M1 to be turned off, the output control terminal select controls the third transistor M3 to be turned off, the phototransistor 10 receives light, and generates a photocurrent according to the light intensity, thereby changing the voltage value of the sensing node N1 and storing the voltage value of the sensing node N1 in the storage capacitor C. During the output phase, the reset port controls the first transistor M1 to be turned off, and the output control terminal select controls the third transistor M3 to be turned on. As a result, the second transistor M2 will generate a corresponding drive current according to its gate-source voltage. Since the second voltage terminal VDD is a constant voltage, the second transistor M2 generates a drive current corresponding to the voltage of the sensing node N1. The drive current will be output to the read line L through the third transistor M3.

[0068] Figure 11 This is a cross-sectional structural diagram of a display panel provided in an embodiment of the present invention, with reference to... Figure 11 The display panel includes the array substrate described in the above embodiments. In this embodiment of the invention, since the display panel includes the array substrate described in the above embodiments, it also includes the photosensitive transistor 10 described in the above embodiments. Therefore, it has the beneficial effects of the photosensitive transistor 10, namely, improving the photosensitivity of the photosensitive transistor 10 and reducing the threshold voltage offset of the photosensitive transistor 10, thereby improving the stability of the fingerprint recognition circuit.

[0069] For example, refer to Figure 11 The display panel may further include a pixel defining layer 512 and a thin-film encapsulation layer 60. A sub-pixel 21 may include an anode 211, an organic light-emitting layer 212, and a cathode 213. The organic light-emitting layer 212 is located between the anode 211 and the cathode 213. The anode 211 is electrically connected to the fourth electrode 33 of the thin-film transistor 30. The pixel defining layer 512 is located between the thin-film encapsulation layer 60 and the planarization layer 59. The organic light-emitting layer 212 is disposed in an opening in the pixel defining layer 512. The thin-film encapsulation layer 60 is located on the side of the sub-pixel 21 away from the substrate 51, serving to prevent moisture and oxygen corrosion. In this embodiment of the invention, the display panel is an organic light-emitting display panel. In other embodiments, the display panel may be other types of display panels, such as micro-LED display panels, etc., and the present invention does not limit this.

[0070] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A photosensitive transistor, characterized in that, It includes a first active layer, a first electrode, a second electrode, a first sub-gate and a second sub-gate, wherein the first electrode is electrically connected to a first end of the first active layer and the second electrode is electrically connected to a second end of the first active layer; In a direction perpendicular to the plane of the first active layer, the first sub-gate overlaps with the first active layer and is located on the side of the first active layer away from the first electrode and the second electrode; the second sub-gate overlaps with the first active layer but does not overlap with the first sub-gate and is located between the first active layer and the first electrode and the second electrode. It also includes an auxiliary electrode, which is electrically connected to the first sub-gate. The second electrode is electrically connected to the second sub-gate. The first sub-gate and the second sub-gate jointly control the channel conductivity of the first active layer, and the first sub-gate and the second sub-gate are used to receive the same electrical signal.

2. An array substrate, characterized in that, include: Substrate; Sub-pixels are located on one side of the substrate; A fingerprint recognition circuit, located on one side of the substrate, includes the photosensitive transistor as described in claim 1.

3. The array substrate according to claim 2, characterized in that, It also includes a pixel driving circuit, which includes a thin-film transistor; The thin-film transistor includes a second active layer, a second gate, a third electrode, and a fourth electrode. The third electrode is electrically connected to a first end of the second active layer, and the fourth electrode is electrically connected to a second end of the second active layer. The second active layer is located between the third electrode, the fourth electrode, and the substrate. In a direction perpendicular to the plane of the substrate, the second gate overlaps with the second active layer; The second gate is on the same layer as either the first sub-gate or the second sub-gate.

4. The array substrate according to claim 3, characterized in that, The second gate is on the same layer as the first sub-gate; The second gate is located between the second active layer and the substrate, or the second gate is located between the third electrode and the fourth electrode and the second active layer.

5. The array substrate according to claim 4, characterized in that, The third electrode and the fourth electrode are on the same layer as the second sub-gate.

6. The array substrate according to claim 4, characterized in that, The second gate is located between the second active layer and the substrate, and the first active layer and the second active layer are on the same layer.

7. The array substrate according to claim 3, characterized in that, The second gate and the second sub-gate are on the same layer; The second gate is located between the third electrode and the fourth electrode and the second active layer.

8. The array substrate according to claim 4 or 7, characterized in that, The first electrode, the second electrode, the third electrode, and the fourth electrode are in the same layer.

9. The array substrate according to claim 7, characterized in that, The first active layer and the second active layer are on the same layer.

10. The array substrate according to claim 6 or 9, characterized in that, The first active layer and the second active layer are made of the same material.

11. A display panel, characterized in that, Includes the array substrate as described in any one of claims 2-10.

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