Circuit, chip and electronic device for preventing leakage of field effect transistor

Abstract

The embodiment of the present disclosure discloses a circuit for preventing leakage of field effect transistor, a chip and an electronic device. The circuit comprises a MOSFET module and a substrate voltage generation module. The MOSFET module comprises a first resistor, a first switch and a first MOSFET. The first input end of the substrate voltage generation module is connected with a first voltage source, the second input end is connected with a second voltage source, and the output end is connected with the substrate of the first MOSFET. The source of the first MOSFET is connected with the first voltage source, the drain is connected with the second voltage source, and the gate is connected with the first end of the first resistor. The first end of the first resistor is connected with the first end of the first switch. The second end of the first switch is connected with one end of a current source. The second end of the first resistor is connected with the substrate of the first MOSFET. Through the circuit structure, the channel leakage of the MOSFET is effectively avoided.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuits, and more specifically to a circuit, chip, and electronic device for preventing leakage current in a field-effect transistor. Background Technology

[0002] With the widespread use of metal-oxide-semiconductor field-effect transistors (MOSFETs) in analog and digital circuits, the channel leakage current problem of MOSFETs has gradually attracted attention.

[0003] Currently, MOSFETs are typically configured with their gate and source terminals grounded. Theoretically, this voltage divider can ensure that the gate and source voltages are identical, thus preventing channel leakage. However, in practical applications, it's difficult to guarantee identical gate and source voltages using voltage divider alone. With a P-type MOSFET, if the gate voltage is less than a threshold voltage compared to the source voltage, current will flow, causing channel leakage. Similarly, with an N-type MOSFET, if the gate voltage is greater than a threshold voltage compared to the source voltage, current will also flow, leading to channel leakage.

[0004] Therefore, how to effectively avoid channel leakage in MOSFETs has become a technical problem that urgently needs to be solved. Summary of the Invention

[0005] To address the problems in the related technologies, embodiments of this disclosure provide a circuit, chip, and electronic device for preventing leakage current in field-effect transistors.

[0006] In a first aspect, embodiments of this disclosure provide a circuit for preventing leakage current in a field-effect transistor.

[0007] Specifically, the circuit includes a MOSFET module and a substrate voltage generation module, wherein the MOSFET module includes a first resistor, a first switch, and a first MOSFET;

[0008] Wherein, the first input terminal of the substrate voltage generation module is connected to the first voltage source, the second input terminal of the substrate voltage generation module is connected to the second voltage source, and the output terminal of the substrate voltage generation module is connected to the substrate of the first MOSFET;

[0009] The source of the first MOSFET is connected to the first voltage source, the drain of the first MOSFET is connected to the second voltage source, the gate of the first MOSFET is connected to the first end of the first resistor, the first end of the first resistor is also connected to the first end of the first switch, the second end of the first switch is connected to one end of the current source, and the second end of the first resistor is connected to the substrate of the first MOSFET.

[0010] The first MOSFET is a P-type MOSFET. The substrate voltage generation module is used to output the higher voltage of the first voltage and the second voltage through the output terminal of the substrate voltage generation module in response to the first voltage of the first voltage source and the second voltage of the second voltage source satisfying a first preset condition.

[0011] Alternatively, the first MOSFET is an N-type MOSFET, and the substrate voltage generation module is used to output the lower voltage of the first voltage and the second voltage through the output terminal of the substrate voltage generation module in response to the first voltage of the first voltage source and the second voltage of the second voltage source satisfying a second preset condition.

[0012] In one implementation of this disclosure, the substrate voltage generation module includes: a second MOSFET and a third MOSFET;

[0013] Wherein, the drain of the second MOSFET is connected to the first input terminal of the substrate voltage generation module, the gate of the second MOSFET is connected to the second input terminal of the substrate voltage generation module, the substrate of the second MOSFET is connected to the substrate of the first MOSFET and the substrate of the third MOSFET respectively, and the source of the second MOSFET is connected to the substrate of the first MOSFET and the source of the third MOSFET respectively.

[0014] The source of the third MOSFET is connected to the substrate of the first MOSFET, the substrate of the third MOSFET is connected to the substrate of the first MOSFET, the drain of the third MOSFET is connected to the second input terminal of the substrate voltage generation module, and the gate of the third MOSFET is connected to the first input terminal of the substrate voltage generation module.

[0015] In one implementation of this disclosure, the substrate voltage generation module further includes: a second resistor and a third resistor;

[0016] Wherein, one end of the second resistor is connected to the first input terminal of the substrate voltage generation module, and the other end of the second resistor is connected to the gate of the third MOSFET;

[0017] One end of the third resistor is connected to the second input terminal of the substrate voltage generation module, and the other end of the third resistor is connected to the gate of the second MOSFET.

[0018] In one implementation of this disclosure, the first MOSFET, the second MOSFET, and the third MOSFET are all P-type MOSFETs. The substrate voltage generation module is used to output the first voltage through its output terminal in response to a voltage difference between the first voltage and the second voltage being greater than or equal to a first preset threshold voltage.

[0019] In one implementation of this disclosure, the first MOSFET, the second MOSFET, and the third MOSFET are all P-type MOSFETs. The substrate voltage generation module is used to output the second voltage through the output terminal of the substrate voltage generation module in response to the voltage difference obtained by subtracting the first voltage from the second voltage being greater than or equal to the first preset threshold voltage.

[0020] In one implementation of this disclosure, the first MOSFET, the second MOSFET, and the third MOSFET are all N-type MOSFET transistors. The substrate voltage generation module is used to output the second voltage through the output terminal of the substrate voltage generation module in response to the voltage difference obtained by subtracting the second voltage from the first voltage being greater than or equal to a second preset threshold voltage.

[0021] In one implementation of this disclosure, the first MOSFET, the second MOSFET, and the third MOSFET are all N-type MOSFETs. The substrate voltage generation module is used to output the first voltage through the output terminal of the substrate voltage generation module in response to the voltage difference obtained by subtracting the first voltage from the second voltage being greater than or equal to the second preset threshold voltage.

[0022] In one implementation of this disclosure, the resistance of the first resistor is 250 kiloohms.

[0023] In one implementation of this disclosure, the current source has a current magnitude of 10 microamps.

[0024] Secondly, this disclosure provides a chip that includes the circuitry described in the first aspect and any possible implementation thereof.

[0025] Thirdly, embodiments of this disclosure provide an electronic device that includes the chip described in the second aspect.

[0026] The technical effects provided by the embodiments of this disclosure may include the following beneficial effects:

[0027] With the circuit structure provided in this disclosure, when the first MOSFET is a P-type MOSFET, the substrate voltage generation module provides the higher of the first voltage and the second voltage to the substrate of the first MOSFET. If the first switch is open, the voltage between the gate and the substrate of the first MOSFET is the same, both being the higher of the first and second voltages, meaning that both the gate and the substrate of the first MOSFET are at a high level, thereby avoiding channel leakage of the P-type first MOSFET. The gate and the substrate of the first MOSFET are connected through a first resistor. Correspondingly, when the first MOSFET is an N-type MOSFET, the substrate voltage generation module provides the lower of the first voltage and the second voltage to the substrate of the first MOSFET. If the first switch is open, the voltage between the gate and the substrate of the first MOSFET is the same, both being the lower of the first and second voltages, meaning that both the gate and the substrate of the first MOSFET are at a low level, thereby similarly avoiding channel leakage of the N-type first MOSFET. Therefore, with the circuit structure provided in this disclosure, channel leakage of the MOSFET can be effectively avoided.

[0028] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0029] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings.

[0030] Figure 1 A circuit diagram illustrating the prevention of leakage current in a field-effect transistor according to an embodiment of the present disclosure is shown.

[0031] Figure 2 Another schematic diagram of a circuit for preventing leakage current in a field-effect transistor according to an embodiment of the present disclosure is shown.

[0032] Figure 3 Another schematic diagram of a circuit for preventing leakage current in a field-effect transistor according to an embodiment of the present disclosure is shown. Detailed Implementation

[0033] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings to enable those skilled in the art to readily implement them. Furthermore, for clarity, portions unrelated to the description of exemplary embodiments have been omitted from the drawings.

[0034] In this disclosure, it should be understood that terms such as “comprising” or “having” are intended to indicate the presence of features, figures, steps, behaviors, components, parts or combinations thereof disclosed in this specification, and are not intended to exclude the possibility of the presence or addition of one or more other features, figures, steps, behaviors, components, parts or combinations thereof.

[0035] It should also be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0036] As mentioned above, MOSFETs are typically configured with their gate and source terminals grounded. Theoretically, this voltage divider ensures that the gate and source voltages are identical, thus preventing channel leakage. However, in practical applications, it's difficult to guarantee identical gate and source voltages using voltage divider alone. With a P-type MOSFET, if the gate voltage is less than a threshold voltage compared to the source voltage, current will flow, causing channel leakage. Similarly, with an N-type MOSFET, if the gate voltage is greater than a threshold voltage compared to the source voltage, current will also flow, leading to channel leakage.

[0037] In view of the above-mentioned defects, this disclosure provides a circuit for preventing leakage current in a field-effect transistor. The circuit includes a MOSFET module consisting of a first resistor, a first switch, and a first MOSFET, and a substrate voltage generation module. The first input terminal of the substrate voltage generation module is connected to a first voltage source, the second input terminal is connected to a second voltage source, the output terminal is connected to the substrate of the first MOSFET, the source of the first MOSFET is connected to the first voltage source, the drain of the first MOSFET is connected to the second voltage source, and the gate of the first MOSFET is connected to the substrate via the first resistor. Thus, with this circuit structure, when the first MOSFET is a P-type MOSFET, the substrate voltage generation module provides the higher of the first and second voltages to the substrate of the first MOSFET. If the first switch is open, the voltages of the gate and substrate of the first MOSFET are the same, both being the higher of the first and second voltages, i.e., both the gate and substrate of the first MOSFET are at a high level, thus avoiding channel leakage current in the P-type first MOSFET. Accordingly, when the first MOSFET is an N-type MOSFET, the substrate voltage generation module provides the lower of the first and second voltages to the substrate of the first MOSFET. If the first switch is turned on, the voltage between the gate and the substrate of the first MOSFET is the same, which is the lower of the first and second voltages. That is, both the gate and the substrate of the first MOSFET are at a low level, thus avoiding channel leakage of the N-type first MOSFET. Therefore, this circuit structure can effectively prevent channel leakage of the MOSFET.

[0038] Figure 1 A circuit diagram illustrating the prevention of leakage current in a field-effect transistor according to an embodiment of the present disclosure is shown.

[0039] like Figure 1 As shown, the circuit includes a MOSFET module and a substrate voltage generation module.

[0040] The MOSFET module includes a first resistor R1, a first switch S1, and a first MOSFET M1.

[0041] The first input terminal L1 of the substrate voltage generation module is connected to the first voltage source V1, the second input terminal L2 of the substrate voltage generation module is connected to the second voltage source V2, and the output terminal L3 of the substrate voltage generation module is connected to the substrate B of the first MOSFET M1.

[0042] In this configuration, the source S of the first MOSFET M1 is connected to the first voltage source V1, the drain D of the first MOSFET M1 is connected to the second voltage source V2, the gate G of the first MOSFET M1 is connected to the first terminal L4 of the first resistor R1, the first terminal L4 of the first resistor is also connected to the first terminal L6 of the first switch S1, the second terminal L7 of the first switch is connected to one end of the current source I, and the second terminal L5 of the first resistor R1 is connected to the substrate B of the first MOSFET M1.

[0043] like Figure 1 In the circuit shown, when the first MOSFET M1 is a P-type MOSFET, the substrate voltage generation module is used to output the higher voltage of the first voltage v1 and the second voltage v2 through the output terminal L3 of the substrate voltage generation module in response to the first voltage v1 of the first voltage source V1 and the second voltage v2 of the second voltage source V2 satisfying a first preset condition; or, when the first MOSFET M1 is an N-type MOSFET, the substrate voltage generation module is used to output the lower voltage of the first voltage v1 and the second voltage v2 through the output terminal L3 of the substrate voltage generation module in response to the first voltage v1 of the first voltage source V1 and the second voltage v2 of the second voltage source V2 satisfying a second preset condition.

[0044] In one embodiment of this disclosure, the first preset condition is: the voltage difference obtained by subtracting the second voltage v2 from the first voltage v1 is greater than or equal to the preset threshold voltage of the P-type MOSFET, or the voltage difference obtained by subtracting the first voltage v1 from the second voltage v2 is greater than or equal to the preset threshold voltage of the P-type MOSFET.

[0045] In one embodiment of this disclosure, the second preset condition is: the voltage difference obtained by subtracting the second voltage v2 from the first voltage v1 is greater than or equal to the preset threshold voltage of the N-type MOSFET, or the voltage difference obtained by subtracting the first voltage v1 from the second voltage v2 is greater than or equal to the preset threshold voltage of the N-type MOSFET.

[0046] In the above embodiments, by Figure 1In the circuit structure shown, when the first MOSFET M1 is a P-type MOSFET, the substrate voltage generation module outputs the higher of the first voltage v1 and the second voltage v2 through the output terminal L3 of the substrate voltage generation module. That is, it provides the higher of the first voltage v1 and the second voltage v2 to the substrate B of the first MOSFET M1. If the first switch S1 is opened at this time, the gate G of the first MOSFET M1 and the substrate B are equivalent to the first resistance R1. Then the voltage of the gate G of the first MOSFET M1 and the substrate B are the same, which is the higher of the first voltage v1 and the second voltage v2. That is, the gate G of the first MOSFET M1 and the substrate B are both at a high level, thus avoiding channel leakage of the P-type first MOSFET M1.

[0047] Correspondingly, when the first MOSFET M1 is an N-type MOSFET, the substrate voltage generation module will output the lower of the first voltage v1 and the second voltage v2 through the output terminal L3 of the substrate voltage generation module. That is, it provides the lower of the first voltage v1 and the second voltage v2 to the substrate B of the first MOSFET M1. If the first switch S1 is opened at this time, the gate G of the first MOSFET M1 and the substrate B are equivalent to the first resistance R1. Then the voltage of the gate G of the first MOSFET M1 and the substrate B are the same, which is the lower of the first voltage v1 and the second voltage v2. That is, the gate G of the first MOSFET M1 and the substrate B are both at a low level, which also avoids channel leakage of the N-type first MOSFET M1.

[0048] It should be understood that when the first MOSFET M1 is a P-type MOSFET, the substrate voltage generation module provides the higher of the first voltage v1 and the second voltage v2 to the substrate B of the first MOSFET M1, meaning the level of the substrate B of the first MOSFET M1 is always high, thus preventing leakage of the substrate B of the P-type first MOSFET M1. Correspondingly, when the first MOSFET M1 is an N-type MOSFET, the substrate voltage generation module provides the lower of the first voltage v1 and the second voltage v2 to the substrate B of the first MOSFET M1, meaning the level of the substrate B of the first MOSFET M1 is always low, similarly preventing leakage of the substrate B of the N-type first MOSFET M1.

[0049] Figure 2 Another schematic diagram of a circuit for preventing leakage current in a field-effect transistor according to an embodiment of the present disclosure is shown.

[0050] like Figure 2 As shown, the circuit includes a MOSFET module and a substrate voltage generation module.

[0051] The substrate voltage generation module includes a second MOSFET M2 and a third MOSFET M3.

[0052] In this configuration, the drain D of the second MOSFET M2 is connected to the first input terminal L1 of the substrate voltage generation module, the gate G of the second MOSFET M2 is connected to the second input terminal L2 of the substrate voltage generation module, the substrate B of the second MOSFET M2 is connected to the substrate B of the first MOSFET M1 and the substrate B of the third MOSFET M3, respectively, and the source S of the second MOSFET M2 is connected to the substrate B of the first MOSFET M1 and the source S of the third MOSFET M3, respectively. The source S of the third MOSFET M3 is connected to the substrate B of the first MOSFET M1, the substrate B of the third MOSFET M3 is connected to the substrate B of the first MOSFET M1, the drain D of the third MOSFET M3 is connected to the second input terminal L2 of the substrate voltage generation module, and the gate G of the third MOSFET M3 is connected to the first input terminal L1 of the substrate voltage generation module.

[0053] In one embodiment of this disclosure, Figure 2 The first MOSFET M1, the second MOSFET M2, and the third MOSFET M3 shown are all P-type MOSFETs.

[0054] In one embodiment of this disclosure, Figure 2 The substrate voltage generation module shown may further include a second resistor R2 and a third resistor R3. One end of the second resistor R2 is connected to the first input terminal L1 of the substrate voltage generation module, and the other end of the second resistor R2 is connected to the gate G of the third MOSFET M3. One end of the third resistor R3 is connected to the second input terminal L2 of the substrate voltage generation module, and the other end of the third resistor R3 is connected to the gate G of the second MOSFET M2.

[0055] It should be understood that the specific structure of the MOSFET module can be referred to the aforementioned description. Figure 1 The relevant description of the MOSFET module shown will not be repeated here.

[0056] like Figure 2In the circuit shown, the first MOSFET M1, the second MOSFET M2, and the third MOSFET M3 are all P-type MOSFETs. The substrate voltage generation module is used to output the first voltage v1 through the output terminal L3 in response to the voltage difference obtained by subtracting the second voltage v2 from the first voltage v1 being greater than or equal to the first preset threshold voltage; or, the substrate voltage generation module is used to output the second voltage v1 through the output terminal L3 in response to the voltage difference obtained by subtracting the first voltage v1 from the second voltage v2 being greater than or equal to the first preset threshold voltage.

[0057] In one embodiment of this disclosure, the first preset threshold voltage is the preset threshold voltage of the P-type MOSFET in the substrate voltage generation module.

[0058] In one embodiment of this disclosure, the preset threshold voltage of the P-type second MOSFET M2 is the same as the preset threshold voltage of the P-type third MOSFET M3.

[0059] In the above embodiments, by Figure 2 In the circuit structure shown, when the first MOSFET M1, the second MOSFET M2, and the third MOSFET M3 are all P-type MOSFETs, if the voltage difference obtained by subtracting the second voltage v2 from the first voltage v1 is greater than or equal to the preset threshold voltage of the P-type MOSFET in the substrate voltage generation module, the second MOSFET M2 will be turned on, and the third MOSFET M3 will be turned off. Then, the output terminal L3 of the substrate voltage generation module outputs the first voltage v1, which provides a high voltage, i.e., the first voltage v1, to the substrate B of the first MOSFET M1. If the first switch S1 is open at this time, the gate G of the first MOSFET M1 and the substrate B are equivalent to the first resistance R1. Therefore, the voltages of the gate G of the first MOSFET M1 and the substrate B are the same, both being the first voltage v1. This means that both the gate G of the first MOSFET M1 and the substrate B are at a high level, preventing channel leakage of the P-type first MOSFET M1.

[0060] Correspondingly, if the voltage difference between the second voltage v2 and the first voltage v1 is greater than or equal to the preset threshold voltage of the P-type MOSFET in the substrate voltage generation module, the third MOSFET M3 will turn on and the second MOSFET M2 will turn off. Then, the output terminal L3 of the substrate voltage generation module will output the second voltage v2, which provides a low voltage, i.e., the second voltage v2, to the substrate B of the first MOSFET M1. If the first switch S1 is open at this time, the gate G of the first MOSFET M1 and the substrate B are equivalent to the first resistance R1. Therefore, the voltages of the gate G of the first MOSFET M1 and the substrate B are the same, both being the second voltage v2. This means that the gate G of the first MOSFET M1 and the substrate B are still at a high level, thus preventing channel leakage of the P-type first MOSFET M1.

[0061] For example Figure 2 In the circuit shown, to ensure that the first P-type MOSFET M1 can conduct normally when the first switch S1 is closed, the following (x1) method can be used.

[0062] (x1) Adjust the current of current source I and / or the resistance of the first resistor R1 so that the voltage difference between the voltage of the gate G of the first MOSFET M1 and the voltage of the source S of the first MOSFET M1 is less than or equal to the preset threshold voltage of the first MOSFET M1.

[0063] Figure 3 Another schematic diagram of a circuit for preventing leakage current in a field-effect transistor according to an embodiment of the present disclosure is shown.

[0064] It should be understood that Figure 3 The circuit structure shown can be referred to in the previous section for details. Figure 2 The relevant description of the circuit structure will not be repeated here.

[0065] In one embodiment of this disclosure, Figure 3 The first MOSFET M1, the second MOSFET M2, and the third MOSFET M3 shown are all N-type MOSFETs.

[0066] like Figure 3 In the circuit shown, the first MOSFET M1, the second MOSFET M2, and the third MOSFET M3 are all N-type MOSFETs. The substrate voltage generation module is used to output the second voltage v2 through the output terminal L3 in response to the voltage difference obtained by subtracting the second voltage v2 from the first voltage v1 being greater than or equal to the second preset threshold voltage; or, the substrate voltage generation module is used to output the first voltage v1 through the output terminal L3 in response to the voltage difference obtained by subtracting the first voltage v1 from the second voltage v2 being greater than or equal to the second preset threshold voltage.

[0067] In one embodiment of this disclosure, the second preset threshold voltage is the preset threshold voltage of the N-type MOSFET in the substrate voltage generation module.

[0068] In one embodiment of this disclosure, the preset threshold voltage of the N-type second MOSFET M2 is the same as the preset threshold voltage of the N-type third MOSFET M3.

[0069] In the above embodiments, by Figure 3 In the circuit structure shown, when the first MOSFET M1, the second MOSFET M2, and the third MOSFET M3 are all N-type MOSFETs, if the voltage difference between the first voltage v1 and the second voltage v2 is greater than or equal to the preset threshold voltage of the N-type MOSFET in the substrate voltage generation module, the third MOSFET M3 will turn on, and the second MOSFET M2 will turn off. Then, the output terminal L3 of the substrate voltage generation module will output the second voltage v2, which provides a low voltage, i.e., the second voltage v2, to the substrate B of the first MOSFET M1. If the first switch S1 is open at this time, the gate G of the first MOSFET M1 and the substrate B are equivalent to the first resistance R1. Therefore, the voltages of the gate G of the first MOSFET M1 and the substrate B are the same, both being the second voltage v2. This means that both the gate G of the first MOSFET M1 and the substrate B are at a low level, preventing channel leakage of the N-type first MOSFET M1.

[0070] Correspondingly, if the voltage difference between the second voltage v2 and the first voltage v1 is greater than or equal to the preset threshold voltage of the N-type MOSFET in the substrate voltage generation module, the second MOSFET M2 will be turned on and the third MOSFET M3 will be turned off. Then, the output terminal L3 of the substrate voltage generation module will output the first voltage v1, which means providing a low voltage, i.e., the first voltage v1, to the substrate B of the first MOSFET M1. If the first switch S1 is turned on at this time, the gate G of the first MOSFET M1 and the substrate B are equivalent to the first resistance R1. Then, the voltage of the gate G of the first MOSFET M1 and the substrate B are the same, both being the first voltage v1. That is, the gate G of the first MOSFET M1 and the substrate B are still at a low level, thus avoiding channel leakage of the N-type first MOSFET M1.

[0071] For example Figure 3 In the circuit shown, to ensure that the first N-type MOSFET M1 can conduct normally when the first switch S1 is closed, the following (x2) method can be used.

[0072] (x2) Adjust the current of current source I and / or the resistance of the first resistor R1 so that the voltage difference between the voltage of the gate G of the first MOSFET M1 and the voltage of the source S of the first MOSFET M1 is greater than or equal to the preset threshold voltage of the first MOSFET M1.

[0073] In one embodiment of this disclosure, for Figures 1 to 3 In any of the circuit diagrams shown, the resistance of the first resistor R1 can be 250 kiloohms.

[0074] In one embodiment of this disclosure, for Figures 1 to 3 In any of the circuit diagrams shown, the current source I can have a current of 10 microamps.

[0075] In another aspect, this disclosure also provides a chip that includes Figures 1 to 3 The circuit shown is one that prevents leakage current from a field-effect transistor.

[0076] In another respect, this disclosure also provides an electronic device that includes the aforementioned chip.

[0077] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

Claims

1. A circuit for preventing leakage current in a field-effect transistor, characterized in that, The circuit includes: a metal-oxide-semiconductor field-effect transistor (MOSFET) module and a substrate voltage generation module, wherein the MOSFET module includes: a first resistor, a first switch, and a first MOSFET; Wherein, the first input terminal of the substrate voltage generation module is connected to the first voltage source, the second input terminal of the substrate voltage generation module is connected to the second voltage source, and the output terminal of the substrate voltage generation module is connected to the substrate of the first MOSFET; The source of the first MOSFET is connected to the first voltage source, the drain of the first MOSFET is connected to the second voltage source, the gate of the first MOSFET is connected to the first end of the first resistor, the first end of the first resistor is also connected to the first end of the first switch, the second end of the first switch is connected to one end of the current source, and the second end of the first resistor is connected to the substrate of the first MOSFET. The first MOSFET is a P-type MOSFET. The substrate voltage generation module is used to output the higher voltage of the first voltage and the second voltage through the output terminal of the substrate voltage generation module in response to the first voltage of the first voltage source and the second voltage of the second voltage source satisfying a first preset condition. Alternatively, the first MOSFET is an N-type MOSFET, and the substrate voltage generation module is used to output the lower voltage of the first voltage and the second voltage through the output terminal of the substrate voltage generation module in response to the first voltage of the first voltage source and the second voltage of the second voltage source satisfying a second preset condition.

2. The circuit according to claim 1, characterized in that, The substrate voltage generation module includes: a second MOSFET and a third MOSFET; Wherein, the drain of the second MOSFET is connected to the first input terminal of the substrate voltage generation module, the gate of the second MOSFET is connected to the second input terminal of the substrate voltage generation module, the substrate of the second MOSFET is connected to the substrate of the first MOSFET and the substrate of the third MOSFET respectively, and the source of the second MOSFET is connected to the substrate of the first MOSFET and the source of the third MOSFET respectively. The source of the third MOSFET is connected to the substrate of the first MOSFET, the substrate of the third MOSFET is connected to the substrate of the first MOSFET, the drain of the third MOSFET is connected to the second input terminal of the substrate voltage generation module, and the gate of the third MOSFET is connected to the first input terminal of the substrate voltage generation module.

3. The circuit according to claim 2, characterized in that, The substrate voltage generation module further includes: a second resistor and a third resistor; Wherein, one end of the second resistor is connected to the first input terminal of the substrate voltage generation module, and the other end of the second resistor is connected to the gate of the third MOSFET; One end of the third resistor is connected to the second input terminal of the substrate voltage generation module, and the other end of the third resistor is connected to the gate of the second MOSFET.

4. The circuit according to claim 2 or 3, characterized in that, The first MOSFET, the second MOSFET, and the third MOSFET are all P-type MOSFETs. The substrate voltage generation module is used to output the first voltage through the output terminal of the substrate voltage generation module in response to the voltage difference obtained by subtracting the second voltage from the first voltage being greater than or equal to a first preset threshold voltage.

5. The circuit according to claim 2 or 3, characterized in that, The first MOSFET, the second MOSFET, and the third MOSFET are all P-type MOSFETs. The substrate voltage generation module is used to output the second voltage through the output terminal of the substrate voltage generation module in response to the voltage difference obtained by subtracting the first voltage from the second voltage being greater than or equal to a first preset threshold voltage.

6. The circuit according to claim 2 or 3, characterized in that, The first MOSFET, the second MOSFET, and the third MOSFET are all N-type MOSFET transistors. The substrate voltage generation module is used to output the second voltage through the output terminal of the substrate voltage generation module in response to the voltage difference obtained by subtracting the second voltage from the first voltage being greater than or equal to the second preset threshold voltage.

7. The circuit according to claim 2 or 3, characterized in that, The first MOSFET, the second MOSFET, and the third MOSFET are all N-type MOSFETs. The substrate voltage generation module is used to output the first voltage through the output terminal of the substrate voltage generation module in response to the voltage difference obtained by subtracting the first voltage from the second voltage being greater than or equal to a second preset threshold voltage.

8. The circuit according to any one of claims 1 to 3, characterized in that, The resistance of the first resistor is 250 kiloohms.

9. The circuit according to any one of claims 1 to 3, characterized in that, The current source has a current of 10 microamps.

10. A chip, characterized in that, The circuit includes any one of claims 1 to 9.

11. An electronic device, characterized in that, Includes the chip as described in claim 10.

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