falling edge delay circuit, rising edge delay circuit, and memory

Abstract

This disclosure provides a falling edge delay circuit and a rising edge delay circuit. The falling edge delay circuit includes: a first inverter, a second inverter, a first capacitor, a second capacitor, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; the first PMOS transistor, the first NMOS transistor, and the second NMOS transistor are connected in series between a power supply and ground, and the first PMOS transistor, the first NMOS transistor, and the second NMOS transistor are electrically connected to the first inverter; the first capacitor is connected between the first inverter and the first NMOS transistor; the second PMOS transistor and the third NMOS transistor are connected in series between a power supply and ground, and the second PMOS transistor and the third NMOS transistor are electrically connected to the first NMOS transistor; the fourth NMOS transistor is connected to the input signal, and its drain is connected to the input terminal of the second inverter; the input terminal of the second inverter is electrically connected to the second PMOS transistor. This circuit can provide a substantially consistent delay time when the power supply voltage is different.

Description

Technical Field

[0001] This disclosure relates to the field of circuit technology, and more specifically, to a falling edge delay circuit, a rising edge delay circuit, and a memory. Background Technology

[0002] Delay circuits are widely used in the semiconductor industry. However, the delay circuits in related technologies use a combination of inverters and capacitors to achieve the delay function. When the power supply voltage changes, the delay time will change drastically with the change of power supply voltage, affecting the circuit performance.

[0003] The information disclosed in the background section is only intended to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] This disclosure provides a falling edge delay circuit, a rising edge delay circuit, and a memory, which can solve the problem of drastic changes in delay time with changes in power supply voltage, and can provide a basically consistent delay time when the power supply voltage is different.

[0005] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0006] This disclosure provides a falling edge delay circuit, comprising: a first inverter, a second inverter, a first capacitor, a second capacitor, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; the input terminal of the first inverter is connected to an input signal; the first PMOS transistor, the first NMOS transistor, and the second NMOS transistor are connected in series between a power supply terminal and ground, and the control terminals of the first PMOS transistor, the first NMOS transistor, and the second NMOS transistor are electrically connected to the output terminal of the first inverter; the first capacitor is electrically connected between the output terminal of the first inverter and the source terminal of the first NMOS transistor; the second PMOS transistor and the third NMOS transistor are connected in series between a power supply terminal and ground, and the control terminals of the second PMOS transistor and the third NMOS transistor are electrically connected to the drain terminal of the first NMOS transistor; the control terminal of the fourth NMOS transistor is connected to the input signal, its source terminal is connected to ground, and its drain terminal is connected to the input terminal of the second inverter; the input terminal of the second inverter is also electrically connected to the drain terminal of the second PMOS transistor.

[0007] In some exemplary embodiments of this disclosure, the falling edge delay circuit further includes a third PMOS transistor; the third PMOS transistor is connected between the drain terminal of the second PMOS transistor and the input terminal of the second inverter, and the control terminal of the third PMOS transistor is electrically connected to the input signal.

[0008] In some exemplary embodiments of this disclosure, when the power supply voltage at the power supply terminal is within a preset range, the change ratio of the delay time of the delay circuit is within a preset ratio.

[0009] In some exemplary embodiments of this disclosure, the aspect ratios of the first NMOS transistor, the second NMOS transistor, and the second PMOS transistor are all less than 1.

[0010] This disclosure provides a rising edge delay circuit, including: a PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, and a third NMOS transistor; the input terminal of a first inverter is connected to an input signal; the first PMOS transistor, the third PMOS transistor, and the first NMOS transistor are connected in series between a power supply terminal and ground, and the control terminals of the first PMOS transistor, the third PMOS transistor, and the first NMOS transistor are electrically connected to the output terminal of the first inverter; a first capacitor is electrically connected between the output terminal of the first inverter and the source terminal of the third PMOS transistor; the second PMOS transistor and the third NMOS transistor are connected in series between a power supply terminal and ground, and the control terminals of the second PMOS transistor and the third NMOS transistor are electrically connected to the drain terminal of the third PMOS transistor; the control terminal of the fourth PMOS transistor is connected to the input signal, its source terminal is connected to the power supply terminal, and its drain terminal is connected to the input terminal of the second inverter; the input terminal of the second inverter is also electrically connected to the drain terminal of the third NMOS transistor, and the output terminal of the second inverter serves as the output terminal of the rising edge delay circuit.

[0011] In some exemplary embodiments of this disclosure, the rising edge delay circuit further includes two NMOS transistors; the second NMOS transistor is connected between the drain terminal of the second PMOS transistor and the input terminal of the second inverter, and the control terminal of the second NMOS transistor is electrically connected to the input signal.

[0012] In some exemplary embodiments of this disclosure, when the power supply voltage at the power supply terminal is within a preset range, the change ratio of the delay time of the delay circuit is within a preset ratio.

[0013] In some exemplary embodiments of this disclosure, the aspect ratios of the second PMOS transistor, the third PMOS transistor, and the first NMOS transistor are all less than 1.

[0014] The falling edge delay circuit and rising edge delay circuit provided in the embodiments of this disclosure can solve the problem that the delay time changes drastically with the change of power supply voltage, and can provide a basically consistent delay time when the power supply voltage is different.

[0015] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this disclosure. Attached Figure Description

[0016] The above and other objects, features and advantages of this disclosure will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0017] Figure 1 This is a schematic diagram of a delay circuit in related technologies.

[0018] Figure 2 This is a circuit diagram of a falling edge delay circuit according to an exemplary embodiment.

[0019] Figure 3 This is a circuit diagram of a falling edge delay circuit according to another exemplary embodiment.

[0020] Figure 4 This is a circuit diagram illustrating a rising edge delay circuit according to an exemplary embodiment. Detailed Implementation

[0021] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0022] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known structures, methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0023] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0024] Figure 1 This is a schematic diagram of a delay circuit in related technologies. For example... Figure 1 As shown, the delay circuit in the related technology includes inverter A00, inverter A01, inverter C, NOR gate B, capacitor C00, and capacitor C01.

[0025] In related technologies, when the input signal IN changes from low to high, it is input to the NOR gate B, causing the output of NOR gate B to directly change from low to high. The delay unit composed of the inverter and capacitor has no effect. That is, when the input signal IN is a rising edge signal, the delay circuit in related technologies has no delay effect.

[0026] When the input signal IN changes from high to low, the PMOS transistor in inverter A00 charges capacitor C00, and the NMOS transistor in inverter A01 discharges capacitor C01, causing the voltage at the output of inverter A01 to gradually decrease. When the voltage at the output of inverter A01 is less than the flip threshold voltage of NOR gate B, the output of NOR gate B changes from high to low, thus achieving a delay when the input signal IN is a falling edge signal.

[0027] In related technologies, different delay times can be controlled by setting different combinations of inverters and capacitors. However, when the power supply voltage changes, the delay time will change drastically, seriously affecting the circuit performance.

[0028] To address the technical problems existing in the aforementioned related technologies, this disclosure provides a falling edge delay circuit and a rising edge delay circuit, which can provide a basically consistent delay time when the power supply voltage is different.

[0029] Figure 2This is a circuit diagram of a falling edge delay circuit according to an exemplary embodiment.

[0030] like Figure 2 As shown, the falling edge delay circuit provided in this embodiment may include: a first inverter A11, a second inverter A12, a first capacitor C10, a second capacitor C11, a PMOS transistor P11, an NMOS transistor N11, an NMOS transistor N12, a PMOS transistor P12, an NMOS transistor N13, and an NMOS transistor N14.

[0031] In this paper, PMOS transistor P11 is referred to as the first PMOS transistor, NMOS transistor N11 is referred to as the first NMOS transistor, NMOS transistor N12 is referred to as the second NMOS transistor, PMOS transistor P12 is referred to as the second PMOS transistor, NMOS transistor N13 is referred to as the third NMOS transistor, and NMOS transistor N14 is referred to as the fourth NMOS transistor.

[0032] The input terminal of the first inverter A11 is connected to the input signal IN. The input signal IN is, for example, a clock signal, with a high level of, for example, the power supply voltage VDD, and a low level of, for example, 0V. An NMOS transistor N11 is positioned between the first capacitor C10 and the second capacitor C11. PMOS transistors P11, NMOS transistors N11 and NMOS transistor N12 are connected in series between the power supply terminal and ground. The control terminals (gates) of PMOS transistors P11, NMOS transistors N11 and NMOS transistor N12 are all electrically connected to the output terminal of the first inverter A11. The first terminal (source) of PMOS transistor P11 is electrically connected to the power supply terminal, the second terminal (drain) of PMOS transistor P11 is electrically connected to the second terminal (drain) of NMOS transistor N11, the first terminal (source) of NMOS transistor N11 is electrically connected to the second terminal (drain) of NMOS transistor N12, and the first terminal (source) of NMOS transistor N12 is grounded.

[0033] PMOS transistor P11, NMOS transistor N11, and NMOS transistor N12 form a third inverter. The input terminal is the gate of the three transistors, and the output terminal is the drain terminal of PMOS transistor P11. The first terminal of the first capacitor C10 is electrically connected to the output terminal of the first inverter A11, and the second terminal of the first capacitor C10 is electrically connected to the source terminal of the NMOS switch N11.

[0034] PMOS transistor P12 and NMOS transistor N13 are connected in series between the power supply and ground. The control terminals (gates) of both PMOS transistor P12 and NMOS transistor N13 are electrically connected to the drain of PMOS transistor P11. The first terminal (source) of PMOS transistor P12 is electrically connected to the power supply. The second terminal (drain) of PMOS transistor P12 is electrically connected to the second terminal (drain) of NMOS transistor N13. The first terminal (source) of NMOS transistor N13 is grounded. PMOS transistor P12 and NMOS transistor N13 form a fourth inverter, with the third and fourth inverters connected in series.

[0035] The second capacitor C11 is positioned between the input and output of the fourth inverter. Specifically, the first terminal of the second capacitor C11 is electrically connected to the drain of PMOS transistor P11, and the second terminal of the second capacitor C11 is electrically connected to the drain of PMOS transistor P12. The control terminal (gate) of NMOS transistor N14 is connected to the input signal IN. The second terminal (drain) of NMOS transistor N14 and the drain of NMOS transistor N13 are both connected to the input of the second inverter A12. The first terminal (source) of NMOS transistor N14 is grounded. The output of the second inverter A12 serves as the output of the falling edge delay circuit.

[0036] The first inverter A11 and the second inverter A12 are, for example, inverters consisting of one PMOS transistor and one NMOS transistor. To achieve a falling edge delay, the aspect ratio of the PMOS transistor in the first inverter A11 can be set relatively small (e.g., smaller than the aspect ratio of the corresponding NMOS transistor), resulting in a weaker PMOS current capability in the first inverter A11; similarly, the aspect ratio of the NMOS transistor in the second inverter A12 can be set relatively small (e.g., smaller than the aspect ratio of the corresponding PMOS transistor), resulting in a weaker NMOS current capability. The aspect ratios can also be adjusted according to the required falling edge delay time in actual situations, and this disclosure does not impose any limitations on this.

[0037] During the low-level period of the input signal IN (before the rising edge of the input signal IN), the voltage v1 at the output terminal of the first inverter A11 is high (i.e., VDD), PMOS transistor P11 is off, and NMOS transistors N11 and N12 are on. The voltage v1 at the first terminal of the first capacitor C10 is VDD, and the voltage v2 at the second terminal is 0. The voltage v3 at the first terminal of the second capacitor C11 is 0, PMOS transistor P12 is on, NMOS transistor N13 is off, and the voltage v4 at the second terminal is VDD.

[0038] When the input signal IN changes from low to high (the rising edge of the input signal IN), the NMOS transistor N14 turns on, the voltage v4 at the input terminal of the second inverter A12 becomes low, and therefore the voltage at the output terminal of the second inverter A12 changes from low to high. Figure 2 The circuit shown has no delay on the rising edge of the input signal. At the rising edge of the input signal IN, the voltage v1 at the first terminal of the first capacitor C10 changes from high to low, and the voltage v2 at the second terminal of the first capacitor C10 (i.e., the drain voltage of NMOS transistor N12) is coupled from 0V to -VDD. PMOS transistor P11 turns on, and the first terminal of the second capacitor C11 begins to charge, with the drain voltage v3 of PMOS transistor P11 gradually rising to VDD. The gate voltages of NMOS transistors N11 and N12 are both 0, and the source voltage of NMOS transistor N11 and the drain voltage of NMOS transistor N12 are both -VDD. NMOS transistors N11 and N12 turn on, and the voltage v2 at the second terminal of the first capacitor C10 gradually charges from -VDD to -Va. Then, NMOS transistors N11 and N12 turn off, and Va is approximately equal to the threshold voltages of NMOS transistors N11 and N12. The voltage v4 at the second terminal of the second capacitor C11 discharges to 0 through NMOS transistor N13.

[0039] During the high-level period of the input signal IN (before the falling edge of the input signal IN), the voltage v1 at the first terminal of the first capacitor C10 is 0, and the voltage v2 at the second terminal is -Va. The voltage v3 at the first terminal of the second capacitor C11 is VDD, and the voltage v4 at the second terminal is 0.

[0040] When the input signal IN changes from high to low (falling edge of the input signal IN), the voltage v1 at the output of the first inverter A11 changes from low to high, the PMOS transistor P11 is turned off, and the voltage v2 at the second terminal of the first capacitor C10 is coupled to VDD-Va. At this time, the gate voltage of the NMOS transistor N11 is high VDD, the drain voltage v3 of the NMOS transistor N11 is VDD, and the source voltage v2 of the NMOS transistor N11 = VDD-Va. Therefore, the current of the NMOS transistor N11 is small and cannot immediately discharge the voltage v2 at the second terminal of the first capacitor C10 and the voltage v3 at the first terminal of the second capacitor C11 to 0.

[0041] For a certain period after the falling edge of the input signal IN, because the voltage v3 at the first terminal of the second capacitor C11 cannot immediately discharge to 0, the NMOS transistor N13 is turned on and the PMOS transistor P12 is turned off for a certain period after the falling edge, and the voltage v4 at the second terminal of the second capacitor C11 remains 0V. When the voltage v3 at the first terminal of the second capacitor C11 drops to VDD-Vt12, the PMOS transistor P12 starts to turn on, the second terminal of the second capacitor C11 begins to charge, and the voltage v4 at the second terminal of the second capacitor C11 gradually increases. Vt12 is the threshold voltage of the PMOS transistor P12. When the voltage v4 at the second terminal of the second capacitor C11 rises to the threshold voltage of the NMOS transistor in the second inverter A12, the second inverter A12 starts to output a low level. Therefore, the falling edge delay is equal to the delay of the first inverter A11, the delay of the second inverter A12, the time required for the voltage v3 at the first terminal of the second capacitor C11 to drop to VDD-Vt12, plus the time required for the voltage v4 at the second terminal of the second capacitor C11 to rise to the threshold voltage of the NMOS transistor in the second inverter A12. The discharge path of the voltage v3 at the first terminal of the second capacitor C11 is through NMOS transistors N11 and N12 to ground, and the charging path of the voltage v4 at the second terminal of the second capacitor C11 is from the power supply terminal through PMOS transistor P12 to the second terminal of the second capacitor C11.

[0042] When the power supply voltage VDD is high, the voltage v3 at the first terminal of the second capacitor C11 takes longer to drop to VDD-Vt12, and the voltage v4 at the second terminal of the second capacitor C11 takes shorter to rise to the threshold voltage of the NMOS transistor in the second inverter A12. The two compensate for each other and cancel each other out, which can ensure that the falling edge delay time remains basically unchanged.

[0043] When the power supply voltage VDD is low, the time required for the voltage v3 at the first terminal of the second capacitor C11 to drop to VDD-Vt12 is shorter, and the time required for the voltage v4 at the second terminal of the second capacitor C11 to rise to the threshold voltage of the NMOS transistor in the second inverter A12 is longer. The two compensate for each other and cancel each other out, which can ensure that the falling edge delay time remains basically unchanged.

[0044] In an exemplary embodiment, keeping the falling edge delay substantially constant means that when the power supply voltage at the power supply terminal is within a preset range, the change in the delay time of the falling edge delay circuit is within a preset proportion. In this embodiment of the present disclosure, when the power supply voltage is within a wide range of 2.3V to 4V, the change in delay time can be controlled within 10%.

[0045] In an exemplary embodiment, the aspect ratios of NMOS transistors N11, NMOS transistor N12, and PMOS transistor P12 can all be less than 1. The aspect ratios of NMOS transistors N11 and NMOS transistor N12 are less than 1, thereby enabling slow discharge of the second terminal of the first capacitor C10 and the first terminal of the second capacitor C11; the aspect ratio of PMOS transistor P12 is less than 1, thereby enabling slow charging of the second terminal of the second capacitor C11.

[0046] The falling edge delay circuit provided in this embodiment can solve the problem of drastic changes in delay time with changes in power supply voltage, and achieve a basically constant delay time under different power supply voltages, that is, the delay time does not change with changes in power supply voltage.

[0047] Figure 3 This is a circuit diagram illustrating a falling edge delay circuit according to another exemplary embodiment. Compared to Figure 2 Compared to the falling edge delay circuit shown, Figure 3 The falling edge delay circuit shown also includes a PMOS transistor P13 connected in series with PMOS transistor P12 and NMOS transistor N13. The drain of PMOS transistor P13 is connected to the source of NMOS transistor N13, the source of PMOS transistor P13 is connected to the drain of PMOS transistor P12, and the gate of PMOS transistor P13 is connected to the input signal IN. In this paper, PMOS transistor P13 is referred to as the third PMOS transistor.

[0048] When the input signal IN rises, PMOS transistor P13 is turned off, the second terminal of the second capacitor C11 is disconnected, and the input terminal of the second inverter A12 is disconnected; NMOS transistor N14 is turned on, and the voltage v5 at the input terminal of the second inverter A12 is pulled low to a low level by NMOS transistor N14, and the output terminal of the second inverter A12 outputs a high level.

[0049] At the falling edge of the input signal IN, the discharge process of voltage v2 at the second terminal of the first capacitor C10 and voltage v3 at the first terminal of the second capacitor C11 and Figure 2 The falling edge delay circuit shown is the same. When the voltage v3 at the first terminal of the second capacitor C11 drops to a level that enables the PMOS transistor P12 to turn on, the power supply begins to charge the second terminal of the second capacitor C11 through the PMOS transistor P12. The PMOS transistor P13 turns on, and the voltage v5 at the input terminal of the second inverter A12 is equal to the voltage v4 at the second terminal of the second capacitor C11.

[0050] By setting PMOS transistor P13 to disconnect the second terminal of the second capacitor C11 and the input terminal of the second inverter A12 at the rising edge of the input signal IN, the influence on the rising edge of the output signal can be reduced.

[0051] Figure 4 This is a circuit diagram illustrating a rising edge delay circuit according to an exemplary embodiment. Figure 4 As shown, the rising edge delay circuit provided in this embodiment may include: a first inverter A21, a second inverter A22, a first capacitor C20, a second capacitor C21, a PMOS transistor P21, a PMOS transistor P22, a PMOS transistor P23, an NMOS transistor N11, an NMOS transistor N22, an NMOS transistor N23, and a PMOS transistor P24.

[0052] In this paper, PMOS transistor P21 is referred to as the first PMOS transistor, PMOS transistor P22 as the second PMOS transistor, PMOS transistor P23 as the third PMOS transistor, NMOS transistor N11 as the first NMOS transistor, NMOS transistor N22 as the second NMOS transistor, NMOS transistor N23 as the third NMOS transistor, and PMOS transistor P24 as the fourth PMOS transistor.

[0053] The input terminal of the first inverter A21 is connected to the input signal IN. The input signal IN is, for example, a clock signal, where the high level is, for example, the power supply voltage VDD, and the low level is, for example, 0V. PMOS transistors P21, PMOS transistor P23, and NMOS transistor N21 are connected in series between the power supply terminal and ground, forming the third inverter. The gates of PMOS transistors P21, PMOS transistor P23, and NMOS transistor N21 are all electrically connected to the output terminal of the first inverter A21. The source terminal of PMOS transistor P21 is connected to the power supply terminal, the drain terminal of PMOS transistor P21 is connected to the source terminal of PMOS transistor P23, the drain terminal of PMOS transistor P23 is connected to the drain terminal of NMOS transistor N21, the source terminal of NMOS transistor N21 is grounded, and the drain terminal of PMOS transistor P23 serves as the output terminal of the third inverter. The first terminal of the first capacitor C20 is electrically connected to the output terminal of the first inverter A21, and the second terminal of the first capacitor C20 is electrically connected to the drain terminal of PMOS transistor P23.

[0054] PMOS transistor P22, NMOS transistors N22 and NMOS transistor N23 are connected in series between the power supply and ground. The gates of PMOS transistor P22 and NMOS transistor N23 are both electrically connected to the drain of PMOS transistor P23. The gate of NMOS transistor N22 receives the input signal IN. The source of PMOS transistor P22 is connected to the power supply, the drain of PMOS transistor P22 is connected to the drain of NMOS transistor N22, the source of NMOS transistor N22 is connected to the drain of NMOS transistor N23, and the source of NMOS transistor N23 is grounded. The first terminal of the second capacitor C21 is connected to the drain of NMOS transistor N21, and the second terminal of the second capacitor C21 is connected to the drain of PMOS transistor P22. The source of PMOS transistor P24 is connected to the power supply, its gate receives the input signal IN, and its drain is connected to the input of the second inverter A22. The input of the second inverter A22 is also connected to the drain of NMOS transistor N23.

[0055] In some embodiments, NMOS transistor N22 may be omitted, and the drain of PMOS transistor P22 may be directly connected to the drain of NMOS transistor N23, that is, the second terminal of the second capacitor C21 may be directly connected to the input terminal of the second inverter A22.

[0056] The width-to-length ratio of the NMOS in the first inverter A21 can be set to be relatively small, resulting in a weaker current capability of the NMOS in the first inverter A21; the width-to-length ratio of the PMOS in the second inverter A22 can also be set to be relatively small, resulting in a weaker current capability of the PMOS in the second inverter A22. The width-to-length ratio can also be adjusted according to the required rise time in actual situation, and this disclosure does not impose any restrictions on this.

[0057] During the high-level period of the input signal IN (before the falling edge of the input signal IN), the voltage v1 at the output of the first inverter A21 is low, PMOS transistors P21 and P23 are turned on, NMOS transistor N21 is turned off, the voltage v1 at the first terminal of the first capacitor C20 is 0V, and the voltage v2 at the second terminal is VDD. The drain voltage v3 of PMOS transistor P23 is VDD, PMOS transistor P22 is turned off, NMOS transistors N22 and N23 are turned on, the voltage v3 at the first terminal of the second capacitor C21 is VDD, and the voltage v4 at the second terminal is 0. The voltage v5 at the input of the second inverter A22 is also 0.

[0058] When the input signal IN changes from high to low (falling edge of the input signal IN), PMOS transistor P24 turns on, the voltage v5 at the input terminal of the second inverter A22 becomes high, and therefore the voltage at the output terminal of the second inverter A22 changes from high to low. Figure 4The circuit shown has no delay on the falling edge of the input signal. The voltage v1 at the first terminal of the first capacitor C20 (i.e., the output of the first inverter A21) changes from low to high, and the voltage v2 at the second terminal of the first capacitor C20 (i.e., the drain voltage of PMOS transistor P21) is coupled to 2VDD. Then, the second terminal of the first capacitor C20 discharges through PMOS transistors P21 and P23. When the voltage v2 at the second terminal of the first capacitor C20 drops to VDD + Vb, PMOS transistors P21 and P23 disconnect, and Vb is approximately equal to the threshold voltages of PMOS transistors P21 and P23. The voltage v3 at the first terminal of the second capacitor C21 is 0, and the voltage v4 at the second terminal is VDD.

[0059] During the low-level period of the input signal IN (before the rising edge of the input signal IN), the voltage v1 at the first terminal of the first capacitor C20 is VDD, and the voltage v2 at the second terminal is VDD+Vb. The voltage v3 at the first terminal of the second capacitor C21 is 0, and the voltage v4 at the second terminal is VDD.

[0060] When the input signal IN changes from low to high (rising edge of the input signal IN), the voltage v1 at the output of the first inverter A21 changes from high to low. The voltage v2 at the second terminal of the first capacitor C20 is first coupled to Vb, and then the second terminal of the first capacitor C20 is charged to VDD through the conducting PMOS transistor P21. The higher the power supply voltage VDD, the faster the charging speed of the second terminal of the first capacitor C20. The voltage v3 at the first terminal of the second capacitor C21 also rises from 0 to VDD through the conducting PMOS transistor P23. When the voltage v3 at the first terminal of the second capacitor C21 rises to the threshold voltage of the NMOS transistor N23, the second terminal of the second capacitor C21 begins to discharge. When the voltage v4 at the second terminal of the second capacitor C21 discharges to the voltage that turns on the PMOS transistor in the second inverter A22, the second inverter A22 begins to output a high level. The higher the power supply voltage VDD, the shorter the process of the second terminal of the second capacitor C21 discharging from VDD to VDD-Vt.

[0061] Therefore, the rising edge delay is equal to the delay of the first inverter A21, the delay of the second inverter A22, the time it takes for the first terminal of the second capacitor C21 to charge to the threshold voltage of the NMOS transistor N23, and the time it takes for the second terminal of the second capacitor C21 to discharge to the voltage that turns on the PMOS transistor in the second inverter A22. The charging path of the first terminal of the second capacitor C21 is through PMOS transistors P21 and P23, and the discharging path of the second terminal of the second capacitor C21 is through the NMOS transistor N23.

[0062] When the power supply voltage VDD is high, the charging process of the first end of the second capacitor C21 is shorter, and the discharging process of the second end of the second capacitor C21 is longer. The two compensate for each other and cancel each other out, which can ensure that the rise time delay remains basically unchanged.

[0063] When the power supply voltage VDD is low, the charging process of the first end of the second capacitor C21 is longer, and the discharging process of the second end of the second capacitor C21 is shorter. The two compensate for each other and cancel each other out, which can ensure that the rise time delay remains basically unchanged.

[0064] Therefore, the delay circuit provided in this embodiment can achieve a substantially constant delay time under different power supply voltages, that is, the delay time does not change with the change of power supply voltage. In an exemplary embodiment, when the power supply voltage at the power supply terminal is within a preset range, the change ratio of the delay time of the delay circuit is within a preset proportion. In this embodiment, when the power supply voltage is within a wide range of 2.3V to 4V, the change in delay time can be controlled within 10%.

[0065] In an exemplary embodiment, the aspect ratios of PMOS transistors P21 and P23 and NMOS transistor N23 can both be less than 1. The aspect ratio of PMOS transistors P21 and P23 is less than 1, thereby enabling slow charging of the first terminal of the second capacitor C21; the aspect ratio of NMOS transistor N23 is less than 1, thereby enabling slow discharging of the second segment of the second capacitor C21.

[0066] The rising edge delay circuit provided in this embodiment can solve the problem of drastic changes in delay time with changes in power supply voltage, and achieve a basically constant delay time under different power supply voltages, that is, the delay time does not change with changes in power supply voltage.

[0067] This disclosure also provides a memory. Memory includes, for example, volatile and non-volatile memory. Volatile memory requires power to maintain data, and includes, for example, random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM). Non-volatile memory can maintain stored data even when power is off, and includes, for example, NAND flash memory, NOR flash memory, electrically erasable programmable ROM (EEPROM), phase-change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM). The memory includes a memory cell array and peripheral circuitry. Peripheral circuitry includes, for example, control logic, read / write circuitry, decoders, and operating voltage generation circuitry. The peripheral circuitry controls various operations of the memory cell array, such as read operations, write operations, and erase operations. The falling edge delay circuit and rising edge delay circuit provided in this disclosure can be applied in the peripheral circuitry of the memory to solve the problem of insufficient margin during read, write, and erase operations caused by drastic changes in delay time due to power supply voltage variations, thereby improving chip performance.

[0068] Exemplary embodiments of this disclosure have been specifically illustrated and described above. It should be understood that this disclosure is not limited to the detailed structures, arrangements, or implementation methods described herein; rather, this disclosure is intended to cover various modifications and equivalent arrangements contained within the spirit and scope of the appended claims.

Claims

1. A falling edge delay circuit, characterized in that, include: First inverter, second inverter, first capacitor, second capacitor, first PMOS transistor, second PMOS transistor, first NMOS transistor, second NMOS transistor, third NMOS transistor, and fourth NMOS transistor; The input terminal of the first inverter is connected to an input signal; The first PMOS transistor, the first NMOS transistor, and the second NMOS transistor are connected in series between the power supply terminal and ground, and the control terminals of the first PMOS transistor, the first NMOS transistor, and the second NMOS transistor are electrically connected to the output terminal of the first inverter. The first capacitor is electrically connected between the output terminal of the first inverter and the source terminal of the first NMOS transistor; The first terminal of the second capacitor is electrically connected to the drain terminal of the first PMOS transistor, and the second terminal of the second capacitor is electrically connected to the drain terminal of the second PMOS transistor. The second PMOS transistor and the third NMOS transistor are connected in series between the power supply terminal and ground, and the control terminals of the second PMOS transistor and the third NMOS transistor are electrically connected to the drain terminal of the first NMOS transistor. The control terminal of the fourth NMOS transistor is connected to the input signal, the source terminal is connected to ground, and the drain terminal is connected to the input terminal of the second inverter. The input terminal of the second inverter is also electrically connected to the drain terminal of the second PMOS transistor, and the output terminal of the second inverter serves as the output terminal of the falling edge delay circuit.

2. The falling edge delay circuit according to claim 1, characterized in that, It also includes a third PMOS transistor; The third PMOS transistor is connected between the drain terminal of the second PMOS transistor and the input terminal of the second inverter, and the control terminal of the third PMOS transistor is electrically connected to the input signal.

3. The falling edge delay circuit according to claim 1 or 2, characterized in that, When the power supply voltage at the power supply terminal is within a preset range, the change ratio of the delay time of the delay circuit is within a preset ratio.

4. The falling edge delay circuit according to claim 1 or 2, characterized in that, The aspect ratios of the first NMOS transistor, the second NMOS transistor, and the second PMOS transistor are all less than 1.

5. A rising edge delay circuit, characterized in that, include: First inverter, second inverter, first capacitor, second capacitor, first PMOS transistor, second PMOS transistor, third PMOS transistor, fourth PMOS transistor, first NMOS transistor and third NMOS transistor; The input terminal of the first inverter is connected to an input signal; The first PMOS transistor, the third PMOS transistor, and the first NMOS transistor are connected in series between the power supply terminal and ground, and the control terminals of the first PMOS transistor, the third PMOS transistor, and the first NMOS transistor are electrically connected to the output terminal of the first inverter. The first capacitor is electrically connected between the output terminal of the first inverter and the source terminal of the third PMOS transistor; The first terminal of the second capacitor is electrically connected to the drain terminal of the first NMOS transistor; The second terminal of the second capacitor is electrically connected to the drain terminal of the second PMOS transistor, or the second terminal of the second capacitor is electrically connected to the input terminal of the second inverter; The second PMOS transistor and the third NMOS transistor are connected in series between the power supply terminal and ground, and the control terminals of the second PMOS transistor and the third NMOS transistor are electrically connected to the drain terminal of the third PMOS transistor. The control terminal of the fourth PMOS transistor is connected to the input signal, the source terminal is connected to the power supply terminal, and the drain terminal is connected to the input terminal of the second inverter. The input terminal of the second inverter is also electrically connected to the drain terminal of the third NMOS transistor, and the output terminal of the second inverter serves as the output terminal of the rising edge delay circuit.

6. The rising edge delay circuit according to claim 5, characterized in that, It also includes a second NMOS transistor; The second NMOS transistor is connected between the drain terminal of the second PMOS transistor and the input terminal of the second inverter, and the control terminal of the second NMOS transistor is electrically connected to the input signal.

7. The rising edge delay circuit according to claim 5 or 6, characterized in that, When the power supply voltage at the power supply terminal is within a preset range, the change ratio of the delay time of the delay circuit is within a preset ratio.

8. The rising edge delay circuit according to claim 5 or 6, characterized in that, The aspect ratios of the second PMOS transistor, the third PMOS transistor, and the first NMOS transistor are all less than 1.

9. A memory, characterized in that, Includes the falling edge delay circuit as described in any one of claims 1-4.

10. A memory, characterized in that, Includes the rising edge delay circuit as described in any one of claims 5-8.

Images