Semiconductor structure and its fabrication method
By forming a complex lower electrode structure in a semiconductor structure and increasing the surface area of the lower electrode using atomic layer deposition, the problem of limited charge storage capacity of capacitor structures is solved, and better charge storage performance is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2021-07-05
- Publication Date
- 2026-07-17
Smart Images
Figure CN115589719B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for fabricating the same. Background Technology
[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device. DRAM consists of several repeating memory cells, each of which includes a capacitor structure configured to store charge. The capacitor structure affects the storage capacity of DRAM.
[0003] With the development of semiconductor technology, there is a growing demand for DRAM to store charge. However, improving the charge storage capacity of DRAM is limited by the size of the capacitor structure. How to improve the charge storage capacity of the capacitor structure by utilizing the remaining space of the capacitor structure without increasing its size is one of the technical challenges in this field. Summary of the Invention
[0004] To address the aforementioned technical problems, this disclosure provides a semiconductor structure and a method for fabricating the same.
[0005] A first aspect of this disclosure provides a method for fabricating a semiconductor structure, the method comprising:
[0006] An initial structure is provided, the initial structure including a capacitor contact region and a target layer located on the capacitor contact region;
[0007] A first lower electrode structure is formed within the target layer, and the first lower electrode structure is connected to at least a portion of the capacitor contact area.
[0008] A second lower electrode structure is formed within the target layer and connected to the first lower electrode structure.
[0009] The formation of the first lower electrode structure within the target layer includes:
[0010] A first trench is formed within the target layer, the first trench exposing the capacitor contact area;
[0011] A first lower electrode structure connected to the capacitor contact area is formed on the sidewall and bottom surface of the trench.
[0012] Wherein, the formation of a second lower electrode structure connected to the first lower electrode structure within the target layer includes:
[0013] A first sacrificial layer is formed on the sidewall of the first lower electrode structure, and a second trench is formed in the first trench, the second trench exposing a portion of the bottom surface of the first lower electrode structure;
[0014] A second lower electrode structure is formed in the second trench to fill the second trench.
[0015] The target layer includes a first dielectric layer, and after forming the second lower electrode structure, it further includes: simultaneously removing the first dielectric layer and the first sacrificial layer.
[0016] The formation of the first lower electrode structure within the target layer includes:
[0017] A third trench is formed within the target layer, the third trench exposing a portion of the capacitor contact area;
[0018] The first lower electrode structure is formed by filling the third trench.
[0019] Wherein, the formation of a second lower electrode structure connected to the first lower electrode structure within the target layer includes:
[0020] A fourth trench is defined in the target layer, the fourth trench exposing the capacitive contact area that was not exposed by the third trench;
[0021] A second lower electrode structure, which is connected to the first lower electrode structure, is formed on the sidewall and bottom surface of the fourth trench.
[0022] The step of defining a fourth trench in the target layer, wherein the fourth trench exposes the capacitive contact area not exposed by the third trench, includes:
[0023] A mask layer is formed, the mask layer covering the first lower electrode structure and a portion of the target layer, and the mask layer forms an opening around the first lower electrode structure on the surface of the target layer;
[0024] Remove the target layer corresponding to the opening to expose the capacitor contact area that was not exposed by the third trench, thus forming the fourth trench.
[0025] The target layer includes a second dielectric layer, and after forming the second lower electrode structure, the second dielectric layer is removed.
[0026] In some possible embodiments, after forming the second lower electrode structure, the method further includes:
[0027] Simultaneously, dielectric structures and upper electrode structures are sequentially formed on the surfaces of the first lower electrode structure and the second lower electrode structure.
[0028] A second aspect of this disclosure provides a semiconductor structure, comprising:
[0029] Substrate;
[0030] The capacitor contact area is located within the substrate;
[0031] The first lower electrode structure is located on the substrate and is connected to at least a portion of the capacitor contact area;
[0032] The second lower electrode structure is connected to the first lower electrode structure.
[0033] The first lower electrode structure is disposed on the capacitor contact area and is in contact with the capacitor contact area;
[0034] The second lower electrode structure is disposed on the first lower electrode structure and is connected to the first lower electrode structure.
[0035] The first lower electrode structure forms a capacitor hole;
[0036] The second lower electrode structure is disposed in the capacitor hole, and the bottom wall of the second lower electrode structure is connected to a portion of the bottom wall of the capacitor hole.
[0037] The first lower electrode structure is disposed on the capacitor contact area and contacts a portion of the capacitor contact area;
[0038] The second lower electrode structure is disposed on the substrate surrounding the first lower electrode structure, and the second lower electrode structure is in contact with another portion of the capacitor contact area.
[0039] Wherein, the first lower electrode structure is a columnar structure, and the bottom wall of the columnar structure is in contact with part of the capacitor contact area;
[0040] The second lower electrode structure includes an annular portion and a cylindrical portion surrounding the first lower electrode structure. The inner ring of the annular portion is connected to the bottom wall of the first lower electrode structure, and the cylindrical portion of the outer ring of the annular portion is connected to it.
[0041] In some possible embodiments, the semiconductor structure further includes:
[0042] A dielectric structure covering the surfaces of the first lower electrode structure and the second lower electrode structure;
[0043] An upper electrode structure that covers the surface of the dielectric structure.
[0044] The method for fabricating a semiconductor structure disclosed herein forms a first lower electrode structure and a second lower electrode structure within a target layer, thereby increasing the outer surface area of the lower electrode and increasing the charge storage capacity of the semiconductor structure. Attached Figure Description
[0045] The accompanying drawings, which form part of this disclosure, are used to provide a further understanding of this disclosure. The illustrative embodiments of this disclosure and their descriptions are used to explain this disclosure and do not constitute an undue limitation of this disclosure. In the drawings:
[0046] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure in an exemplary embodiment of this disclosure;
[0047] Figure 2 This is a flowchart of a method for fabricating a semiconductor structure in an exemplary embodiment of this disclosure;
[0048] Figure 3 This is a flowchart of a method for fabricating a semiconductor structure in an exemplary embodiment of this disclosure;
[0049] Figure 4 This is a flowchart of a method for fabricating a semiconductor structure in an exemplary embodiment of this disclosure;
[0050] Figure 5 This is a flowchart of a method for fabricating a semiconductor structure in an exemplary embodiment of this disclosure;
[0051] Figure 6 This is a flowchart of a method for fabricating a semiconductor structure in an exemplary embodiment of this disclosure;
[0052] Figure 7 This is a flowchart of a method for fabricating a semiconductor structure in an exemplary embodiment of this disclosure;
[0053] Figure 8 This is a flowchart of a method for fabricating a semiconductor structure in an exemplary embodiment of this disclosure;
[0054] Figure 9 This is a flowchart of a method for fabricating a semiconductor structure in an exemplary embodiment of this disclosure;
[0055] Figure 10 This is a schematic diagram of the initial structure involved in the method for fabricating a semiconductor structure in an exemplary embodiment of this disclosure;
[0056] Figure 11 This is a schematic diagram of forming a first trench in a target layer in the method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure;
[0057] Figure 12 This is a schematic diagram of the formation of the first lower electrode structure involved in the method of fabricating the semiconductor structure in an exemplary embodiment of this disclosure;
[0058] Figure 13 This is a schematic diagram of the formation of a first sacrificial layer involved in the method of fabricating a semiconductor structure in an exemplary embodiment of this disclosure;
[0059] Figure 14This is a schematic diagram of the formation of a second trench involved in the method of fabricating a semiconductor structure in an exemplary embodiment of this disclosure;
[0060] Figure 15 This is a schematic diagram of the deposition of a second lower electrode structure involved in the method for fabricating a semiconductor structure in an exemplary embodiment of this disclosure;
[0061] Figure 16 This is a process diagram of forming a second lower electrode structure involved in the method of fabricating a semiconductor structure in an exemplary embodiment of this disclosure;
[0062] Figure 17 This is a schematic diagram of the removal of the first sacrificial layer involved in the method of fabricating a semiconductor structure in an exemplary embodiment of this disclosure;
[0063] Figure 18 This is a schematic diagram of the formation of a photoresist mask involved in the method of fabricating a semiconductor structure in an exemplary embodiment of this disclosure;
[0064] Figure 19 This is a schematic diagram of the removal of a portion of the support layer c involved in the method of fabricating a semiconductor structure in an exemplary embodiment of this disclosure;
[0065] Figure 20 This is a schematic diagram of the removal of dielectric layer b involved in the method of fabricating a semiconductor structure in an exemplary embodiment of this disclosure;
[0066] Figure 21 This is a schematic diagram of the removal of a portion of the support layer b involved in the method of fabricating a semiconductor structure in an exemplary embodiment of this disclosure;
[0067] Figure 22 This is a schematic diagram of the removal of dielectric layer a involved in the method of fabricating a semiconductor structure in an exemplary embodiment of this disclosure;
[0068] Figure 23 This is a schematic diagram of the formation of a dielectric structure involved in the method of fabricating a semiconductor structure in an exemplary embodiment of this disclosure;
[0069] Figure 24 This is a schematic diagram of the formation of the upper electrode structure involved in the method of fabricating the semiconductor structure in an exemplary embodiment of this disclosure;
[0070] Figure 25 This is a schematic diagram of the formation of an upper electrode filling structure involved in the method of fabricating a semiconductor structure in an exemplary embodiment of this disclosure;
[0071] Figure 26 This is a schematic diagram of the initial structure involved in the method for fabricating a semiconductor structure in an exemplary embodiment of this disclosure;
[0072] Figure 27This is a schematic diagram of forming a third trench in a target layer in a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure;
[0073] Figure 28 This is a schematic diagram of the deposition of a first lower electrode structure involved in the method of fabricating a semiconductor structure in an exemplary embodiment of this disclosure;
[0074] Figure 29 This is a schematic diagram of the formation of the first lower electrode structure involved in the method of fabricating the semiconductor structure in an exemplary embodiment of this disclosure;
[0075] Figure 30 This is a schematic diagram of the formation of a third mask layer involved in the method of fabricating a semiconductor structure in an exemplary embodiment of this disclosure;
[0076] Figure 31 This is a schematic diagram of the formation of a fourth trench involved in the method of fabricating a semiconductor structure in an exemplary embodiment of this disclosure;
[0077] Figure 32 This is a schematic diagram of the formation of a second lower electrode structure involved in the method of fabricating a semiconductor structure in an exemplary embodiment of this disclosure;
[0078] Figure 33 This is a schematic diagram of the removal of the second dielectric layer involved in the method of fabricating a semiconductor structure in an exemplary embodiment of this disclosure;
[0079] Figure 34 This is a schematic diagram of the formation of a dielectric structure involved in the method of fabricating a semiconductor structure in an exemplary embodiment of this disclosure;
[0080] Figure 35 This is a schematic diagram of the formation of the upper electrode structure involved in the method of fabricating the semiconductor structure in an exemplary embodiment of this disclosure;
[0081] Figure 36 This is a schematic diagram of the formation of an upper electrode filling structure involved in the method of fabricating a semiconductor structure in an exemplary embodiment of this disclosure;
[0082] Figure 37 This is a schematic diagram of the trench formation involved in the method of fabricating the semiconductor structure in the exemplary comparative example of this disclosure;
[0083] Figure 38 This is a schematic diagram of the method for fabricating a semiconductor structure in the exemplary comparative example of this disclosure, involving the formation of a capacitor hole;
[0084] Figure 39 This is a schematic diagram of the formation of the lower electrode structure involved in the method of fabricating the semiconductor structure in the exemplary comparative example of this disclosure;
[0085] Figure 40This is a schematic diagram of the formation of dielectric structures involved in the method of fabricating semiconductor structures in the exemplary comparative examples of this disclosure;
[0086] Figure 41 This is a schematic diagram of the formation of the upper electrode structure involved in the method of fabricating the semiconductor structure in the exemplary comparative example of this disclosure.
[0087] Figure label:
[0088] 01. Initial structure; 100. Substrate; 200. Capacitor contact area; 300. Target layer; 310. Dielectric layer; 310a. Dielectric layer a; 310b. Dielectric layer b; 320. Support layer; 320a. Support layer a; 320b. Support layer b; 320c. Support layer c; 11. First lower electrode structure; 12. Second lower electrode structure; 121. Annular portion; 122. Cylindrical portion; 001. First trench; 400, First mask layer; 410, First opening; 011, Capacitor hole; 002, Second trench; 500, First sacrificial layer; 30, Photoresist mask; 31, First dielectric layer; 32, Second dielectric layer; 13, Dielectric structure; 14, Top electrode structure; 003, Third trench; 600, Second mask layer; 610, Second opening; 004, Fourth trench; 700, Third mask layer; 710, Third opening;
[0089] 01' Initial structure; 100' Substrate; 200' Capacitor contact area; 300' Target layer; 400' Mask layer; 410' First opening; 011' Capacitor hole; 001' Trench; 11' Lower electrode structure; 13' Dielectric structure; 14' Upper electrode structure. Detailed Implementation
[0090] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and feature vectors in the embodiments of this disclosure can be arbitrarily combined with each other.
[0091] like Figure 37-41As shown, the current method for fabricating a capacitor structure first provides an initial structure 01', which includes a capacitor contact region 200' and a target layer 300' located on the capacitor contact region 200'. A mask layer 400' is formed on the top surface of the target layer 300', and the mask layer 400' has a first opening 410'. A trench 001' is formed by etching the target layer 300' according to the mask layer 400'. A lower electrode structure 11' is formed in the trench 001', and the lower electrode structure 11' is disposed on the substrate 100' to form a capacitor hole 011'. The bottom of the lower electrode structure 11' is connected to a portion of the structure of the capacitor contact region 200'. Next, a dielectric structure 13' is deposited on the lower electrode structure 11', and the dielectric structure 13' covers the outer surface of the lower electrode structure 11'. An upper electrode structure 14' is deposited on the dielectric structure 13', and the upper electrode structure 14' covers the outer surface of the dielectric structure 13'.
[0092] The structure of the capacitor obtained by the above-described capacitor fabrication method is as follows: Figure 41 As shown, the small exposed surface area of the lower electrode structure 11' and the small deposition area of the dielectric structure 13' limit the charge storage capacity of the capacitor structure.
[0093] Therefore, embodiments of this disclosure provide a method for fabricating a semiconductor structure. Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of this disclosure, as shown below. Figure 1 As shown, the method in this embodiment includes the following steps:
[0094] S110: Provides an initial structure, which includes a capacitor contact area and a target layer located on the capacitor contact area.
[0095] like Figure 10 As shown, the provided initial structure 01 includes a substrate 100 and a target layer 300 disposed on the substrate 100. A capacitor contact region 200 is disposed in the substrate 100, wherein a portion of the bottom surface of the target layer 300 contacts the capacitor contact region 200. In this embodiment, the target layer 300 includes a support layer 320 and a dielectric layer 310 alternately disposed on the substrate 100. A semiconductor structure is formed by etching the target layer 300. The specific number and stack height of the support layer 320 and dielectric layer 310 of the target layer 300 are set according to the height of the semiconductor structure to be formed.
[0096] The dielectric layer 310 is made of silicon oxide or BPSG (boro-phospho-silicate glass). The dielectric layer 310 may be doped with boron or phosphorus. The support layer 320 is made of any one or any combination of two or more of silicon nitride, silicon oxynitride, and silicon carbonitride.
[0097] S120: A first lower electrode structure is formed within the target layer, and the first lower electrode structure is connected to at least a portion of the capacitor contact area.
[0098] like Figure 12 , Figure 25 As shown, the first lower electrode structure 11 is disposed in the target layer 300, and the first lower electrode structure 11 is connected to all or part of the capacitor contact area 200. The first lower electrode structure 11 can be deposited using atomic layer deposition (ALD). The material of the first lower electrode structure 11 includes compounds formed from one or two of metal nitrides and metal silicides, such as titanium nitride, titanium silicide, nickel silicide, and titanium silicon nitride (TiSixNy). In this embodiment, the material of the first lower electrode structure 11 is titanium nitride.
[0099] S130: A second lower electrode structure connected to the first lower electrode structure is formed within the target layer.
[0100] like Figure 17 , Figure 32 As shown, the bottom surface of the second lower electrode structure 12 is connected to the first lower electrode structure 11, and the remaining part of the second lower electrode structure 12 is separated from the first lower electrode structure 11. In this embodiment, the second lower electrode structure 12 can be deposited in the target layer 300 using atomic layer deposition (ALD). The material of the second lower electrode structure includes compounds formed by one or two of metal nitrides and metal silicides, such as titanium nitride, titanium silicide, nickel silicide, and titanium silicon nitride (TiSixNy). In this embodiment, the first lower electrode structure 11 and the second lower electrode structure 12 are made of the same material, which is titanium nitride.
[0101] The lower electrode of the semiconductor structure fabricated in this embodiment includes a first lower electrode structure 11 and a second lower electrode structure 12. The first lower electrode structure 11 and the second lower electrode structure 12 are partially connected. While keeping the space occupied by the lower electrode in the semiconductor structure unchanged, the exposed surface area of the first lower electrode structure 11 and the second lower electrode structure 12 is larger, so that the capacitor structure has better charge storage performance.
[0102] The semiconductor structure fabrication method of this disclosure improves the semiconductor structure fabrication process, makes full use of the remaining space of the semiconductor structure, increases the proportion of the lower electrode structure, and increases the charge storage capacity of the semiconductor structure.
[0103] As one embodiment of this disclosure, a method for fabricating a semiconductor structure is provided. Figure 2 This is a flowchart of the semiconductor structure fabrication method provided in this embodiment, such as... Figure 2 As shown, the method in this embodiment includes the following steps:
[0104] S210: Provides an initial structure, which includes a capacitor contact area and a target layer located on the capacitor contact area.
[0105] S220: A first lower electrode structure is formed within the target layer, and the first lower electrode structure is connected to at least a portion of the capacitor contact area.
[0106] S230: A second lower electrode structure connected to the first lower electrode structure is formed within the target layer.
[0107] Steps S210 and S230 in this embodiment are implemented in the same way as steps S110 and S130 in the above embodiment, and will not be described again here.
[0108] like Figure 11 As shown, in step S220, a first trench 001 is formed within the target layer 300, exposing the entire capacitor contact area 200, as indicated by [reference]. Figure 12 A first lower electrode structure 11 is formed in the first trench 001, and the first lower electrode structure 11 is connected to the capacitor contact area 200.
[0109] like Figure 10 As shown, a first mask layer 400 is formed on the target layer 300 of the initial structure. The first mask layer 400 includes a first opening 410, which corresponds to the location of the capacitor contact region 200 on the substrate. The target layer 300 is etched according to the first mask layer 400, and the target layer 300 corresponding to the first opening 410 is etched until the capacitor contact region 200 is exposed. Etching is then stopped. Figure 11 As shown, a first trench 001 is obtained. In this embodiment, the size of the first opening 410 can be greater than or equal to the size of the capacitor contact area 200, and the projection of the capacitor contact area 200 on the substrate 100 is located within the projection range of the first opening 410 on the substrate 100, so that the first trench 001 etched according to the first opening 410 exposes the entire capacitor contact area 200.
[0110] like Figure 12 This illustrates the process of forming a first lower electrode structure 11 in the first trench 001, and connecting the first lower electrode structure 11 to the capacitor contact area 200, with reference to... Figure 11As shown, a first lower electrode structure 11 is formed on the sidewall and bottom surface of the first trench 001. The first lower electrode structure 11 is in contact with the capacitor contact area 200 and forms a capacitor hole 011. The first lower electrode structure 11 can be deposited on the sidewall and bottom surface of the first trench 001 and on the top surface of the target layer 300 using atomic layer deposition (ALD). Then, a dry etching process is used to remove the first lower electrode structure 11 located on the top surface of the target layer 300, while retaining the first lower electrode structure 11 located on the sidewall and bottom surface of the first trench 001.
[0111] In this embodiment, the first lower electrode structure 11 covers the sidewall and bottom surface of the first trench 001, and the first lower electrode structure 11 forms a capacitor hole 011, providing space for the subsequent deposition of the second lower electrode structure 12.
[0112] As one embodiment of this disclosure, a method for fabricating a semiconductor structure is provided. Figure 3 This is a flowchart of the semiconductor structure fabrication method provided in this embodiment, such as... Figure 3 As shown, the method in this embodiment includes the following steps:
[0113] S310: Provides an initial structure, which includes a capacitor contact area and a target layer located on the capacitor contact area 200.
[0114] S320: A first lower electrode structure is formed within the target layer, and the first lower electrode structure is connected to the capacitor contact area.
[0115] S330: A second lower electrode structure is formed within the target layer and connected to the first lower electrode structure.
[0116] like Figure 13 As shown, refer to Figure 12 First, a first sacrificial layer 500 is deposited in the capacitor via 011. The first sacrificial layer 500 covers the sidewalls of the first lower electrode structure 11, the bottom wall of the first lower electrode structure 11, and the top surface of the target layer 300. Then, as... Figure 14 As shown, the first sacrificial layer 500 covering the bottom wall of the first lower electrode structure 11 and the top surface of the target layer 300 is removed by an etching process, while the first sacrificial layer 500 covering the side wall of the first lower electrode structure 11 is retained, so as to form a second trench 002 in the first trench 001. The first sacrificial layer 500 surrounds the side wall of the first lower electrode structure 11 to form the second trench 002, and the second trench 002 exposes part of the bottom surface of the first lower electrode structure 11.
[0117] In this embodiment, atomic layer deposition (ALD) can be used to deposit a first sacrificial layer 500 on the sidewalls and bottom of the first lower electrode structure 11, as well as on the top surface of the target layer 300. When etching the first sacrificial layer 500, a high-selectivity dry etching process can be used to remove the first sacrificial layer 500 located on the top surface of the target layer 300 and the bottom wall of the first lower electrode structure 11, leaving the first sacrificial layer 500 located on the sidewalls of the first trench 001. The material of the first sacrificial layer 500 includes silicon oxide or BPSG (boro-phospho-silicate glass), and the material of the first sacrificial layer 500 may be doped with boron or phosphorus.
[0118] like Figure 15 As shown, refer to Figure 14 In this embodiment, an atomic layer deposition (ALD) process is used to deposit a second lower electrode structure 12 in the second trench 002 and on the top surface of the target layer 300. Then, as... Figure 16 As shown, a dry etching process is used to remove the second lower electrode structure 12 located on the top surface of the target layer 300, while retaining the second lower electrode structure 12 located in the second trench 002. The second lower electrode structure 12 is flush with the top surface of the target layer 300. In this embodiment, the first lower electrode structure 11 and the second lower electrode structure 12 are made of the same material, titanium nitride.
[0119] In this embodiment, after the first lower electrode structure 11 is formed, the first lower electrode structure 11 covers the sidewall and bottom surface of the first trench 001. There is still unused remaining space in the first trench 001. The second lower electrode structure 12 continues to be deposited in the first trench 001. The bottom of the portion of the first lower electrode structure 11 and the second electrode structure 12 covering the bottom wall of the first trench 001 are connected. A gap is formed between the first lower electrode structure 11 and the second electrode structure 12 covering the sidewall of the first trench 001. The second electrode structure 12 makes full use of the remaining space in the first lower electrode structure 11 and increases the outer surface area of the lower electrode.
[0120] As one embodiment of this disclosure, a method for fabricating a semiconductor structure is provided. Figure 4 This is a flowchart of the semiconductor structure fabrication method provided in this embodiment, such as... Figure 4 As shown, the method in this embodiment includes the following steps:
[0121] S410: Provides an initial structure, which includes a capacitor contact area and a target layer located on the capacitor contact area.
[0122] S420: A first lower electrode structure is formed within the target layer, and the first lower electrode structure is connected to the capacitor contact area.
[0123] S430: A second lower electrode structure is formed within the target layer and connected to the first lower electrode structure.
[0124] S440: Simultaneously remove the first dielectric layer and the first sacrificial layer of the target layer.
[0125] In this embodiment, steps S410-S430 are implemented in the same way as steps S310-S330 in the above embodiment, and will not be described again here.
[0126] by Figure 15 The direction shown is a reference direction. In this embodiment, the target layer 300 includes a support layer a320a, a dielectric layer a310a, a support layer b320b, a dielectric layer b310b, and a support layer c320c, which are stacked sequentially from bottom to top. Figure 16 As shown, after the second lower electrode structure 12 is formed, the remaining dielectric layers a310a and b310b form the first dielectric layer 31.
[0127] like Figure 17 As shown, and refer to Figure 16 In this embodiment, the first sacrificial layer 500 and the first dielectric layer 31 can be removed by dry etching or wet etching. First, all of the first sacrificial layer 500 can be removed, and then the dielectric layer b310b and the dielectric layer a310a can be removed.
[0128] like Figure 17-22 As shown, the process of the first dielectric layer 31 is as follows: a photoresist mask 30 is formed on the upper surface of the support layer c320c, the photoresist mask 30 at least covers the edge area of the support layer c320c, the support layer c320c not covered by the photoresist mask 30 is etched away to expose the dielectric layer b310b, the dielectric layer b310b is removed by dry or wet etching to expose the support layer c320c, the support layer b320b is etched again with the photoresist mask 30 as a cover to expose the dielectric layer a310a, and the dielectric layer a310a is removed by dry or wet etching.
[0129] In this embodiment, the first dielectric layer 31 and the first sacrificial layer 500 are removed in preparation for subsequent processing of the semiconductor structure.
[0130] As one embodiment of this disclosure, a method for fabricating a semiconductor structure is provided. Figure 5 This is a flowchart of the semiconductor structure fabrication method provided in this embodiment, such as... Figure 5 As shown, the method in this embodiment includes the following steps:
[0131] S510: Provides an initial structure, which includes a capacitor contact area and a target layer located on the capacitor contact area.
[0132] S520: A first lower electrode structure is formed within the target layer, and the first lower electrode structure is connected to the capacitor contact area.
[0133] S530: A second lower electrode structure is formed within the target layer and connected to the first lower electrode structure.
[0134] S540: Simultaneously remove the first dielectric layer and the first sacrificial layer of the target layer.
[0135] S550: Simultaneously, a dielectric structure and an upper electrode structure are formed sequentially on the surfaces of the first lower electrode structure and the second lower electrode structure.
[0136] Steps S510-S540 in this embodiment are implemented in the same way as steps S410-S440 in the above embodiment, and will not be described again here.
[0137] like Figure 23 As shown, in step S550, an atomic layer deposition (ALD) process can be used to deposit a layer of high-K material as a dielectric structure 13 on the outer surfaces of the first lower electrode structure 11 and the second lower electrode structure 12. The dielectric structure 13 at least covers the outer surfaces of the first lower electrode structure 11 and the second lower electrode structure 12.
[0138] like Figure 24 As shown, an upper electrode structure 14 can be deposited on the outer surface of the dielectric structure 13 using an atomic layer deposition (ALD) process. The upper electrode structure 14 includes a compound formed by one or two of metal nitrides and metal silicides, such as titanium nitride, titanium silicide, nickel silicide, and titanium silicon nitride (TiSixNy).
[0139] In this embodiment, such as Figure 25 As shown, after depositing the upper electrode structure 14 on the outer surface of the dielectric structure 13, an upper electrode filling structure 15 is formed. The upper electrode filling structure 15 covers the outer surface of the upper electrode structure 14 and fills the gaps between the upper electrode structures 14. The material of the upper electrode filling structure 15 includes boron-doped germanium silicon.
[0140] In this embodiment, a capacitor structure is obtained by sequentially depositing a dielectric structure 13 and an upper electrode structure 14 on the first lower electrode structure 11 and the second lower electrode structure 12, and then encapsulating them. In this embodiment, the dielectric structure 13 of the semiconductor structure has a larger deposition area, which further increases the charge storage capacity of the capacitor structure.
[0141] As one embodiment of this disclosure, a method for fabricating a semiconductor structure is provided. Figure 6 This is a flowchart of the semiconductor structure fabrication method provided in this embodiment, such as... Figure 6 As shown, the method in this embodiment includes the following steps:
[0142] S610: Provides an initial structure, which includes a capacitor contact region and a target layer located on the capacitor contact region. The initial structure includes a substrate, the capacitor contact region is disposed in the substrate, the target layer is disposed on the substrate, and a portion of the bottom surface of the target layer contacts the capacitor contact region.
[0143] S620: A third trench is formed within the target layer, exposing part of the capacitor contact area; a first lower electrode structure is formed by filling the third trench.
[0144] S630: A second lower electrode structure is formed within the target layer and connected to the first lower electrode structure.
[0145] Steps S610 and S630 in this embodiment are implemented in the same way as steps S110 and S130 in the previous embodiment, and will not be described again here.
[0146] like Figure 27 As shown, and refer to Figure 26 In step S620 of this embodiment, a third trench 003 is formed within the target layer 300, and the third trench 003 exposes a portion of the capacitor contact area 200. For example... Figure 26 As shown, a second mask layer 600 is formed on the target layer 300, and the second mask layer 600 forms a second opening 610, which corresponds to the location of the capacitor contact region 200 in the substrate 100. The target layer 300 is etched according to the second opening 610 of the second mask layer 600 until the capacitor contact region 200 is exposed, at which point the etching stops, resulting in a third trench 003. The size of the second opening 610 is smaller than the size of the capacitor contact region 200, and the projection of the second opening 610 onto the substrate 100 is within the range of the projection of the capacitor contact region 200 onto the substrate 100. The third trench 003 obtained by etching according to the second opening 610 exposes the central region of the capacitor contact region 200, while the edge regions of the capacitor contact region 200 remain covered by the target layer 300.
[0147] like Figure 28 ,like Figure 29As shown, in step S630 of this embodiment, referring to Figure 27 As shown, filling the third trench 003 to form the first lower electrode structure 11 includes: depositing the first lower electrode structure 11, filling the third trench 003 and covering the top surface of the target layer 300, removing the first lower electrode structure 11 covering the top surface of the target layer 300 by dry etching, and retaining the first lower electrode structure 11 in the third trench 003 and flush with the top surface of the target layer 300.
[0148] The semiconductor structure fabrication method of this disclosure improves the semiconductor structure fabrication process, makes full use of the remaining space of the semiconductor structure, increases the proportion of the lower electrode structure, and increases the charge storage capacity of the semiconductor structure.
[0149] As one embodiment of this disclosure, a method for fabricating a semiconductor structure is provided. Figure 7 This is a flowchart of the semiconductor structure fabrication method provided in this embodiment, such as... Figure 7 As shown, the method in this embodiment includes the following steps:
[0150] S710: Provides an initial structure, which includes a capacitor contact region and a target layer located on the capacitor contact region. The initial structure includes a substrate, the capacitor contact region is disposed in the substrate, the target layer is disposed on the substrate, and a portion of the bottom surface of the target layer contacts the capacitor contact region.
[0151] S720: A third trench is formed within the target layer, exposing part of the capacitor contact area; the third trench is filled to form a first lower electrode structure.
[0152] S730: Define a fourth trench in the target layer, the fourth trench exposing the capacitor contact area not exposed by the third trench; form a second lower electrode structure connected to the first lower electrode structure on the sidewall and bottom surface of the fourth trench.
[0153] Steps S710 and S730 in this embodiment are implemented in the same way as steps S610 and S630 in the previous embodiment, and will not be described again here.
[0154] like Figure 30 As shown, refer to Figure 29 A third mask layer 700 is formed on the target layer 300, covering the first lower electrode structure 11 and part of the target layer 300. The third mask layer 700 forms a third opening 710 surrounding the first lower electrode structure 11 on the surface of the target layer 300. The target layer 300 is etched according to the third mask layer 700 to remove the target layer 300 corresponding to the third opening 710, exposing the capacitor contact area 200 not exposed by the third trench 003. Figure 31 As shown, the fourth trench 004 is formed.
[0155] A second lower electrode material is deposited in the fourth trench 004, covering the bottom and sidewalls of the fourth trench 004 and the top surface of the target layer 300. The second lower electrode material on the top surface of the target layer 300 is removed by dry etching. Figure 32 As shown, the second lower electrode material covering the bottom and side walls of the fourth trench 004 is retained as the second lower electrode structure 12.
[0156] In this embodiment, a second lower electrode structure 12 is formed around the first lower electrode structure 11. The second lower electrode structure 12 surrounds the first lower electrode structure 11 and makes partial contact with the first lower electrode structure 11, making full use of the space of the semiconductor structure, increasing the proportion of the lower electrode, and also increasing the exposed surface area of the lower electrode structure.
[0157] As one embodiment of this disclosure, a method for fabricating a semiconductor structure is provided. Figure 8 This is a flowchart of the semiconductor structure fabrication method provided in this embodiment, such as... Figure 8 As shown, the method in this embodiment includes the following steps:
[0158] S810: Provides an initial structure, which includes a capacitor contact region and a target layer located on the capacitor contact region. The initial structure includes a substrate, the capacitor contact is disposed in the substrate, the target layer is disposed on the substrate, a portion of the bottom surface of the target layer contacts the capacitor contact region, and the target layer includes a dielectric layer.
[0159] S820: A third trench is formed within the target layer, exposing part of the capacitor contact area; the third trench is filled to form a first lower electrode structure.
[0160] S830: Define a fourth trench in the target layer, the fourth trench exposing the capacitor contact area not exposed by the third trench; form a second lower electrode structure connected to the first lower electrode structure on the sidewall and bottom surface of the fourth trench.
[0161] S840: Remove the second dielectric layer of the target layer.
[0162] Steps S810-S830 in this embodiment are implemented in the same way as steps S710-S730 in the previous embodiment, and will not be described again here.
[0163] like Figure 32 As shown, after forming the second lower electrode structure 12, the remaining dielectric layer 320 forms the second dielectric layer 32. In this embodiment, referring to... Figure 33 After forming the second lower electrode structure 12, all the second dielectric layers 32 in the first sacrificial layer 500 and the substrate 100 are removed simultaneously.
[0164] In this embodiment, the removal of the second dielectric layer 32 is in preparation for subsequent processing of the semiconductor structure.
[0165] As one embodiment of this disclosure, a method for fabricating a semiconductor structure is provided. Figure 9 This is a schematic flowchart of the semiconductor structure fabrication method provided in this embodiment, as shown below. Figure 9 As shown, the method in this embodiment includes the following steps:
[0166] S910: Provides an initial structure, which includes a capacitor contact region and a target layer located on the capacitor contact region. The initial structure includes a substrate, the capacitor contact region is disposed in the substrate, the target layer is disposed on the substrate, and a portion of the bottom surface of the target layer contacts the capacitor contact region.
[0167] S920: A third trench is formed within the target layer, exposing part of the capacitor contact area; the third trench is filled to form a first lower electrode structure.
[0168] S930: Define a fourth trench in the target layer, the fourth trench exposing the capacitor contact area not exposed by the third trench; form a second lower electrode structure connected to the first lower electrode structure on the sidewall and bottom surface of the fourth trench.
[0169] S940: Remove the second dielectric layer from the target layer.
[0170] S950: Simultaneously, a dielectric structure and an upper electrode structure are formed sequentially on the surfaces of the first lower electrode structure and the second lower electrode structure.
[0171] In this embodiment, steps S910-940 are the same as steps S810-S840 in the above embodiment.
[0172] Steps S910-S940 in this embodiment are implemented in the same way as steps S810-S840 in the previous embodiment, and will not be described again here.
[0173] like Figure 34 As shown, a high-k material is deposited onto the semiconductor structure as a dielectric structure 13. The dielectric structure 13 at least covers the outer surfaces of the first lower electrode structure 11 and the second lower electrode structure 12, as shown. Figure 35 As shown, an upper electrode structure 14 is deposited, which covers the outer surface of the dielectric structure 13.
[0174] like Figure 36 As shown, in this embodiment, after depositing the upper electrode structure 14 on the outer surface of the dielectric structure 13, an upper electrode filling structure 15 is formed. The upper electrode filling structure 15 covers the outer surface of the upper electrode structure 14 and fills the gaps between the upper electrode structures 14. The material of the upper electrode filling structure 15 includes boron-doped germanium silicon.
[0175] One embodiment of this disclosure provides a semiconductor structure, such as Figure 20 , 33 As shown, it includes: a substrate 100, a capacitor contact area 200 located within the substrate 100, a first lower electrode structure 11 located on the substrate 100, and a second lower electrode structure 12 connected to the first lower electrode structure 11, wherein the first lower electrode structure 11 is connected to at least a portion of the capacitor contact area 200.
[0176] In this embodiment, without changing the size and volume of the semiconductor structure, the second lower electrode structure 12 surrounds the first lower electrode 11, increasing the exposed surface area of the lower electrode of the semiconductor structure, making full use of the space of the semiconductor structure, and increasing the charge storage capacity of the capacitor.
[0177] As one embodiment of this disclosure, such as Figure 20 As shown, the semiconductor structure includes: a substrate 100, a capacitor contact region 200 located on the substrate 100, a first lower electrode structure 11 located on the substrate 100, and a second lower electrode structure 12 connected to the first lower electrode structure 11. The first lower electrode structure 11 is disposed on the capacitor contact region 200 and connected to the capacitor contact region 200; the second lower electrode structure 12 is disposed on the first lower electrode structure 11 and connected to the first lower electrode structure 11.
[0178] The first lower electrode structure 11 forms a capacitor hole 011, and the second lower electrode structure 12 is disposed in the capacitor hole 011. The bottom wall of the second lower electrode structure 12 is connected to a portion of the bottom wall of the capacitor hole 011.
[0179] Among them, such as Figure 23 , 24 As shown, the semiconductor structure also includes a dielectric structure 13 covering the surfaces of the first lower electrode structure 11 and the second lower electrode structure 12, and an upper electrode structure 14 covering the surface of the dielectric structure 13.
[0180] In this embodiment, a second lower electrode structure 12 is added to the first lower electrode structure 11. The bottom wall of the second lower electrode structure 12 is in contact with a portion of the bottom wall of the first lower electrode structure 11, and a gap is formed between the side wall of the second lower electrode structure 12 and the side wall of the first lower electrode structure 11. This increases the surface area exposed by the lower electrode structure, makes full use of the remaining space of the capacitor hole 011, and increases the charge storage capacity of the semiconductor structure.
[0181] As one embodiment of this disclosure, such as Figure 33As shown, the semiconductor structure includes: a substrate 100, a capacitor contact region 200 located on the substrate 100, a first lower electrode structure 11 located on the substrate 100, and a second lower electrode structure 12 connected to the first lower electrode structure 11. The first lower electrode structure 11 is disposed on the capacitor contact region 200 and partially connected to it. The second lower electrode structure 12 is disposed around the first lower electrode structure 11 on the substrate 100 and contacts another portion of the capacitor contact region 200.
[0182] Among them, such as Figure 33 As shown, the first lower electrode structure 11 is a columnar structure, and the bottom wall of the columnar structure contacts part of the capacitor contact area 200; the second lower electrode structure 12 includes an annular portion 121 and a cylindrical portion 122 arranged around the first lower electrode structure 11. The inner ring of the annular portion 121 is connected to the bottom wall of the first lower electrode structure 11, and the cylindrical portion 122 of the outer ring of the annular portion 121 is connected.
[0183] In this embodiment, such as Figure 34 , 35 As shown, dielectric structure 13 covers the surfaces of the first lower electrode structure 11 and the second lower electrode structure 12; upper electrode structure 14 covers the surface of dielectric structure 13.
[0184] In this embodiment, the second lower electrode structure 12 includes an annular portion 121 and a cylindrical portion 122 surrounding the first lower electrode structure 11. The inner ring of the annular portion 121 is connected to the bottom wall of the first lower electrode structure 11, and the cylindrical portion 122 of the outer ring of the annular portion 121 is connected. The cylindrical portion 122 surrounds the first lower electrode structure 11 and does not contact the first lower electrode structure 11. An annular space is formed between the cylindrical portion 122 and the first lower electrode structure 11. Without changing the size and volume of the semiconductor structure, the second lower electrode structure 12 increases the exposed surface area of the lower electrode of the semiconductor structure by surrounding the first lower electrode 11, making full use of the space of the semiconductor structure and increasing the charge storage capacity of the capacitor.
[0185] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or device. Without further limitation, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the article or device that includes said element.
[0186] The above embodiments are only used to illustrate the technical solutions of this disclosure and are not intended to limit it. The disclosure has been described in detail with reference to preferred embodiments. Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of this disclosure without departing from the spirit and scope of this disclosure, and all such modifications and substitutions should be covered within the scope of the claims of this disclosure.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, The method includes: An initial structure is provided, the initial structure including a capacitor contact region and a target layer located on the capacitor contact region; A first lower electrode structure is formed within the target layer, and the first lower electrode structure is connected to at least a portion of the capacitor contact area. A second lower electrode structure, connected to the first lower electrode structure, is formed within the target layer; The formation of the first lower electrode structure within the target layer includes: A first trench is formed within the target layer, the first trench exposing the capacitor contact area; A first lower electrode structure connected to the capacitor contact area is formed on the sidewall and bottom surface of the trench; The process of forming a second lower electrode structure connected to the first lower electrode structure within the target layer includes: A first sacrificial layer is formed on the sidewall of the first lower electrode structure, and a second trench is formed in the first trench, the second trench exposing a portion of the bottom surface of the first lower electrode structure; A second lower electrode structure is formed in the second trench to fill the second trench.
2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The target layer includes a first dielectric layer, and after forming the second lower electrode structure, it further includes: simultaneously removing the first dielectric layer and the first sacrificial layer.
3. A method for fabricating a semiconductor structure, characterized in that, The method includes: An initial structure is provided, the initial structure including a capacitor contact region and a target layer located on the capacitor contact region; A first lower electrode structure is formed within the target layer, and the first lower electrode structure is connected to at least a portion of the capacitor contact area. A second lower electrode structure, connected to the first lower electrode structure, is formed within the target layer; The formation of the first lower electrode structure within the target layer includes: A third trench is formed within the target layer, the third trench exposing a portion of the capacitor contact area; The first lower electrode structure is formed by filling the third trench; The process of forming a second lower electrode structure connected to the first lower electrode structure within the target layer includes: A fourth trench is defined in the target layer, the fourth trench exposing the capacitive contact area that was not exposed by the third trench; A second lower electrode structure, which is connected to the first lower electrode structure, is formed on the sidewall and bottom surface of the fourth trench.
4. The method for fabricating a semiconductor structure according to claim 3, characterized in that, The definition of a fourth trench in the target layer, the fourth trench exposing the capacitive contact area not exposed by the third trench, includes: A mask layer is formed, the mask layer covering the first lower electrode structure and a portion of the target layer, and the mask layer forms an opening around the first lower electrode structure on the surface of the target layer; Remove the target layer corresponding to the opening to expose the capacitor contact area that was not exposed by the third trench, thus forming the fourth trench.
5. The method for fabricating a semiconductor structure according to claim 4, characterized in that, The target layer includes a second dielectric layer, and after forming the second lower electrode structure, the second dielectric layer is removed.
6. The method for fabricating a semiconductor structure according to claim 2 or 5, characterized in that, After forming the second lower electrode structure, the process also includes: Simultaneously, dielectric structures and upper electrode structures are sequentially formed on the surfaces of the first lower electrode structure and the second lower electrode structure.
7. A semiconductor structure, characterized in that, include: Substrate; The capacitor contact area is located within the substrate; The first lower electrode structure is disposed on the capacitor contact area and is in contact with the capacitor contact area; The second lower electrode structure is disposed on the first lower electrode structure and connected to the first lower electrode structure; The first lower electrode structure forms a capacitor hole, and the second lower electrode structure fills the capacitor hole to form a columnar structure. The sidewalls of the second lower electrode structure and the sidewalls of the first lower electrode structure are not connected, and the bottom of the second lower electrode structure is connected to the first lower electrode structure.
8. A semiconductor structure, characterized in that, include: Substrate; The capacitor contact area is located within the substrate; The first lower electrode structure is a columnar structure, and the bottom wall of the columnar structure is in contact with part of the capacitor contact area; A second lower electrode structure is disposed on the substrate surrounding the first lower electrode structure. The second lower electrode structure includes an annular portion and a cylindrical portion surrounding the first lower electrode structure. The inner ring of the annular portion is connected to the bottom wall of the first lower electrode structure, and the cylindrical portion of the outer ring of the annular portion is connected to it.
9. The semiconductor structure according to claim 8, characterized in that, The inner ring of the annular portion is connected to the bottom wall of the first lower electrode structure and contacts another part of the capacitor contact area.
10. The semiconductor structure according to claim 7 or 8, characterized in that, Semiconductor structures also include: A dielectric structure covering the surfaces of the first lower electrode structure and the second lower electrode structure; An upper electrode structure that covers the surface of the dielectric structure.