Fabrication method of embedded flash memory devices

Abstract

This invention provides a method for fabricating an embedded flash memory device, comprising: providing a substrate including a memory region and a peripheral logic region, wherein a gate oxide layer, a floating gate, an ONO dielectric layer, a control gate, and a first silicon nitride layer are formed on the substrate; during the fabrication of some film layers in the memory region, a smile effect occurs in the floating gate of the peripheral logic region; forming a second silicon nitride layer and a photoresist layer; removing the photoresist layer on the peripheral logic region; removing the second silicon nitride layer, the first silicon nitride layer, the control gate, the ONO dielectric layer, and the floating gate on the peripheral logic region, at which point, floating gate polysilicon material remains in the gate oxide layer on the STI side of the peripheral logic region; removing the remaining photoresist layer on the peripheral logic region; and performing a rapid thermal oxidation process. This application uses a rapid thermal oxidation process to fuse the floating gate polysilicon residue with the gate oxide layer, eliminating the floating gate polysilicon residue and avoiding peeling defects of the floating gate polysilicon residue after subsequent wet acid bath processing.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and specifically to a method for fabricating an embedded flash memory device. Background Technology

[0002] Currently, in the manufacturing process of embedded flash memory devices, during the thermal oxidation process on the select gate surface of the storage area to form the select gate oxide layer, it is often unavoidable that the floating gate near the shallow trench isolation structure in the peripheral logic area is oxidized into a gate oxide layer. This results in the floating gate near the shallow trench isolation structure becoming thinner while the gate oxide layer becomes thicker. This phenomenon is called the smiling effect.

[0003] However, after the etching process to remove the floating gate in the peripheral logic area, due to the characteristics of the etching process, which is generally etched vertically downwards, floating gate polysilicon residue is easily generated in the gate oxide layer on both sides of the shallow trench isolation structure. Furthermore, after subsequent wet acid bath operations, the surrounding gate oxide layer is partially or completely etched, resulting in the peeling off of floating gate polysilicon residue. The fallen floating gate polysilicon residue may scratch the device surface, thereby affecting the performance of the embedded flash memory device. Summary of the Invention

[0004] This application provides a method for fabricating an embedded flash memory device, which can solve at least one of the following problems: the inability to etch away residual floating gate polysilicon material caused by the smile effect in the peripheral logic area, and the problem that residual floating gate polysilicon material falls off and scratches the device after acid washing.

[0005] On one hand, embodiments of this application provide a method for fabricating an embedded flash memory device, including:

[0006] A substrate is provided, the substrate including a storage region and a peripheral logic region, a plurality of shallow trench isolation structures are formed in the substrate, and stacked gate oxide, floating gate, ONO dielectric layer, control gate and first silicon nitride layer are formed on the substrate.

[0007] A first sidewall structure, a second sidewall structure, a tunneling oxide layer, a select gate, and a select gate oxide layer are sequentially formed on the storage area. The first sidewall structure is located within the first silicon nitride layer. The second sidewall structure is located within the control gate and the ONO dielectric layer and covers a portion of the sidewall of the first sidewall structure. The tunneling oxide layer is located within the floating gate and the gate oxide layer and covers the remaining sidewalls of the second sidewall structure and the first sidewall structure. The tunneling oxide layer is U-shaped. The select gate fills the U-shaped space formed inside the tunneling oxide layer. The select gate oxide layer covers the surface of the select gate. At this time, the floating gates on both sides of the shallow trench isolation structure of the peripheral logic area exhibit a smile effect.

[0008] A second silicon nitride layer and a photoresist layer are sequentially formed on the surface of the select gate oxide layer on the memory region and on the surface of the first silicon nitride layer on the peripheral logic region;

[0009] Remove the photoresist layer on the peripheral logic region;

[0010] Remove the second silicon nitride layer, the first silicon nitride layer, the control gate, the ONO dielectric layer, and the floating gate on the peripheral logic region. At this time, the polysilicon material of the floating gate remains in the gate oxide layer on both sides of the shallow trench isolation structure on the peripheral logic region.

[0011] The residual photoresist layer on the peripheral logic region is removed using an ashing process;

[0012] A wet cleaning process is performed on the shallow trench isolation structure and the gate oxide layer on the peripheral logic region.

[0013] A rapid thermal oxidation process is performed to fuse the polycrystalline silicon material with the gate oxide layer.

[0014] Optionally, in the method for fabricating the embedded flash memory device, the process parameters of the rapid thermal oxidation process include: oxidation temperature of 600℃~800℃; oxidation time of 5min~10min; and oxygen flow rate of 5SLM~7SLM.

[0015] Optionally, in the method for fabricating the embedded flash memory device, during the rapid thermal oxidation process to fuse the polycrystalline silicon material with the gate oxide layer, the oxidation temperature is 800°C, the oxidation time is 10 min, and the oxygen flow rate is 6 SLM.

[0016] Optionally, in the method for fabricating the embedded flash memory device, the ONO dielectric layer comprises, from top to bottom, a top silicon oxide layer, an intermediate silicon nitride layer, and a bottom silicon oxide layer.

[0017] Optionally, in the method for fabricating the embedded flash memory device, the step of removing the second silicon nitride layer, the first silicon nitride layer, the control gate, the ONO dielectric layer, and the floating gate on the peripheral logic region includes:

[0018] The second silicon nitride layer, the first silicon nitride layer, the control gate, and the top silicon oxide layer on the peripheral logic region are etched using a dry etching process.

[0019] The intermediate silicon nitride layer on the peripheral logic region is etched using a wet etching process;

[0020] The underlying silicon oxide layer and the floating gate on the peripheral logic region are etched using a dry etching process.

[0021] Optionally, in the method for fabricating the embedded flash memory device, the step of forming the first sidewall structure, the second sidewall structure, the tunneling oxide layer, the select gate, and the select gate oxide layer in the storage region includes:

[0022] The first silicon nitride layer of the storage region is etched to form a first trench;

[0023] A first sidewall structure is formed in the first trench, and the first sidewall structure covers the sidewall of the first trench;

[0024] The control gate and the ONO dielectric layer on the bottom wall of the first trench are etched to form a second trench;

[0025] A second sidewall structure is formed in the second trench, and the second sidewall structure covers part of the sidewall of the second trench;

[0026] The floating gate and the gate oxide layer on the bottom wall of the second trench are etched to form the third trench;

[0027] A tunneling oxide layer is formed, which covers the bottom and sidewalls of the third trench;

[0028] A selection gate is formed, the selection gate filling the third trench; and,

[0029] A select gate oxide layer is formed, which covers the select gate.

[0030] Optionally, in the method for fabricating the embedded flash memory device, after performing a rapid thermal oxidation process to fuse the polycrystalline silicon material with the gate oxide layer, the method further includes:

[0031] Remove the gate oxide layer from the upper surface of the shallow trench isolation structure of the peripheral logic region and the surface of the substrate.

[0032] Optionally, in the method for fabricating the embedded flash memory device, after performing a rapid thermal oxidation process to fuse the polycrystalline silicon material with the gate oxide layer, the method further includes:

[0033] An active region ion implantation process is performed on the substrate of the storage region.

[0034] The technical solution of this application has at least the following advantages:

[0035] After removing the residual photoresist layer on the peripheral logic region, this application uses a rapid thermal oxidation process to fuse the polysilicon material with the gate oxide layer, thereby eliminating the residual polysilicon material of the floating gate. This also avoids the peeling defects of the polysilicon residue of the floating gate after subsequent wet acid bath operations, and prevents the peeled polysilicon residue of the floating gate from scratching the device surface, thus improving the device yield. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0037] Figure 1 This is a flowchart of a method for fabricating an embedded flash memory device according to an embodiment of the present invention;

[0038] Figures 2-5 This is a schematic diagram of the semiconductor structure in each process step of fabricating an embedded flash memory device according to an embodiment of the present invention;

[0039] The reference numerals in the attached figures are explained as follows:

[0040] A - Storage area, B - Peripheral logic area;

[0041] 100-Substrate, 101-Shallow trench isolation structure, 110-Gate oxide layer, 120-Floating gate, 121-Polysilicon material / floating gate polysilicon residue, 130-ONO dielectric layer, 140-Control gate, 150-First silicon nitride layer, 160-First sidewall structure, 170-Second sidewall structure, 180-Tunneling oxide layer, 190-Select gate, 200-Second silicon nitride layer, 210-Photoresist layer, 300-Select gate oxide layer. Detailed Implementation

[0042] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0043] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0044] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0045] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0046] This application provides a method for fabricating an embedded flash memory device, referring to... Figure 1 , Figure 1 This is a flowchart of a method for fabricating an embedded flash memory device according to an embodiment of the present invention. The method for fabricating the embedded flash memory device includes:

[0047] Step S10: As Figure 2 As shown, a substrate 100 is provided, the substrate 100 including a memory region A and a peripheral logic region B, and multiple shallow trench isolation structures (STI) 101 are formed in both the memory region A and the peripheral logic region B of the substrate 100. Figure 1 Only one of the shallow trench isolation structures 101 in the substrate 100 of the peripheral logic region B is shown. The shallow trench isolation structure 101 in the storage region A is not shown. Stacked gate oxide layer 110, floating gate 120, ONO dielectric layer 130, control gate 140 and first silicon nitride layer 150 are formed on the substrate 100.

[0048] Step S20: As Figure 2As shown, a first sidewall structure 160, a second sidewall structure 170, a tunneling oxide layer 180, a select gate 190, and a select gate oxide layer 300 are sequentially formed on the storage area A. The first sidewall structure 160 is located within the first silicon nitride layer 150; the second sidewall structure 170 is located within the control gate 140 and the ONO dielectric layer 130 and covers a portion of the sidewall of the first sidewall structure 160; the tunneling oxide layer 180 is located within the floating gate 120 and the gate oxide layer 110 and covers the remaining sidewalls of the second sidewall structure 170 and the first sidewall structure 160, and the tunneling oxide layer 180 is U-shaped; the select gate 190 fills the U-shaped space formed inside the tunneling oxide layer 180; and the select gate oxide layer 300 covers the surface of the select gate 190.

[0049] In this embodiment, the step of forming the first sidewall structure 160, the second sidewall structure 170, the tunneling oxide layer 180, the select gate 190, and the select gate oxide layer 300 in the storage area A may specifically include:

[0050] The first silicon nitride layer 150 of the storage region A is etched to form a first trench;

[0051] A first sidewall structure 160 is formed in the first trench, and the first sidewall structure 160 covers the sidewall of the first trench;

[0052] The control gate 140 and the ONO dielectric layer 130 on the bottom wall of the first trench are etched to form a second trench;

[0053] A second sidewall structure 170 is formed in the second trench, and the second sidewall structure 170 covers part of the sidewall of the second trench.

[0054] The floating gate 120 and the gate oxide layer 110 on the bottom wall of the second trench are etched to form the third trench;

[0055] A tunneling oxide layer 180 is formed, which covers the bottom and sidewalls of the third trench;

[0056] Forming a selection gate 190, the selection gate 190 filling the third trench; and,

[0057] A select gate oxide layer 300 is formed, which covers the select gate 190.

[0058] like Figure 3As shown, in the process of forming the select gate oxide layer 300, this embodiment adopts a thermal oxidation process to oxidize the polysilicon on the surface of the select gate 190 into a select gate oxide layer 300. While the select gate oxide layer 300 is formed by thermal oxidation, the floating gates 120 on both sides of the shallow trench isolation structure 101 in the peripheral logic region B exhibit a smile effect. That is, the floating gates 120 in the peripheral logic region B that are close to the shallow trench isolation structure 101 are oxidized into a gate oxide layer 110, and the thickness of the floating gates 120 that are close to the shallow trench isolation structure 101 becomes thinner while the gate oxide layer 110 becomes thicker.

[0059] Furthermore, the ONO dielectric layer 130 comprises, from top to bottom, a top silicon oxide layer, an intermediate silicon nitride layer, and a bottom silicon oxide layer.

[0060] Step S30: A second silicon nitride layer 200 and a photoresist layer 210 are sequentially formed on the surface of the select gate oxide layer 300 on the storage region A and on the surface of the first silicon nitride layer 150 on the peripheral logic region B;

[0061] Step S40: Expose the photoresist layer 210 to the photoresist layer 210 on the peripheral logic region B, that is, open the area where the peripheral logic region B is located.

[0062] Step S50: As Figure 4 As shown, after removing the second silicon nitride layer 200, the first silicon nitride layer 150, the control gate 140, the ONO dielectric layer 130, and the floating gate 120 on the peripheral logic region B, the polysilicon material 121 of the floating gate 120 remains in the gate oxide layer 110 on both sides of the shallow trench isolation structure 101 on the peripheral logic region B.

[0063] Specifically, the step of removing the second silicon nitride layer, the first silicon nitride layer, the control gate, the ONO dielectric layer, and the floating gate from the peripheral logic region may include:

[0064] The top silicon oxide layer in the second silicon nitride layer 200, the first silicon nitride layer 150, the control gate 140, and the ONO dielectric layer 130 on the peripheral logic region B is etched using a dry etching process.

[0065] The intermediate silicon nitride layer in the ONO dielectric layer 130 on the peripheral logic region B is etched using a wet etching process;

[0066] The bottom silicon oxide layer and the floating gate 120 in the ONO dielectric layer 130 on the peripheral logic region are etched using a dry etching process.

[0067] It is worth noting that in step S50, because the multiple film layers on the upper surface of the shallow trench isolation structure 101 are relatively thin, the gate oxide layer 110 on the upper surface of the shallow trench isolation structure 101 is also basically etched away during the etching of the floating gate 120. A certain thickness of the gate oxide layer 110 remains on both sides of the shallow trench isolation structure 101 and on the surface of the substrate 100. Furthermore, due to the characteristics of the dry etching process, the polysilicon material 121 of the floating gate 120 will definitely remain in the gate oxide layer 110 on both sides of the shallow trench isolation structure 101.

[0068] Step S60: Remove the residual photoresist layer 210 on the peripheral logic region B using an ashing process. Specifically, a certain flow rate of oxygen can be introduced to participate in the ashing process, and the oxygen introduction time should not exceed 30 seconds, for example, the oxygen introduction time is 30 seconds.

[0069] Step S70: Perform a wet cleaning process on the shallow trench isolation structure 101 and the gate oxide layer 110 on the peripheral logic region B to completely remove the residual photoresist layer 210 on the peripheral logic region B.

[0070] Step S80: As Figure 5 As shown, a rapid thermal oxidation process is performed to fuse the polycrystalline silicon material 121 with the gate oxide layer 110. At this time, the polycrystalline silicon material 120 and the gate oxide layer 110 on both sides of the shallow trench isolation structure 110 are fused with the shallow trench isolation structure 101. The polycrystalline silicon material 120, the gate oxide layer 110, and the shallow trench isolation structure 101 after thermal oxidation are all made of silicon dioxide. Specifically, the process parameters of the rapid thermal oxidation process include: oxidation temperature of 600℃~800℃; oxidation time of 5min~10min; and oxygen flow rate of 5SLM~7SLM.

[0071] Preferably, during the rapid thermal oxidation process to fuse the polycrystalline silicon material 121 with the gate oxide layer 110, the oxidation temperature is 800°C, the oxidation time is 10 min, and the oxygen flow rate is 6 SLM.

[0072] Furthermore, after performing a rapid thermal oxidation process to fuse the polysilicon material 120 with the gate oxide layer 110, the fabrication method of the embedded flash memory device may further include: using a wet cleaning process to remove the gate oxide layer from the upper surface of the shallow trench isolation structure 110 of the peripheral logic region B and the surface of the substrate 100. At this time, a portion of the gate oxide layer 110 and the oxidized polysilicon material 120 will remain on both sides of the shallow trench isolation structure 110, and the portion of the gate oxide layer 110 and the oxidized polysilicon material 120 become part of the shallow trench isolation structure 110.

[0073] In this application, after removing the residual photoresist layer 210 on the peripheral logic region B, a rapid thermal oxidation process is used to fuse the polysilicon material 121 with the gate oxide layer 110, thereby eliminating the residual polysilicon material 121 of the floating gate. This also avoids the peeling defects of the residual polysilicon 121 of the floating gate after wet acid bath operation (wet cleaning process), and prevents the peeled-off residual polysilicon 121 of the floating gate from scratching the device surface, thus improving the device yield.

[0074] In this embodiment, after performing a rapid thermal oxidation process to fuse the polycrystalline silicon material with the gate oxide layer, the method for fabricating the embedded flash memory device may further include: using a photoresist as a mask to protect the peripheral logic region B, and performing an active region ion implantation process on the substrate of the storage region A.

[0075] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for fabricating an embedded flash memory device, characterized in that, include: A substrate is provided, the substrate including a storage region and a peripheral logic region, a plurality of shallow trench isolation structures are formed in the substrate, and stacked gate oxide, floating gate, ONO dielectric layer, control gate and first silicon nitride layer are formed on the substrate. A first sidewall structure, a second sidewall structure, a tunneling oxide layer, a select gate, and a select gate oxide layer are sequentially formed on the storage area. The first sidewall structure is located within the first silicon nitride layer. The second sidewall structure is located within the control gate and the ONO dielectric layer and covers a portion of the sidewall of the first sidewall structure. The tunneling oxide layer is located within the floating gate and the gate oxide layer and covers the remaining sidewalls of the second sidewall structure and the first sidewall structure. The tunneling oxide layer is U-shaped. The select gate fills the U-shaped space formed inside the tunneling oxide layer. The select gate oxide layer covers the surface of the select gate. At this time, the floating gates on both sides of the shallow trench isolation structure of the peripheral logic area exhibit a smile effect. A second silicon nitride layer and a photoresist layer are sequentially formed on the surface of the select gate oxide layer on the memory region and on the surface of the first silicon nitride layer on the peripheral logic region; Remove the photoresist layer on the peripheral logic region; Remove the second silicon nitride layer, the first silicon nitride layer, the control gate, the ONO dielectric layer, and the floating gate on the peripheral logic region. At this time, the polysilicon material of the floating gate remains in the gate oxide layer on both sides of the shallow trench isolation structure on the peripheral logic region. The residual photoresist layer on the peripheral logic region is removed using an ashing process; A wet cleaning process is performed on the shallow trench isolation structure and the gate oxide layer on the peripheral logic region. A rapid thermal oxidation process is performed to fuse the polycrystalline silicon material with the gate oxide layer.

2. The method for fabricating an embedded flash memory device according to claim 1, characterized in that, The process parameters of the rapid thermal oxidation process include: oxidation temperature of 600℃~800℃; oxidation time of 5min~10min; and oxygen flow rate of 5SLM~7SLM.

3. The method for fabricating an embedded flash memory device according to claim 2, characterized in that, During the rapid thermal oxidation process to fuse the polycrystalline silicon material with the gate oxide layer, the oxidation temperature is 800°C, the oxidation time is 10 min, and the oxygen flow rate is 6 SLM.

4. The method for fabricating an embedded flash memory device according to claim 1, characterized in that, The ONO dielectric layer comprises, from top to bottom, a top silicon oxide layer, an intermediate silicon nitride layer, and a bottom silicon oxide layer.

5. The method for fabricating an embedded flash memory device according to claim 4, characterized in that, The steps of removing the second silicon nitride layer, the first silicon nitride layer, the control gate, the ONO dielectric layer, and the floating gate on the peripheral logic region include: The second silicon nitride layer, the first silicon nitride layer, the control gate, and the top silicon oxide layer on the peripheral logic region are etched using a dry etching process. The intermediate silicon nitride layer on the peripheral logic region is etched using a wet etching process; The underlying silicon oxide layer and the floating gate on the peripheral logic region are etched using a dry etching process.

6. The method for fabricating an embedded flash memory device according to claim 1, characterized in that, The steps of forming the first sidewall structure, the second sidewall structure, the tunneling oxide layer, the select gate, and the select gate oxide layer in the storage area include: The first silicon nitride layer of the storage region is etched to form a first trench; A first sidewall structure is formed in the first trench, and the first sidewall structure covers the sidewall of the first trench; The control gate and the ONO dielectric layer on the bottom wall of the first trench are etched to form a second trench; A second sidewall structure is formed in the second trench, and the second sidewall structure covers part of the sidewall of the second trench; The floating gate and the gate oxide layer on the bottom wall of the second trench are etched to form the third trench; A tunneling oxide layer is formed, which covers the bottom and sidewalls of the third trench; A selection gate is formed, the selection gate filling the third trench; and, A select gate oxide layer is formed, which covers the select gate.

7. The method for fabricating an embedded flash memory device according to claim 1, characterized in that, After performing a rapid thermal oxidation process to fuse the polycrystalline silicon material with the gate oxide layer, the method for fabricating the embedded flash memory device further includes: Remove the gate oxide layer from the upper surface of the shallow trench isolation structure of the peripheral logic region and the surface of the substrate.

8. The method for fabricating an embedded flash memory device according to claim 1, characterized in that, After performing a rapid thermal oxidation process to fuse the polycrystalline silicon material with the gate oxide layer, the method for fabricating the embedded flash memory device further includes: An active region ion implantation process is performed on the substrate of the storage region.

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