Detection system, signal source and power supply device for integrated circuit devices

Abstract

The present disclosure provides a detection system, a signal source and a power supply device of an integrated circuit device. The signal source provides a plurality of supply voltages and a programming voltage to a plurality of semiconductor chip groups. The signal source includes a power supply device and a switch set. The power supply device is configured to generate an additional voltage, a plurality of base voltages and the programming voltage; the switch set is configured between the power supply device and the semiconductor chip groups, and converts the additional voltage and the base voltages into the supply voltages.

Description

Technical Field

[0001] This disclosure relates to a testing system, signal source, and power supply device for an integrated circuit device, and particularly to a testing system, signal source, and power supply device for an integrated circuit device that improves testing capabilities through power distribution. Background Technology

[0002] In the manufacturing process of integrated circuit devices, testing procedures are crucial steps to ensure the proper functioning of the device. In a typical testing procedure, automated test equipment (ATE) generates test signals. The ATE is coupled to a wafer prober station. The wafer prober station provides test signals to the device-under-test (DUT) via probe heads and probe cards. By measuring the DUT's response to the test signals (e.g., through measurement and / or quantization of the signals), it can be determined whether the DUT's operation and / or performance are normal.

[0003] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0004] One embodiment of this disclosure provides a signal source, including: a power supply device configured to generate an additional voltage, a plurality of base voltages and a programming voltage; and a set of switches configured between the power supply device and the semiconductor chip group to convert the additional voltage and the base voltages into a plurality of supply voltages.

[0005] In embodiments of this disclosure, the switch set includes a first switch coupled between the power supply device and the semiconductor chip group, and located on the path of the additional voltage transmission.

[0006] In embodiments of this disclosure, the switch set includes a plurality of second switches electrically coupled between the power supply device and the semiconductor chip group, and located on the transmission path of the base voltage.

[0007] In embodiments of this disclosure, the additional voltage is transmitted to the semiconductor chip group via the second switches.

[0008] In embodiments of this disclosure, when the second switches enter the conducting state, the power supply device provides a base current to each of the semiconductor chip groups, and when the first switch enters the conducting state, the power supply device provides an additional current to each of the semiconductor chip groups, the additional current being less than the base current.

[0009] In embodiments of this disclosure, the switch set further includes a plurality of third switches coupled between the power supply device and the complex semiconductor chip group, and located in the transmission path of the programming voltage.

[0010] In embodiments of this disclosure, when the third switches enter a conducting state, the power supply device provides a programming current to each of the semiconductor chip groups, the programming current being less than the additional current.

[0011] In embodiments of this disclosure, the programming current is equal to the base current.

[0012] In embodiments of this disclosure, the signal source further includes a controller electrically connected to the first switch, the second switch, and the third switch, wherein the first switch, the second switch, and the third switch are controlled by the controller to switch between an on state and an off state.

[0013] In embodiments of this disclosure, the power supply device includes: a first power supply configured to generate the additional voltage; a second power supply configured to generate the base voltages; and a third power supply configured to generate the programming voltage.

[0014] Another embodiment of this disclosure provides a detection system, including: a first chip; a second chip; and a power supply device; wherein the power supply device includes a first power supply configured to generate an additional current; and a second power supply configured to generate a first base current and a second base current; wherein one of the additional current and the first base current is provided to the first chip, and the additional current and the second base current are provided to the second chip.

[0015] In embodiments of this disclosure, the detection system further includes a first switch, wherein the additional voltage of the first power supply is transmitted to the first chip and the second chip via the first switch.

[0016] In embodiments of this disclosure, the detection system further includes a plurality of second switches, wherein the additional voltage of the first power supply and the first base current and the second base current of the second power supply are respectively transmitted to the first chip and the second chip via the second switches.

[0017] In embodiments of this disclosure, the detection system further includes a third power supply configured to generate a programming voltage for the first chip and the second chip.

[0018] In embodiments of this disclosure, the first chip further includes a first contact pad, the second chip further includes a second contact pad, and the programming voltage enters the first chip via the first contact pad and the programming voltage enters the second chip via the second contact pad.

[0019] In embodiments of this disclosure, the detection system further includes a plurality of third switches, through which the programming voltage of the third power supply is transmitted to the first chip and the second chip.

[0020] Another embodiment of this disclosure provides a power supply device, including: a first power supply providing an additional voltage; a second power supply providing a base voltage; and a third power supply configured to provide a programming voltage; wherein the first power supply is electrically coupled to the second power supply to cooperate in generating a combined current.

[0021] In embodiments of this disclosure, the power supply device further includes a first switch, wherein the additional voltage of the first power supply is transmitted to the first chip and the second chip via the first switch.

[0022] In embodiments of this disclosure, the power supply device further includes a plurality of second switches, wherein the additional voltage of the first power supply and the first base current and the second base current of the second power supply are respectively transmitted to the first chip and the second chip via the second switches.

[0023] In embodiments of this disclosure, the first chip further includes a first contact pad, the second chip further includes a second contact pad, and the programming voltage enters the first chip via the first contact pad and the programming voltage enters the second chip via the second contact pad.

[0024] In embodiments of this disclosure, the power supply device further includes a plurality of third switches, through which the programming voltage of the third power supply is transmitted to the first chip and the second chip respectively.

[0025] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, thereby enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0026] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the accompanying drawings in conjunction with the embodiments and claims. The same element symbols in the drawings refer to the same elements.

[0027] Figure 1 The diagram illustrates a detection system according to an embodiment of the present disclosure.

[0028] Figure 2 This is a top view illustrating the object under test according to an embodiment of this disclosure.

[0029] Figure 3 This is a schematic diagram illustrating the probe group and semiconductor chip of an embodiment of the present disclosure.

[0030] Figure 4 It is a circuit block, illustrating the transmission of electrical signals and response signals between the detection system and the object under test in an embodiment of this disclosure.

[0031] Figure 5 This is a circuit block diagram illustrating a signal source and a device under test according to an embodiment of this disclosure.

[0032] Figure 6 This is a circuit diagram illustrating a signal source and a device under test according to an embodiment of this disclosure.

[0033] Figure 7 This is a circuit block diagram illustrating a signal source and a device under test according to an embodiment of this disclosure.

[0034] Figure 8 This is a circuit diagram illustrating a signal source and a device under test according to an embodiment of this disclosure.

[0035] Figure 9 This is a circuit block diagram illustrating a signal source and a device under test according to an embodiment of this disclosure.

[0036] Figure 10 This is a circuit diagram illustrating a signal source and a device under test according to an embodiment of this disclosure.

[0037] [List of Labels in the Attached Image]

[0038] 10: Detection System

[0039] 20: Test object

[0040] 30: Detection System

[0041] 40: Controller

[0042] 100: Platform

[0043] 102: Bearing surface

[0044] 200_1: Semiconductor Chip Group

[0045] 210_2: Semiconductor Chip Group

[0046] 210: Semiconductor chip

[0047] 210_1: Semiconductor chip

[0048] 210_2: Semiconductor chip

[0049] 212: Contact pad

[0050] 212A: Contact pad

[0051] 212B: Contact pad

[0052] 220: Semiconductor wafer

[0053] 230: Pre-defined dividing line

[0054] 310: Ontology

[0055] 312: Test Card

[0056] 314: Probe Set

[0057] 316: Probe

[0058] 320: Signal Source

[0059] 325: Signal Analyzer

[0060] 330: Power supply unit

[0061] 320a: Signal source

[0062] 325: Signal Analyzer

[0063] 330a: Power supply unit

[0064] 330_1: First power supply

[0065] 330_2: Second power supply

[0066] 330_3: Third power supply

[0067] 340: Switch Set

[0068] 350: Control element

[0069] 3102: Mounting surface

[0070] D1: First Distance

[0071] D2: Second Distance

[0072] I1: Additional current

[0073] I2: Base current

[0074] I3: Programming current

[0075] S1: First switch

[0076] S2: Second switch

[0077] S3: Third switch

[0078] V1: Additional voltage

[0079] V2_1: Base voltage

[0080] V2_2: Base voltage

[0081] VDD: Supply voltage

[0082] VPP: Programming Voltage Detailed Implementation

[0083] The following description of this disclosure, accompanied by the accompanying drawings which are incorporated in and form a part of this specification, illustrates embodiments of this disclosure; however, this disclosure is not limited to these embodiments. Furthermore, the following embodiments may be appropriately integrated to complete another embodiment.

[0084] Terms such as “an embodiment,” “an embodiment,” “an exemplary embodiment,” “another embodiment,” and “another embodiment” indicate that the embodiments described in this disclosure may include specific features, structures, or characteristics; however, not every embodiment must include that specific feature, structure, or characteristic. Furthermore, repeated use of the phrase “in an embodiment” does not necessarily refer to the same embodiment, but may refer to the same embodiment.

[0085] To enable a full understanding of this disclosure, the following description provides detailed steps and structures. It is obvious that implementation of this disclosure does not limit the specific details known to those skilled in the art. Furthermore, known structures and steps are not detailed further to avoid unnecessarily limiting this disclosure. Preferred embodiments of this disclosure are detailed below. However, in addition to the detailed description, this disclosure can also be widely implemented in other embodiments. The scope of this disclosure is not limited to the detailed description, but is defined by the claims.

[0086] Furthermore, for ease of explanation, spatial relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another (other elements or features). These spatial relative terms are intended to encompass different orientations of the elements in use or operation, in addition to those shown in the figures as disclosed herein. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0087] Figure 1 A schematic diagram illustrating the detection system 10 of this disclosure is shown. (Refer to...) Figure 1 The testing system 10 includes a test object 20 and a testing system 30; the testing system 30 is configured to inspect the operation and / or performance of a plurality of semiconductor chips 210 in the test object 20, thereby determining whether the performance of each semiconductor chip 210 meets the design specifications.

[0088] Figure 2 A top view of the object under test 20 of this disclosure is shown. (Refer to...) Figure 2 The test object 20 may include a semiconductor wafer 220 (e.g., a silicon wafer), the surface of which is divided into multiple functional regions by intersecting predetermined dividing lines 230, and semiconductor chips 210 are respectively located within these functional regions; in other words, adjacent semiconductor chips 210 are separated by the predetermined dividing lines 230. Each semiconductor chip 210 may include one or more active elements (e.g., diodes, transistors), one or more passive elements (e.g., resistors, capacitors), and multiple patterned interconnect components for electrically coupling the active and passive elements; the active elements, passive elements, and interconnect components are formed in and / or on the surface of the semiconductor wafer 220 through a series of integrated circuit fabrication processes including doping, deposition, photolithography, etching, and planarization. Typically, the semiconductor chips 210 of the test object 20 have the same structure. Here, the semiconductor chip 210 is a memory, such as a dynamic random access memory including metal-oxide-semiconductor transistors and capacitors.

[0089] The semiconductor chip 210 has multiple contact pads 212 that can be electrically connected to different active components, passive components, or combinations of active and passive components within the semiconductor chip 210. Thus, when the device under test 20 is tested, the testing system 30 can measure the electrical properties of the active components, passive components, and circuits composed of active and passive components through the contact pads 212, thereby ensuring the quality of each semiconductor chip 210. The contact pads 212 are primarily made of metallic materials (e.g., copper, aluminum). Figure 2 In this configuration, the contact pads 212 of each semiconductor chip 210 are arranged in a straight line, with adjacent contact pads 212 spaced apart by a first distance D1. In some embodiments, the contact pads 212 may be arranged in a matrix or other shapes that facilitate detection by the detection system 30.

[0090] Reference Figure 1 Before the semiconductor chip 210 is fabricated but not yet individualized, the inspection system 30 inspects the test object 20 to identify semiconductor chips 210 that do not meet the requirements of the fabrication process. The individualization of the semiconductor chip 210 involves using a mechanical saw or laser to cut the semiconductor wafer 220 along a predetermined dicing line 230 to form multiple independent chips, each chip comprising at least one semiconductor chip 210. In other words, the inspection system 30 is primarily used to perform wafer-level testing on the test object 20.

[0091] Reference Figure 1 and Figure 3 The detection system 30 includes a body 310 and a test card 312. The body 310 may have a mounting surface 3102, and the test card 312 is fixed to the mounting surface 3102 of the body 310. In some embodiments, the test card 312 may be locked to the body 310 using screws (not shown). When the body 310 is driven by the controller 40 to translate (i.e., move in the XY direction) or lift (i.e., move in the Z-axis direction), the position of the test card 312 will change accordingly. The test card 312 is provided with multiple probe groups 314, each probe group 314 including multiple probes 316 (e.g., ...). Figure 3 (As shown). Probe 316 is primarily made of a conductive material, such as platinum, rhodium, palladium, silver, copper, iridium, or alloys thereof. The surface of the test card 312 may be provided with conductive lines (not shown) for electrically connecting corresponding probes 316 in probe groups 314. For example, the conductive lines may allow the leftmost probe 316 in each probe group 314 to form an electrical connection. In other words, the test card 312, in addition to housing the probes 316, can also be used to transmit electrical signals. In some embodiments, the test card 312 includes a circuit board.

[0092] Reference Figure 3The probe 316 can be a vertical probe or a cantilever probe. Vertical probes primarily provide elastic force through bending, and are characterized by their small size, ease of assembly, and replacement. Cantilever probes have a small tip distance, making them suitable for electrical testing of semiconductor chips 210 with narrow-pitch contact pads 212. In some embodiments, the number of probe groups 314 is equal to the number of semiconductor chips 210 on the test object 20, and the number of probes 316 can be equal to the number of contact pads 212, thereby effectively reducing testing time. Furthermore, in each probe group 312, the second distance D2 between the tips of two adjacent probes 316 is not less than the first distance D1 between two adjacent contact pads 212, thereby avoiding the transmission of erroneous test signals to components or circuits within the semiconductor chip 210, which could lead to incorrect test results or even damage to components within the semiconductor chip 210.

[0093] Reference Figure 1 The detection system 10 may further include a platform 100 having a support surface 102 facing the probe card 312. Before detection, the distance between the tip of the probe 316 and the support surface 102 of the platform 100 is greater than the height of the object under test 20 to facilitate placement of the object under test 20. The platform 100 and the detection system 30 may be electrically connected to the controller 40. After the semiconductor chip 210 is fabricated, the object under test 20 is mounted on the support surface 102 of the platform 100 in preparation for testing. When testing the object under test 20, the controller 40 first moves the platform 100 or the detection system 30 horizontally to align the probe 316 of the probe card 312 with the contact pad 212 of the semiconductor chip 210. Then, the controller 40 can lower the probe card 312 of the detection system 30 to bring the probe 316 into contact with the corresponding contact pad 212. In some embodiments, after the probe 316 and contact pad 212 are aligned, the controller 40 can bring the probe 316 into contact with the contact pad 212 by vertically raising the platform 100. The controller 40 may be configured to have a height detection function to ensure that the probe 316 and contact pad 212 make contact with each other, but the probe 316 does not press against the position of the contact pad 212, thereby avoiding damage to the semiconductor chip 210 or breakage of the probe 316.

[0094] Reference Figure 3 and Figure 4 After the probe 316 contacts the corresponding contact pad 212, the detection system 30 generates multiple electrical signals S, which can be transmitted to the semiconductor chip 210 through the probe 316 to perform electrical detection on the components and / or circuits composed of multiple components in the semiconductor chip 210; wherein, the parameters and contents of the detection of components or circuits in the semiconductor chip 210 can be adjusted according to design or usage requirements.

[0095] Reference Figure 4 The detection system 30 includes at least one signal source 320 that generates at least one electrical signal S. For example, the signal source 320 may be placed in the body 310 of the detection system 30 and electrically connected to the test card 312 via wires (not shown); the electrical signal S transmitted to the test card 312 may be transmitted to the probe 316 via conductive lines on its surface and therein. When the semiconductor chip 210 is a semiconductor memory (e.g., dynamic random access memory), the electrical signal generated by the signal source 320 may include instructions suitable for performing write and read tests on the semiconductor chip 210.

[0096] Reference Figure 4 The detection system 30 further includes a signal analyzer 325 that receives a response signal Sr provided by the semiconductor chip 210, wherein the response signal Sr can represent the response of the components or circuits within the semiconductor chip 210 to the electrical signal S provided by the detection system 30. The detection system 30 can determine the basic electrical properties of each semiconductor chip 210 by analyzing the response signal. After completing the basic electrical property testing of the semiconductor chip 210, the detection system 10 can also mark defective semiconductor chips 210 to save on packaging and cost testing costs. In some embodiments, some probes 316 in the probe group 314, in addition to transmitting the electrical signal S to the semiconductor chip 210, can also transmit the response signal Sr provided by the semiconductor chip 210 to the detection system 30.

[0097] Reference Figure 4 The electrical signal generated by the signal source 320 may further include a power signal for driving the semiconductor chip 210; specifically, the signal source of the detection system 30 may include one or more power supply devices 330 to generate the voltage and current required by the semiconductor chip 210 when performing write and read tests.

[0098] Figure 5 This is a functional block diagram illustrating the signal source 320 and the object under test 20 according to an embodiment of the present disclosure; Figure 6 A circuit diagram illustrating the signal source 320 and the object under test 20 according to an embodiment of this disclosure is provided. (Refer to...) Figure 5 and Figure 6 The test object 20 includes two semiconductor chip groups 200_1 and 200_2, each of which may include a plurality of semiconductor chips 210; in some embodiments, all semiconductor chip groups 200_1 and 200_2 have the same number of semiconductor chips 210.

[0099] Reference Figure 5 and Figure 6The signal source 320 can be configured to generate two supply voltages VDD_1 and VDD_2 and a programming voltage VPP. When the semiconductor chip 210 is a dynamic random access memory, the supply voltages VDD_1 and VDD_2 are used to start / drive the semiconductor chip 210, and the programming voltage VPP is used to provide voltage to the word lines of the semiconductor chip 210. Further, when the semiconductor chip 210 is a fourth-generation double-data-rate synchronous dynamic random access memory (DDR4 SDRAM), the supply voltages VDD_1 and VDD_2 are 1.2 volts, and the programming voltage VPP is 2.5 volts.

[0100] Reference Figure 5 and Figure 6 The signal source 320 may include a power supply device 330, a switch set 340, and a control element 350. The power supply device 330 is configured to generate an additional voltage V1 and multiple base voltages V2_1 and V2_2. The switch set 340 is disposed between the power supply device 330 and the semiconductor chip groups 200_1 and 200_2, and is controlled by the control element 350 to convert the additional voltage V1 and base voltages V2_1 and V2_2 generated by the power supply device 330 into supply voltages VDD_1 and VDD_2.

[0101] Reference Figure 6 The switch assembly 340 includes a first switch S1 and multiple second switches S2; the number of second switches S2 is equal to the number of semiconductor chips 210. The second switches S2 are coupled between the power supply device 330 and the semiconductor chips 210. Specifically, each second switch S2 is connected in series with one semiconductor chip 210 to form a switching circuit; multiple switches composed of multiple second switches S2 and multiple semiconductor chips 210 are connected in parallel with open circuits. When a second switch S2 receives a control signal generated by the control element 350 and enters the conducting state, a basic current I2 enters each semiconductor chip 210 for electrical testing. Furthermore, the first switch S1 is coupled between the power supply device 330 and the semiconductor chips 210. When the first switch S1 receives a control signal provided by the control element 350 and enters the conducting state, the semiconductor devices 210 are connected in parallel, and the first switch S1 is connected in series between the power supply device 330 and the multiple semiconductor devices 210 connected in parallel.

[0102] Furthermore, referring to Figure 6When the first switch S1 and the second switch S2 are simultaneously turned on, the additional current I1 and the base current I2 flow together through the second switch S2 into the semiconductor chip 210 for electrical testing; wherein, the base current I2 is greater than the additional current I1. For example, the additional current I1 can be 100 milliamperes and the base current I2 can be 200 milliamperes; in other words, the power supply device 330 can provide 300 milliamperes of current to the semiconductor chip 210, thereby starting the semiconductor chip 210.

[0103] In addition, refer to Figure 6 The signal source 320 can also generate a programming voltage VPP for each semiconductor chip 210; when the programming voltage VPP is applied to the semiconductor chip 210, a programming current I3 enters the semiconductor chip 210. The programming current I3 can be, for example, 100 milliamperes.

[0104] With the aforementioned circuit configuration, the control element 350 can determine whether each semiconductor chip 210 can operate normally by changing the state of the first switch S1 and each of the second switches S2. For example, if the semiconductor chip 210 can still perform write and read tests even when the power supply device 330 does not provide the programming voltage VPP to the semiconductor chip 210, it can be determined that the components and circuits in the semiconductor chip 210 are damaged.

[0105] Figure 7 This invention discloses a functional block diagram of the signal source 320 and the object under test 20. Figure 8 The circuit diagram of the signal source 320 and the object under test 20 in this embodiment is shown as an example. (Refer to...) Figure 7 and Figure 8 The test object 20 includes two semiconductor chip groups 200_1 and 200_2, each of which may include a plurality of semiconductor chips 210; in some embodiments, semiconductor chip groups 200_1 and 200_2 have the same number of semiconductor chips 210.

[0106] Reference Figure 7 and Figure 8 The signal source 320 may include a power supply device 330, a switch assembly 340, and a control element 350. The power supply device 330 is configured to generate an additional voltage V1, multiple base voltages V2_1 and V2_2, and a programming voltage VPP; wherein the programming voltage VPP, the additional voltage V1, and the base voltages V2_1 and V2_2 are transmitted to the switch assembly 340 from different output terminals of the power supply device 330.

[0107] Reference Figure 7 and Figure 8A switch assembly 340 is configured between the power supply device 330 and the semiconductor chip groups 200_1 and 200_2, and transmits at least one of the programming voltage VPP, the additional voltage V1, and the base voltages V2_1 and V2_2 to the semiconductor chip groups 200_1 and 200_2 according to the control signal generated by the control element 350. Specifically, the switch assembly 340 includes a first switch S1, a plurality of second switches S2, and a plurality of third switches S3. When the second switch S2 is in the on state, the base current I2 enters the semiconductor chip 210 through the first contact pad 212A; in addition, when the first switch S1 is in the on state, the additional current I1 enters the semiconductor chip 210 through the first contact pad 212A.

[0108] Furthermore, when the first switch S1 and the second switch S2 are simultaneously turned on, the additional current I1 and the basic current I2 flow together through the second switch S2 and through the first contact pad 212A into the semiconductor chip 210, thereby activating the semiconductor chip 210. Additionally, when the third switch S3 is turned on, the programming current I3 flows through a second contact pad 212B into the semiconductor chip 210.

[0109] By changing the states of the first switch S1 and each of the second switches S2, it can be determined whether each semiconductor chip 210 can operate normally. For example, if the semiconductor chip 210 can still perform write and read tests even when the power supply device 320 does not provide the programming voltage VPP to the semiconductor chip 210, it can be determined that the components and circuits in the semiconductor chip 210 are damaged.

[0110] Figure 9 This invention discloses a functional block diagram illustrating the signal source 320a and the object under test 20. Figure 10 The circuit diagram of the signal source 320a and the object under test 20 of this embodiment is shown as an example. (Refer to...) Figure 9 and Figure 10 The tested object 20 includes two semiconductor chips 210_1 and 210_2.

[0111] Signal source 320a may include a power supply device 330a, a switch assembly 340, and a control element 350. Power supply device 330a includes a first power supply 330_1, a second power supply 330_2, and a third power supply 330_3. The first power supply 330_1 is configured to generate an additional voltage V1, the second power supply 330_2 is configured to generate two base voltages V2_1 and V2_2, and the third power supply 330_3 is configured to generate a programming voltage VPP. The switch assembly 340 is disposed between power supply device 330a and semiconductor chip groups 200_1 and 200_2, and is controlled by control element 350 to convert the additional voltage V1 and base voltages V2_1 and V2_2 generated by power supply device 330a into supply voltages VDD_1 and VDD_2.

[0112] Reference Figure 9 and Figure 10 The switch assembly 340 includes a first switch S1 and a plurality of second switches S2; wherein the number of second switches S2 is equal to the number of semiconductor chip groups 200_1 and 200_2. The second switches S2 are coupled between the power supply device 330a and the semiconductor chips 210_1 and 210_2. Specifically, each second switch S2 is connected in series with one semiconductor chip 210_1 and 210_2 to form a switching circuit; the plurality of switches consisting of multiple second switches S2 and multiple semiconductor chips 210_1 and 210_2 are connected in parallel with open circuits. When the second switch S2 receives a control signal generated by the control element 350 and enters the conducting state, the base current I2 enters each semiconductor chip 210_1 and 210_2 for electrical testing. In addition, the first switch S1 is coupled between the power supply 340 and the semiconductor chips 210_1 and 210_2. When the first switch S1 receives a control signal provided by the control element 350 and enters the conducting state, the semiconductor chips 210_1 and 210_2 are connected in parallel. The first switch S1 is connected in series between the power supply 330a and the multiple semiconductor chips 210_1 and 210_2 connected in parallel.

[0113] Furthermore, when the first switch S1 and the second switch S2 simultaneously enter the conducting state, the additional current I1 and the basic current I2 form a combined current, which flows through the second switch S2 into the semiconductor chips 210_1 and 210_2 for electrical testing; wherein, the basic current I2 is greater than the additional current I1. For example, the additional current I1 can be 100 milliamperes, and the basic current I2 can be 200 milliamperes. In other words, the power supply device 330a can provide 300 milliamperes of current to the semiconductor chip 210, thereby starting the semiconductor chip 210.

[0114] In addition, the third power supply 330_3 of the signal source 320 generates a programming voltage VPP for semiconductor chips 210_1 and 210_2; when the third switch S3 enters the conducting state, the third power supply 330_3 applies the programming voltage VPP to semiconductor chips 210_1 and 210_2, and the programming current I3 enters each semiconductor chip group 200_1 and 200_2, wherein the programming current I3 may be, for example, 100 milliamperes.

[0115] With the aforementioned circuit configuration, the control element 350 can determine whether each semiconductor chip 210 can operate normally by changing the state of the first switch S1 and each of the second switches S2. For example, if the power supply device 330a does not provide the programming voltage VPP to the semiconductor chips 210_1 and 210_2, and if the semiconductor chips 210_1 and 210_2 can still perform write and read tests, then it can be determined that the components and circuits in the semiconductor chips 210_1 and 210_2 are damaged.

[0116] This disclosure provides a signal source for providing multiple supply voltages and a programming voltage to multiple groups of semiconductor chips. The signal source includes a power supply device and a switch assembly. The power supply device is configured to generate an additional voltage, multiple base voltages, and the programming voltage; the switch assembly is disposed between the power supply device and the groups of semiconductor chips and is used to convert the additional voltage and the base voltages into the supply voltage.

[0117] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0118] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A signal source for providing a test command and multiple power signals required for electrical testing of multiple groups of semiconductor chips, the signal source comprising: A power supply device is configured to generate an additional voltage, a plurality of base voltages and a programming voltage, the additional voltage and the plurality of base voltages serving as a plurality of power signals required for electrical testing of the plurality of semiconductor chip groups, and the programming voltage serving as a test command required for electrical testing of the plurality of semiconductor chip groups. as well as A set of switches is configured between the power supply device and the plurality of semiconductor chip groups. in, This switch set couples the plurality of base voltages to the plurality of semiconductor chip groups for electrical testing, or The switch set allows the additional voltage, along with the multiple base voltages, to be coupled to the multiple semiconductor chip groups for electrical testing.

2. The signal source of claim 1, wherein the switch set includes a first switch coupled between the power supply device and the plurality of semiconductor chip groups and located on the transmission path of the additional voltage.

3. The signal source of claim 2, wherein the switch set includes a plurality of second switches electrically coupled between the power supply device and the plurality of semiconductor chip groups, and located on the transmission path of the plurality of base voltages.

4. The signal source of claim 3, wherein the additional voltage is transmitted to the plurality of semiconductor chip groups via the plurality of second switches.

5. The signal source of claim 4, wherein when the plurality of second switches enter a conducting state, the power supply device provides a base current to each of the semiconductor chip groups, and when the first switch enters a conducting state, the power supply device provides an additional current to each of the semiconductor chip groups, the additional current being less than the base current.

6. The signal source of claim 5, wherein the switch set further comprises a plurality of third switches coupled between the power supply device and the plurality of semiconductor chip groups and located in the transmission path of the programming voltage.

7. The signal source of claim 6, wherein when the plurality of third switches enter a conducting state, the power supply device provides a programming current to each of the semiconductor chip groups, the programming current being less than the additional current.

8. The signal source of claim 7, wherein the programming current is equal to the base current.

9. The signal source of claim 6 further includes a controller electrically connected to the first switch, the plurality of second switches and the plurality of third switches, wherein the first switch, the plurality of second switches and the plurality of third switches are controlled by the controller to switch between the on state and an off state.

10. The signal source of claim 1, wherein the power supply device comprises: A first power supply is configured to generate the additional voltage; A second power supply, configured to generate the plurality of base voltages; as well as A third power supply is configured to generate the programmed voltage.

11. A detection system, comprising: The first chip; A second chip; A power supply device is used to provide multiple power signals required by the first chip and the second chip during electrical testing. The power supply device includes: A first power supply, configured to generate an additional current; and A second power supply, configured to generate a first base current and a second base current, wherein the additional current, the first base current, and the second base current serve as the plurality of power signals required for electrical testing of the first chip and the second chip; and A set of switches is configured between the power supply device and the first chip, and between the power supply device and the second chip. in, The switch assembly allows the first base current and the second base current to be respectively applied to the first chip and the second chip for electrical testing of the first chip and the second chip; or The switch assembly allows the first base current to enter the first chip, the second base current to enter the second chip, and the additional current to enter the first chip and the second chip, in order to perform electrical tests on the first chip and the second chip.

12. The detection system of claim 11 further includes a first switch, wherein the additional current from the first power supply is transmitted to the first chip and the second chip via the first switch.

13. The detection system of claim 12 further includes a plurality of second switches, wherein the additional current of the first power supply and the first base current and the second base current of the second power supply are respectively transmitted to the first chip and the second chip via the plurality of second switches.

14. The detection system of claim 11 further includes a third power supply configured to generate a programming voltage for the first chip and the second chip.

15. The detection system of claim 14, wherein the first chip further includes a first contact pad, the second chip further includes a second contact pad, and the programming voltage enters the first chip through the first contact pad and the programming voltage enters the second chip through the second contact pad.

16. The detection system of claim 15 further includes a plurality of third switches, wherein the programming voltage of the third power supply is transmitted to the first chip and the second chip via the plurality of third switches.

17. A power supply device for providing a test command and multiple power signals required for detecting electrical testing of a semiconductor chip, the power supply device comprising: A primary power supply provides an additional voltage; A second power supply provides a base voltage, the additional voltage and the base voltage serving as the plurality of power signals required when the semiconductor chip is subjected to electrical testing; as well as A third power supply is configured to provide a programming voltage that is the test command required when the semiconductor chip is electrically tested; in, The second power supply provides the base voltage to the semiconductor chip independently for electrical testing, or the first power supply and the power supply work together to provide the base voltage and the additional voltage to the semiconductor chip for electrical testing.

18. The power supply device of claim 17, further comprising a first switch, wherein the additional voltage of the first power supply is transmitted to the first chip and the second chip via the first switch.

19. The power supply device of claim 18, further comprising a plurality of second switches, wherein the additional voltage of the first power supply and the base voltage of the second power supply are respectively transmitted to the first chip and the second chip via the plurality of second switches.

20. The power supply device of claim 18, wherein the first chip further includes a first contact pad, the second chip further includes a second contact pad, and the programming voltage enters the first chip via the first contact pad and the programming voltage enters the second chip via the second contact pad.

21. The power supply device of claim 17 further includes a plurality of third switches, wherein the programming voltage of the third power supply is transmitted to the first chip and the second chip respectively via the plurality of third switches.

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