A method for controlling input power, an electronic device, and a storage medium

Abstract

Embodiments of the present application provide a kind of input power control method, electronic equipment and storage medium, related to data storage technical field, can be adaptively set the input power of memory.The method comprises: obtaining the current read-write frequency of memory, the current read-write frequency is used to characterize the data read-write times to be reached in unit time in current time by the memory;Based on current read-write frequency, determine the target input power corresponding to the current read-write frequency from the corresponding relationship between read-write frequency and input power;The target input power is the input power needed when the memory uses the current read-write frequency to read and write data;The current input power of the memory is set to target input power.

Description

Technical Field

[0001] This application relates to the field of data storage technology, and in particular to a method for controlling input power, an electronic device, and a storage medium. Background Technology

[0002] With the development of internet technology, the application of memory has become increasingly widespread. As is well known, memory is set with a fixed power consumption at the factory, and in practical applications, the memory can only perform data read and write operations within this fixed power range.

[0003] However, in practical applications, the actual input power required for the memory to achieve the number of read / write operations per second (IOPS) may not match the fixed input power mentioned above; therefore, how to adaptively set the input power of the memory has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] This application provides an input power control method, electronic device, and storage medium that can adaptively set the input power of the memory.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, embodiments of this application provide an input power control method, the method comprising: obtaining the current read / write frequency of a memory, the current read / write frequency being used to characterize the number of data read / write operations that the memory needs to perform per unit time at the current moment; determining a target input power corresponding to the current read / write frequency from the correspondence between the read / write frequency and input power based on the current read / write frequency; the target input power being the input power required by the memory when reading / writing data using the current read / write frequency; and setting the current input power of the memory as the target input power.

[0007] In one possible implementation, the aforementioned correspondence specifically includes a first correspondence between multiple read / write frequencies and multiple input powers; determining the target input power corresponding to the current read / write frequency from the first correspondence based on the current read / write frequency includes: determining a target read / write frequency from multiple read / write frequencies based on the current read / write frequency; determining the target input power from the first correspondence based on the target read / write frequency; the target read / write frequency is one of the multiple read / write frequencies or the multiple read / write frequencies closest to the current read / write frequency.

[0008] Compared to schemes where the input power of the memory is always the initial input power during data read / write operations, the input power control method provided in this application is as follows: based on the correspondence between multiple read / write counts and multiple input powers, the target input power corresponding to the current read / write count is determined, and the current input power of the memory is set as the target input power, so that the memory uses the target read / write count to perform data read / write operations under the target input power; thereby realizing that the memory adaptively sets its own input power according to its current read / write count; and solving the problem that the current read / write count of the memory does not match the input power.

[0009] In one possible implementation, the aforementioned correspondence specifically includes: a second correspondence between multiple read / write frequency intervals and multiple input powers; the determination of the target input power corresponding to the current read / write frequency from the second correspondence based on the current read / write frequency includes: determining the target read / write frequency interval to which the current read / write frequency belongs from the multiple read / write frequency intervals based on the current read / write frequency; and determining the target input power from the aforementioned second correspondence based on the target read / write frequency interval.

[0010] Compared to the approach of setting each read / write operation and its corresponding input power in the aforementioned correspondence, the input power control method provided in this application specifically includes a correspondence between multiple read / write frequency ranges and multiple input powers. Then, it is only necessary to determine the target read / write frequency range to which the current read / write operation of the memory belongs, and determine the input power corresponding to that target read / write frequency range as the target input power. It is not necessary to compare the current read / write operation with each read / write operation in the aforementioned correspondence, thus improving the efficiency of determining the target input power.

[0011] In one possible implementation, the aforementioned correspondence specifically includes: a third correspondence between multiple read / write frequency intervals and multiple input power intervals; the determination of the target input power corresponding to the current read / write frequency from the third correspondence based on the current read / write frequency includes: obtaining a target function; the target function is used to characterize the linear relationship between the read / write frequency in the target read / write frequency interval and the input power in the target power interval; wherein, the target read / write frequency interval is the read / write frequency interval to which the current read / write frequency belongs among the multiple read / write frequency intervals; the target power interval is the input power interval corresponding to the target read / write frequency interval; and the target input power is determined according to the current read / write frequency and the target function.

[0012] Compared to schemes that assign each read / write operation and its corresponding input power to the aforementioned correspondence, this application provides an input power control method that, by setting the aforementioned correspondence, specifically includes a correspondence between multiple read / write frequency intervals and multiple input power intervals, and determines the target input power based on the current read / write operation count and an objective function. This objective function characterizes the linear relationship between the read / write operation counts within the read / write frequency intervals and the input power within the input power intervals. This eliminates the need to compare the current read / write operation count with each read / write operation count in the aforementioned correspondence, thus improving the efficiency of determining the target input power.

[0013] In one possible implementation, before obtaining the target function, the method further includes: determining the target read / write frequency interval to which the current read / write frequency belongs from the plurality of read / write frequency intervals; determining the target power interval corresponding to the target read / write frequency interval based on the third correspondence mentioned above; and determining the target function based on the target read / write frequency interval and the target power interval.

[0014] In one possible implementation, before determining the target input power corresponding to the current read / write frequency from the correspondence between read / write frequency and input power based on the current read / write frequency, the method further includes: receiving the aforementioned correspondence sent by the controller.

[0015] In one possible implementation, the minimum input power in the above correspondence is greater than or equal to the minimum input power supported by the memory; the maximum input power in the above correspondence is less than or equal to the maximum input power supported by the memory.

[0016] This application embodiment ensures that the minimum input power in the above-mentioned correspondence is greater than or equal to the minimum input power supported by the memory, and the maximum input power in the above-mentioned correspondence is less than or equal to the maximum input power supported by the memory. In other words, the target input power determined in this application is always kept within the supported range of the memory, avoiding the risk of the memory being burned out due to excessive input power. It also ensures that the input power of the memory is always above the minimum input power or starts at the minimum input power, avoiding the risk of the memory failing to start due to insufficient input power.

[0017] Secondly, embodiments of this application provide an input power control device, the control method comprising: an acquisition unit, a determination unit, and a setting unit; the acquisition unit is used to acquire the current read / write frequency of the memory, the current read / write frequency being used to characterize the number of data read / write operations the memory needs to perform per unit time at the current moment; the determination unit is used to determine the target input power corresponding to the current read / write frequency from the correspondence between read / write frequency and input power based on the current read / write frequency; the target input power is the input power required by the memory when reading / writing data using the current read / write frequency; the configuration unit module is used to set the current input power of the memory to the target input power.

[0018] In one possible implementation, the determining unit is used to determine a target read / write frequency from multiple read / write frequencies based on the current read / write frequency; and to determine a target input power from a first correspondence relationship based on the target read / write frequency; the correspondence relationship specifically includes a first correspondence relationship between multiple read / write frequencies and multiple input powers; the target read / write frequency is one of the multiple read / write frequencies or the multiple read / write frequencies that are closest to the current read / write frequency.

[0019] In one possible implementation, the determining unit is used to determine the target read / write frequency interval to which the current read / write frequency belongs from multiple read / write frequency intervals of the second correspondence based on the current read / write frequency; wherein, the correspondence specifically includes: a second correspondence between multiple read / write frequency intervals and multiple input powers; and to determine the target input power from the second correspondence according to the target read / write frequency interval.

[0020] In one possible implementation, the acquisition unit is used to acquire a target function; the target function is used to characterize the linear relationship between the read / write frequency in the target read / write frequency range and the input power in the target power range; wherein, the target read / write frequency range is the read / write frequency range to which the current read / write frequency belongs among multiple read / write frequency ranges; the target power range is the input power range corresponding to the target read / write frequency range; the determination unit is used to determine the target input power based on the current read / write frequency and the target function, wherein the above correspondence specifically includes: the correspondence between multiple read / write frequency ranges and multiple input power ranges.

[0021] In one possible implementation, the determining unit is used to determine the target read / write frequency interval to which the current read / write frequency belongs from multiple read / write frequency intervals; and to determine the target power interval corresponding to the target read / write frequency interval based on the third correspondence; the determining unit is also used to determine the objective function based on the target read / write frequency interval and the target power interval.

[0022] In one possible implementation, the acquisition unit is also used to receive the correspondence sent by the controller.

[0023] In one possible implementation, the minimum input power in the correspondence is greater than or equal to the minimum input power supported by the memory; the maximum input power in the correspondence is less than or equal to the maximum input power supported by the memory.

[0024] Thirdly, embodiments of this application provide an electronic device, which includes a first controller and a memory. The first controller includes a processor coupled to the memory. The memory is used to store computer program code, which includes computer instructions. The processor is used to execute the method described in any one of the first aspects and their possible implementations.

[0025] Fourthly, embodiments of this application provide a memory for storing computer instructions, wherein the memory is the memory described in the first aspect above.

[0026] Fifthly, embodiments of this application provide a memory, which includes multiple storage areas, a second controller, and an input interface; the memory is used to store computer instructions, and the second controller is used to execute the method described in any one of the first aspects and their possible implementations.

[0027] In a sixth aspect, embodiments of this application provide a computer-readable storage medium having computer instructions stored thereon, which, when executed on a computing device, cause the computing device to perform the method described in any one of the first aspect and its possible implementations.

[0028] In a seventh aspect, embodiments of this application provide a computer program product that, when run on a computer, causes the computer to perform the method described in any one of the first aspects and its possible implementations.

[0029] It should be understood that the beneficial effects achieved by the second to seventh aspects of the technical solutions and the corresponding possible implementations of the embodiments of this application can be referred to the above-described technical effects of the first aspect and its corresponding possible implementations, and will not be repeated here. Attached Figure Description

[0030] Figure 1 A schematic diagram of an electronic device provided in an embodiment of this application;

[0031] Figure 2 This is a schematic diagram of the internal structure of a memory provided in an embodiment of this application;

[0032] Figure 3 This is a schematic diagram of the hardware structure of a first control device provided in an embodiment of this application;

[0033] Figure 4 This is a schematic flowchart of an input power control method provided in an embodiment of this application;

[0034] Figure 5 This is a schematic flowchart of another input power control method provided in an embodiment of this application;

[0035] Figure 6 A schematic flowchart of another input power control method provided in this application embodiment;

[0036] Figure 7 This is a schematic diagram of the structure of an input power control device provided in an embodiment of this application. Detailed Implementation

[0037] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0038] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0039] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple read / write frequencies refer to two or more read / write frequencies; multiple input powers refer to two or more input powers.

[0040] When a memory is shipped from the factory, the manufacturer sets an initial input power for it. Subsequent data read and write operations are performed at this initial power, which is fixed.

[0041] However, with the continuous development of internet technology, the business needs of the internet industry are becoming increasingly complex. In this scenario, the frequency of data read / write operations required by the memory may vary significantly at different times. Therefore, a fixed input power for the memory is not suitable for this scenario. Specifically, when the initial input power of the memory can support more input / output operations per second (IOPS) than the current IOPS required by the memory, some of the initial input power will be used for extra work, resulting in low actual utilization of the initial input power and wasted resources. When the initial input power of the memory can support fewer IOPS than the current IOPS required by the memory, insufficient input power will cause a large backlog of data read / write requests in the memory, which may lead to data loss in severe cases. Therefore, how to adaptively set the input power of the memory has become a technical problem that urgently needs to be solved by those skilled in the art.

[0042] For example, suppose the initial input power of the memory is 9W, which can support 2500 IOPS. If the memory currently requires 1000 IOPS, and the corresponding input power for 1000 IOPS is 6W, then using the initial input power for data read / write operations at 1000 IOPS would result in a waste of 3W of input power. If the memory currently requires 5000 IOPS, and the corresponding input power for 5000 IOPS is 11W, then using the initial input power for data read / write operations would cause an additional 2500 data read / write requests to accumulate in the memory and not be processed in a timely manner, since the initial input power can only support 2500 IOPS.

[0043] Based on this, embodiments of this application provide an input power control method, which includes the following steps:

[0044] S1, Based on the current read / write frequency, determine the target input power corresponding to the current read / write frequency from the correspondence between read / write frequency and input power; wherein, the target input power is the input power required by the memory when using the current read / write frequency to read and write data; S2, set the current input power of the memory to the target input power.

[0045] The above control method enables adaptive setting of the memory's input power.

[0046] First, some concepts involved in the input power control method and computing device provided in the embodiments of this application will be explained.

[0047] Input power: refers to the power absorbed by the device. For memory, input power equals the product of input voltage and input current.

[0048] The input power control method provided in this application embodiment can be applied to, for example... Figure 1 The electronic device shown includes a first controller 101 and a memory 102.

[0049] In one implementation, the first controller 101 determines the correspondence between read / write frequency and input power, and sends this correspondence to the memory 102. Specifically, it obtains a preset correspondence between read / write frequency and input power by the user in the first controller 101 and sends this correspondence to the memory 102. The memory 102 receives the correspondence sent by the first controller 101 and determines the target input power corresponding to the current read / write frequency based on this correspondence. Then, it sets the current input power of the memory 102 as the target input power. The memory 102 can be a device with storage capabilities, such as a solid-state drive (SSD).

[0050] In another implementation, the first controller 101 determines the correspondence between read / write frequency and input power, and obtains the current read / write frequency of the memory 102; then, based on the correspondence, it determines the target input power corresponding to the current read / write frequency; and sends the target input power to the memory 102. Finally, the memory 102 sets the current input power as the target input power.

[0051] The first controller 101 and the memory 102 are integrated into the same electronic device, which can be a server, computer, laptop, or other electronic device with computing capabilities. The first controller 101 can be a processor or a baseboard management controller in the aforementioned computing device.

[0052] Optionally, the first controller 101 and the memory 102 described above may also be devices in different electronic devices.

[0053] The internal structure diagram of the memory 102 described above is shown below. Figure 2 As shown in the memory 102, the memory 102 includes: an input interface 201, a second controller 202, and storage areas 1-N.

[0054] The input interface 201 is used to receive the correspondence between the read / write frequency and the input power sent by the control device (e.g., the first controller 101), or to receive the target input power sent by the first controller 101. The input interface 201 can be a physical interface or a virtual interface.

[0055] The second controller 202 is used to determine the target input power corresponding to the current read / write frequency of the memory 102 based on the correspondence between the read / write frequency and the input power received by the input interface 201; and set the current input power of the memory 102 as the target input power; or the second controller 202 sets the target input power received by the input interface 201 as the current input power of the memory 102.

[0056] Optionally, the second controller 202 implements the input power control method provided in this application embodiment by reading the instructions stored in storage areas 1-N.

[0057] Storage areas 1-N are used to store data, such as an area corresponding to a Rank, Device, BankGroup, Bank, Row, or Column in an SSD.

[0058] For example, Figure 3 This is a control device provided in the embodiments of this application, such as a hardware schematic diagram of the first controller 101 described above. The control device includes a processor 301, a memory 302, and a network interface 303.

[0059] The processor 301 may include one or more processing units, such as a central processing unit (CPU), an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural network processing unit (NPU). These different processing units may be independent devices or integrated into one or more processors.

[0060] The processor 301 may also include a memory for storing instructions and data. In some embodiments, the memory in the processor 301 is a cache memory. This memory can store instructions or data that the processor 301 has just used or that are used repeatedly. If the processor 301 needs to use the instruction or data again, it can retrieve it directly from the memory.

[0061] It should be noted that the processor 301 mentioned above is a processor independent of the memory 102, and Figure 2 The second controller 202 is a device inside the memory 102.

[0062] The memory 302 includes, but is not limited to, random access memory (RAM), read-only memory (ROM), flash memory, or optical memory.

[0063] Network interface 303 is a wired interface (port), such as an FDDI or GE interface. Alternatively, network interface 303 can be a wireless interface. It should be understood that network interface 303 includes multiple physical ports.

[0064] Optionally, the control device also includes a bus 304, through which the processor 301, memory 302, and network interface 303 are typically interconnected, or in other ways.

[0065] It should be noted that the apparatus for implementing the input power control method provided in the embodiments of this application can be as described above. Figure 2 The second controller 202 in the memory 102 shown.

[0066] The input power control method provided in the embodiments of this application, such as Figure 4 As shown, the method includes S410-S440.

[0067] S410, The correspondence between the read / write frequency and the input power sent by the receiving control device.

[0068] The aforementioned read / write frequency is used to characterize the number of data read / write operations that the memory performs per unit of time. For example, if the control device sends 1,000 data read / write requests to the memory per second, then the read / write frequency of the memory is 1,000 times / second; that is, the current IOPS of the memory is 1,000.

[0069] It should be understood that the input power required by a memory varies depending on its read / write frequency; for example, a memory with a read / write frequency of 1000 times / second requires 6W of input power, while a memory with a read / write frequency of 2000 times / second requires 7W of input power.

[0070] The aforementioned correspondence between read / write frequencies and input power specifically includes: a first correspondence between multiple read / write frequencies and multiple input powers; wherein, this correspondence between multiple read / write frequencies and multiple input powers is a one-to-one correspondence. It can be understood that any one of the multiple read / write frequencies, taking a read / write frequency of 1000 times / second as an example, corresponds to an input power of 6W, which represents the power currently required by the memory. Specifically, as shown in Table 1, when the memory's IOPS is 1000, the actual input power required by the memory is 6W; that is, the input power corresponding to a read / write frequency of 1000 times / second is 6W. When the memory's IOPS is 3000, the actual input power required by the memory is 9W; that is, the input power corresponding to a read / write frequency of 3000 times / second is 9W. When the memory's IOPS is 5000, the actual input power required by the memory is 12W; that is, the input power corresponding to a read / write frequency of 5000 times / second is 12W.

[0071] Table 1

[0072]

[0073] It should be noted that the minimum input power in the first correspondence mentioned above is greater than or equal to the minimum input power supported by the memory; the maximum input power in the above correspondence is less than or equal to the maximum input power supported by the memory. In other words, the target input power determined in this application always remains within the range supported by the memory.

[0074] It should be noted that the correspondence between the multiple read / write frequencies and multiple input powers can be preset by the user in the first controller 101; or it can be determined by the first controller 101 based on the historical read / write frequencies of the memory; or it can be obtained by the memory based on neural network model training; or it can be obtained from other devices. Specifically, this application embodiment does not limit the method for determining the correspondence between the multiple read / write frequencies and multiple input powers.

[0075] S420: Obtain the current read / write frequency of the memory.

[0076] The aforementioned current read / write frequency is used to characterize the number of data read / write operations that the memory needs to achieve per unit time at the current moment (e.g., the memory's IOPS is 1000).

[0077] It should be understood that the current read / write frequency of the aforementioned memory is determined by the number of data read / write requests received by the memory at the current moment.

[0078] S430. Based on the current read / write frequency, determine the target input power corresponding to the current read / write frequency from the correspondence between read / write frequency and input power.

[0079] The target input power mentioned above refers to the input power required by the memory when performing data read and write operations at the current read / write frequency. The specific correspondence is shown in Table 1 above; when the current read / write frequency of the memory is 1000 times / second, the target input power is 6W.

[0080] It should be understood that the above-mentioned correspondence between read / write frequency and input power specifically includes: a first correspondence between multiple read / write frequencies and multiple input powers. Therefore, the above-mentioned S430 essentially involves: determining the target input power corresponding to the current read / write frequency from the first correspondence based on the acquired current read / write frequency of the memory (hereinafter referred to as: current read / write frequency). This specifically includes: steps 1 and 2.

[0081] Step 1: Based on the current read / write frequency, determine the target read / write frequency from multiple read / write frequencies in the first correspondence.

[0082] The target read / write frequency is one of the multiple read / write frequencies mentioned above, or it is the one among the multiple read / write frequencies that is closest to the current read / write frequency.

[0083] Step 2: Find the corresponding input power based on the target read / write frequency, and then determine the input power as the target input power.

[0084] For example, assume that the current read / write frequency of the memory is 1500 times / second; the correspondence between multiple read / write IOPS and multiple input power is shown in Table 1 above; at this time, the current read / write frequency is closest to the read / write frequency of 1000 times / second in Table 1, therefore, the read / write frequency of 1000 times / second is taken as the target read / write frequency; the input power of 6W corresponding to the read / write frequency of 1000 times / second is determined as the target input power.

[0085] S440. Set the current input power of the memory to the target input power.

[0086] The above-mentioned S440 sets the current input power of the memory to the target input power so that the memory can use the target read / write frequency to read and write data at the target input power.

[0087] Optionally, the execution entity of the above S410-S430 is the first controller 101, which sends the determined target input power to the memory so that the memory executes the above S440.

[0088] Compared to schemes where the input power of the memory is always the initial input power during data read / write operations, the input power control method provided in this application is as follows: based on the correspondence between multiple read / write frequencies and multiple input powers, the target input power corresponding to the current read / write frequency is determined, and the current input power of the memory is set as the target input power, so that the memory uses the target read / write frequency for data read / write at the target input power; thereby realizing that the memory adaptively sets its own input power according to its current read / write frequency; and solving the problem of the current read / write frequency of the memory not matching the input power.

[0089] It should be noted that since the read / write frequency of the memory is constantly changing in practical applications, if all the changing read / write frequencies are set in this correspondence, the amount of data for multiple read / write frequencies in the first correspondence will be large, which will increase the time required to determine the target input power. Furthermore, there will still be a period where the actual power required by the memory does not match the input power, resulting in wasted resources. Based on this, this application provides two implementation methods, as follows:

[0090] In one implementation, this application provides another method for controlling input power, such as... Figure 5 As shown, the method includes: S510-S550.

[0091] S510, The correspondence between the read / write frequency and the input power sent by the receiving control device.

[0092] It should be noted that the description of read / write frequency is similar to that in S410. For the specific description of read / write frequency in S510, please refer to the relevant description of S410 above, which will not be repeated here.

[0093] The correspondence between the above-mentioned read / write frequency and input power specifically includes: a second correspondence between multiple read / write frequency intervals and multiple input powers; wherein, any two read / write frequency intervals do not intersect, any two input powers are different, and there is a one-to-one correspondence between the multiple read / write frequency intervals and multiple input powers, that is, the input powers corresponding to any two read / write frequency intervals are different.

[0094] For example, as shown in Table 2 below, the correspondence between multiple read / write frequency ranges and multiple input powers is as follows: When the read / write frequency range is 0 times / second to 2000 times / second, the memory requires 6W of input power; when the read / write frequency range is 2001 times / second to 4000 times / second, the memory requires 9W of input power; when the read / write frequency range is 4001 times / second to 6000 times / second, the memory requires 12W of input power.

[0095] Table 2

[0096] 1 0 times / second - 2000 times / second 6W 2 2001 times / second - 4000 times / second 9W 3 4001 times / second - 6000 times / second 12W

[0097] It should be noted that the minimum input power in the second correspondence mentioned above is greater than or equal to the minimum input power supported by the memory; the maximum input power in the correspondence mentioned above is less than or equal to the maximum input power supported by the memory. In other words, the target input power determined in this application always remains within the range supported by the memory.

[0098] It should be noted that the correspondence between the multiple read / write frequency ranges and the multiple input powers can be preset by the user in the first controller 101; or it can be determined by the first controller 101 based on the historical read / write frequency of the memory; or it can be obtained by the memory based on neural network model training; or it can be obtained from other devices. Specifically, this application embodiment does not limit the method for determining the correspondence between the multiple read / write frequencies and the multiple input powers.

[0099] S520: Obtain the current read / write frequency of the memory.

[0100] It should be noted that the implementation of S520 is similar to that of S420. For a detailed description of S520, please refer to the relevant description of S420 above. It will not be repeated here.

[0101] S530. Based on the current read / write frequency, determine the target read / write frequency range to which the current read / write frequency belongs from multiple read / write frequency ranges.

[0102] It should be noted that the aforementioned multiple read / write frequency ranges are the multiple read / write frequency ranges included in the aforementioned second correspondence; the aforementioned target read / write frequency range is the read / write frequency range to which the current read / write frequency of the memory belongs, which is included in the multiple read / write frequency ranges.

[0103] For example, assuming the current read / write frequency of the memory is 1500 times / second, the above correspondence is shown in Table 2 above; then, since 1500 times / second belongs to the read / write frequency range of 0 times / second to 2000 times / second, the read / write frequency range of 0 times / second to 2000 times / second is determined as the target read / write frequency range.

[0104] S540. Determine the target input power from the second correspondence based on the target read / write frequency range.

[0105] For example, based on the example in S530 above; when the current read / write frequency of the memory is 1500 times / second, the read / write frequency range of 0 times / second to 2000 times / second is determined as the target read / write frequency range; then, the input power of 6W corresponding to the target read / write frequency range is determined as the target input power.

[0106] S550: Set the current input power of the memory to the target input power.

[0107] It should be noted that the implementation of S550 is similar to that of S440. For a detailed description of S550, please refer to the relevant description of S440 above. It will not be repeated here.

[0108] Compared to the approach of setting each read / write frequency and its corresponding input power in the aforementioned correspondence, the input power control method provided in this application, by setting the aforementioned correspondence, specifically includes: receiving the correspondence between multiple read / write frequency intervals and multiple input powers; then, determining the target read / write frequency interval to which the current read / write frequency of the memory belongs; and determining the input power corresponding to the target read / write frequency interval as the target input power. This eliminates the need to compare the current read / write frequency with each read / write frequency in the aforementioned correspondence, thereby improving the efficiency of determining the target input power and further improving the efficiency of setting the memory input power.

[0109] In another implementation, embodiments of this application provide a method for controlling input power, such as... Figure 6 As shown, the method includes: S610-S670.

[0110] S610, The correspondence between the read / write frequency and the input power sent by the receiving control device.

[0111] It should be noted that the description of the read / write frequency mentioned above is similar to the description of the read / write frequency in S410. For the specific description of the read / write frequency in S610, please refer to the relevant description of S410 above, which will not be repeated here.

[0112] The above correspondence specifically includes: a third correspondence between multiple read / write frequency intervals and multiple input power intervals; any two read / write frequency intervals do not intersect, any two input power intervals are different, and there is a one-to-one correspondence between the multiple read / write frequency intervals and multiple input power intervals, that is, any two read / write frequency intervals correspond to different input power intervals.

[0113] For example, as shown in Table 3 below, the correspondence between multiple read / write frequency ranges and multiple input power ranges is as follows: When the read / write frequency range is 0 times / second to 3000 times / second, the required input power range for the memory is 6-8W, that is, the input power range corresponding to the read / write frequency range of 0 times / second to 3000 times / second is 6-8W. When the read / write frequency range is 3001 times / second to 6000 times / second, the required input power range for the memory is 9-11W, that is, the input power range corresponding to the read / write frequency range of 3001 times / second to 6000 times / second is 9-11W. When the read / write frequency range is 6001 times / second to 9000 times / second, the required input power range for the memory is 12-14W, that is, the input power range corresponding to the read / write frequency range of 6001 times / second to 9000 times / second is 12-14W.

[0114] Table 3

[0115] 1 0 times / second - 3000 times / second 6-8W 2 3001 times / second - 6000 times / second 9-11W 3 6001 times / second - 9000 times / second 12-14W

[0116] It should be noted that the minimum input power in the third correspondence mentioned above is greater than or equal to the minimum input power supported by the memory; the maximum input power in the above correspondence is less than or equal to the maximum input power supported by the memory. In other words, the target input power determined in this application always remains within the range supported by the memory.

[0117] It should be noted that the correspondence between the multiple read / write frequency ranges and the multiple input power ranges mentioned above can be preset by the user in the first controller 101; or it can be determined by the first controller 101 based on the historical read / write frequency ranges of the memory; or it can be obtained by the memory based on neural network model training; or it can be obtained from other devices. Specifically, this application embodiment does not limit the method for determining the correspondence between the multiple read / write frequency ranges and the multiple input power ranges.

[0118] S620: Obtain the current read / write frequency of the memory.

[0119] It should be noted that the implementation of S620 is similar to that of S420. For a detailed description of S620, please refer to the relevant description of S420 above. It will not be repeated here.

[0120] S630. Determine the target read / write frequency range to which the current read / write frequency belongs from multiple read / write frequency ranges.

[0121] It should be noted that the above-mentioned multiple read / write frequency ranges are the multiple read / write frequency ranges included in the above correspondence; the above-mentioned target read / write frequency range is the read / write frequency range to which the current read / write frequency of the memory belongs among the multiple read / write frequency ranges.

[0122] For example, assuming the current read / write frequency of the memory is 1500 times / second, the above correspondence is shown in Table 3 above; then, since 1500 times / second belongs to the read / write frequency range of 0 times / second to 3000 times / second, the read / write frequency range of 0 times / second to 3000 times / second is determined as the target read / write frequency range.

[0123] S640. Determine the target power range corresponding to the target read / write frequency range based on the third correspondence.

[0124] The input power range corresponding to the target read / write frequency range is the target power range; the multiple input power ranges include the target power range, that is, the input power range corresponding to the target read / write frequency range among the multiple input power ranges is determined as the target power range.

[0125] For example, assuming the current frequency of the memory is 1500 times / second, the third correspondence mentioned above is shown in Table 3. Since 1500 times / second falls within the read / write frequency range of 0 to 3000 times / second, this range is determined as the target read / write frequency range. Then, the memory determines the input power range of 6-8W corresponding to the target read / write frequency range of 0 to 3000 times / second in Table 3 as the target input power range.

[0126] S650. Determine the objective function based on the target read / write frequency range and the target power range.

[0127] It should be noted that the above objective function is used to characterize the linear relationship between the read / write frequency in the target read / write frequency range and the input power in the target power range.

[0128] It should be understood that the above objective function is a linear function, that is: the basic function of the objective function is y = ax + b, where x is the read / write frequency, y is the input power, a represents the slope of the linear function, and b is a constant.

[0129] For example, assuming the target read / write frequency range is 0 to 3000 times / second and the target power range is 6-8W, when the target read / write frequency is 0, the target power range is 6, so b = 6. When the target read / write frequency is 3000, the target power is 8W, so a = 1 / 1500. Therefore, the objective function can be obtained as y = (x / 1500) + 6.

[0130] It should be noted that the objective function is determined after the memory receives the third correspondence sent by the control device. After the objective function is determined, it will be stored in the memory and retrieved directly from the memory when used later.

[0131] S660. Determine the target input power based on the current read / write frequency and the objective function.

[0132] It should be noted that the target power range mentioned above includes the target input power.

[0133] For example, based on the example in S650 above, the objective function is y = (x / 1500) + 6; when the current read / write frequency of the memory is 3000 times / second, the above target input power is 8W.

[0134] S670, Set the current input power of the memory to the target input power.

[0135] It should be noted that the implementation of S670 is similar to that of S440. For a detailed description of S670, please refer to the relevant description of S440 above. It will not be repeated here.

[0136] Compared to the approach of setting each read / write frequency and its corresponding input power within the aforementioned correspondence, the input power control method provided in this application, by setting the aforementioned correspondence, specifically includes: receiving the correspondence between multiple read / write frequency intervals and multiple input power intervals, and determining a target function based on the correspondence to characterize the linear relationship between the number of read / write operations in the read / write frequency intervals and the input power in the input power intervals; then, determining the target input power based on the current read / write frequency and the target function. This eliminates the need to compare the current read / write frequency with each read / write frequency in the aforementioned correspondence, thereby improving the efficiency of determining the target input power and further improving the efficiency of setting the memory input power.

[0137] Accordingly, this application provides an input power control device, hereinafter referred to as a control device, which is used to execute the various steps in the above-described method for determining the inspection strategy. This application can divide the control device into functional modules based on the above method example. For example, each function can be divided into its own functional modules, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module. The module division in this application is illustrative and only represents a logical functional division; other division methods may be used in actual implementation.

[0138] When dividing each functional unit according to its corresponding function. Figure 7 A schematic diagram of a possible structure of the control device involved in the above embodiments is shown. For example... Figure 7 As shown, the control device includes: an acquisition unit 701, a determination unit 702, and a setting unit 703.

[0139] The acquisition unit 701 is used to acquire the current number of read and write operations of the memory; for example, it executes step S420 in the above method embodiment.

[0140] The determining unit 702 is used to determine the target input power corresponding to the current read / write frequency from the correspondence between the read / write frequency and the input power based on the current read / write frequency; for example, by executing step S430 in the above method embodiment.

[0141] The setting unit 703 is used to set the current input power of the memory to the target input power; for example, by performing step S440 in the above method embodiment.

[0142] Optionally, the determining unit 702 determines the target read / write frequency from multiple read / write frequencies based on the current read / write frequency, and determines the target input power from the first correspondence according to the target read / write frequency; for example, performing steps 1-2 in step S430 of the above method embodiment.

[0143] Optionally, the determining unit 702 is used to determine the target read / write frequency range to which the current read / write frequency belongs from multiple read / write frequency ranges based on the current read / write frequency; for example, by executing step S530 in the above method embodiment.

[0144] The aforementioned determining unit 702 is further configured to determine the target input power from the second correspondence based on the target read / write frequency range; for example, by executing step S540 in the above method embodiment.

[0145] Optionally, the acquisition unit 701 described above is used to acquire the objective function.

[0146] The aforementioned determining unit 702 is used to determine the target input power based on the current read / write frequency and the target function; for example, by executing step S660 in the above method embodiment.

[0147] Optionally, the determining unit 702 is used to determine the target read / write frequency interval to which the current read / write frequency belongs from multiple read / write frequency intervals; and to determine the target power interval corresponding to the target read / write frequency interval based on the third correspondence; for example, to execute steps S630-S640 in the above method embodiment.

[0148] The aforementioned determining unit 702 is used to determine the target function based on the target read / write frequency range and the target power range; for example, by executing step S650 in the above method embodiment.

[0149] Optionally, the acquisition unit 701 is used to receive the correspondence between multiple read / write counts and multiple input powers sent by the first controller; for example, to execute step S410 in the above method embodiment.

[0150] Each unit of the above-mentioned control device can also be used to perform other actions in the above-mentioned method embodiments. All relevant content of each step involved in the above-mentioned method embodiments can be referred to the functional description of the corresponding functional unit, and will not be repeated here.

[0151] Some or all of the steps in the determining unit 702 and the setting unit 703 can be achieved through... Figure 2 The second controller 202 executes the code in storage areas 1-N. Some or all of the steps in the aforementioned acquisition unit 701 can be implemented through... Figure 2 The input interface 201 is implemented in the middle.

[0152] Optionally, some or all of the steps in the determining unit 702 described above can be performed by... Figure 1 The first controller 101 executes the code implementation in the memory 102.

[0153] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software programs, implementation can be, in whole or in part, in the form of a computer program product. This computer program product includes one or more computer instructions. When these computer instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center integrating one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., digital video discs (DVDs)), or semiconductor media (e.g., solid-state drives (SSDs)).

[0154] Through the above description of the embodiments, those skilled in the art will clearly understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. The specific working process of the system, device, and unit described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0155] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0156] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0157] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0158] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as flash memory, portable hard disk, read-only memory, random access memory, magnetic disk, or optical disk.

[0159] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for controlling input power, characterized in that, include: The current read / write frequency of the memory is obtained, which represents the number of data read / write operations that the memory needs to perform per unit time at the current moment; the current read / write frequency is determined by the number of data read / write requests received by the memory at the current moment. Based on the current read / write frequency, the target input power corresponding to the current read / write frequency is determined from the correspondence between read / write frequency and input power; The target input power is the input power required by the memory when it reads and writes data using the current read / write frequency; The current input power of the memory is set as the target input power; the memory includes: an input interface, a second controller, and a storage area; the input interface is used to receive the correspondence sent by the first controller; the second controller is used to determine the target input power of the memory based on the correspondence received by the input interface; the second controller implements the control method based on reading the instructions stored in the storage area; the storage area is used to store data, including an area corresponding to Rank, Device, BankGroup, Bank, Row, or Column; The memory is an SSD.

2. The method according to claim 1, characterized in that, The correspondence specifically includes a first correspondence between multiple read / write frequencies and multiple input powers; The step of determining the target input power corresponding to the current read / write frequency from the first correspondence based on the current read / write frequency includes: determining the target read / write frequency from the plurality of read / write frequencies based on the current read / write frequency; The target input power is determined from the first correspondence based on the target read / write frequency; the target read / write frequency is one of the plurality of read / write frequencies or the one of the plurality of read / write frequencies that is closest to the current read / write frequency.

3. The method according to claim 1, characterized in that, The correspondence specifically includes: a second correspondence between multiple read / write frequency ranges and multiple input powers; The step of determining the target input power corresponding to the current read / write frequency from the second correspondence based on the current read / write frequency includes: Based on the current read / write frequency, determine the target read / write frequency interval to which the current read / write frequency belongs from the plurality of read / write frequency intervals; The target input power is determined from the second correspondence based on the target read / write frequency range.

4. The method according to claim 1, characterized in that, The correspondence specifically includes: a third correspondence between multiple read / write frequency intervals and multiple input power intervals; the step of determining the target input power corresponding to the current read / write frequency from the third correspondence based on the current read / write frequency includes: Obtain the objective function; the objective function is used to characterize the linear relationship between the read / write frequency in the target read / write frequency range and the input power in the target power range; wherein, the target read / write frequency range is the read / write frequency range to which the current read / write frequency belongs among the plurality of read / write frequency ranges; the target power range is the input power range corresponding to the target read / write frequency range; The target input power is determined based on the current read / write frequency and the objective function.

5. The method according to claim 4, characterized in that, Before obtaining the target function, the method further includes: Determine the target read / write frequency range to which the current read / write frequency belongs from the plurality of read / write frequency ranges; Based on the third correspondence, the target read / write frequency range is determined to correspond to the target power range; The objective function is determined based on the target read / write frequency range and the target power range.

6. According to claim 1 The method described in any one of the following five aspects is characterized in that, Before determining the target input power corresponding to the current read / write frequency from the correspondence between read / write frequency and input power based on the current read / write frequency, the method further includes: The correspondence is sent by the receiver controller.

7. The method according to claim 6, characterized in that, The minimum input power in the correspondence is greater than or equal to the minimum input power supported by the memory; The maximum input power in the correspondence is less than or equal to the maximum input power supported by the memory.

8. An electronic device, characterized in that, The device includes a first controller and a memory, the first controller including a processor coupled to the memory; the memory is used to store computer program code, the computer program code including computer instructions; the processor is used to perform the method as described in any one of claims 1 to 7.

9. A memory, characterized in that, The memory is used to store computer instructions, and the memory is as described in claim 1. In the memory of 7.

10. A memory, characterized in that, It includes multiple storage areas, a second controller, and an input interface; the memory is used to store computer instructions, and the second controller is used to execute as described in claim 1. The method described in any one of the 7.

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