A highly compressed temporal FFT system and FFT method

Abstract

This invention discloses a highly time-compressed FFT system and method, including a state machine, registers, an address generation module, a butterfly unit, and a modulus calculation module. The butterfly unit preprocesses the data to be processed written to the register when the period count reaches a threshold, and stores the preprocessed result at the original storage location of the data to be processed. It then performs butterfly operations based on the data address and the twiddle factor address to obtain the FFT calculation result. This invention performs preprocessing synchronously when writing the data to be processed, stores the preprocessing result in the original location, generates an address for the preprocessing result, and directly uses the preprocessing result in subsequent butterfly operations. This overlaps some of the computation timing and data transmission timing, reducing the overall time consumption and thus better meeting the requirements of real-time computing.

Description

Technical Field

[0001] This invention relates to the field of FFT chip design, and more specifically to a highly time-compressed FFT system and FFT method. Background Technology

[0002] N-point radix-4 FFT in parallel structure Each butterfly unit operates in parallel, processing N data points per cycle. Therefore, computation must wait for all data to be received before starting. However, the sequential FFT (Fast Fourier Transform) uses only one butterfly unit, processing only 4 data points per cycle, requiring... It takes several cycles to complete one level of calculation, and there are a total of log4N levels. However, it still waits for all the data to be received before starting the calculation, and it only starts to calculate the modulus after all the butterfly operations are completed.

[0003] Traditional sequential FFT structures consume the fewest resources, but the computation cycle is inversely proportional to the resource consumption, leading to a linear increase in time consumption, which cannot meet the real-time data processing requirements of modern radar. Traditional methods simply reduce resource consumption but increase the corresponding computation time, and overall, they do not offer a significant change compared to parallel structures. In fact, their computation cycles are often too long to meet the demands of real-time computing. Summary of the Invention

[0004] To address the aforementioned shortcomings in the existing technology, this invention provides a highly compressed temporal FFT system and FFT method that solves the problem that the computation cycle of existing sequential FFT structures is too long to meet the requirements of real-time computation.

[0005] To achieve the above-mentioned objectives, the technical solution adopted by this invention is as follows:

[0006] A highly compressed timing FFT system is provided, comprising:

[0007] The state machine is used to respond to the start pulse signal, enter the data reading state, and count the data to be processed and the cycle count; when the count result N of the amount of data to be processed reaches the set value, the data reading state stops and the address generation module is started; the generated data address is adjusted according to the cycle count result;

[0008] The register is used to write the data to be processed when the state machine is in the data read state, and to store the data generated by the address generation module, the butterfly unit and the modulus calculation module;

[0009] The address generation module is used to generate data addresses from the data obtained by preprocessing the butterfly unit, and to generate rotation factor addresses;

[0010] The butterfly unit is used to preprocess the data to be processed written to the register when the period count value reaches the threshold, and store the preprocessing result in the original storage location of the data to be processed; butterfly operation is performed according to the data address and the rotation factor address to obtain the FFT calculation result;

[0011] The modulus module is used to perform modulus calculations on the FFT results to obtain the modulus value.

[0012] Furthermore, the first number received from the register Starting with the first data to be processed, the four adders of the butterfly unit calculate the sum of the a-th data and the first data. The result of adding the real and imaginary parts of each of the a-th data to be processed, and the result of adding the real and imaginary parts of the a-th data to be processed. The result of subtracting the real and imaginary parts of each of the a-th data to be processed is obtained, and thus the result of subtracting the real and imaginary parts of the a-th data to be processed is obtained. The result of adding and subtracting the a-th data to be processed; the result of adding and subtracting the a-th data to be processed; and the result of adding and subtracting the a-th data to be processed. The results of adding and subtracting the data to be processed are respectively sent back to the two original data addresses for storage;

[0013] Furthermore, the address generation module generates four data addresses in parallel. The initial value of the first data address is 0, and the initial value of the second data address is... The initial value of the third data address is The initial value of the fourth data address is C represents the number of stages required for a radix-4 FFT to compute N data points, with an initial value of 1; the initial value of the cycle count I is 1; the data address and the cycle count I are incremented by 1 in each clock cycle.

[0014] When the value of the fourth data address is N-1, the value of stage C is incremented by 1;

[0015] when At that time, according to the formula:

[0016] add1 * =add4 z +1

[0017]

[0018]

[0019]

[0020] Adjust the generated data address; where add1 * This indicates the address of the first data path after adjustment; add2 *This indicates the adjusted address of the second data path; add3 * This indicates the adjusted third data address; add4 * This indicates the adjusted fourth data address; add4 z This indicates the latest value of the fourth data address before the adjustment;

[0021] When the value of level C is 4, all addresses are initialized, and the address generation of the data to be processed in the current batch is completed.

[0022] Furthermore, the number of butterfly units is 1, and a butterfly operation is performed once per clock cycle. Each butterfly operation uses four data addresses and generates four complex number outputs. The formula for a single radix-4 butterfly operation by the butterfly unit is:

[0023] x1_o=(x1_i+x2_i)+(x3_i+x4_i)

[0024]

[0025]

[0026]

[0027] in j is the imaginary unit, k is the rotation factor, π is pi, n = 1, 2, 3; x1_o is the first complex output; x2_o is the second complex output; x3_o is the third complex output; x4_o is the fourth complex output; x1_i is the a-th data to be processed; x2_i is the... The number of data to be processed; x3_i is the number of... The nth data to be processed; x4_i is the nth data. There are a data points to be processed; (x1_i + x2_i) represents the a-th data point and the data point to be processed. The result of adding the a-th data to be processed; (x1_i-x2_i) represents the sum of the a-th data to be processed and the a-th data. The result of subtracting the nth data to be processed; (x3_i+x4_i) represents the nth... The data to be processed and the first The result of adding the n data to be processed; (x3_i-x4_i) represents the nth data. The data to be processed and the first The result of subtracting the data to be processed.

[0028] Furthermore, the set value for the FFT calculation data count result N is 64.

[0029] A highly compressed time series FFT method is provided, which includes the following steps:

[0030] S1. Write the data to be processed into the register, count the written data, and perform periodic counting.

[0031] S2. Continuously monitor the cycle count value. When the cycle count value reaches the threshold, preprocess the data to be processed written to the register and store the preprocessing result in the original storage location of the data to be processed.

[0032] S3. Continuously monitor the count result N of the amount of data to be processed. When it reaches the set value, stop writing the data to be processed.

[0033] S4. Generate data addresses and twitch factor addresses from the data preprocessed from the butterfly unit.

[0034] S5. Perform butterfly operations based on the data address and twitch factor address to obtain the FFT calculation result;

[0035] S6. Perform a modulus operation on the FFT calculation results to obtain the modulus value.

[0036] Furthermore, the threshold corresponding to the period count value in step S2 is... Where C represents the number of stages required to compute N data points using a radix-4 FFT, with an initial value of 1; the initial value of the cycle count I is 1, and the cycle count I increments by 1 in each clock cycle.

[0037] Furthermore, the specific method for preprocessing the data to be written to the register in step S2 is as follows:

[0038] Received from register the first Starting with the first data to be processed, the four adders of the butterfly unit calculate the sum of the a-th data and the first data. The result of adding the real and imaginary parts of each of the a-th data to be processed, and the result of adding the real and imaginary parts of the a-th data to be processed. The result of subtracting the real and imaginary parts of each of the a-th data to be processed is obtained, and thus the result of subtracting the real and imaginary parts of the a-th data to be processed is obtained. The result of adding and subtracting the a-th data to be processed; the result of adding and subtracting the a-th data to be processed; and the result of adding and subtracting the a-th data to be processed. The results of adding and subtracting the data to be processed are respectively sent back to the two original data addresses for storage;

[0039] Furthermore, the specific method for step S4 is as follows:

[0040] The data preprocessed from the butterfly unit generates four data addresses. The initial value of the first data address is 0, and the initial value of the second data address is... The initial value of the third data address is The initial value of the fourth data address is

[0041] when At that time, according to the formula:

[0042] add1 * =add4 z +1

[0043]

[0044]

[0045]

[0046] Adjust the generated data address; where add1 * This indicates the address of the first data path after adjustment; add2 * This indicates the adjusted address of the second data path; add3 * This indicates the adjusted third data address; add4 * This indicates the adjusted fourth data address; add4 z This indicates the latest value of the fourth data address before the adjustment;

[0047] When the value of level C is 4, all addresses are initialized, and the calculation of the current batch of data to be processed is completed.

[0048] Furthermore, the specific method for the butterfly operation in step S5 is as follows:

[0049] According to the formula:

[0050] x1_o=(x1_i+x2_i)+(x3_i+x4_i)

[0051]

[0052]

[0053]

[0054] Performing a single butterfly operation yields four complex outputs: x1_o (first channel), x2_o (second channel), x3_o (third channel), and x4_o (fourth channel), which together form the FFT result. j is the imaginary unit, k is the rotation factor, π is pi, n = 1, 2, 3; x1_i is the a-th data to be processed; x2_i is the... The number of data to be processed; x3_i is the number of... The nth data to be processed; x4_i is the nth data. There are a data points to be processed; (x1_i + x2_i) represents the a-th data point and the data point to be processed. The result of adding the a-th data to be processed; (x1_i-x2_i) represents the sum of the a-th data to be processed and the a-th data. The result of subtracting the nth data to be processed; (x3_i+x4_i) represents the nth... The data to be processed and the first The result of adding the n data to be processed; (x3_i-x4_i) represents the nth data. The data to be processed and the first The result of subtracting the data to be processed.

[0055] The beneficial effects of this invention are as follows:

[0056] 1. This invention performs preprocessing simultaneously when writing data to be processed, and stores the preprocessing results in the original location. It generates addresses for the preprocessing results and directly uses the preprocessing results in the subsequent butterfly operation process. This overlaps part of the calculation timing and data transmission timing, reduces the overall time consumed, and thus better meets the requirements of real-time computing.

[0057] 2. This invention can perform data preprocessing when the first N / 2 data are input, reducing the use of adders by half, saving resources and improving efficiency. Attached Figure Description

[0058] Figure 1 This is a block diagram of the structure of this FFT system;

[0059] Figure 2 A schematic diagram of the address generation module;

[0060] Figure 3 This is a schematic diagram of a butterfly-shaped unit;

[0061] Figure 4 To obtain a schematic diagram of the module;

[0062] Figure 5 This is a schematic diagram of the overall calculation of a 16-point radix-4 FFT;

[0063] Figure 6 This is the overall timing diagram of the present invention. Detailed Implementation

[0064] The specific embodiments of the present invention are described below to enable those skilled in the art to understand the present invention. However, it should be understood that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the present invention as defined and determined by the appended claims. All inventions utilizing the concept of the present invention are protected.

[0065] like Figure 1 As shown, this highly compressed timing FFT system includes:

[0066] A state machine is used to respond to a start pulse signal, enter a data reading state, and count the data to be processed and perform cycle counting. When the count result N of the amount of data to be processed reaches a set value, the data reading state stops and the address generation module is started. The generated data address is adjusted according to the cycle counting result. The state machine is equivalent to a controller, used to control the operation of other devices.

[0067] The register (Memory Unit) is used to write data to be processed when the state machine is in the data read state, and to store data generated by the address generation module, butterfly unit, and modulo module; the register can be written to via the SPI interface.

[0068] The address generation module is used to generate data addresses from the data obtained by preprocessing the butterfly unit, and to generate rotation factor addresses;

[0069] The butterfly unit is used to preprocess the data to be processed written to the register when the period count value reaches the threshold, and store the preprocessing result in the original storage location of the data to be processed; butterfly operation is performed according to the data address and the rotation factor address to obtain the FFT calculation result;

[0070] The modulus module is used to perform modulus calculations on the FFT results to obtain the modulus value.

[0071] Received from register the first Starting with the first data to be processed, the four adders of the butterfly unit calculate the sum of the a-th data and the first data. The result of adding the real and imaginary parts of each of the a-th data to be processed, and the result of adding the real and imaginary parts of the a-th data to be processed. The result of subtracting the real and imaginary parts of each of the a-th data to be processed is obtained, and thus the result of subtracting the real and imaginary parts of the a-th data to be processed is obtained. The result of adding and subtracting the a-th data to be processed; the result of adding and subtracting the a-th data to be processed; and the result of adding and subtracting the a-th data to be processed. The results of adding and subtracting the data to be processed are respectively sent back to the two original data addresses for storage;

[0072] The address generation module generates four data addresses in parallel. The initial value of the first data address is 0, and the initial value of the second data address is... The initial value of the third data address is The initial value of the fourth data address is C represents the number of stages required for a radix-4 FFT to compute N data points, with an initial value of 1; the initial value of the cycle count I is 1; the data address and the cycle count I are incremented by 1 in each clock cycle.

[0073] When the value of the fourth data address is N-1, the value of stage C is incremented by 1;

[0074] when At that time, according to the formula:

[0075] add1 * =add4 z +1

[0076]

[0077]

[0078]

[0079] Adjust the generated data address; where add1 * This indicates the address of the first data path after adjustment; add2 * This indicates the adjusted address of the second data path; add3 * This indicates the adjusted third data address; add4 * This indicates the adjusted fourth data address; add4 z This indicates the latest value of the fourth data address before the adjustment;

[0080] When the value of level C is 4, all addresses are initialized, and the address generation of the data to be processed in the current batch is completed.

[0081] The number of butterfly units is 1. A butterfly operation is performed once per clock cycle. Each butterfly operation uses four data addresses and generates four complex number outputs. The formula for a single radix-4 butterfly operation by the butterfly unit is:

[0082] x1_o=(x1_i+x2_i)+(x3_i+x4_i)

[0083]

[0084]

[0085]

[0086] in j is the imaginary unit, k is the rotation factor, π is pi, n = 1, 2, 3; x1_o is the first complex output; x2_o is the second complex output; x3_o is the third complex output; x4_o is the fourth complex output; x1_i is the a-th data to be processed; x2_i is the... The number of data to be processed; x3_i is the number of... The nth data to be processed; x4_i is the nth data. There are a data points to be processed; (x1_i + x2_i) represents the a-th data point and the data point to be processed. The result of adding the a-th data to be processed; (x1_i-x2_i) represents the sum of the a-th data to be processed and the a-th data. The result of subtracting the nth data to be processed; (x3_i+x4_i) represents the nth... The data to be processed and the first The result of adding the n data to be processed; (x3_i-x4_i) represents the nth data. The data to be processed and the first The result of subtracting the data to be processed. The set value corresponding to the FFT calculation data count result N can be 64.

[0087] The FFT method for this highly compressed time series includes the following steps:

[0088] S1. Write the data to be processed into the register, count the written data, and perform periodic counting.

[0089] S2. Continuously monitor the cycle count value. When the cycle count value reaches the threshold, preprocess the data to be processed written to the register and store the preprocessing result in the original storage location of the data to be processed.

[0090] S3. Continuously monitor the count result N of the amount of data to be processed. When it reaches the set value, stop writing the data to be processed.

[0091] S4. Generate data addresses and twitch factor addresses from the data preprocessed from the butterfly unit.

[0092] S5. Perform butterfly operations based on the data address and twitch factor address to obtain the FFT calculation result;

[0093] S6. Perform modulo operation on the FFT calculation results to obtain the modulus value. After all operations are completed, the system enters a idle state, waiting for the next start pulse.

[0094] The threshold corresponding to the period count value in step S2 is Where C represents the number of stages required to compute N data points using a radix-4 FFT, with an initial value of 1; the initial value of the cycle count I is 1, and the cycle count I increments by 1 in each clock cycle.

[0095] The specific method for preprocessing the data to be written to the register in step S2 is as follows: The data received from the register is... Starting with the first data to be processed, the four adders of the butterfly unit calculate the sum of the a-th data and the first data. The result of adding the real and imaginary parts of each of the a-th data to be processed, and the result of adding the real and imaginary parts of the a-th data to be processed. The result of subtracting the real and imaginary parts of each of the a-th data to be processed is obtained, and thus the result of subtracting the real and imaginary parts of the a-th data to be processed is obtained. The result of adding and subtracting the a-th data to be processed; the result of adding and subtracting the a-th data to be processed; and the result of adding and subtracting the a-th data to be processed. The results of adding and subtracting the data to be processed are respectively sent back to the two original data addresses for storage;

[0096] The specific method of step S4 is as follows: Generate four data addresses from the data preprocessed by the butterfly unit. The initial value of the first data address is 0, and the initial value of the second data address is... The initial value of the third data address is The initial value of the fourth data address is

[0097] when At that time, according to the formula:

[0098] add1 * =add4 z +1

[0099]

[0100]

[0101]

[0102] Adjust the generated data address; where add1 * This indicates the address of the first data path after adjustment; add2 * This indicates the adjusted address of the second data path; add3 * This indicates the adjusted third data address; add4 * This indicates the adjusted fourth data address; add4 z This indicates the latest value of the fourth data address before the adjustment;

[0103] When the value of level C is 4, all addresses are initialized, and the calculation of the current batch of data to be processed is completed.

[0104] The specific method for butterfly operation in step S5 is as follows: According to the formula:

[0105] x1_o=(x1_i+x2_i)+(x3_i+x4_i)

[0106]

[0107]

[0108]

[0109] Performing a single butterfly operation yields four complex outputs: x1_o (first channel), x2_o (second channel), x3_o (third channel), and x4_o (fourth channel), which together form the FFT result. j is the imaginary unit, k is the rotation factor, π is pi, n = 1, 2, 3; x1_i is the a-th data to be processed; x2_i is the... The number of data to be processed; x3_i is the number of... The nth data to be processed; x4_i is the nth data. There are a data points to be processed; (x1_i + x2_i) represents the a-th data point and the data point to be processed. The result of adding the a-th data to be processed; (x1_i-x2_i) represents the sum of the a-th data to be processed and the a-th data. The result of subtracting the nth data to be processed; (x3_i+x4_i) represents the nth... The data to be processed and the first The result of adding the n data to be processed; (x3_i-x4_i) represents the nth data. The data to be processed and the first The result of subtracting the data to be processed.

[0110] In one embodiment of the present invention, the address generation module is as follows: Figure 2 As shown, event_start is the pulse signal that starts generating the address, add1, add2, add3 and add4 are the four output address lines, and k is the output rotation factor address.

[0111] like Figure 3 As shown, the radix-4 butterfly unit has four complex inputs: x1_il, x1_ir, x2_il, x2_ir, x3_il, x3_ir, x4_il, and x4_ir, where r represents the real part and l represents the imaginary part. x1_il and x1_ir together represent one complex input. Similarly, the radix-4 butterfly unit has four complex outputs: x1_o, x2_o, x3_o, and x4_o, each of which also includes a real part and an imaginary part.

[0112] Figure 4 The diagram illustrates the modulus calculation module, which employs the CORDIC algorithm and a coordinate-rotating digital computer. CORDIC utilizes the idea of ​​approximation to transform complex computer operations such as trigonometric functions, square roots, and logarithms into simple addition, subtraction, and shift operations. This invention uses a circular rotation mode, iterating 16 times, so it takes 16 clock cycles to output a valid result; the output modulus value is valid.

[0113] Observing the address generation pattern, we can see that the addresses generated in the last level are output sequentially from 1 to N. However, since this invention uses the frequency domain decimation method (FFT), the output needs to be reversed, meaning that modulo operations cannot be performed simultaneously with the calculation of the last level. However, the addresses at the end of the last level can be moved slightly earlier. The modulus calculation begins after each cycle. This is because the reverse address generation pattern is as follows (taking a 64-point FFT as an example):

[0114] add_inv={add[1:0],add[3:2],add[5:4]};

[0115] Where add is the binary representation of the address, and add_inv is the binary representation of the address in reverse order.

[0116] add_inv is obtained by concatenating the binary number add in reverse order, grouping the bits into twos.

[0117] In the first four cycles, add[5:2] is always 0, so the maximum value of add_inv is... This is precisely when the butterfly operation is in the third stage, reaching the [number]th [step]. During the cycle (a total of (cycle), so it can be done in advance. The modulus calculation begins after one cycle. This saves 4 cycles when using a 64-point FFT, and also yields good returns when the number of points increases to 1024 or even higher.

[0118] In the specific implementation process, such as Figure 5 As shown, to intuitively understand the address calculation pattern, taking 16 points as an example, the solid line of four data points and butterfly unit 1 indicates the data address required for the first butterfly operation. The dashed line of four data points and butterfly unit 2 indicates the data address required for the second butterfly operation. Here, each butterfly operation reuses a single butterfly unit. Butterfly units 1, 2, 3, and 4 shown in the diagram are merely to indicate the order of butterfly operations. The diagram only shows the data addresses required for the first and second butterfly operations; the third and fourth operations follow the same pattern. The four data points for a simple butterfly operation are extracted by the address generation module, and one set is sent to the butterfly unit each clock cycle. Calculating one level requires four clock cycles, and a total of eight cycles across two levels are needed to complete the calculation. As can be seen from the diagram, although the address coverage of each set of data is relatively wide, the address generation process shows that the four data points required for the first calculation of the first level are obtained from... The data addresses required for the initial and subsequent calculations increase sequentially. In other words, the butterfly unit can receive data from the input... The calculation process can begin as soon as one piece of data is input, performing a butterfly operation each time, without waiting for all data to be input, thus saving time. The time of one clock cycle.

[0119] This invention utilizes the address generation rules of sequential structures to change the relative positions of computation and modulo operations. This allows sequential structures to not only save resources but also offer greater advantages and features compared to parallel structures, resulting in a reduction in the overall number of cycles. Furthermore, the larger N is, the more pronounced the effect. Moreover, as... Figure 6 As shown, data can be preprocessed during the calculation process, further reducing resource consumption. Figure 6 The clock in the middle is only for displaying relative time and has no practical significance.

Claims

1. A highly compressed temporal FFT system, characterized in that, include: The state machine is used to respond to the start pulse signal, enter the data reading state, and count the data to be processed and the cycle count; when the count result N of the amount of data to be processed reaches the set value, the data reading state stops and the address generation module is started; the generated data address is adjusted according to the cycle count result; The register is used to write the data to be processed when the state machine is in the data read state, and to store the data generated by the address generation module, the butterfly unit and the modulus calculation module; The address generation module is used to generate data addresses from the data obtained by preprocessing the butterfly unit, and to generate rotation factor addresses; The butterfly unit is used to preprocess the data to be processed written to the register when the period count value reaches the threshold, and store the preprocessing result in the original storage location of the data to be processed; butterfly operation is performed according to the data address and the rotation factor address to obtain the FFT calculation result; The modulus module is used to perform modulo operations on the FFT calculation results to obtain the modulus value; Received from register the first Starting with the first piece of data to be processed, the four adders of the butterfly unit calculate the... a The data to be processed and the first The result of adding the real and imaginary parts of the first data to be processed, and the result of adding the real and imaginary parts of the second data to be processed, and the result of adding the real and imaginary parts of the first data to be processed. a The data to be processed and the first The result of subtracting the real and imaginary parts of the first data to be processed is then obtained. a The data to be processed and the first The results of adding and subtracting the first set of data to be processed; the result of adding and subtracting the first set of data to be processed; a The data to be processed and the first The results of adding and subtracting the data to be processed are respectively sent back to the two original data addresses for storage; .

2. The highly compressed timing FFT system according to claim 1, characterized in that, The address generation module generates four data addresses in parallel. The initial value of the first data address is 0, and the initial value of the second data address is... The initial value of the third data address is The initial value of the fourth data address is C represents the number of levels required for a radix-4 FFT to compute N data points, with an initial value of 1. Period count value I The initial value is 1; the data address and cycle count value for each channel. I Increment by 1 in each clock cycle; When the value of the fourth data address is N-1, the value of stage C is incremented by 1; when At that time, according to the formula: Adjust the generated data address; among which This indicates the adjusted address of the first data path; This indicates the adjusted address of the second data path; This indicates the adjusted address of the third data path; This indicates the adjusted address of the fourth data path; This indicates the latest value of the fourth data address before the adjustment; When the value of level C is 4, all addresses are initialized, and the address generation of the data to be processed in the current batch is completed.

3. The highly compressed timing FFT system according to claim 2, characterized in that, The number of butterfly units is 1. A butterfly operation is performed once per clock cycle. Each butterfly operation uses four data addresses and generates four complex number outputs. The formula for a single radix-4 butterfly operation by the butterfly unit is: in , j The imaginary unit, k Where π is the rotation factor and π is the value of pi. ; This is the first channel for complex number output; This is the second complex number output; This is the third complex output; This is the fourth complex output; For the first a One piece of data to be processed; For the first One piece of data to be processed; For the first One set of data to be processed; For the first One piece of data to be processed; Indicates the first a The data to be processed and the first The result of adding up the data to be processed; Indicates the first a The data to be processed and the first The result of subtracting the data to be processed; Indicates the first The data to be processed and the first The result of adding up the data to be processed; Indicates the first The data to be processed and the first The result of subtracting the data to be processed.

4. The highly compressed temporal FFT system according to any one of claims 1 to 3, characterized in that, The set value for the FFT calculation data count result N is 64.

5. A highly compressed temporal FFT method, characterized in that, Includes the following steps: S1. Write the data to be processed into the register, count the written data, and perform periodic counting. S2. Continuously monitor the cycle count value. When the cycle count value reaches the threshold, preprocess the data to be processed written to the register and store the preprocessing result in the original storage location of the data to be processed. S3. Continuously monitor the count result N of the amount of data to be processed. When it reaches the set value, stop writing the data to be processed. S4. Generate data addresses and twitch factor addresses from the data preprocessed from the butterfly unit. S5. Perform butterfly operations based on the data address and twitch factor address to obtain the FFT calculation result; S6. Perform modulo operation on the FFT calculation results to obtain the modulus value; The specific method for preprocessing the data to be written to the register in step S2 is as follows: Received from register the first Starting with the first piece of data to be processed, the four adders of the butterfly unit calculate the... a The data to be processed and the first The result of adding the real and imaginary parts of the first data to be processed, and the result of adding the real and imaginary parts of the second data to be processed, and the result of adding the real and imaginary parts of the first data to be processed. a The data to be processed and the first The result of subtracting the real and imaginary parts of the first data to be processed is then obtained. a The data to be processed and the first The results of adding and subtracting the first set of data to be processed; the result of adding and subtracting the first set of data to be processed; a The data to be processed and the first The results of adding and subtracting the data to be processed are respectively sent back to the two original data addresses for storage; .

6. The FFT method for highly compressed timing according to claim 5, characterized in that, The threshold corresponding to the period count value in step S2 is Where C represents the number of levels required for a radix-4 FFT to compute N data points, with an initial value of 1; Period count value I The initial value is 1, and the period count value is... I Increment by 1 in each clock cycle.

7. The FFT method for highly compressed timing according to claim 6, characterized in that, The specific method for step S4 is as follows: The data preprocessed from the butterfly unit generates four data addresses. The initial value of the first data address is 0, and the initial value of the second data address is... The initial value of the third data address is The initial value of the fourth data address is ; when At that time, according to the formula: Adjust the generated data address; among which This indicates the adjusted address of the first data path; This indicates the adjusted address of the second data path; This indicates the adjusted address of the third data path; This indicates the adjusted address of the fourth data path; This indicates the latest value of the fourth data address before the adjustment; When the value of level C is 4, all addresses are initialized, and the calculation of the current batch of data to be processed is completed.

8. The FFT method for highly compressed timing according to claim 6, characterized in that, The specific method for the butterfly operation in step S5 is as follows: According to the formula: Perform a single butterfly operation to obtain the first complex output. Second complex output Third complex output and the fourth complex output That is, to obtain the FFT calculation result; where , j The imaginary unit, k Where π is the rotation factor and π is the value of pi. ; For the first a One piece of data to be processed; For the first One piece of data to be processed; For the first One piece of data to be processed; For the first One piece of data to be processed; Indicates the first a The data to be processed and the first The result of adding up the data to be processed; Indicates the first a The data to be processed and the first The result of subtracting the data to be processed; Indicates the first The data to be processed and the first The result of adding up the data to be processed; Indicates the first The data to be processed and the first The result of subtracting the data to be processed.

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