A circuit performance simulation modeling method based on veriloga language

Abstract

The application relates to a circuit performance simulation modeling method based on a veriloga language, and belongs to the technical field of modeling. The method establishes a VerilogA behavior level model according to the feasible circuit architecture of an analog-to-digital converter, including a top module, a first-stage module with non-ideal factors, second-stage to fourth-stage noise-free non-ideal factor modules and a fifth-stage ideal flash module; wherein the non-ideal factors include internal non-ideal factors and external non-ideal factors; the internal non-ideal factors include noise non-ideal factors, capacitor mismatch, limited open-loop gain of an operational amplifier, input offset voltage of the operational amplifier, limited bandwidth of the operational amplifier and sub-DAC error; the external non-ideal factors include clock jitter, pressure and temperature. The application can make the VerilogA modeling of the analog-to-digital converter more conform to actual working states and test results.

Description

Technical Field

[0001] This invention belongs to the field of modeling technology and relates to a circuit performance simulation modeling method based on the Veriloga language. Background Technology

[0002] Analog-to-digital converters (ADCs) serve as interface circuits between analog and digital systems, characterized by their wide application, high technological barriers, and irreplaceable nature. Currently, VerilogA models of ADCs are primarily based on functional modeling, failing to characterize the overall performance of the ADC circuit structure and thus lacking in system functional evaluation. Furthermore, existing VerilogA simulation models for ADCs have low accuracy, making it impossible to accurately establish equivalent circuit models of the ADC. Summary of the Invention

[0003] In view of this, the purpose of this invention is to provide a circuit performance simulation modeling method based on the Veriloga language, so as to achieve accurate modeling of the equivalent circuit model of the analog-to-digital converter, and make the VerilogA modeling of the analog-to-digital converter more in line with the actual working conditions and test results.

[0004] To achieve the above objectives, the present invention provides the following technical solution:

[0005] A circuit performance simulation modeling method based on the Veriloga language is proposed. A Veriloga behavioral-level model is established based on the feasible circuit architecture of the analog-to-digital converter (ADC), hiding the core circuit design while realizing the overall circuit function. The feasible circuit architecture includes the overall circuit architecture, the sub-ADC circuit architecture, the MDAC sampling and integration terms, and a 5-bit MDAC transfer characteristic curve with 1.5-bit redundancy.

[0006] The established Verilog A behavioral-level model includes a top-level module 100, a first-level module 110 with non-ideal factors, second to fourth-level modules 120 with noise-free non-ideal factors, and a fifth-level ideal flash module 130. The non-ideal factors include internal and external factors. Internal non-ideal factors mainly include noise non-ideal factors, capacitor mismatch, finite open-loop gain of the op-amp, op-amp input offset voltage, finite bandwidth of the op-amp, and sub-DAC errors. External non-ideal factors mainly include clock jitter, stress, and temperature.

[0007] Furthermore, the top-level module 100 is defined as the input and output ports of the VerilogA behavioral-level model, as well as the port connection method of the instantiation module, so that the residual information output of the previous stage is connected to the analog signal input of the next stage.

[0008] Furthermore, the module 110 with non-ideal factors is a single-stage pipeline model that includes non-ideal factors. Specifically, it converts the analog input signal into a 5-bit digital codeword output and outputs the residual signal to the next stage. Meanwhile, the non-ideal factors added to this module include: noise non-ideal factors (mainly system noise), capacitor mismatch, finite open-loop gain of the op-amp, op-amp input offset voltage, finite bandwidth of the op-amp, sub-DAC error, and clock jitter.

[0009] Furthermore, the noise-free non-ideal factor module 120 is a noise-free non-ideal factor single-stage pipeline model. Specifically, the non-ideal factors added to this module include capacitor mismatch, operational amplifier finite open-loop gain, operational amplifier input offset voltage, operational amplifier finite bandwidth, sub-DAC error, and clock jitter.

[0010] Furthermore, the non-ideal noise factor is to directly set the operational amplifier noise as an adjustable variable.

[0011] Furthermore, the capacitor mismatch is achieved by multiplying the unit capacitance in the pipeline transmission curve expression for each stage by a random number that satisfies a Gaussian distribution.

[0012] Furthermore, adding finite open-loop gain and finite bandwidth to the op-amp involves superimposing gain error and feedback coefficients onto the transfer function of each stage.

[0013] Furthermore, the sub-DAC error is equivalent to the input signal by superimposing a certain amount of voltage.

[0014] Furthermore, the clock jitter is equivalent to superimposing a random voltage quantity Vrand that satisfies a Gaussian distribution on the trigger level.

[0015] The beneficial effects of this invention are as follows: This invention constructs a behavioral model based on the behavioral language VerilogA. By introducing non-ideal factors, while ensuring the basic functions of the analog-to-digital converter, it makes the VerilogA modeling of the analog-to-digital converter more closely match the actual working conditions and test results, thereby increasing the usability and realism of the model.

[0016] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0017] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0018] Figure 1This is a schematic diagram of the overall circuit architecture of the analog-to-digital converter in an embodiment of the present invention;

[0019] Figure 2 This is a diagram illustrating the overall architecture of the Verilog A analog-to-digital converter in an embodiment of the present invention.

[0020] Figure 3 This is the operational amplifier noise equivalent circuit;

[0021] Figure 4 The effect of input offset voltage;

[0022] Figure 5 f in =9.45MHz, v in =990mV, dynamic performance of the ideal model with a sampling depth of 64kpoint;

[0023] Figure 6 This is to explain the impact of some non-ideal factors on dynamic performance.

[0024] Figure reference numerals: 100 - Top-level module, 110 - Module with non-ideal factors, 120 - Noise-free non-ideal factor module, 130 - Ideal flash module, 140 - Codeword alignment circuit module Detailed Implementation

[0025] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0026] Please see Figures 1-6 This embodiment focuses on VerilogA modeling of a 16-bit, 5-stage pipelined digital-to-analog converter. The basic principle is as follows: Figure 1 As shown, the first four stages of the five-stage pipeline each provide 5-bit output, including 1.5-bit redundancy, and provide 3-bit valid output. The last stage is a 4-bit flash analog-to-digital converter. The output of the five-stage pipeline is aligned to a digital codeword, ultimately achieving 16-bit precision.

[0027] based on Figure 1 The circuit architecture shown establishes the basic structure for a Verilog A behavioral-level model, as follows. Figure 2 As shown, the basic structure includes:

[0028] (1) Top-level module 100

[0029] Specifically, it mainly defines the input and output ports of the overall modeling and the port connection method of the instantiated modules, so that the residual information output of the previous stage can be connected to the analog signal input of the next stage.

[0030] (2) Module 110 with non-ideal factors: Single-stage pipeline model containing non-ideal factors.

[0031] Specifically, module 110 contains the basic functions of a single-stage pipeline: converting the analog input signal into a 5-bit digital codeword output, and simultaneously outputting the residual signal to the next stage. Module 110 also contains non-ideal factors: noise non-ideal factors, mainly system noise; capacitor mismatch; finite open-loop gain of the op-amp; op-amp input offset voltage; finite bandwidth of the op-amp; sub-DAC error; clock jitter.

[0032] (3) No noise non-ideal factor module 120: No noise non-ideal factor single-stage pipeline model.

[0033] Specifically, since the noise will attenuate by 8 times in each stage, noise non-ideal factors are only added in the first stage (module 110 with non-ideal factors). The main non-ideal factors in the middle three stages (module 120 without noise non-ideal factors) are: capacitor mismatch; finite open-loop gain of op-amp; op-amp input offset voltage; finite bandwidth of op-amp; sub-DAC error; clock jitter.

[0034] (4) Ideal Flash Module 130:

[0035] according to Figure 1 The circuit architecture uses a flash analog-to-digital converter as the final stage, which offers advantages such as high sampling rate and simple structure. Because it is the last stage of the pipeline, the error is negligible.

[0036] The above constitutes the Verilog A modeling of the pipelined analog-to-digital converter. The modeling system consists of four modules: a top-level module 100, a module 110 with non-ideal factors, a module 120 with noise-free non-ideal factors, and an ideal flash module 130. The overall modeling system outputs 24-bit digital codewords, which are then aligned to a 16-bit digital codeword by the codeword alignment circuit module 140. Different types and magnitudes of non-ideal factors can be added to the modeling system through parameter configuration, thereby achieving functional and performance simulation of the analog-to-digital converter circuit. See [reference needed] for specific effects. Figure 5 and Figure 6 .

[0037] The specific technical solutions for addressing the aforementioned non-ideal factors are as follows:

[0038] (a) Noise non-ideal factors

[0039] In pipelined analog-to-digital converters, thermal noise is the primary source of system noise, and the main sources of thermal noise are the switched-capacitor network and operational amplifier. Let the sampling capacitor of the circuit be C. S The sampling noise caused by the sampling switch circuit is: P noise =KT / C S The sampling and quantization process of this invention first determines the voltage range of the input signal, and then determines the magnitude of the output residual signal based on the described transfer characteristic curve. Since the thermal noise generated during the sampling stage will be reflected back to the input terminal through the feedback loop, a normally distributed signal with a variance of is superimposed on the input signal. The sampling noise is a random voltage quantity. Simultaneously, the sampling noise also affects the residual signal; therefore, the sampling noise must be superimposed on the input signal variable in the transfer characteristic curve expression. The noise during the hold phase is mainly the operational amplifier noise, the principle of which is as follows... Figure 3 As shown, N OP γ is the noise source figure of the operational amplifier (op-amp), which is related to the op-amp's structure and the transconductance of the MOSFET; γ is the thermal noise figure, which is related to the manufacturing process and is 2 / 3 in long-channel processes; k is the Boltzmann constant, and T is room temperature; β is the feedback coefficient of the op-amp. The addition method is the same as in the sampling stage. Considering that op-amp noise involves many variables and some parameters are difficult to calculate, this invention directly sets the op-amp noise as an adjustable variable.

[0040] (b) Capacitor mismatch

[0041] Capacitor mismatch not only introduces gain error but also causes offset in the sub-DAC reference level. The amount of capacitor mismatch follows a Gaussian distribution. By multiplying the unit capacitance in the pipeline transmission curve expression of each stage by a random number that follows a Gaussian distribution, a non-ideal addition of capacitor mismatch can be achieved.

[0042] (c) Operational amplifier finite open-loop gain and finite bandwidth

[0043] The error introduced by the finite open-loop gain A is Where β is the feedback coefficient, the gain error and the feedback coefficient are superimposed on the transfer function of each stage, thereby adding non-ideal factors of finite open-loop gain and finite bandwidth of the operational amplifier.

[0044] (d) Sub-DAC error

[0045] Sub-DAC errors can affect the comparator's judgment of the input signal magnitude, potentially leading to incorrect quantization interval determination. However, due to redundant bit correction, the impact of sub-DAC errors is often negligible. Sub-DAC errors can be equivalently represented by superimposing a certain voltage on the input signal. Unlike noise addition, sub-DAC errors are corrected, therefore their influence is not considered when describing the transfer characteristic curve.

[0046] For ease of explanation, regarding the op-amp input offset voltage, let's take an example with only two sampling capacitors, C1 and C2. Figure 4 As shown, only the input offset voltage V is considered. os In this case, the transfer function is:

[0047]

[0048] It is evident that the offset voltage of the op-amp is amplified step by step by the loop, and its magnitude is independent of the input signal.

[0049] (e) Clock jitter.

[0050] This invention controls sampling and quantization using the `cross` function in Verilog A, performing sampling and quantization operations the instant the input clock exceeds the trigger level. Clock jitter is equivalently represented by superimposing a Gaussian-distributed random voltage `Vrand` onto the trigger level. The equivalent clock jitter can be calculated using the rise time `trise` and voltage amplitude `Vclk` of the external input clock.

[0051] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A circuit performance simulation modeling method based on Veriloga language, characterized in that, A Verilog A behavioral-level model is established based on the feasible circuit architecture of the analog-to-digital converter, including a top-level module (100), a first-level module with non-ideal factors (110), second to fourth-level noise-free non-ideal factor modules (120), and a fifth-level ideal flash module (130). The first four levels each provide 5-bit output, including 1.5-bit redundancy, and 3-bit effective output. The last level provides 4-bit output. Non-ideal factors include internal and external factors. Internal non-ideal factors include noise non-ideal factors, capacitor mismatch, finite open-loop gain of the op-amp, op-amp input offset voltage, finite bandwidth of the op-amp, and sub-DAC error. External non-ideal factors include clock jitter, pressure, and temperature. The module (110) with non-ideal factors is a single-stage pipeline model containing non-ideal factors. Specifically, it converts the analog input signal into a 5-bit digital codeword output and outputs the residual signal to the next stage. Meanwhile, the non-ideal factors added to this module include: noise non-ideal factors, capacitor mismatch, finite open-loop gain of the op-amp, op-amp input offset voltage, finite bandwidth of the op-amp, sub-DAC error, and clock jitter. The noise-free non-ideal factor module (120) is a noise-free non-ideal factor single-stage pipeline model. Specifically, the non-ideal factors added to this module include capacitor mismatch, op-amp finite open-loop gain, op-amp input offset voltage, op-amp finite bandwidth, sub-DAC error, and clock jitter. The non-ideal noise factor is achieved by directly setting the op-amp noise as an adjustable variable; the capacitor mismatch is achieved by multiplying the unit capacitance in the pipeline transfer curve expression of each stage by a random number that satisfies a Gaussian distribution; adding finite open-loop gain and finite bandwidth to the op-amp is achieved by superimposing gain error and feedback coefficient on the transfer function of each stage; the sub-DAC error is equivalently achieved by superimposing a certain voltage amount on the input signal; the clock jitter is equivalently achieved by superimposing a random voltage amount Vrand that satisfies a Gaussian distribution on the trigger level. The top-level module (100), the module with non-ideal factors (110), the module without noise non-ideal factors (120), and the ideal flash module (130) constitute the modeling whole. The modeling whole outputs 24-bit digital codewords, and finally outputs 16-bit digital codewords through the codeword alignment circuit module (140). Since the influence of noise will be attenuated by 8 times at each level, noise non-ideal factors are only added to the module with non-ideal factors (110) at the first level.

2. The circuit performance simulation modeling method according to claim 1, characterized in that, The top-level module (100) is defined as the input and output ports of the VerilogA behavioral-level model, as well as the port connection method of the instantiation module, so that the residual information output of the previous stage is connected to the analog signal input of the next stage.

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