Integrated circuit design method and apparatus

Abstract

The application discloses a kind of integrated circuit design method and device.The layout includes: S1 is loaded power fill to the circuit layout with original metal routing;S2, check whether the area with spacing error exists in current layout;If it exists, enter S3, if it does not exist, output the layout;S3 is cut off a predetermined spacing width delta to the power fill pattern corresponding to each area with spacing error, return to S2.The application can help layout engineers to efficiently solve the metal spacing error caused by adding power fill on the layout, saving time.The layout module repaired by the tool can maximize the retention of the added power fill grid while correcting the spacing error.

Description

Technical Field

[0001] This invention relates to the field of semiconductor memory, and more specifically to an integrated circuit design method and apparatus. Background Technology

[0002] As semiconductor technology continues to evolve, the width of metal interconnects in chips is becoming narrower, leading to increased resistance on these interconnects. Simultaneously, the supply voltage of the chip is decreasing, making the resistive voltage drop (IR drop) effect increasingly pronounced. A significant IR drop slows down the switching speed of transistors (MOSFETs), greatly impacting the overall performance and even the functionality of the chip.

[0003] To mitigate the voltage drop effect of power and ground lines on a chip, designers often increase the density of the power mesh on the layout to help reduce the equivalent resistance from the power pin pad to the logic gate. As the resistance on the power mesh decreases, the resistive voltage drop (IR drop) on the mesh also decreases. This practice of increasing the density of power mesh lines on the layout is called adding power fill to the layout.

[0004] Power fill involves adding large power grids connected to the power supply to each back end of line (BEOL) metal trace on the layout. These power grids help reduce the resistance on the power supply lines. However, since the metal traces in the layout are already very dense, the added power fill grids can easily cause a large number of space-related layout design rule check (DRC) physical verification errors between the metal traces in the circuit.

[0005] How to correct layout design rules to check DRC physical verification errors and obtain sufficient power fill is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0006] The purpose of this invention is to provide an integrated circuit design method and apparatus that, through multiple iterations to correct power fill, ensures that spacing errors can be automatically corrected while leaving sufficient power fill on the layout after trimming.

[0007] To address the above problems, a first aspect of the present invention provides an integrated circuit design method, comprising:

[0008] S1, apply power fill to the layout with the original metal traces;

[0009] S2, check if the current layout includes areas with incorrect spacing; if so, proceed to S3; otherwise, output the layout.

[0010] S3, for each region with spacing errors, trim the power fill pattern by a predetermined spacing width, and return to S2.

[0011] Optionally, step S2 includes:

[0012] Check if the spacing between adjacent metal traces in the current layout is less than the minimum spacing threshold. If so, the area is determined to be a spacing error area.

[0013] Optionally, step S2 further includes:

[0014] After detecting areas with incorrect spacing, the error type of the incorrect spacing area is identified, and the error type includes:

[0015] First type of error: Both metal edges of the spacing error area are formed by the original metal traces;

[0016] Second error type: Both metal edges of the spacing error area are formed by a power fill pattern;

[0017] The third error type: In the area of ​​incorrect spacing, one metal edge is formed by a power fill pattern and the other metal edge is formed by the original metal trace.

[0018] Optionally, if it is the first error type, then power fill patterns connected to the first metal edge and the second metal edge are found along the directions perpendicular to the first metal edge and the second metal edge, respectively, and the predetermined spacing width is cut off.

[0019] Optionally, the power fill patterns connected to the first metal edge and the second metal edge are respectively connected to the power fill patterns of the two metal edges along the width, and each is cut off by half of the predetermined spacing width.

[0020] Optionally, if it is the second error type, the power fill pattern forming the two metal edges is cut off by half of the predetermined spacing width.

[0021] Optionally, if it is a third error type, the power fill pattern forming a metal edge will be trimmed to the predetermined spacing width.

[0022] Optionally, if it is the third error type, then a power fill pattern connected to the other metal edge is found along the direction perpendicular to the other metal edge, and the power fill pattern forming a metal edge is cut off by half the predetermined spacing width.

[0023] Optionally, step S2 includes:

[0024] If the sum of the number of spacing errors of the first error type, the second error type, or the third error type is greater than 0, it is determined that there is a region with spacing errors in the current layout, and proceed to step S3.

[0025] Optionally, the predetermined spacing width is less than 1 / 20 to 1 / 2 of the minimum spacing threshold.

[0026] Another aspect of the present invention provides an integrated circuit design apparatus, including a power fill module, a spacing error checking module, and a repair module;

[0027] The power filling module applies power filling to the layout.

[0028] The spacing error checking module checks whether the current layout includes areas with spacing errors; if so, the repair module repairs them; if not, the repaired layout is output.

[0029] The repair module trims off a predetermined spacing width from the power fill pattern corresponding to each area with a spacing error, and outputs the trimmed layout to the spacing error checking module.

[0030] Optionally, after detecting a region with spacing errors, the error type of the region with spacing errors is identified, and the error type includes:

[0031] First type of error: Both metal edges of the spacing error area are formed by the original metal traces;

[0032] Second error type: Both metal edges of the spacing error area are formed by a power fill pattern;

[0033] The third error type: In the area of ​​incorrect spacing, one metal edge is formed by a power fill pattern and the other metal edge is formed by the original metal trace.

[0034] Optionally, if it is the first error type, the repair module searches for power fill patterns connected to the first metal edge and the second metal edge along the direction perpendicular to the first metal edge and the second metal edge, respectively, and cuts off the predetermined spacing width.

[0035] Optionally, the repair module may cut the power fill patterns connected to the first metal edge and the second metal to half the width of a predetermined spacing.

[0036] Optionally, if it is the second error type, the repair module will cut the power fill pattern of the two metal edges by half the predetermined spacing width.

[0037] Optionally, if it is a third error type, the repair module will form a power fill pattern with a metal edge trimmed to the predetermined spacing width.

[0038] Optionally, if it is a third error type, the repair module searches for a power fill pattern connected to the other metal edge along a direction perpendicular to the other metal edge, and cuts off half of the predetermined spacing width of the power fill pattern forming a metal edge.

[0039] Optionally, if the sum of the number of spacing errors of the first error type, the second error type, or the third error type detected by the spacing error checking module is greater than 0, it determines that there is a region with spacing errors in the current layout and starts the repair module.

[0040] Optionally, the predetermined spacing width is less than 1 / 20 to 1 / 2 of the minimum spacing threshold.

[0041] The above-described technical solution of the present invention has the following beneficial technical effects:

[0042] During layout repair, spacing errors are numerous. Tools and methods for addressing these errors can dynamically check the DRC space of the layout in real time and automatically determine whether to continue trimming the power fill mesh in the next iteration based on the check results. This greatly simplifies the usage process and improves the user experience. This tool helps layout engineers efficiently resolve metal DRC spacing errors caused by adding power fill in the layout, significantly saving them time. The layout module repaired by this tool can retain the added power fill mesh to the maximum extent while correcting spacing errors. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of power supply filling in the prior art;

[0044] Figure 2 (a) is a schematic diagram of the clipping area in the prior art; Figure 2 (b) is Figure 2 (a) Schematic diagram of the cropped area after clipping;

[0045] Figure 3 A schematic diagram illustrating the principle of iterative trimming is provided.

[0046] Figure 4 An exemplary integrated circuit layout workflow diagram is shown;

[0047] Figure 5 (a) is a diagram illustrating how the tool checks for error areas in real time. Figure 5 (b) An illustrative diagram showing the output results of multiple iterations after real-time tool checks is provided.

[0048] Figure 6 (a) is a schematic diagram of the area for real-time detection of spacing errors in a preferred embodiment; Figure 6 (b) is a schematic diagram of the classification of spacing error areas in the preferred embodiment;

[0049] Figure 7 This is a schematic diagram of the trimmable area in a preferred embodiment;

[0050] Figure 8 This is a schematic diagram of the step-by-step pruning process in a preferred embodiment;

[0051] Figure 9 This is a schematic diagram of the step-by-step pruning process in a preferred embodiment;

[0052] Figure 10 This is a schematic diagram of an integrated circuit layout device. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments and the accompanying drawings. It should be understood that these descriptions are merely exemplary and not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0054] Combination Figure 1 When the added power fill (shape1) and an existing metal trace 1 (shape2) in the layout are located on the same net, the added power fill "shape" will be merged with the existing metal trace in the layout, such as... Figure 1 The diagram shows "shape1" and "shape2". When they are not on the same net, the power padding and the Metal1 trace maintain a certain spacing, where "signal" represents the metal trace signal. However, merging the same net introduces new DRC (Dual Recognition Code) spatial physical verification errors. The merging of shape1 and shape2 results in a new Metal1 segment on the layout that is wider than the original shape2. Because Metal1 is thicker, this Metal1 trace needs to be spaced further apart from other Metal1 traces on the layout. This increased width of Metal1 leads to the Metal1 spacing error indicated by the double-headed arrow.

[0055] Figure 1Such physical verification errors in DRC spacing caused by added power fill as shown are on the order of several hundred thousand across the entire chip. Due to the huge quantity, manual repair by layout engineers is extremely time-consuming. In addition, in these layout regions with DRC spacing physical verification errors, DRC can only report that the distance between metal traces is too small, and it is impossible to know to what extent the distance between metal traces in each error region needs to be increased during specific correction. Therefore, for these DRC spacing errors caused by the merging of power fills, the simplest approach is to directly use the DRC spacing check threshold to clip the added power fills. However, this rough approach will cause a large area of power fills to be clipped when both sides of the DRC spacing error are newly added power fills, which does not meet the designer's requirements.

[0056] As shown in Figure 2 (a), the spacing s marked by the double-headed arrow is smaller than the minimum spacing "value" of Metal1 traces. Since the specific value of s is unknown, only s<value is known. To fix this DRC spacing error, the simplest method is to directly use the value of "value" to clip the power fills on both sides of the DRC spacing error, and the clipping result is as shown in Figure 2 (b). After this rough clipping, a relatively large gap region (within the dashed box) will appear on Metal1, which does not meet the design requirements. Because the length of the region clipped by this method is equal to s+2value, the length of the clipped region is excessively large.

[0057] The ideal clipping value for Metal1 power fill should be (value-s) / 2 for each side, as marked in Figure 3 . Approaching this clipping value can ensure that the spacing of the vacated region after the power fill is clipped is approximately equal to the minimum spacing "value" required for Metal1 traces. This can not only fix the DRC spacing error, but also leave sufficient power fills on the layout.

[0058] In view of the above, there is a need for a tool that can perform real-time checks on the layout, and perform real-time tiny-step trimming on the power fill grid according to the DRC spacing results of the real-time check, instead of removing a large portion at one time, and automatically control the number of clipping iterations.

[0059] To add as much power fill as possible to the layout, while correcting the extra DRC physical verification errors related to layout spacing caused thereby, the present invention provides an integrated circuit design method and apparatus, which can automatically repair spacing errors after power fill, in particular, can automatically and real-timely repair spacing errors in a stepwise manner. The main steps of automatically repairing spacing errors after power fill include performing real-time DRC spacing check on the layout, stepwise trimming the power fill grid according to the check result to repair the DRC spacing error, and deciding whether to proceed to the next iteration, through multiple iterative trimming, until all spacing errors are repaired.

[0060] Figure 4 shows a schematic flowchart of the integrated circuit design method of the present invention.

[0061] In a preferred embodiment, the method for repairing layout spacing errors of the present invention includes the following steps:

[0062] S1, loading power fill on the circuit layout;

[0063] S2, checking whether the current layout includes regions with spacing errors; if yes, proceeding to S3, if no, outputting the layout with no spacing errors;

[0064] S3 trimming a predetermined spacing width delta from the power fill pattern corresponding to each region with a spacing error, and returning to S2.

[0065] After the power fill grid is added in step S1, the merged wider metal traces are subjected to real-time DRC spacing check to calculate regions with spacing errors, that is, regions where the metal trace spacing is less than a value, where the Value is the minimum allowable metal trace spacing given by the process, that is, the minimum spacing threshold. The minimum spacing threshold is related to the width of the metal trace.

[0066] Further, in step S2, regions with spacing errors are found through DRC spacing check, and the metal wiring spacing of a region with a spacing error is less than the minimum spacing threshold. Two metal edges tangent to the region with the spacing error can be found, and the spacing of the two metal edges along the width direction is less than the minimum spacing threshold.

[0067] Further, the error types of regions with spacing errors include three types, see Figure 6-7 :

[0068] First error type TypeA: both two metal edges of the error region are formed by original metal traces;

[0069] Second error type TypeB: both two metal edges of the error region are formed by power fill patterns;

[0070] The third error type, Type C, is where one metal edge of the error region is formed by a power-fill pattern and the other metal edge is formed by the original metal trace.

[0071] Further, in step S3, after locating all metal traces with spacing errors in the layout, the repair module finds the edge on the metal trace tangent to the spacing error and automatically trims this edge inwards by a very small predetermined spacing width. After each trimming, the detection module checks whether the spacing errors still exist in the entire layout. If they still exist, it continues to trim by another predetermined spacing width based on the previous trimming. This iterative trimming of the predetermined spacing width continues until all spacing errors are resolved. A very small trimming value delta is set, and the power fill mesh is gradually modified through iterative trimming until there are no spacing errors in the final layout.

[0072] Furthermore, in the width direction, which is either the first direction or the opposite of the first direction, the distance between the two metal edges tangent to the area with the incorrect spacing along the width direction is less than the minimum spacing threshold. The cutting direction is either the first direction or the opposite of the first direction. The result of the cutting is that the spacing between the two metal edges increases by a predetermined spacing width delta.

[0073] Furthermore, for each region with spacing errors, the power fill pattern corresponding to that region is trimmed by a predetermined spacing width delta, including:

[0074] For the first error type, Type A, both metal edges are formed by the original metal traces. Since the original metal traces cannot be cut, the method of this invention uses a power fill pattern that is merged with or overlaps with the original metal traces in the error area as a cuttable area. In this case, the power fill pattern connected to the two original metal traces is cut at a predetermined distance delta / 2 along the direction of increasing spacing. The connection includes electrical contact; after power filling, the power fill pattern and the original metal traces form electrical contact.

[0075] For the second error type Type B, both metal edges of the error area are formed by power fill patterns. Therefore, the two power fill patterns on both sides of the error area are cuttable areas. At this time, half of the predetermined spacing width, delta / 2, is cut off for each power fill pattern.

[0076] For the third error type, Type C, where the two metal edges of the error region are formed by a power fill pattern and the original metal trace respectively, the power fill pattern on one side of the error region is a trimmable area. In this case, the power fill pattern is trimmed by a predetermined spacing delta along the direction of increasing spacing. Alternatively, the power fill pattern connected to the original metal trace can be trimmed by a predetermined spacing delta / 2 along the direction of increasing spacing, and the power fill pattern forming the metal edge can also be trimmed by a predetermined spacing delta / 2 along the direction of increasing spacing.

[0077] Furthermore, Figure 5 In (a), the areas marked 1 and 2 represent regions where spacing needs to be increased due to merging; the area within the dashed box indicates the thickened metal portion. Real-time DRC space checking and the automatic iteration engine analyze DRC spacing errors in metal traces in real time. Figure 5 (b) shows a layout that was automatically corrected and iterated multiple times, and which did not result in a layout with incorrect spacing.

[0078] This integrated circuit layout method helps layout engineers efficiently resolve metal DRC spacing errors caused by adding power fill in the layout, greatly saving their time. By using an automatic stepping approach to repair DRC spacing errors caused by adding power fill in the chip layout, the method can preserve the added power fill grid to the maximum extent while correcting the DRC spacing errors.

[0079] The tool for automatically correcting DRC spacing errors after power supply filling is described in further detail below with reference to a preferred embodiment. Figure 6 (a) is a schematic diagram of the area for real-time detection of spacing errors in the preferred embodiment;

[0080] Figure 6 (b) is a schematic diagram of the classification of spacing error areas in the preferred embodiment; Figure 7 This is a schematic diagram of the trimmable area in a preferred embodiment; Figure 8 This is a schematic diagram of the step-by-step pruning in the preferred embodiment; Figure 9 This is a schematic diagram of the step-by-step pruning process in this preferred embodiment.

[0081] The integrated circuit layout process is as follows:

[0082] S1, load power fill onto the layout.

[0083] S2, check if the current layout includes areas with incorrect spacing; if so, proceed to S3; otherwise, output the corrected layout.

[0084] S3, for each region with spacing errors, trim the power fill pattern by a predetermined spacing width, and return to S2.

[0085] In step S2, it is found that after the power fill is added, the metal traces on the same network line merge, resulting in the widening of the metal traces, which leads to DRC spacing errors in the areas marked by double-headed arrows. The spacing of these areas needs to be increased, as Figure 6 shown in (a), the double-headed arrow portions represent the areas with DRC spacing errors, and 1, 2, 3 in the figure represent the areas where the metal is widened and the spacing needs to be increased. The areas where the metal trace spacing is less than the value. Combined with Figure 6 (b), the areas with DRC spacing errors in the layout are divided into three types:

[0086] Type A: The two metal edges with spacing errors are the original designed metal traces;

[0087] Type B: Both of the two metal edges with spacing errors are the metal grids of the power fill pattern;

[0088] Type C: Of the two metal edges with spacing errors, one is the original designed metal trace, and the other is the metal grid of the power fill pattern.

[0089] As shown Figure 7 , the engine performs real-time calculation on the Type A, Type B and Type C spacing error areas in the layout at the same time to find the trimmable areas of Type A, Type B and Type C, that is, the areas marked by 4, 5 and 6 in the figure. Type A trimmable area: Since the original metal traces in the design cannot be trimmed, the engine will automatically find the power fill grid merged with the original metal traces as the Type A trimmable area.

[0090] Combined with Figure 8 , the repair module performs real-time processing on the Type A, Type B and Type C areas in the layout at the same time, and trims a very small predetermined spacing width delta for the trimmable areas. For Type A, the trimmable area of the power fill grid is trimmed by the distance of the predetermined spacing width delta along the arrow direction. For Type B, the trimmable area of the power fill grid is trimmed by the distance of delta / 2 along the arrow direction, and the total distance in two directions is the predetermined spacing width delta. For Type C, the trimmable area of the power fill grid is trimmed by the distance of the predetermined spacing width delta along the arrow direction.

[0091] Combined with Figure 9After the repair module trims the power fill grid of Type A, Type B, and Type C regions in the layout by the predetermined spacing width delta, the detection module automatically performs a real-time DRC space check on the entire layout. The Type A spacing error in region 7 is corrected, but the Type B spacing error in region 8 and the Type C spacing error in region 9 remain. A new Type A spacing error has been generated in region 10. Regions 8, 9, and 10 require further repair.

[0092] If the total number of errors for Type A + Type B + Type C is still greater than 0, the engine automatically proceeds to the next round of power fill mesh trimming iterations based on the predetermined spacing width delta. If the total number of errors for Type A + Type B + Type C is 0, the engine terminates the power fill mesh trimming iteration. Figure 9 After the cropping is performed in step S3, return to step S2 and re-perform the DRC space check. If space errors are found in areas 8, 9, and 10, return to step S3 to repair them until there are no space errors.

[0093] On the other hand, it provides an integrated circuit design device, combined with Figure 10 It includes a power filling module, a spacing error checking module, and a repair module.

[0094] The power filling module applies power filling to the layout.

[0095] The spacing error checking module checks whether the current layout includes areas with spacing errors; if so, the repair module repairs them; if not, the repaired layout is output.

[0096] The repair module trims off a predetermined spacing width from the power fill pattern corresponding to each area with a spacing error, and outputs the trimmed layout to the spacing error checking module.

[0097] Furthermore, the spacing error detection module checks for areas with spacing errors, including two metal edges tangent to the area with the spacing error, wherein the spacing between the two metal edges along the width direction is less than the minimum spacing threshold.

[0098] Furthermore, the error types of areas with incorrect spacing include three cases:

[0099] First type of error: Both metal edges are formed by the original metal traces;

[0100] Second error type: Both metal edges are formed by power-filled patterns;

[0101] The third error type: One metal edge is formed by a power-filled pattern and the other metal edge is formed by the original metal trace.

[0102] Furthermore, under the first error type, both metal edges are formed by the original metal traces. The repair module searches for power fill patterns connecting the first metal edge and the second metal edge along directions perpendicular to the first metal edge and the second metal edge, respectively, and cuts off the predetermined spacing width. Further, the repair module cuts off half of the predetermined spacing width, i.e., delta / 2, of the power fill patterns connecting the first metal edge and the second metal edge.

[0103] Furthermore, under the second error type, if both metal edges are formed by power fill patterns, the repair module will cut the power fill patterns forming the two metal edges by half the predetermined spacing width, i.e., delta / 2.

[0104] Furthermore, under the third error type, if one of the two metal edges is formed by a power fill pattern and the other by the original metal trace, the repair module will trim the predetermined spacing width of the power fill pattern forming one metal edge. Alternatively, the repair module can also search for a power fill pattern connected to the other metal edge along a direction perpendicular to it, and trim it by half the predetermined spacing width, i.e., delta / 2, compared to the power fill pattern forming one metal edge.

[0105] Furthermore, the predetermined spacing width delta is less than 1 / 20 to 1 / 2 of the minimum spacing threshold.

[0106] In summary, this invention discloses an integrated circuit design method and apparatus. The layout process includes: S1 applying power fill to a circuit layout with original metal traces; S2 checking if the current layout includes regions with spacing errors; if so, proceeding to S3; otherwise, outputting the layout; S3 trimming the power fill pattern corresponding to each region with spacing errors by a predetermined spacing width, and returning to S2. This invention helps layout engineers efficiently resolve metal spacing errors caused by adding power fill to the layout, saving time. The layout module, after tool repair, can retain the added power fill grid to the maximum extent while correcting spacing errors.

[0107] It should be understood that the specific embodiments described above are merely illustrative or explanatory of the principles of the invention and do not constitute a limitation thereof. Therefore, any modifications, equivalent substitutions, improvements, etc., made without departing from the spirit and scope of the invention should be included within the protection scope of the invention. Furthermore, the appended claims are intended to cover all variations and modifications falling within the scope and boundaries of the appended claims, or equivalent forms of such scope and boundaries.

Claims

1. An integrated circuit design method, characterized in that, Includes the following steps: S1, apply power fill to the layout with the original metal traces; S2, check if the spacing between adjacent metal traces in the current layout is less than the minimum spacing threshold; If so, it is determined that there is a region with incorrect spacing in the current layout, and the error type of the region with incorrect spacing is identified. The error types include: First type of error: Both metal edges of the spacing error area are formed by the original metal traces; Second error type: Both metal edges of the spacing error area are formed by a power fill pattern; Third error type: In the area of ​​incorrect spacing, one metal edge is formed by a power fill pattern and the other metal edge is formed by the original metal trace; If there are areas with incorrect spacing, proceed to S3; otherwise, output the layout. S3, trim a predetermined spacing width from the power fill pattern corresponding to each area with spacing errors; If it is the first error type, then find the power fill pattern connected to the first metal edge and the second metal edge along the direction perpendicular to the first metal edge and the second metal edge respectively, and cut off the predetermined spacing width in total; After cropping, return to S2 and repeat the cropping process multiple times until all spacing errors are corrected.

2. The integrated circuit design method according to claim 1, characterized in that, The power fill patterns connected to the first metal edge and the second metal are each cut to half the predetermined spacing width.

3. The integrated circuit design method according to claim 1, characterized in that, If it is the second error type, the power fill pattern forming the two metal edges is cut off by half the predetermined spacing width.

4. The integrated circuit design method according to claim 1, characterized in that, If it is the third error type, the power fill pattern forming a metal edge will be trimmed to the predetermined spacing width.

5. The integrated circuit design method according to claim 4, characterized in that, If it is the third error type, then find the power fill pattern connected to the other metal edge along the direction perpendicular to the other metal edge, and cut the power fill pattern that forms a metal edge by half the predetermined spacing width.

6. The integrated circuit design method according to claim 1, characterized in that, Step S2 includes: If the sum of the number of spacing errors of the first error type, the second error type, or the third error type is greater than 0, it is determined that there is a region with spacing errors in the current layout, and proceed to step S3.

7. The integrated circuit design method according to claim 1, characterized in that, The predetermined spacing width is 1 / 20 to 1 / 2 of the minimum spacing threshold.

8. An integrated circuit design apparatus, characterized in that, Includes a power filling module, a spacing error checking module, and a repair module; The power filling module applies power filling to the layout. The spacing error detection module checks whether the spacing between adjacent metal traces in the current layout is less than the minimum spacing threshold. If so, it determines that there is a spacing error area in the current layout and identifies the error type of the spacing error area. The error types include: First type of error: Both metal edges of the spacing error area are formed by the original metal traces; Second error type: Both metal edges of the spacing error area are formed by a power fill pattern; Third error type: In the area of ​​incorrect spacing, one metal edge is formed by a power fill pattern and the other metal edge is formed by the original metal trace; If there are areas with incorrect spacing, the repair module will fix them; otherwise, the repaired layout will be output. The repair module trims off a predetermined spacing width from the power fill pattern corresponding to each area with a spacing error, and outputs the trimmed layout to the spacing error checking module. If it is the first error type, the repair module searches for the power fill pattern connected to the first metal edge and the second metal edge along the direction perpendicular to the first metal edge and the second metal edge, and cuts off the predetermined spacing width. After cropping, the result is output to the spacing error checking module. Through multiple iterations of cropping, all spacing errors are corrected.

9. The integrated circuit design apparatus according to claim 8, characterized in that, The repair module will cut the power fill patterns connected to the first metal edge and the second metal to half the predetermined spacing width.

10. The integrated circuit design apparatus according to claim 8, characterized in that, If it is the second error type, the repair module will cut the power fill pattern of the two metal edges by half the predetermined spacing width.

11. The integrated circuit design apparatus according to claim 10, characterized in that, If it is the third error type, the repair module will form a power fill pattern with a metal edge trimmed to the predetermined spacing width.

12. The integrated circuit design apparatus according to claim 10, characterized in that, If it is the third error type, the repair module searches for a power fill pattern connected to the other metal edge along the direction perpendicular to the other metal edge, and cuts off half of the predetermined spacing width of the power fill pattern that forms a metal edge.

13. The integrated circuit design apparatus according to claim 8, characterized in that, If the sum of the number of spacing errors of the first error type, the second error type, or the third error type detected by the spacing error detection module is greater than 0, it determines that there is a region with spacing errors in the current layout and activates the repair module.

14. The integrated circuit design apparatus according to claim 8, characterized in that, The predetermined spacing width is less than 1 / 20 to 1 / 2 of the minimum spacing threshold.

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