Pixel circuit and display device including the same

Abstract

Disclosed in embodiments are a pixel circuit and a display device including the same. The pixel circuit according to an embodiment includes a first pixel circuit connected in parallel to an initialization voltage line to which an initialization voltage is applied, and including a first-first switching element connected to a first-first gate line and a first-second switching element connected to a first-second gate line, and a second pixel circuit connected in parallel to the initialization voltage line, and including a second-first switching element connected to a second-first gate line and a second-second switching element connected to a second-second gate line, and the first-second gate line is electrically connected to the second-first gate line.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2021-0090004, filed on July 8, 2021, and Korean Patent Application No. 10-2021-0183586, filed on December 21, 2021, the disclosure of which is incorporated herein by reference in its entirety. background 1. Technical Field

[0004] This disclosure relates to pixel circuits and display devices including such pixel circuits. 2. Background Technology

[0006] Display devices include liquid crystal displays (LCDs), electroluminescent displays, field emission displays (FEDs), plasma display panels (PDPs), etc.

[0007] Electroluminescent display devices are classified into inorganic and organic light-emitting display devices based on the material of their light-emitting layer. Active-matrix organic light-emitting display devices use self-emissive elements such as organic light-emitting diodes (hereinafter referred to as "OLEDs") to reproduce input images. The advantages of organic light-emitting display devices include fast response time, high luminous efficiency, brightness, and wide viewing angle.

[0008] Some display devices, such as liquid crystal displays or organic light-emitting diode displays, include: a display panel comprising multiple sub-pixels; a driver that outputs drive signals for driving the display panel; and a power supply that generates power to be supplied to the display panel or the driver. The driver includes: a gate driver that supplies scan signals or gate signals to the display panel; and a data driver that supplies data signals to the display panel.

[0009] In such a display device, when drive signals such as scan signals, EM signals and data signals are supplied to multiple sub-pixels formed in the display panel, the selected sub-pixels transmit light or emit light directly, thereby displaying an image. Summary of the Invention

[0010] However, because the planar cathode electrode structure is applied to all pixels in the display panel, the impact of low-potential power supply voltage (EVSS) ripple is significant. That is, in pixels with internal compensation circuitry, pixel rows subjected to both scan pulses and sensing pulses are affected by each other's low-potential power supply voltage ripple during voltage charging. This low-potential power supply voltage ripple is generated when the voltage at the source node of the driving element changes rapidly, thus requiring methods to prevent rapid changes in the source node voltage.

[0011] This disclosure aims to address all the aforementioned necessities and issues.

[0012] This disclosure provides a pixel circuit for reducing low-potential power supply voltage ripple, and also provides a display device including the pixel circuit.

[0013] It should be noted that the purpose of this disclosure is not limited to the above-described purposes, and other purposes of this disclosure will be apparent to those skilled in the art from the following description.

[0014] The pixel circuit according to this disclosure includes: a first pixel circuit connected in parallel to an initialization voltage line to which an initialization voltage is applied, and including a first-first switching element connected to a first-first gate line and a first-second switching element connected to a first-second gate line; and a second pixel circuit connected in parallel to the initialization voltage line, and including a second-first switching element connected to a second-first gate line and a second-second switching element connected to a second-second gate line, wherein the first-second gate line is electrically connected to the second-first gate line.

[0015] The display device according to this disclosure includes: a display panel having a plurality of sub-pixels, wherein each sub-pixel includes: a first pixel circuit, the first pixel circuit being connected in parallel to an initialization voltage line to which an initialization voltage is applied, and including a first-first switching element connected to a first-first gate line and a first-second switching element connected to a first-second gate line; and a second pixel circuit, the second pixel circuit being connected in parallel to the initialization voltage line, and including a second-first switching element connected to a second-first gate line and a second-second switching element connected to a second-second gate line, wherein the first-second gate line is electrically connected to the second-first gate line.

[0016] The pixel circuit according to this disclosure includes: a first switching element and a second switching element connected in parallel to an initialization voltage line to which an initialization voltage is applied, wherein the first switching element and the second switching element are applied an initialization pulse, and the pixel circuit is configured to share the initialization pulse with other pixel circuits spaced apart from the pixel circuit by a predetermined number of pixel rows.

[0017] According to this disclosure, by connecting two switching elements in parallel to an initialization voltage line to which an initialization voltage is applied, the dropgap of the source node voltage of the driving element can be reduced through two initialization sections, thereby reducing the low-potential power supply voltage ripple that occurs during voltage charging.

[0018] This disclosure can minimize in-plane charging non-uniformity by reducing low-potential supply voltage ripple.

[0019] The effects of this disclosure are not limited to those described above, and those skilled in the art will clearly understand, based on the following description and the appended claims, other effects not mentioned. Attached Figure Description

[0020] The above and other objects, features, and advantages of this disclosure will become more apparent to those skilled in the art from the exemplary embodiments described in detail with reference to the accompanying drawings, in which:

[0021] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0022] Figure 2 It is shown Figure 1 A diagram showing the cross-sectional structure of the display panel;

[0023] Figure 3 This is a diagram illustrating a pixel circuit according to an embodiment of the present disclosure;

[0024] Figure 4 It is shown Figure 3 The diagram shows the driving timing of the pixel circuit.

[0025] Figure 5 and Figure 6 This is a diagram illustrating the connection principle of a pixel circuit according to an embodiment of the present disclosure;

[0026] Figure 7 This is a diagram showing the connection relationship of the pixel circuit according to the first embodiment of the present disclosure;

[0027] Figure 8 It is shown Figure 7 The diagram shows the driving timing of the pixel circuit.

[0028] Figures 9A to 9C It is shown Figure 7 The diagram shows the connection relationship of the pixel circuits;

[0029] Figure 10 This is a diagram showing the connection relationship of the pixel circuit according to the second embodiment of the present disclosure;

[0030] Figure 11 It is shown Figure 10 The diagram shows the driving timing of the pixel circuit; and

[0031] Figures 12A to 12C It is shown Figure 10 The diagram shows the connection relationship of the pixel circuit. Detailed Implementation

[0032] The advantages and features of this disclosure, as well as the methods for implementing this disclosure, will become more clearly understood from the embodiments described below with reference to the accompanying drawings. However, this disclosure is not limited to the following embodiments, but can be implemented in various different forms. Rather, these embodiments will make the disclosure complete and enable those skilled in the art to fully understand the scope of this disclosure. This disclosure is defined only within the scope of the appended claims.

[0033] The shapes, dimensions, ratios, angles, numbers, etc., shown in the accompanying drawings to describe embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout this specification, the same reference numerals generally denote the same elements. Furthermore, in describing this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure.

[0034] Terms such as “including,” “comprising,” “having,” and “consisting of” used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Any reference to the singular may include the plural unless explicitly stated otherwise.

[0035] Even without explicit explanation, components are interpreted as including the normal tolerance range.

[0036] When using terms such as “on top of,” “above,” “below,” and “beside” to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless these terms are used with the terms “immediately adjacent” or “directly.”

[0037] The terms “first”, “second”, etc., can be used to distinguish components from each other, but the function or structure of a component is not limited by the serial number or name preceding the component.

[0038] Throughout this disclosure, the same reference numerals may refer to substantially the same elements.

[0039] The following implementations may be partially or wholly combined or integrated with each other, and may be technically linked and operated in various ways. The implementations may be performed independently of each other or in relation to each other.

[0040] In the following, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0041] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure, and Figure 2 It is shown Figure 1 The diagram shows the cross-sectional structure of the display panel.

[0042] Reference Figure 1 The display device according to embodiments of the present disclosure includes: a display panel 100; a display panel driving circuit for writing pixel data to pixels of the display panel 100; and a power supply 140 for generating power required to drive the pixels and the display panel driving circuit.

[0043] The display panel 100 includes a pixel array AA for displaying an input image. The pixel array AA includes: a plurality of data lines 102; a plurality of gate lines 103 intersecting the data lines 102; and pixels arranged in a matrix.

[0044] The pixel array AA includes multiple pixel rows L1 to Ln. Each of the pixel rows L1 to Ln includes a row of pixels arranged along the row direction X in the pixel array AA of the display panel 100. Pixels arranged on a pixel row share a gate line 103. Sub-pixels arranged along the data line direction Y share the same data line 102. A horizontal time period 1H is the time obtained by dividing a frame time period by the total number of pixel rows L1 to Ln.

[0045] A touch sensor can be installed on the display panel 100. Touch input can be sensed using a separate touch sensor, or it can be sensed by pixels. The touch sensor can be set as an on-cell type or add-on type on the screen of the display panel, or it can be implemented as an in-cell type touch sensor embedded in the pixel array AA.

[0046] The display panel 100 can be implemented as a flexible display panel. The flexible display panel can be made of a plastic OLED panel. An organic thin film can be disposed on the back of the plastic OLED panel, and a pixel array AA can be formed on the organic thin film.

[0047] The backsheet of a plastic OLED can be a polyethylene terephthalate (PET) substrate. An organic thin film is formed on the backsheet. Pixel arrays (AA) and touch sensor arrays can be formed on the organic thin film. The backsheet prevents moisture penetration, thus protecting the pixel arrays (AA) from moisture. The organic thin film can be a thin polyimide (PI) film substrate. Multilayer buffer films (not shown) can be formed on the organic thin film using an insulating material. Lines can be formed on the organic thin film to supply power or signals applied to the pixel arrays (AA) and touch sensor arrays.

[0048] To achieve color, each pixel can be divided into a red subpixel (hereinafter referred to as "R subpixel"), a green subpixel (hereinafter referred to as "G subpixel"), and a blue subpixel (hereinafter referred to as "B subpixel"). Each pixel may also include a white subpixel. Each of the subpixels 101 includes pixel circuitry. The pixel circuitry is connected to data line 102 and gate line 103.

[0049] In the following text, a pixel can be interpreted as having the same meaning as a subpixel.

[0050] like Figure 2 As shown, when viewed from a cross-sectional view, the display panel 100 may include a circuit layer 12, a light-emitting element layer 14, and an encapsulation layer 16 stacked on the substrate 10.

[0051] Circuit layer 12 may include: pixel circuitry connected to wiring such as data lines, gate lines, and power lines; gate drivers (GIPs) connected to the gate lines; a demultiplexer array 112; circuitry (not shown) for automated probe inspection, etc. The wiring and circuitry elements of circuit layer 12 may include: multiple insulating layers; two or more metal layers separated by an insulating layer between them; and an active layer comprising semiconductor material. All transistors formed in circuit layer 12 may be implemented as oxide TFTs having an n-channel oxide semiconductor.

[0052] The light-emitting element layer 14 may include light-emitting elements EL driven by pixel circuitry. The light-emitting elements EL may include red (R) light-emitting elements, green (G) light-emitting elements, and blue (B) light-emitting elements. The light-emitting element layer 14 may include white light-emitting elements and color filters. The light-emitting elements EL of the light-emitting element layer 14 may be covered by a protective layer comprising an organic film and a passivation film.

[0053] Encapsulation layer 16 covers light-emitting element layer 14 to seal circuit layer 12 and light-emitting element layer 14. Encapsulation layer 16 may have a multilayer insulating structure in which organic and inorganic films are alternately stacked. The inorganic film blocks the penetration of moisture and oxygen. The organic film planarizes the surface of the inorganic film. When organic and inorganic films are stacked into multiple layers, the movement path of moisture or oxygen becomes longer compared to a single layer, thereby effectively blocking the penetration of moisture and oxygen that affect light-emitting element layer 14.

[0054] A touch sensor layer can be disposed on the encapsulation layer 16. The touch sensor layer may include a capacitive touch sensor that senses touch input based on capacitance changes before and after the touch input. The touch sensor layer may include a metal wiring pattern forming the capacitor of the touch sensor and an insulating layer. The capacitor of the touch sensor may be formed between the metal wiring patterns. A polarizer may be disposed on the touch sensor layer. The polarizer can improve visibility and contrast by converting the polarization of external light reflected by the metal of the touch sensor layer and circuit layer 12. The polarizer may be implemented as a polarizer in which a linear polarizer and a phase retardation film are bonded, or as a circular polarizer. A cover glass may be adhered to the polarizer.

[0055] The display panel 100 may further include a touch sensor layer and a color filter layer stacked on the encapsulation layer 16. The color filter layer may include red, green, and blue color filters, as well as a black matrix pattern. The color filter layer can replace a polarizer and increases color purity by absorbing certain wavelengths of light reflected from the circuit layer and the touch sensor layer. In this embodiment, by applying a color filter layer 20 with a higher transmittance than a polarizer to the display panel, the transmittance of the display panel PNL can be improved, as can the thickness and flexibility of the display panel PNL. A cover glass may be adhered to the color filter layer.

[0056] Power supply 140 generates the DC power required to drive the pixel array AA and display panel driving circuitry of display panel 100 using a DC-DC converter. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc. Power supply 140 can adjust the DC input voltage from a host system (not shown) and thereby generate DC voltages such as a gamma reference voltage VGMA, gate on-state voltages VGH and VEH, gate off-state voltages VGL and VEL, pixel drive voltage EVDD, and pixel low-level power supply voltage EVSS. The gamma reference voltage VGMA is supplied to data driver 110. The gate on-state voltages VGH and VEH and the gate off-state voltages VGL and VEL are supplied to gate driver 120. The pixel drive voltage EVDD and the pixel low-level power supply voltage EVSS are jointly supplied to the pixels.

[0057] Under the control of the timing controller (TCON) 130, the display panel driving circuit writes the pixel data (digital data) of the input image into the pixels of the display panel 100.

[0058] The display panel driving circuit includes a data driver 110 and a gate driver 120.

[0059] A demultiplexer (DEMUX) 112 can be placed between the data driver 110 and the data lines 102. The demultiplexer 112 sequentially connects one channel of the data driver 110 to multiple data lines 102 and distributes the data voltage output from one channel of the data driver 110 to the data lines 102 in a time-division manner, thereby reducing the number of channels of the data driver 110. The demultiplexer array 112 can be omitted. In this case, the output buffer AMP of the data driver 110 is directly connected to the data lines 102.

[0060] The display panel driving circuit may also include a touch sensor driver for driving the touch sensor. Figure 1 The touch sensor driver is omitted. In mobile devices, the timing controller 130, power supply 140, data driver 110, etc., can be integrated into a single driver integrated circuit (IC).

[0061] Data driver 110 generates a data voltage Vdata by converting pixel data of the input image received from timing controller 130 for each frame period into a gamma-compensated voltage using a digital-to-analog converter (DAC). The gamma reference voltage VGMA is divided into individual gray levels by a voltage divider circuit. The gamma-compensated voltages divided from the gamma reference voltage VGMA are provided to the DAC of data driver 110. The data voltage Vdata is output through the output buffer AMP in each channel of data driver 110.

[0062] In the data driver 110, the output buffer AMP included in one channel can be connected to the adjacent data line 102 via the demultiplexer array 112. The demultiplexer array 112 can be formed directly on the substrate of the display panel 100, or integrated into a driver IC together with the data driver 110.

[0063] The gate driver 120 can be implemented as an in-panel gate (GIP) circuit directly formed on the bezel BZ region of the display panel 100 along with the TFT array of the pixel array AA. Under the control of the timing controller 130, the gate driver 120 sequentially outputs the gate signal to the gate line 103. The gate driver 120 can also sequentially supply the gate signal to the gate line 103 by using a shift register to shift the gate signal.

[0064] The gate signal may include: a scan signal for selecting a pixel that writes data in sync with the data voltage; and an EM signal for defining the emission time of the pixel when it is charged with the data voltage.

[0065] The gate driver 120 may include a scan driver 121, an EM driver 122, and an initialization driver 123.

[0066] Scan driver 121 outputs a scan signal SCAN in response to a start pulse and a shift clock from timing controller 130, and shifts the scan signal SCAN according to the shift clock timing. EM driver 122 outputs an EM signal EM in response to a start pulse and a shift clock from timing controller 130, and shifts the EM signal EM sequentially according to the shift clock. Initialization driver 123 outputs an initialization signal INIT in response to a start pulse and a shift clock from timing controller 130, and shifts the initialization signal INIT according to the shift clock timing. Therefore, the scan signal SCAN, the EM signal EM, and the initialization signal INIT are sequentially supplied to the gate lines 103 of pixel rows L1 to Ln. In the borderless model, at least some of the transistors constituting gate driver 120 and the clock wiring can be distributed throughout the pixel array AA.

[0067] The timing controller 130 receives digital video data DATA of the input image and timing signals synchronized with it from the host system (not shown). The timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a master clock CLK, and a data enable signal DE. Since the vertical and horizontal time periods can be determined by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE has a period of one horizontal time period (1H).

[0068] The host system can be any of the following: a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a vehicle system, and a mobile device system.

[0069] The timing controller 130 multiplies the input frame frequency by i and controls the operation timing of the display panel driver circuit with a frame frequency of input frame frequency × i (i is a positive integer greater than 0) Hz. The input frame frequency is 60 Hz in the NTSC (National Television Standards Committee) scheme and 50 Hz in the PAL (Progressive Line Inverter) scheme.

[0070] Based on the timing signals Vsync, Hsync, and DE received from the host system, the timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110, MUX signals MUX1 and MUX2 for controlling the operation timing of the demultiplexer array 112, and a gate timing control signal for controlling the operation timing of the gate driver 120.

[0071] The voltage level of the gate timing control signal output from the timing controller 130 can be converted into gate on-state voltages VGH and VEH and gate off-state voltages VGL and VEL by a level shifter (not shown), and then supplied to the gate driver 120. That is, the level shifter converts the low-level voltage of the gate timing control signal into the gate off-state voltages VGL and VEL, and converts the high-level voltage of the gate timing control signal into the gate on-state voltages VGH and VEH. The gate timing signal includes a start pulse and a shift clock.

[0072] In embodiments of this disclosure, an initialization transistor is added to reduce the impact of low-potential power supply voltage ripple on charging, and a pre-initialization section is added before the initialization section to improve the low-potential power supply voltage ripple generated during charging.

[0073] Figure 3 This is a diagram illustrating a pixel circuit according to an embodiment of the present disclosure, and Figure 4 It is shown Figure 3 The diagram shows the driving timing of the pixel circuit.

[0074] Reference Figure 3 and Figure 4 The pixel circuit according to embodiments of this disclosure includes: a light-emitting element EL; a driving element DT for supplying current to the light-emitting element EL; a plurality of switching elements M01, M02, M03 and M04 for switching current paths connected to the driving element DT; and a capacitor Cst for storing the gate-source voltage of the driving element DT. The driving element DT and the plurality of switching elements M01, M02, M03 and M04 can be implemented as an N-channel oxide TFT.

[0075] The light-emitting element EL emits light by applying current through the channel of the driving element DT according to the gate-source voltage Vgs of the driving element DT, which varies according to the data voltage Vdata. The light-emitting element EL can be implemented as an OLED comprising an organic compound layer formed between the anode and cathode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emissive layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The anode of the light-emitting element EL is connected to the driving element DT through a third node n3, and the cathode of the light-emitting element EL is connected to a second power line 42 to which a low-potential power supply voltage EVSS is applied.

[0076] Organic light-emitting diodes (OLEDs) used as light-emitting elements can have a series structure in which multiple light-emitting layers are stacked. OLEDs with a series structure can improve pixel brightness and lifespan.

[0077] The driving element DT drives the light-emitting element EL by supplying current to the light-emitting element EL according to the gate-source voltage Vgs. The driving element DT includes: a gate electrode connected to the first node n1; a first electrode connected to the first power line 41 to which the pixel driving voltage EVDD is applied; and a second electrode connected to the second node n2.

[0078] The first switching element M01 is turned on by the first initialization signal INIT1 and applies an initialization voltage Vinit to the first node n1. The first switching element M01 can be turned on during the first initialization period (Pre-initial) and apply the initialization voltage Vinit to the first node n1. The first switching element M01 includes: a first electrode connected to the third power line 43 to which the initialization voltage is applied; a gate electrode to which the first initialization signal is applied; and a second electrode connected to the first node n1.

[0079] The second switching element M02 is turned on by the second initialization signal INIT2 and applies an initialization voltage Vinit to the first node n1. The second switching element M02 can be turned on during the second initialization period Initial and apply the initialization voltage Vinit to the first node n1. The second switching element M02 includes: a first electrode connected to a third power line 43 to which the initialization voltage is applied; a gate electrode to which the second initialization signal is applied; and a second electrode connected to the first node n1.

[0080] The third switching element M03 is turned on by the scan signal SCAN and applies a data voltage to the first node n1. The third switching element M03 includes: a first electrode connected to the fourth power line 44 to which the data voltage is applied; a gate electrode to which the scan signal is applied; and a second electrode connected to the first node n1.

[0081] The fourth switching element M04 is turned on by the sensing signal SENSE and applies a reference voltage Vref to the second node n2. The fourth switching element M04 includes: a first electrode connected to the second node n2; a gate electrode to which the sensing signal is applied; and a second electrode connected to the fifth power line 45 to which the reference voltage is applied.

[0082] The capacitor Cst stores the gate-source voltage of the driving element DT. The capacitor is connected between the first node n1 and the second node n2.

[0083] like Figure 4 As shown, the pixel circuit can be driven in the following order: first initialization step Tini1, second initialization step Tini2, sensing step Ts, data writing step Tw, and light emission step Tem.

[0084] In the pixel circuit, the first switching element M01 can be turned on in the first initialization step Tini1 to initialize the first node for the first time, and the second switching element M02 can be turned on in the second initialization step Tini2 to initialize the first node for the second time. By using the two initialization processes of the first switching element M01 and the second switching element M02—that is, the primary initialization process and the secondary initialization process—the source voltage of the driving element DT, i.e., the voltage of the second node n2, is reduced twice to decrease its fluctuation range. This can reduce the EVSS ripple that occurs during voltage charging.

[0085] In the sensing step Ts following the second initialization step Tini2, the threshold voltage Vth of the driving element DT can be sensed and stored in the capacitor Cst. Subsequently, in the data writing step Tw, the data voltage Vdata of the pixel data can be applied to the second node n2. Subsequently, in the emission step Tem, the light-emitting element EL can emit light with a brightness corresponding to the grayscale value of the pixel data.

[0086] Figure 5 and Figure 6 This is a diagram illustrating the connection principle of a pixel circuit according to an embodiment of the present disclosure.

[0087] Reference Figure 5 In this embodiment, the initialization pulse applied to the pixel circuit located in the current pixel row is shared with the pixel circuit located in the next pixel row, thereby initializing the next pixel row.

[0088] Therefore, the pixel circuit may further include a switching element capable of sharing the initialization pulse with pixel circuits located in the previous pixel row or the next pixel row. Thus, the pixel circuit of this embodiment may include two switching elements to which an initialization pulse is applied. The two switching elements are connected in parallel to an initialization voltage line to which an initialization voltage is applied, and are turned on when the initialization pulse is applied, but they may be turned on in different sections.

[0089] In one example, when an initialization pulse is applied to the second switching element M02 of the eleventh pixel circuit PX11, the initialization pulse is also applied to the first switching element M01 of the twenty-first pixel circuit PX21, so that the two switching elements can be turned on.

[0090] In another example, when an initialization pulse is applied to the second switching element M02 of the twelfth pixel circuit PX12, the initialization pulse is also applied to the first switching element M01 of the twenty-second pixel circuit PX22, so that the two switching elements can be turned on.

[0091] In the above scenario, the eleventh pixel circuit PX11 and the twenty-first pixel circuit PX21 can be configured to share an initialization pulse, and the twelfth pixel circuit PX12 and the twenty-second pixel circuit PX22 can also be configured to share an initialization pulse. In this case, the pixel circuits sharing the initialization pulse may not be located in adjacent pixel rows, but rather in pixel rows spaced apart from each other. This is to prevent the first and second initialization portions from overlapping.

[0092] like Figure 6 As shown, the arrangement interval between pixel circuits sharing an initialization pulse can be set by considering a horizontal time period of 1H and the initialization time. In this case, the arrangement interval between pixel circuits can be set to be equal to or greater than the value obtained by dividing the initialization time by a horizontal time period of 1H, and can vary according to resolution, frequency, initialization time, etc.

[0093] For example, in the case where the horizontal time interval is 5μs and the initialization time is 150μs, the arrangement interval between the two pixel circuits sharing the initialization pulse can be at least 30 (150 / 5) pixel rows.

[0094] Figure 7 This is a diagram illustrating the connection relationship of the pixel circuit according to the first embodiment of this disclosure. Figure 8 It is shown Figure 7 The diagram shows the driving timing of the pixel circuit, and Figures 9A to 9C It is shown Figure 7 The diagram shows the connection relationship of the pixel circuit.

[0095] Reference Figure 7 Based on the connection relationship with the pixel circuits sharing the initialization pulse, the pixel circuits according to the first embodiment of this disclosure are mainly divided into three groups: a first pixel group PXG1, a second pixel group PXG2, and a third pixel group PXG3. In this case, the gate lines of each of the first pixel group PXG1, the second pixel group PXG2, and the third pixel group PXG3 are connected to the first signal transmission group STG1, the second signal transmission group STG2, and the third signal transmission group STG3, and an initialization pulse can be applied through the gate lines. For example, the gate line of the second switching element M02 in the first pixel circuit PX1 in the first pixel group PXG1 is connected to ST1 in the first signal transmission group STG1; the gate line of the second switching element M02 in the second pixel circuit PX2 in the second pixel group PXG2 is connected to ST2 in the second signal transmission group STG2; and the gate line of the second switching element M02 in the third pixel circuit PX3 in the third pixel group PXG3 is connected to ST3 in the third signal transmission group STG3.

[0096] The three-group scenario is described here as an example, but this disclosure is not limited thereto. The number of groups can vary depending on the arrangement spacing between pixel circuits sharing a gate line.

[0097] like Figure 8 As shown, there may be only one initialization part in the first pixel group PXG1, and there may be two initialization parts in each of the second pixel group PXG2 and the third pixel group PXG3.

[0098] The gate line of the second switching element M02 in the first pixel circuit PX1 located in the first pixel group PXG1, through which the initialization pulse is applied, can be connected to the first switching element M01 in the second pixel circuit PX2 located in the second pixel group PXG2.

[0099] Reference Figure 9A Since the first pixel circuit PX1 in the first pixel group PXG1 has no previous pixel row, there are no two initialization parts and only one initialization part can exist.

[0100] The first-first gate line GL1a of the first switching element M01 connected to the first pixel circuit PX1 is in a floating state in which no initialization pulse is applied, and the second switching element M02 can be turned on during the initialization period via an initialization pulse applied through the first-second gate line GL1b.

[0101] In the initialization section, an initialization pulse is applied to the second switching element M02 in the first pixel circuit PX1, and the initialization pulse can also be applied to the first switching element M01 in the second pixel circuit PX2 located in the second pixel group PXG2.

[0102] The gate line of the second switching element M02 in the second pixel circuit PX2 located in the second pixel group PXG2, through which the initialization pulse is applied, can be connected to the first switching element M01 in the third pixel circuit PX3 located in the third pixel group PXG3.

[0103] Reference Figure 9B Since the second pixel circuit PX2 located in the second pixel group PXG2 has the previous pixel row and the next pixel row, there can be two initialization parts.

[0104] The first switching element M01 can be turned on in the first initialization portion via an initialization pulse applied through the second-first gate line GL2a, and the second switching element M02 can be turned on in the second initialization portion via an initialization pulse applied through the second-second gate line GL2b.

[0105] The second-first gate line GL2a can be electrically connected to the first-second gate line GL1b.

[0106] In the first initialization section, an initialization pulse applied to the second switching element M02 in the first pixel circuit PX1 located in the first pixel group PXG1 can be applied to the first switching element M01 in the second pixel circuit PX2.

[0107] In the second initialization section, an initialization pulse is applied to the second switching element M02 in the second pixel circuit PX2, and the initialization pulse may also be applied to the first switching element M01 in the third pixel circuit PX3 located in the third pixel group PXG3.

[0108] Since the third pixel circuit PX3 in the third pixel group PXG3 has no next pixel row, there are no two initialization periods and only one initialization part can exist.

[0109] Reference Figure 9C The third pixel circuit PX3, located in the third pixel group PXG3, has the previous pixel row but no next pixel row, but it can have two initialization parts.

[0110] The first switching element M01 can be turned on in the first initialization section via an initialization pulse applied through the third-first gate line GL3a, and the second switching element M02 can be turned on in the second initialization section via an initialization pulse applied through the third-second gate line GL3b.

[0111] The third-first gate line GL3a can be electrically connected to the second-second gate line GL2b.

[0112] In the first initialization section, the initialization pulse applied to the second switching element M02 in the second pixel circuit PX2 located in the second pixel group PXG2 can be applied to the first switching element M01 in the third pixel circuit PX3.

[0113] In the second initialization section, an initialization pulse can be applied to the second switching element M02 in the third pixel circuit PX3.

[0114] Since the third pixel circuit PX3 in the third pixel group PXG3 does not have a next pixel row but is connected to the previous pixel row, two initialization parts can exist.

[0115] Figure 10 This is a diagram illustrating the connection relationship of the pixel circuit according to the second embodiment of this disclosure. Figure 11 It is shown Figure 10 The diagram shows the driving timing of the pixel circuit, and Figures 12A to 12C It is shown Figure 10 The diagram shows the connection relationship of the pixel circuit.

[0116] Reference Figure 10 Based on the connection relationship with the pixel circuits sharing the initialization pulse, the pixel circuits according to the second embodiment of this disclosure are mainly divided into three groups: a first pixel group PXG1-1, a second pixel group PXG2-1, and a third pixel group PXG3-1. In this case, each gate line of the first pixel group PXG1-1, the second pixel group PXG2-1, and the third pixel group PXG3-1 is connected to the first signal transmission group STG1, the second signal transmission group STG2, and the third signal transmission group STG3, and an initialization pulse can be applied through the gate lines.

[0117] The three-group scenario is described here as an example, but this disclosure is not limited thereto. The number of groups can vary depending on the arrangement spacing between pixel circuits sharing a gate line.

[0118] like Figure 11 As shown, each of the first pixel group PXG1-1, the second pixel group PXG2-1, and the third pixel group PXG3-1 may contain two initialization parts.

[0119] The first switching element M01 in the first pixel circuit PX1-1 located in the first pixel group PXG1-1 is connected to the virtual gate line DGL connected to DST1 in the virtual level DSTG, and the gate line GL1-1 of the second switching element M02 in the first pixel circuit PX1-1, which applies the initialization pulse through it, can be connected to the first switching element M01 in the second pixel circuit PX2-1 located in the second pixel group PXG2-1.

[0120] Reference Figure 12A Since the first pixel circuit PX1-1 in the first pixel group PXG1-1 has no previous pixel row, two initialization periods can exist by adding a virtual gate line connected to the virtual stage.

[0121] The first switching element can be turned on in the first initialization portion via an initialization pulse applied through the first-first gate line GL1a-1, and the second switching element can be turned on in the second initialization portion via an initialization pulse applied through the first-second gate line GL1b-1.

[0122] The first gate line GL1a-1 can be electrically connected to the virtual gate line DGL.

[0123] In the first initialization section, an initialization pulse can be applied to the first switching element M01 in the first pixel circuit PX1-1.

[0124] In the second initialization section, an initialization pulse is applied to the second switching element M02 in the first pixel circuit PX1-1, and the initialization pulse can also be applied to the first switching element M01 in the second pixel circuit PX2-1 located in the second pixel group PXG2-1.

[0125] The gate line of the second switching element M02 in the second pixel circuit PX2-1 located in the second pixel group PXG2-1, which applies the initialization pulse, can be connected to the first switching element M01 in the third pixel circuit PX3-1 located in the third pixel group PXG3-1.

[0126] Reference Figure 12B Since the second pixel circuit PX2-1 located in the second pixel group PXG2-1 has the previous pixel row and the next pixel row, there can be two initialization parts.

[0127] The first switching element can be turned on in the first initialization portion via an initialization pulse applied through the second-first gate line GL2a-1, and the second switching element can be turned on in the second initialization portion via an initialization pulse applied through the second-second gate line GL2b-1.

[0128] The second-first gate line GL2a-1 can be electrically connected to the first-second gate line GL1b-1.

[0129] In the first initialization section, the initialization pulse applied to the second switching element M02 in the first pixel circuit PX1-1 located in the first pixel group PXG1-1 can be applied to the first switching element M01 in the second pixel circuit PX2-1.

[0130] In the second initialization section, an initialization pulse is applied to the second switching element M02 in the second pixel circuit PX2-1, and the initialization pulse can also be applied to the first switching element M01 in the third pixel circuit PX3-1 located in the third pixel group PXG3-1.

[0131] Since the third pixel circuit PX3-1 in the third pixel group PXG3-1 has no next pixel row, there are no two initialization parts and only one initialization part can exist.

[0132] Reference Figure 12C The third pixel circuit PX3-1 in the third pixel group PXG3-1 has the previous pixel row but no next pixel row, but it can have two initialization parts.

[0133] The first switching element M01 can be turned on in the first initialization section via an initialization pulse applied through the third-first gate line GL3a-1, and the second switching element M02 can be turned on in the second initialization section via an initialization pulse applied through the third-second gate line GL3b-1.

[0134] The third-first gate line GL3a-1 can be electrically connected to the second-second gate line GL2b-1.

[0135] In the first initialization section, the initialization pulse applied to the second switching element M02 in the second pixel circuit PX2-1 located in the second pixel group PXG2-1 can be applied to the first switching element M01 in the third pixel circuit PX3-1.

[0136] In the second initialization section, an initialization pulse can be applied to the second switching element M02 in the third pixel circuit PX3-1.

[0137] Since the third pixel circuit PX3-1 in the third pixel group PXG3-1 is not connected to the previous pixel row but has no next pixel row, both initialization parts can exist.

[0138] While embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto, and the present disclosure may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in this disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all respects and do not limit the present disclosure. The scope of protection of this disclosure should be interpreted based on the appended claims, and all technical concepts within their equivalents should be interpreted as falling within the scope of this disclosure.

Claims

1. A pixel circuit, comprising: The first pixel circuit includes a first driving element, a first-first switching element, and a first-second switching element. The first-first switching element and the first-second switching element are connected in parallel between an initialization voltage line to which an initialization voltage is applied and a first-first node connected to the gate electrode of the first driving element. The first-first switching element is connected to a first-first gate line, and the first-second switching element is connected to a first-second gate line. as well as The second pixel circuit includes a second driving element, a second-first switching element, and a second-second switching element. The second-first switching element and the second-second switching element are connected in parallel between the initialization voltage line and the second-first node connected to the gate electrode of the second driving element. The second-first switching element is connected to the second-first gate line, and the second-second switching element is connected to the second-second gate line. The first-second gate line is electrically connected to the second-first gate line.

2. The pixel circuit according to claim 1, wherein, The first pixel circuit includes the first driving element, the first-first switching element, the first-second switching element, the first-third switching element, and the first-fourth switching element. The first driving element includes a first electrode connected to a pixel driving voltage line, a gate electrode connected to the first node, and a second electrode connected to the second node. The first-first switching element includes a first electrode connected to the initialization voltage line, a gate electrode connected to the first-first gate line, and a second electrode connected to the first-first node. The first and second switching elements include a first electrode connected to the initialization voltage line, a gate electrode connected to the first and second gate lines, and a second electrode connected to the first node. The first and third switching elements include a first electrode connected to a data voltage line, a gate electrode to which a scan pulse is applied, and a second electrode connected to the first node. The first-fourth switching element includes a first electrode connected to the first-second node, a gate electrode to which a sensing pulse is applied, and a second electrode connected to a reference voltage line.

3. The pixel circuit according to claim 2, wherein, In the first pixel circuit The first-first gate line is in a floating state, and When an initialization pulse is applied to the first-second gate line during the initialization section, the first-second switching element is turned on to apply the initialization voltage to the first-first node.

4. The pixel circuit according to claim 2, wherein, The first gate line is connected to the dummy gate line. When an initialization pulse is applied from the virtual gate line in the first initialization section, the first-first switching element is turned on to apply the initialization voltage to the first-first node for the first time, and When an initialization pulse is applied to the first-second gate line in the second initialization section, the first-second switching element is turned on to apply the initialization voltage to the first-first node for the second time.

5. The pixel circuit according to claim 2, wherein, The second pixel circuit includes a second driving element, a second-first switching element, a second-second switching element, a second-third switching element, and a second-fourth switching element. The second driving element includes a first electrode connected to a pixel driving voltage line, a gate electrode connected to the second-first node, and a second electrode connected to the second-second node. The second-first switching element includes a first electrode connected to the initialization voltage line, a gate electrode connected to the second-first gate line, and a second electrode connected to the second-first node. The second-second switching element includes a first electrode connected to the initialization voltage line, a gate electrode connected to the second-second gate line, and a second electrode connected to the second-first node. The second-third switching element includes a first electrode connected to a data voltage line, a gate electrode to which a scan pulse is applied, and a second electrode connected to the second-first node. The second-fourth switching element includes a first electrode connected to the second-second node, a gate electrode to which a sensing pulse is applied, and a second electrode connected to a reference voltage line.

6. The pixel circuit according to claim 5, wherein, The second-to-second gate line is electrically connected to the gate line of the next pixel row. When an initialization pulse is applied to the first-second gate line in the first initialization section, the second-first switching element is turned on to apply the initialization voltage to the second-first node for the first time, and When an initialization pulse is applied to the second-second gate line in the second initialization section, the second-second switching element is turned on to apply the initialization voltage to the second-first node for the second time.

7. The pixel circuit according to claim 5, wherein, The second-to-second gate line is not electrically connected to the gate line of the next pixel row. When an initialization pulse is applied to the first-second gate line in the first initialization section, the second-first switching element is turned on to apply the initialization voltage to the second-first node for the first time, and When an initialization pulse is applied to the second-second gate line in the second initialization section, the second-second switching element is turned on to apply the initialization voltage to the second-first node.

8. The pixel circuit according to claim 1, wherein, The second pixel circuit is spaced apart from the first pixel circuit by a predetermined number of pixel rows k, where k is a positive integer.

9. The pixel circuit according to claim 8, wherein, The k is an integer greater than or equal to the value obtained by dividing the initialization time by the time of a horizontal time interval.

10. A display device, comprising: A display panel, wherein multiple sub-pixels are provided; Each sub-pixel includes: A first pixel circuit, comprising a first driving element, a first-first switching element, and a first-second switching element, wherein the first-first switching element and the first-second switching element are connected in parallel between an initialization voltage line to which an initialization voltage is applied and a first-first node connected to the gate electrode of the first driving element; the first-first switching element is connected to a first-first gate line, and the first-second switching element is connected to a first-second gate line; and The second pixel circuit includes a second driving element, a second-first switching element, and a second-second switching element. The second-first switching element and the second-second switching element are connected in parallel between the initialization voltage line and the second-first node connected to the gate electrode of the second driving element. The second-first switching element is connected to the second-first gate line, and the second-second switching element is connected to the second-second gate line. The first-second gate line is electrically connected to the second-first gate line.

11. The display device according to claim 10, wherein, The first pixel circuit includes the first driving element, the first-first switching element, the first-second switching element, the first-third switching element, and the first-fourth switching element. The first driving element includes a first electrode connected to a pixel driving voltage line, a gate electrode connected to the first node, and a second electrode connected to the second node. The first-first switching element includes a first electrode connected to the initialization voltage line, a gate electrode connected to the first-first gate line, and a second electrode connected to the first-first node. The first and second switching elements include a first electrode connected to the initialization voltage line, a gate electrode connected to the first and second gate lines, and a second electrode connected to the first node. The first and third switching elements include a first electrode connected to a data voltage line, a gate electrode to which a scan pulse is applied, and a second electrode connected to the first node. The first-fourth switching element includes a first electrode connected to the first-second node, a gate electrode to which a sensing pulse is applied, and a second electrode connected to a reference voltage line.

12. The display device according to claim 11, wherein, In the first pixel circuit The first-first gate line is in a floating state, and When an initialization pulse is applied to the first-second gate line during the initialization section, the first-second switching element is turned on to apply the initialization voltage to the first-first node.

13. The display device according to claim 11, wherein, The first gate line is connected to the dummy gate line. When an initialization pulse is applied from the virtual gate line in the first initialization section, the first-first switching element is turned on to apply the initialization voltage to the first-first node for the first time, and When an initialization pulse is applied to the first-second gate line in the second initialization section, the first-second switching element is turned on to apply the initialization voltage to the first-first node for the second time.

14. The display device according to claim 11, wherein, The second pixel circuit includes a second driving element, a second-first switching element, a second-second switching element, a second-third switching element, and a second-fourth switching element. The second driving element includes a first electrode connected to a pixel driving voltage line, a gate electrode connected to the second-first node, and a second electrode connected to the second-second node. The second-first switching element includes a first electrode connected to the initialization voltage line, a gate electrode connected to the second-first gate line, and a second electrode connected to the second-first node. The second-second switching element includes a first electrode connected to the initialization voltage line, a gate electrode connected to the second-second gate line, and a second electrode connected to the second-first node. The second-third switching element includes a first electrode connected to a data voltage line, a gate electrode to which a scan pulse is applied, and a second electrode connected to the second-first node. The second-fourth switching element includes a first electrode connected to the second-second node, a gate electrode to which a sensing pulse is applied, and a second electrode connected to a reference voltage line.

15. The display device according to claim 14, wherein, The second-to-second gate line is electrically connected to the gate line of the next pixel row. When an initialization pulse is applied to the first-second gate line in the first initialization section, the second-first switching element is turned on to apply the initialization voltage to the second-first node for the first time, and When an initialization pulse is applied to the second-second gate line in the second initialization section, the second-second switching element is turned on to apply the initialization voltage to the second-first node for the second time.

16. The display device according to claim 14, wherein, The second-to-second gate line is not electrically connected to the gate line of the next pixel row. When an initialization pulse is applied to the first-second gate line in the first initialization section, the second-first switching element is turned on to apply the initialization voltage to the second-first node for the first time, and When an initialization pulse is applied to the second-second gate line in the second initialization section, the second-second switching element is turned on to apply the initialization voltage to the second-first node.

17. The display device according to claim 10, wherein, The second pixel circuit is spaced apart from the first pixel circuit by a predetermined number of pixel rows k, where k is a positive integer.

18. The display device according to claim 17, wherein, The k is an integer greater than or equal to the value obtained by dividing the initialization time by the time of a horizontal time interval.

19. The display device according to claim 10, wherein, All transistors in the display panel are implemented using oxide thin-film transistors (TFTs) that include n-channel oxide semiconductors.

20. The display device according to claim 10, wherein, The display panel also includes multiple data lines, multiple gate lines intersecting the multiple data lines, and multiple power lines to which different constant voltages are applied. The display device further includes: A data driver that supplies data voltages of pixel data to the plurality of data lines; and A gate driver that supplies gate signals to the plurality of gate lines.

21. A pixel circuit, comprising: A driving element that supplies current to the light-emitting element; A first switching element and a second switching element are connected in parallel between an initialization voltage line to which an initialization voltage is applied and the gate electrode of the driving element, wherein the initialization voltage is to be applied to the driving element; as well as A capacitor is connected between the first switching element and the light-emitting element. Wherein, the first switching element receives a first initialization pulse through a first gate line, and the second switching element receives a second initialization pulse through a second gate line, and the first initialization pulse and the second initialization pulse are applied at different time periods. The second gate line of the pixel circuit is electrically connected to the first gate line of other pixel circuits, and the other pixel circuits have the same structure as the pixel circuit and are spaced apart from the pixel circuit by a predetermined number of pixel rows.

Images