Adaptive body bias management for in-memory compute operations

Abstract

Embodiments of the present disclosure relate to adaptive body bias management for in-memory compute operations. An in-memory compute circuit includes a memory array having SRAM cells connected in rows by word lines and in columns by bit lines. Body bias nodes of transistors in each SRAM cell are biased by a modulated body bias voltage. Row controller circuitry simultaneously and in parallel excites the word lines for in-memory compute operations. Column processing circuitry processes analog voltages generated on the bit lines in response to the simultaneous excitation to generate decision outputs for the in-memory compute operations. Voltage generator circuitry switches the modulated body bias voltage from a non-negative voltage level to a negative voltage level during the simultaneous excitation. The negative voltage level is adjusted according to integrated circuit processing and / or temperature conditions in order to optimize protection against unwanted memory cell data flips.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 220,088, filed July 9, 2021, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The embodiments relate to an in-memory computing circuit utilizing a static random access memory (SRAM) array, and more specifically, to a circuit for controlling the body bias voltage of transistors applied to memory cells of the SRAM array during in-memory computing operations that simultaneously access multiple rows of the SRAM array. Background Technology

[0004] refer to Figure 1 , Figure 1 A schematic diagram of in-memory computation circuitry 10 is shown. Circuitry 10 utilizes a static random access memory (SRAM) array 12, which is formed by standard 6T SRAM memory cells 14 arranged in a matrix format with N rows and M columns. Alternatively, any bit cells with similar topology and / or functionality can be used. Each memory cell 14 is programmed to store bits for computational weights, for example, used in in-memory computational operations. In this context, in-memory computational operations are understood as high-dimensional matrix-vector multiplication (MVM) that supports multi-bit weights stored in multiple bit cells of memory. Groups of bit cells (in the case of multi-bit weights) can be considered as virtual synaptic elements. Each bit of the computational weight has a logic "1" or logic "0" value.

[0005] Each SRAM cell 14 includes a word line WL and a pair of complementary bit lines BLT and BLC. Cells 14 in a common row of the matrix are connected to each other via the common word line WL. Cells 14 in a common column of the matrix are connected to each other via the pair of common complementary bit lines BLT and BLC. Each word line WL is driven by a word line driver circuit 16, which may be implemented as a CMOS driver circuit (e.g., a series-connected pair of p-channel and n-channel MOSFET transistors forming a logic inverter circuit). The word line signal applied to the word line and driven by the word line driver circuit 16 is generated by feature data input to the in-memory computing circuit 10 and controlled by the row controller circuit 18. The column processing circuit 20 senses analog signal voltages on the complementary bit line pairs BLT and BLC of M columns and generates decision outputs for in-memory computing operations based on these analog signal voltages. The column processing circuit 20 may be implemented to support a process in which the voltages on the columns are first processed individually, followed by a recombination of multiple column outputs.

[0006] Although not in Figure 1As explicitly shown, but should be understood, circuit 10 also includes conventional row decoding, column decoding and read / write circuitry known to those skilled in the art, to be used in combination to write the bits of the calculated weights to the SRAM cells 14 of the memory array 12 and to read the bits of the calculated weights from the SRAM cells 14 of the memory array 12.

[0007] Now for reference Figure 2 Each memory cell 14 includes two cross-coupled CMOS inverters 22 and 24, each inverter including a series-connected pair of p-channel and n-channel MOSFET transistors. The inputs and outputs of inverters 22 and 24 are coupled to form a latch circuit having a true data storage node QT and a complementary data storage node QC that store the complementary logic states of the stored data bits. Cell 14 also includes two transfer gate transistors 26 and 28, whose gate terminals are driven by word line WL. The source-drain path of transistor 26 is connected between the true data storage node QT and the node associated with the true bit line BLT. The source-drain path of transistor 28 is connected between the complementary data storage node QC and the node associated with the complementary bit line BLC. The source terminals of p-channel transistors 30 and 32 in each inverter 22 and 24 are coupled to receive a high supply voltage (e.g., Vdd) at the high supply node, while the source terminals of n-channel transistors 34 and 36 in each inverter 22 and 24 are coupled to receive a low supply voltage (e.g., ground (Gnd) reference) at the low supply node. The word line driver circuit 16 is also typically coupled to receive a high supply voltage (Vdd) at the high supply node and a low supply voltage (Gnd) at the reference low supply node.

[0008] Line controller circuit 18 executes the select word line WL <0> To WL<N-1> The function determines which of the following will be accessed (or activated) simultaneously during in-memory computation operations, and further executes the function of controlling the application of pulse signals to word lines based on characteristic data of the in-memory computation operations. This is merely an example. Figure 1 This illustrates the simultaneous activation of all N word lines using pulse word line signals. It should be understood that in-memory computation operations can alternatively utilize the simultaneous activation of fewer than all rows of the SRAM array. The analog signal voltages generated on a given complementary bit line pair BLT and BLC depend on the logic state of the bits of the computationally weighted data stored in the memory cells 14 of the corresponding columns and the width of the pulse word line signals generated from the feature data and applied to those memory cells 14.

[0009] Figure 1The illustrated implementation shows an example of pulse-width modulation (PWM) in the form of applied word line signals for in-memory computation operations. Using PWM or periodic pulse modulation (PTM) for applied word line signals is a common technique for in-memory computation operations based on the linearity of vectors in multiply-accumulate (MAC) operations. The pulsed word line signal format can be further developed into coded pulse sequences to manage the block sparsity of characteristic data for in-memory computation operations. Therefore, it should be appreciated that when multiple word lines are driven simultaneously, any set of encoding schemes for the applied word line signals can be used. Furthermore, in a simpler implementation, it should be understood that all word line signals applied in simultaneous excitation can alternatively have the same pulse width.

[0010] Figure 3 This is a timing diagram showing the assertion (logic high) of the precharge control signal PCH, which causes the bit line precharge circuit to charge complementary bit line pairs BLT and BLC to the Vdd voltage level, and then de-asserts the precharge control signal PCH (logic low). Subsequently, for a given in-memory computation operation, pulse-width modulated word line signals (depending on the feature data) are simultaneously applied to multiple rows of memory cells 14 in the SRAM array 12. Analog signal voltages Va,T and Va,C evolve over time on the complementary bit line pairs BLT and BLC, respectively, decreasing from the precharge voltage Vdd in response to the pulse width of those word line signals and the logic state of the bits of the computation weights stored in memory cells 14. The representation of the analog voltage Va level shown is merely an example. After the application of the pulse-width modulated word line signals and the sampling of the analog voltages are completed, the precharge control signal PCH is asserted (logic high) again. However, it should be noted that there is a risk that the analog voltage on at least one of the bit lines BLT and BLC may drop from Vdd to a level that causes an unwanted data flip relative to the stored data bit value in one of the column memory cells 14. For example, a logic "1" state stored in column cell 14 can be flipped to a logic "0" state. Such a data flip introduces data errors into the computational weights stored in the memory cell, thereby jeopardizing the accuracy of subsequent in-memory computational operations.

[0011] Undesirable data flips due to excessive bit line voltage drops are primarily caused by simultaneous parallel access of word lines in matrix-vector multiplication mode during in-memory computation operations. This problem differs from normal data flips in SRAM bit cells due to a static noise margin (SNM) issue that occurs during serial bit cell access when the bit lines approach the supply voltage Vdd. During serial access, normal data flips are instead caused by ground bounces from the data storage node QT or QC of the individual bit cell being accessed.

[0012] A known solution to the Serial Bit Cell Access (SNM) failure problem is to reduce the word line voltage by a small amount, typically achieved by shorting the word line driver and using a bleeder path. Another known solution is to apply a fixed word line voltage reduction (e.g., applying a voltage equal to Vdd / 2, VWLUD) at all IC processing corners to ensure the worst-case processing corner. However, this word line underdrive (WLUD) solution has a known drawback: the read current on the bit lines is correspondingly reduced, which can negatively impact computational performance. Furthermore, the use of a fixed word line underdrive voltage increases the variability of the read current across the array, leading to a loss of accuracy in in-memory computational operations.

[0013] Another solution is to use a dedicated bit cell circuit design for each memory cell 14, which is less likely to suffer unwanted data flips during simultaneous (parallel) access across multiple rows. The concern with this solution is the increased circuit area occupied by such bit cell circuitry. For some in-memory computing applications, it is preferable to retain the standard 6TSRAM cells used in array 12. Figure 2 The advantages offered by 8TSRAM cells.

[0014] Therefore, there is a need in the field for in-memory computing circuitry that supports the use of standard 6TSRAM cells, while ensuring that unwanted data flips are prevented during simultaneous row access. Summary of the Invention

[0015] In one embodiment, the in-memory computing circuitry includes: a memory array comprising a plurality of static random access memory (SRAM) cells arranged in a matrix having multiple rows and multiple columns, each row including word lines connected to the SRAM cells in the row, and each column including at least one bit line connected to the SRAM cells in the column; wherein each SRAM cell includes a first body bias voltage line connected to a body node of a first type of transistor of the SRAM; word line driving circuitry for each row having an output connected to drive the word lines of the row; and row controller circuitry configured to simultaneously stimulate the plurality of word lines by applying pulses to the word lines via the word line driver circuitry. For in-memory computation operations; column processing circuitry connected to the at least one bit line for each column and configured to process analog voltages generated on the bit lines in response to simultaneous excitation of the plurality of word lines to generate a decision output for the in-memory computation operation; and voltage generator circuitry configured to generate a first modulated body bias voltage applied to the first body bias voltage line, the first modulated body bias voltage having a non-negative voltage level prior to simultaneous excitation of the plurality of word lines for the in-memory computation operation, and having a negative voltage level during simultaneous excitation of the plurality of word lines for the in-memory computation operation.

[0016] In one embodiment, the in-memory computing circuitry includes: a memory array comprising a plurality of static random access memory (SRAM) cells arranged in a matrix having multiple rows and multiple columns, each row including word lines connected to the SRAM cells in the row, and each column including at least one bit line connected to the SRAM cells in the column; wherein each SRAM cell includes a first body bias voltage line connected to a first body node of a first type transistor of the SRAM and a second body bias voltage line connected to a second body node of a second type transistor of the SRAM; a word line driving circuitry for each row having an output connected to drive the word lines of the row; and a row controller circuitry configured to simultaneously stimulate the plurality of word lines for in-memory computing operations by applying pulses to the word lines via the word line driver circuitry. The column processing circuit is connected to the at least one bit line for each column and configured to process analog voltages generated on the bit lines in response to simultaneous excitation of the plurality of word lines to generate a decision output for in-memory computation operations; and a voltage generator circuit is configured to generate a first modulator bias voltage applied to the first body bias voltage line and a second modulator bias voltage applied to the second body bias voltage line, wherein the voltage generator circuit switches the first modulator bias voltage to a first negative voltage level during simultaneous excitation of the plurality of word lines for in-memory computation operations, and wherein the voltage generator circuit switches the second modulator bias voltage to a second negative voltage level during simultaneous excitation of the plurality of word lines for in-memory computation operations. Attached Figure Description

[0017] To better understand the embodiments, reference will now be made to the accompanying drawings by way of example only, wherein:

[0018] Figure 1 This is a schematic diagram of the computing circuitry within the memory;

[0019] Figure 2 Is using Figure 1 The circuit diagram shown is of a standard 6T static random access memory (SRAM) cell in a memory array for in-memory computing circuitry.

[0020] Figure 3 This is an explanation Figure 1 Timing diagram of the computational operations within the memory of the circuit;

[0021] Figure 4 This is a circuit diagram of an embodiment of in-memory computing circuitry, wherein a modulator bias voltage is applied to the SRAM cells of the memory array.

[0022] Figure 5 Is Figure 4The circuit diagram shows the 6T static random access memory (SRAM) cells used in the memory array of the in-memory computing circuit shown.

[0023] Figure 6 This is an explanation Figure 4 Timing diagram of the computational operations within the memory of the circuit;

[0024] Figure 7 This is a circuit diagram of an embodiment of in-memory computing circuitry, wherein a modulator bias voltage is applied to the SRAM cells of the memory array.

[0025] Figure 8 Is Figure 7 The circuit diagram shows the 6T static random access memory (SRAM) cells used in the memory array of the in-memory computing circuit shown.

[0026] Figure 9 This is an explanation Figure 4 Timing diagram of the computational operations within the memory of the circuit;

[0027] Figure 10A and Figure 10B A cross-section of an integrated circuit including a p-channel MOSFET transistor and an n-channel MOSFET transistor supporting modulator bias is shown.

[0028] Figure 11A , Figure 11B and Figure 11C This is a circuit diagram of an embodiment of a circuit used to provide a modulator bias voltage;

[0029] Figure 12A and Figure 12B This is a circuit diagram of an embodiment of a circuit used to provide a modulator bias voltage;

[0030] Figure 13A and Figure 13B This is a circuit diagram of an embodiment of a circuit for providing a modulator bias voltage; and

[0031] Figure 14 It's a flowchart. Detailed Implementation

[0032] Now for reference Figure 4 , Figure 4 A circuit diagram of an embodiment of the in-memory computing circuit 110 is shown. Figure 1 and Figure 4The same reference numerals in the figures denote the same or similar components, and their descriptions will not be repeated (see the description above). Circuit 110 differs from circuit 10 in that a modulated body bias voltage Vsub is applied to the body node (i.e., substrate, back gate, well, etc.) of the transistors in the SRAM cells of the memory array. A body bias modulation circuit 122 is provided to control the voltage level of the body bias voltage Vsub applied to the body node of the p-channel MOSFET and n-channel MOSFET devices of each SRAM cell 14 during in-memory computation operations. Specifically, during each memory computation operation, as indicated by the assertion of the enable signal En, the body bias modulation circuit 122 reduces the body bias voltage Vsub from a default reference (e.g., ground Gnd) level to a negative voltage level – Vneg. The effect of applying a negative voltage is to enhance the p-channel MOSFET devices and degrade the n-channel MOSFET devices. Therefore, it is more difficult for a decrease in the analog bit line voltage Va,T or Va,C to cause unwanted data flips of the stored data bit values ​​in any memory cell 14. An additional benefit of using the negative voltage generated for body bias during in-memory computation operations is reduced current dissipation in n-channel MOSFET devices, and consequently, reduced power consumption.

[0033] Now for reference Figure 5 Each memory cell 14 includes two cross-coupled CMOS inverters 22 and 24, each inverter including a series-connected pair of p-channel and n-channel MOSFET transistors. The inputs and outputs of inverters 22 and 24 are coupled to form a latch circuit having a true data storage node QT and a complementary data storage node QC storing complementary logic states of the stored data bits. Cell 14 also includes two transfer gate transistors 26 and 28, whose gate terminals are driven by word line WL. The source-drain path of transistor 26 is connected between the true data storage node QT and the node associated with the true bit line BLT. The source-drain path of transistor 28 is connected between the complementary data storage node QC and the node associated with the complementary bit line BLC. The body nodes (i.e., substrate, back gate, well, etc.) of transistors 26 and 28 are coupled to a body bias voltage line 38, which receives a modulated body bias voltage Vsub from a body bias modulation circuit 122. The source terminals of p-channel transistors 30 and 32 in each inverter 22 and 24 are coupled to receive a high supply voltage (e.g., Vdd) at the high supply node, while the source terminals of n-channel transistors 34 and 36 in each inverter 22 and 24 are coupled to receive a low supply voltage (e.g., ground (Gnd) reference) at the low supply node. The body nodes of transistors 30, 32, 34, and 36 are also coupled to receive a modulated body bias voltage Vsub from body bias voltage line 38. Although Figure 5It specifically uses a 6T-type SRAM cell, but those skilled in the art will recognize that any bit cell with similar topology and / or functionality and supporting volume bias control can be used instead.

[0034] In an example embodiment, the negative voltage level – Vneg – applied by the body bias modulation circuit 122 as the body bias voltage Vsub is fixed at a nominal voltage level selected based on typical processing and / or temperature conditions. Alternatively, the nominal voltage level of the negative voltage – Vneg can be selected based on worst-case processing and / or temperature conditions. In another alternative embodiment, the body bias modulation circuit 122 is configured to select the level of the negative voltage – Vneg through tuning operations that depend on integrated circuit processing and / or temperature information. For example, in response to process information (process) received by the body bias modulation circuit 122, the negative voltage level – Vneg can be positively or negatively adjusted relative to the nominal voltage level to ensure optimal performance in suppressing unwanted data flips given an applicable processing angle. For example, consider a case where the processing information indicates that p-channel transistors 30 and 32 are fast and / or n-channel transistors 34 and 36 are slow. In response to this processing information, the body bias modulation circuit 122 can adjust the negative voltage level – Vneg to be less than the nominal negative voltage level. Similarly, in response to the temperature information (Temp) received by the body bias modulation circuit 122, the negative voltage level – Vneg – can be adjusted positively or negatively relative to the nominal voltage level to ensure optimal performance in suppressing unwanted data flips under given applicable temperature conditions. For example, consider a specific case where the temperature information indicates that the integrated circuit temperature is decreasing. In response to this temperature information, the body bias modulation circuit 122 can adjust the negative voltage level – Vneg – to be more negative than the nominal negative voltage level to increase the strength of the pull-up n-channel transistor in the bit cell.

[0035] Figure 6 This is a timing diagram showing the enable signal En being deasserted, and the body bias modulation circuit 122 generating a body bias voltage Vsub at a default reference voltage level (here, ground Gnd voltage level is shown only for example). At this time, the precharge control signal PCH (logic high) is also asserted, causing the bit line precharge circuit to charge the complementary bit line pairs BLT and BLC to the Vdd voltage level. At the start of the computation mode for an in-memory computation operation, the enable signal En is asserted, and the body bias modulation circuit 122 changes the body bias voltage Vsub to a negative voltage – Vneg level (set to the nominal level or further modulated / tuned in response to process and / or temperature information). It is important to recognize that this negative voltage – Vneg – is being applied to all memory cells 14, for example, to multiple cells in each column of the memory array, which participate in the execution of a given in-memory computation operation. One or more individual computation cycles can be performed in combination with each in-memory computation operation. Figure 6An example of performing multiple computation cycles is shown. For each computation cycle, the precharge control signal PCH is deasserted (logic low). This is followed by the simultaneous application of pulse-width modulated word line signals, depending on the feature data, to multiple rows of memory cells 14 in the SRAM array 12 for in-memory computation operations. Analog signal voltages Va,T and Va,C evolve over time on complementary bit line pairs BLT and BLC, respectively, decreasing from the precharge voltage Vdd in response to the pulse width of those word line signals and the logic state of the bits representing the computational weights stored in memory cells 14. The representation of the analog voltage Va level shown is merely an example. After the application of the pulse-width modulated word line signals and the sampling of the analog voltages are complete, the precharge control signal PCH is asserted (logic high), and the computation cycle ends (followed by the next computation cycle if necessary).

[0036] The enable signal En remains valid for the duration of the in-memory computation operation (i.e., during multiple computation cycles, the body bias modulation circuit 122 maintains the body bias voltage Vsub at a negative voltage level – Vneg). At the end of the in-memory computation operation, the enable signal En is deasserted, and the body bias modulation circuit 122 returns the body bias voltage Vsub to a default (e.g., ground Gnd) voltage level.

[0037] As previously described, circuits 10, 110 also include conventional row decoding, column decoding, and read / write circuitry, which are used in combination to write the calculated weight bits to the SRAM cells 14 of the memory array 12 and to read the calculated weight bits from the SRAM cells 14 of the memory array 12. Because the negative voltage level of the body bias voltage Vsub—Vneg—can adversely affect normal write and read operations of the SRAM cells 14, the generation of the enable signal En is controlled to be deasserted during normal memory read / write operations, such that the body bias voltage Vsub is set to the default (e.g., ground Gnd) voltage level.

[0038] Now for reference Figure 7 It shows a circuit diagram of an embodiment of the in-memory computing circuit 210. Figure 4 and Figure 7The same reference numerals in the figures denote the same or similar components, and their descriptions will not be repeated (see the description above). Circuit 210 differs from circuit 110 in that a first modulated body bias voltage VsubN is applied to the body node of the n-channel MOSFET device of the SRAM cell in the memory array, while a second modulated body bias voltage VsubP is applied to the body node of the p-channel MOSFET device of the SRAM cell in the memory array. Therefore, circuit 210 supports independent body bias modulation for the n-type and p-type transistors during memory computation operations. Body bias modulation circuit 222 is provided to control the voltage levels of the body bias voltages VsubN and VsubP applied to the body nodes (i.e., substrate, back gate, well, etc.) of the n-channel MOSFET device and p-channel MOSFET device of each SRAM cell 14, respectively, during in-memory computation operations. Specifically, during each memory computation operation, as indicated by the assertion of the enable signal En, the body bias modulation circuit 222 reduces the body bias voltages VsubN and VsubP from the default reference (e.g., ground Gnd) voltage level to negative voltage levels -VnegN and -VnegP, respectively.

[0039] Now for reference Figure 8Each memory cell 14 includes two cross-coupled CMOS inverters 22 and 24, each inverter including a series-connected pair of p-channel and n-channel MOSFET transistors. The inputs and outputs of inverters 22 and 24 are coupled to form a latch circuit having a true data storage node QT and a complementary data storage node QC storing complementary logic states of the stored data bits. Cell 14 also includes two n-channel transmission (transmission gate) transistors 26 and 28, whose gate terminals are driven by word line WL. The source-drain path of transistor 26 is connected between the true data storage node QT and the node associated with the true bit line BLT. The source-drain path of transistor 28 is connected between the complementary data storage node QC and the node associated with the complementary bit line BLC. The body nodes (i.e., substrate, back gate, well, etc.) of n-channel transistors 26 and 28 are coupled to a first body bias voltage line 38N, which receives a modulated body bias voltage VsubN from body bias modulation circuit 222. The source terminals of p-channel transistors 30 and 32 in each inverter 22 and 24 are coupled to receive a high supply voltage (e.g., Vdd) at the high supply node, while the source terminals of n-channel transistors 34 and 36 in each inverter 22 and 24 are coupled to receive a low supply voltage (e.g., ground (Gnd) reference) at the low supply node. The body nodes of p-channel transistors 30 and 32 are coupled to a second body bias voltage line 38P, which receives a modulated body bias voltage VsubP from body bias modulation circuit 222. The body nodes (n) of n-channel transistors 34 and 36 are also coupled to receive a modulated body bias voltage VsubN from body bias voltage line 38N. Although Figure 8 This is specific to the 6T type SRAM cell, but those skilled in the art will recognize that any bit cell with similar topology and / or functionality can be used alternatively.

[0040] In an exemplary embodiment, the levels of the negative voltages –VnegN, –VnegP applied by the body bias modulation circuit 222 are fixed at a nominal voltage level selected based on typical processing and / or temperature conditions. Alternatively, the nominal voltage level may be selected based on worst-case processing and / or temperature conditions. In an alternative embodiment, the body bias modulation circuit 222 is configured to select the levels of the negative voltages –VnegN, –VnegP based on integrated circuit processing and / or temperature information. For example, in response to processing information received by the body bias modulation circuit 222, the levels of the negative voltages –VnegN, –VnegP may be positively or negatively adjusted relative to the nominal voltage level to ensure optimal performance in suppressing unwanted data flips given an applicable processing angle. For example, consider a case where the processing information indicates that the MOSFET devices of memory cell 12 are at a slow-fast (where NMOS is slow and PMOS is fast) processing angle. In response to this processed information, the body bias modulation circuit 222 can adjust the negative voltage level -VnegN to be lower than its nominal negative voltage level, and adjust the negative voltage level -VnegP to be much lower than its nominal negative voltage level. Similarly, in response to the temperature information (Temp) received by the body bias modulation circuit 222, the levels of the negative voltages -VnegN and -VnegP can be positively or negatively adjusted relative to the corresponding nominal voltage levels to ensure optimal performance in suppressing unwanted data flips under given applicable temperature conditions. For example, consider a specific case where the temperature information indicates that the integrated circuit temperature is decreasing. In response to this temperature information, the body bias modulation circuit 222 can adjust the levels of the negative voltages -VnegN and -VnegP to be more negative than the corresponding nominal negative voltage levels in order to increase the strength of the pull-up p-channel transistors.

[0041] Figure 9 This is a timing diagram showing the enable signal En being deasserted, and the body bias modulation circuit 222 generating body bias voltages VsubN and VsubP at a default reference voltage level (here, ground Gnd voltage level is shown only by example). At this time, the precharge control signal PCH is also asserted (logic high), causing the bit line precharge circuit to charge the complementary bit line pairs BLT and BLC to the Vdd voltage level. At the start of the computation mode for an in-memory computation operation, the enable signal En is asserted, and the body bias modulation circuit 222 changes the body bias voltages VsubN and VsubP to negative voltages –VnegN and –VnegP levels (set to nominal levels or further modulated in response to process and / or temperature information). It is important to recognize that the negative voltages –VnegN and –VnegP are applied to all memory cells 14, for example, to multiple cells in each column of the memory array, which participate in the execution of a given in-memory computation operation. One or more computation cycles can be performed in combination with each in-memory computation operation. Figure 9An example of performing multiple computation cycles is shown. For each computation cycle, the precharge control signal PCH is deasserted (logic low). This is followed by the simultaneous application of pulse-width modulated word line signals to multiple rows of memory cells 14 in the SRAM array 12 for in-memory computation operations. Analog signal voltages Va,T and Va,C evolve over time on complementary bit line pairs BLT and BLC, respectively, decreasing from the precharge voltage Vdd in response to the pulse width of those word line signals and the logic state of the bits containing computational weights or feature data stored in memory cells 14. The representation of the analog voltage Va level shown is merely an example. After the application of the pulse-width modulated word line signals and the sampling of the analog voltages are complete, the precharge control signal PCH is asserted (logic high) and the computation cycle ends. The next computation cycle can be immediately followed if needed.

[0042] The enable signal En remains valid for the duration of the in-memory computation operation (i.e., the body bias modulation circuit 122 maintains the body bias voltages VsubN and VsubP at negative voltage levels –VnegN and –VnegP throughout multiple computation cycles). At the end of the in-memory computation operation, the enable signal En is deasserted, and the body bias modulation circuit 122 returns the body bias voltage Vsub to its default (e.g., ground Gnd) voltage level.

[0043] As previously described, circuits 10, 110, and 210 also include conventional row decoding, column decoding, and read / write circuitry, which are used in combination to write the calculated weight bits to the SRAM cells 14 of the memory array 12 and to read the calculated weight bits from the SRAM cells 14 of the memory array 12. Because the negative voltage levels –VnegN and –VnegP used for the body bias voltages VsubN and VsubP, respectively, may adversely affect the normal write and read operations of the SRAM cells 14, the enable signal En is deasserted during memory read / write operations, causing the body bias voltages VsubN and VsubP to be set to default (e.g., ground Gnd) voltage levels.

[0044] The p-channel and n-channel MOSFET transistors of memory cell 14 can be implemented using any suitable technique that supports modulation of the body bias voltage. Figure 10A and 10B Cross-sections of integrated circuits including p-channel MOSFET (pMOS) transistors and n-channel MOSFET (nMOS) transistors implemented using fully depleted silicon-on-insulator (FD-SOI) technology are shown. Specifically, Figure 10A It shows the use of Figure 5 The circuit implementation shown is a single-well implementation in FD-SOI, while Figure 10B It shows the use of Figure 8The circuit implementation shown is a dual-well implementation in FD-SOI. The SOI substrate 50 includes a fully depleted semiconductor film layer 52, which is insulated from the semiconductor support 54 by an insulating layer 56 (commonly referred to in the art as a buried oxide (BOX) layer). A shallow trench isolation 58 defines the active region of the semiconductor film layer 52 on which pMOS and nMOS transistors are fabricated. The pMOS transistor includes a p-type doped source and drain region 60 in the active region, while the nMOS transistor includes an n-type doped source and drain region 62 in the active region. A gate structure 64 is formed on the channel region of the active region in the semiconductor film layer 52 between the source and drain regions. The body nodes (e.g., substrate, back gate, well) of the pMOS and nMOS transistors are formed by the semiconductor support 54 and portions of buried doped regions 66 (doped with the same conductivity type as the wells they are located in) located beneath each transistor. Specifically, for Figure 10A In one embodiment, a single (p-type doped) pwell for the body node is formed by a semiconductor support 54 extending beneath the pMOS and nMOS transistors. However, for Figure 10B In one embodiment, the dual-well configuration has an n-type well (nwell) for a pMOS body node formed in the semiconductor support 54 and extending below the pMOS transistor, and a p-type well (pwell) for an nMOS body node formed in the semiconductor support 54 and extending below the nMOS transistor. Shallow trench isolation 56 also defines sink regions 70 for entering the wells. Each sink region 70 includes heavily doped contact regions 72 (p-type doping for p-type wells and n-type doping for n-type wells). This is to support the voltage bias of the body node provided by the wells (in... Figure 10A It has a negative voltage -Vneg, in Figure 10B An electrical contact 74 is created for each contact area 72, which has a negative voltage (-VnegN, -VnegP). It should be noted that... Figure 10A and Figure 10B The FD-SOI implementation described herein is merely an example, and different n-well / p-well combinations with n+ / p+ injection can be selected depending on the processing / technology. The design and fabrication of MOS transistors in FD-SOI technology are well known in the art.

[0045] Now for reference Figure 11A , Figure 11AA circuit diagram of an embodiment of circuit 300 within bias voltage modulation circuit 122 for providing a modulated body bias voltage Vsub is shown. Circuit 300 includes an n-channel MOSFET device 302, whose source is coupled (preferably directly connected) to a default reference (e.g., ground Gnd) node and whose drain is coupled (preferably directly connected) to a body bias voltage line 38. The gate of transistor 302 is coupled to receive an enable signal En. More specifically, the enable signal En is fed through a delay circuit before being applied to the gate of transistor 302 to avoid overlap between a gate driven low and Vsub becoming negative. Capacitor 304 has a first terminal coupled (preferably directly connected) to the gate of transistor 302 and a second terminal coupled (preferably directly connected) to the body bias voltage line 38.

[0046] Circuit 300 operates as follows. When the enable signal En is deasserted (logic high), transistor 302 is turned on, and a voltage approximately equal to the logic high voltage of the enable signal En is stored across capacitor 304. Furthermore, because transistor 302 is turned on, the voltage Vsub at body bias line 38 remains at the default (e.g., ground Gnd) reference voltage. When the enable signal En is asserted (logic low), the voltage Vsub at body bias line 38 is boosted to a negative voltage level – Vneg – by the voltage stored across capacitor 304.

[0047] exist Figure 11B In the illustrated embodiment, similar to Figure 11A The pair of circuits shown can be used in bias voltage modulation circuit 222 to provide negative voltages -VnegN, -VnegP in response to enable signal En, for application to body bias voltage lines 38N, 38P, respectively. Similarly, enable signal En is fed to the gate of transistor 302 via appropriate delay circuitry.

[0048] Figure 11C An alternative implementation of circuit 300 within bias voltage modulation circuit 222 is shown to provide negative voltages –VnegN, –VnegP for VsubN and VsubP, respectively. Circuit 300 includes two n-channel MOSFET devices 302, each having a source coupled (preferably directly connected) to a default (e.g., ground Gnd) reference node, and the drain of one transistor coupled (preferably directly connected) to body bias voltage line 38N, while the drain of the other transistor is coupled (preferably directly connected) to body bias voltage line 38P. The gate of transistor 302 is coupled to receive an enable signal En.

[0049] The negative boost circuit of circuit 300 is formed by a plurality of switched capacitor circuits 301, which are connected in parallel and coupled between the node receiving the delayed enable signal EN and the body bias voltage lines 38N and 38P, respectively. Each switched capacitor circuit 301 includes a capacitor C connected in series with a switch S (which may be implemented by a transistor device). Digital control circuit 303 generates a multi-bit digital control signal Csel, which, in conjunction with the generation and selective application of negative voltages -VnegN and -VnegP, selectively excites one or more switches S of the switched capacitor circuit 301.

[0050] Circuit 300 operates as follows. When the enable signal En is de-asserted (logic high), transistor 302 is turned on, and a default (e.g., ground Gnd) voltage is applied to body bias voltage lines 38N and 38P. Digital control circuit 303 controls all switches S of switched capacitor circuit 301 to close. However, when the enable signal EN is asserted (logic low) for in-memory computation operations, digital control circuit 303 selectively de-energizes switches S of switched capacitor circuit 301 to support modulation of the levels of negative voltages -VnegN and -VnegP.

[0051] The selective de-energization of switch S provides flexibility in modulating the negative voltage level. This offers the opportunity to program the negative voltage level based on processing and / or temperature conditions. Regarding the modulation of the negative voltage levels –VnegN, –VnegP – which depend on integrated circuit processing information, processing data regarding whether the MOSFET device of memory cell 12 is in a certain processing angle can be provided to digital control circuit 303, and in response, digital control circuit 303 can assert bits of the multi-bit digital control signal Csel to control the selection of switched capacitor circuit 301 to tune the negative voltage level for optimal performance. Similarly, for the modulation of the negative voltage levels –VnegN, –VnegP – which depend on integrated circuit temperature information, data regarding the current temperature conditions can be provided to digital control circuit 340, and in response, digital control circuit 303 can assert bits of the multi-bit digital control signal Cse1 to control the selection of switched capacitor circuit 301 to tune the negative voltage level for optimal performance.

[0052] Now for reference Figure 12AThe diagram illustrates a circuit diagram of an embodiment of circuit 330 within body bias modulation circuit 122 for providing a modulated body bias voltage Vsub. Circuit 330 includes a voltage generator circuit 332 configured to generate a negative body bias voltage – Vneg. The voltage generator circuit 332 may, for example, include a voltage regulator circuit (such as a low dropout (LDO) regulator) that generates the negative body bias voltage – Vneg from an input voltage. Alternatively, the voltage generator circuit 332 may, for example, include a charge pump circuit that generates the negative body bias voltage – Vneg from a supply voltage Vdd.

[0053] The switching circuit 334 (illustrated herein as an analog multiplexing circuit by way of example only) has a first input configured to receive a negative body bias voltage – Vneg – output from the voltage generator circuit 332 and a second input configured to receive a default (e.g., ground Gnd) reference voltage. The output of the switching circuit 334 is coupled (preferably directly connected) to the body bias voltage line 38. The selection operation performed by the switching circuit 334 is controlled by an enable signal En. When the enable signal En is deasserted, the switching circuit 334 applies the default (ground Gnd) reference voltage as the modulated body bias voltage Vsub. Conversely, when the enable signal En is asserted, the switching circuit 334 applies the negative voltage – Vneg – generated by the voltage generator circuit 332 as the body bias voltage Vsub.

[0054] exist Figure 12B In the illustrated embodiment, similar to Figure 12A The pair of circuits shown can be used for bias voltage modulation circuit 222 to provide negative voltages -VnegN, -VnegP in response to enable signal En, for application to body bias voltage lines 38N, 38P respectively.

[0055] Now for reference Figure 13A The diagram shows a circuit diagram of an embodiment of the circuit 430 within the body bias modulation circuit 122 for providing the modulator bias voltage Vsub. Figure 12A and 13A The same reference numerals in the figures indicate the same or similar parts, and their descriptions will not be repeated (see the description above). Circuit 430 differs from circuit 330 in that the level of the negative body bias voltage – Vneg – is not fixed (e.g., fixed to a nominal or typical level), but is modulated according to integrated circuit processing and / or temperature conditions.

[0056] Voltage generator circuit 332 receives a control signal. In one embodiment, the control signal is a multi-bit digital control signal Vsel, but it should be understood that the control signal can also be implemented as an analog signal. The value of the control signal (specifically, the digital value of the bits of the control signal Vsel) selects the voltage level of the negative body bias voltage – Vneg – output by voltage generator circuit 332. The control signal Vsel is generated by control circuit 114 in response to integrated circuit processing and / or temperature information, therefore the voltage level of the negative body bias voltage – Vneg is modulated in a manner dependent on integrated circuit processing and / or temperature information.

[0057] Integrated circuit processing information is provided in digital codes generated and stored in the memory M within the control circuit 114. The digital codes represent the center of the processing batch and are generated by a circuit such as a ring oscillator (RO), the output frequency of which varies according to the integrated circuit processing. Therefore, the output frequency of the RO circuit represents the processing center and can be easily converted into digital codes (e.g., using a counter circuit). The processing monitoring circuit 116 within the control circuit 114 can generate a value for a control signal Vsel based on the stored digital codes for integrated circuit processing. For example, the process monitoring circuit 116 may include a lookup table (LUT) that associates each digital code with a value for the control signal Vsel to provide a specific voltage level for the negative body bias voltage – Vneg, which will generate an optimal protection level for unwanted data flips at the integrated circuit processing corner. The control circuit 114 outputs the value of the control signal Vsel associated with the stored digital codes, and the voltage generator circuit 112 responds by generating a corresponding level for the negative body bias voltage – Vneg.

[0058] Temperature information is generated by temperature sensing circuit 118 and represents the current temperature of the integrated circuit. Temperature sensing circuit 118 can optionally modify or adjust the value of control signal Vsel, which is a function of the sensed temperature. For example, temperature sensing circuit 118 may include a lookup table (LUT) that specifies a particular (positive or negative) adjustment of the value of control signal Vsel to provide a corresponding tuning for a specific voltage level of negative body bias voltage – Vneg, which will generate the optimal protection level against unwanted data flips given the integrated circuit processing angle and current temperature conditions.

[0059] Figure 13B An implementation of circuit 430 within the body bias modulation circuit 222 for generating negative voltages -VnegN, -VnegP is shown, wherein the voltage level is modulated according to integrated circuit processing and / or temperature conditions. The value of the control signal selects the voltage level of the negative body bias voltages -VnegN, -VnegP output by the voltage generator circuit 332.

[0060] Now for reference Figure 14 It shows the use of Figure 13A and 13B The flowchart describes the operation of the control circuit 114 and process monitoring circuit 116 of the circuit. In step 140, the stored digital code for integrated circuit processing is read from the memory M. In one embodiment, the digital code for integrated circuit processing is loaded into the memory M at the factory, and the digital code is based on the identified integrated circuit processing characteristics (processing angle, etc.) for the integrated circuit manufacturing batch (e.g., source wafer), from which integrated circuits are obtained. Next, in step 142, it is determined whether the read digital code for integrated circuit processing indicates that the MOSFET device of memory cell 12 is in a (worst-case) slow p-channel, fast n-channel integrated circuit processing angle. If yes, then in step 144, the value of the control signal Vsel is selected, which corresponds to the read digital code and will cause the voltage generator circuit 332 to generate a nominal negative level of the body bias voltage Vsub (or VsubN, VsubP). If no in step 142, then in step 146, it is determined whether the read digital code for integrated circuit processing indicates that the MOSFET device of memory cell 12 is in a slow p-channel, slow n-channel integrated circuit processing angle. If yes, then in step 148, the value of the control signal Vsel, corresponding to the read digital code, is selected, and the voltage generator circuit 332 will generate a small negative level for the body bias voltage Vsub (or VsubN, VsubP). If no in step 146, then in step 150, other processing angle conditions can be tested, and the negative level of the body bias voltage Vsub (or VsubN, VsubP) can be modulated accordingly.

[0061] although Figure 14 The process illustrates a limited evaluation of digital codes used for integrated circuit processing; however, it should be understood that the evaluation process can be significantly more complex in terms of evaluating multiple processing angles with modulator bias voltages Vsub (or VsubN, VsubP). Additional test steps can be added. Figure 14 During the process, other integrated circuit processing angles or process-related conditions are tested, where each test has an associated digital code and a control signal Vsel value to set the corresponding negative voltage levels of the body bias voltages VsubN and VsubP generated by the voltage generator circuit 332. For example, consider the following table:

[0062] nMOS pMOS VsubP VsubN slow slow <-VnegP <-VnegN fast slow -VnegP -VnegN slow fast <<-VnegP <-VnegN fast fast <-VnegP <=-VnegN

[0063] In the example illustrated by the aforementioned table, the nominal negative voltages –VnegN, –VnegP are set to provide optimal protection against unwanted data flips based on the worst-case processing angle (i.e., the "FS" angle, where NMOS is fast and PMOS is slow). A digital code stored in memory M for integrated circuit processing specifies the identified integrated circuit processing characteristic (e.g., slow / slow, fast / slow, slow / fast, fast / fast corner). Control circuit 114 and process monitoring circuit 116 operate to determine which angle is specified by the digital code. If the digital code specifies the "FS" angle, voltage generator circuit 332 generates nominal negative body bias voltages –VnegN, –VnegP. If the digital code specifies the "SS" angle, voltage generator circuit 332 generates even smaller (i.e., smaller amplitude) negative body bias voltages VsubN and VsubP; or even (or even positive) than the nominal negative body bias voltages –VnegN, –VnegP. If the digital code specifies the "SF" angle, the voltage generator circuit 332 will generate a body bias voltage VsubN that is more negative (possibly even at ground or positive) than the nominal negative body bias voltage -VnegN, and the voltage generator circuit 332 will generate a body bias voltage VsubP that is more negative (possibly even at ground or positive) than the nominal negative body bias voltage -VnegP. Finally, if the digital code specifies the "FF" angle, the voltage generator circuit 332 will generate a body bias voltage VsubN that is less than or equal to the nominal negative body bias voltage -VnegN, and the voltage generator circuit 332 will generate a body bias voltage VsubP that is more negative (possibly even at ground or positive) than the nominal negative body bias voltage -VnegP.

[0064] More generally: a) If the digital code used for processing characteristics specifies a slow pMOS, a body bias voltage VsubP with a negative voltage –VnegP is generated, which has a sufficient magnitude to meet reliability requirements in ensuring the prevention of unwanted data flips; b) If the digital code used for processing characteristics specifies a fast pMOS, a body bias voltage VsubP with a lower magnitude (possibly even at ground level) is generated, which has a sufficient magnitude to meet reliability requirements in ensuring the prevention of unwanted data flips; c) If the digital code used for process characteristics specifies a fast nMOS, a body bias voltage VsubN with a negative voltage –VnegN is generated, which has a sufficient magnitude to meet reliability requirements in ensuring the prevention of unwanted data flips and further provides optimization of power consumption; and d) If the digital code used for process characteristics specifies a slow nMOS, a negative voltage VsubP with a lower magnitude (possibly even at ground level) is generated, which has a sufficient magnitude to meet reliability requirements in ensuring the prevention of unwanted data flips without reducing read current in the context of absolute values ​​and local variations.

[0065] The foregoing description has provided a complete and informative description of exemplary embodiments of the invention through exemplary and non-limiting examples. However, various modifications and adaptations will become apparent to those skilled in the art when read in conjunction with the accompanying drawings and appended claims, given the foregoing description. Nevertheless, all such modifications and similar alterations taught in this invention will still fall within the scope of the invention as defined by the appended claims.

Claims

1. An in-memory computing circuit, comprising: A memory array includes a plurality of static random access memory (SRAM) cells arranged in a matrix having a plurality of rows and a plurality of columns, each row including word lines connected to the SRAM cells in the row, and each column including at least one bit line connected to the SRAM cells in the column. Each SRAM cell includes a first body bias voltage line connected to the body node of a first type of transistor in the SRAM cell. A word line driver circuit for each row, having outputs connected to drive the word lines of said row; The line controller circuit is configured to simultaneously stimulate the plurality of word lines by applying pulses to the word lines via the word line driver circuit for in-memory computation operations; A column processing circuit, connected to the at least one bit line for each column, and configured to process analog voltages formed on the bit lines in response to simultaneous excitation of the plurality of word lines to generate decision outputs for computational operations within the memory; as well as A voltage generator circuit is configured to generate a first modulated body bias voltage applied to the first body bias voltage line, the first modulated body bias voltage having a non-negative voltage level before the simultaneous excitation of the plurality of word lines for computation operations in the memory, and having a negative voltage level during the simultaneous excitation of the plurality of word lines for computation operations in the memory. The voltage generation circuit is controlled to generate the negative voltage level at an optimal level to ensure that unwanted flips are prevented during in-memory computation operations of the data stored in the SRAM cell. The optimal level is selected based on the temperature conditions of the integrated circuit.

2. The in-memory computing circuit according to claim 1, wherein the first type of transistor in the SRAM cell is a p-channel transistor.

3. The in-memory computing circuit of claim 1, wherein the voltage generator circuit is an adjustable voltage regulator configured to adjust the negative voltage level according to integrated circuit processing and / or temperature conditions.

4. The in-memory computing circuit of claim 3 further includes a control circuit configured to generate a control signal for application to the voltage generator circuit.

5. The in-memory computing circuit of claim 4, wherein the control signal is configured to cause the negative voltage level to modulate away from the nominal level in response to the applicable integrated circuit processing angle of the transistor for the SRAM cell.

6. An in-memory computing circuit, comprising: A memory array includes a plurality of static random access memory (SRAM) cells arranged in a matrix having a plurality of rows and a plurality of columns, each row including word lines connected to the SRAM cells in the row, and each column including at least one bit line connected to the SRAM cells in the column. Each SRAM cell includes a first body bias voltage line connected to the body node of a first type of transistor in the SRAM cell. A word line driver circuit for each row, having outputs connected to drive the word lines of said row; The line controller circuit is configured to simultaneously stimulate the plurality of word lines by applying pulses to the word lines via the word line driver circuit for in-memory computation operations; A column processing circuit, connected to the at least one bit line for each column, and configured to process analog voltages formed on the bit lines in response to simultaneous excitation of the plurality of word lines to generate decision outputs for computational operations within the memory; as well as A voltage generator circuit is configured to generate a first modulated body bias voltage applied to the first body bias voltage line, the first modulated body bias voltage having a non-negative voltage level before the simultaneous excitation of the plurality of word lines for computation operations in the memory, and having a negative voltage level during the simultaneous excitation of the plurality of word lines for computation operations in the memory. The voltage generator circuit described therein is an adjustable voltage regulator configured to adjust the negative voltage level according to integrated circuit processing and / or temperature conditions; The control circuit is configured to generate a control signal for application to the voltage generator circuit. The control signal is configured to modulate the negative voltage level away from the nominal level in response to the applicable integrated circuit processing angle of the transistor for the SRAM cell; The applicable integrated circuit processing angle is indicated by programming code stored in the control circuit, and the control circuit includes a lookup table (LUT) that associates the programming code with the value of the control signal.

7. An in-memory computing circuit, comprising: A memory array includes a plurality of static random access memory (SRAM) cells arranged in a matrix having a plurality of rows and a plurality of columns, each row including word lines connected to the SRAM cells in the row, and each column including at least one bit line connected to the SRAM cells in the column. Each SRAM cell includes a first body bias voltage line connected to the body node of a first type of transistor in the SRAM cell. A word line driver circuit for each row, having outputs connected to drive the word lines of said row; The line controller circuit is configured to simultaneously stimulate the plurality of word lines by applying pulses to the word lines via the word line driver circuit for in-memory computation operations; A column processing circuit, connected to the at least one bit line for each column, and configured to process analog voltages formed on the bit lines in response to simultaneous excitation of the plurality of word lines to generate decision outputs for computational operations within the memory; as well as A voltage generator circuit is configured to generate a first modulated body bias voltage applied to the first body bias voltage line, the first modulated body bias voltage having a non-negative voltage level before the simultaneous excitation of the plurality of word lines for computation operations in the memory, and having a negative voltage level during the simultaneous excitation of the plurality of word lines for computation operations in the memory. The voltage generator circuit described therein is an adjustable voltage regulator configured to adjust the negative voltage level according to integrated circuit processing and / or temperature conditions; The control circuit is configured to generate a control signal for application to the voltage generator circuit. The control signal is configured to modulate the negative voltage level away from the nominal level in response to the applicable integrated circuit processing angle of the transistor for the SRAM cell; The control circuit further includes a temperature sensor, and the control signal is configured to induce temperature-dependent tuning of the negative voltage level.

8. The in-memory computing circuit of claim 7, wherein the control circuit includes a lookup table (LUT) that associates the sensed integrated circuit temperature with a tuning level for the value of the control signal.

9. An in-memory computing circuit, comprising: A memory array includes a plurality of static random access memory (SRAM) cells arranged in a matrix having a plurality of rows and a plurality of columns, each row including word lines connected to the SRAM cells in the row, and each column including at least one bit line connected to the SRAM cells in the column. Each SRAM cell includes a first body bias voltage line connected to the body node of a first type of transistor in the SRAM cell. A word line driver circuit for each row, having outputs connected to drive the word lines of said row; The line controller circuit is configured to simultaneously stimulate the plurality of word lines by applying pulses to the word lines via the word line driver circuit for in-memory computation operations; A column processing circuit, connected to the at least one bit line for each column, and configured to process analog voltages formed on the bit lines in response to simultaneous excitation of the plurality of word lines to generate decision outputs for computational operations within the memory; as well as A voltage generator circuit is configured to generate a first modulated body bias voltage applied to the first body bias voltage line, the first modulated body bias voltage having a non-negative voltage level before the simultaneous excitation of the plurality of word lines for computation operations in the memory, and having a negative voltage level during the simultaneous excitation of the plurality of word lines for computation operations in the memory. The voltage generator circuit described therein is an adjustable voltage regulator configured to adjust the negative voltage level according to integrated circuit processing and / or temperature conditions; The control circuit is configured to generate a control signal for application to the voltage generator circuit. The control circuit further includes a temperature sensor, and the control signal is configured to modulate the negative voltage level away from the nominal level in response to the temperature of the integrated circuit sensed by the temperature sensor.

10. The in-memory computing circuit of claim 9, wherein the control circuit includes a lookup table (LUT) that correlates the sensed integrated circuit temperature with the value of the control signal.

11. The in-memory computing circuit of claim 1, wherein each SRAM cell further includes a second body bias voltage line connected to the body node of a second type transistor of the SRAM cell, and wherein the voltage generator circuit is further configured to generate a second modulated body bias voltage applied to the second body bias voltage line, the second modulated body bias voltage having a non-negative voltage level prior to the simultaneous activation of the plurality of word lines for the in-memory computing operation, and having a negative voltage level during the simultaneous activation of the plurality of word lines for the in-memory computing operation.

12. The in-memory computing circuit of claim 11, wherein the first type transistor of the SRAM cell is a p-channel transistor, and wherein the second type transistor of the SRAM cell is an n-channel transistor.

13. The in-memory computing circuit of claim 1, wherein the voltage generator circuit includes a voltage boost circuit configured to boost the first modulator bias voltage from a ground voltage to the negative voltage level in response to a control signal.

14. The in-memory computing circuit of claim 13, wherein the control signal is asserted in response to the execution of the in-memory computing operation.

15. An in-memory computing circuit, comprising: A memory array includes a plurality of static random access memory (SRAM) cells arranged in a matrix having a plurality of rows and a plurality of columns, each row including word lines connected to the SRAM cells in the row, and each column including at least one bit line connected to the SRAM cells in the column. Each SRAM cell includes a first body bias voltage line connected to the body node of a first type of transistor in the SRAM cell. A word line driver circuit for each row, having outputs connected to drive the word lines of said row; The line controller circuit is configured to simultaneously stimulate the plurality of word lines by applying pulses to the word lines via the word line driver circuit for in-memory computation operations; A column processing circuit, connected to the at least one bit line for each column, and configured to process analog voltages formed on the bit lines in response to simultaneous excitation of the plurality of word lines to generate decision outputs for computational operations within the memory; as well as A voltage generator circuit is configured to generate a first modulated body bias voltage applied to the first body bias voltage line, the first modulated body bias voltage having a non-negative voltage level before the simultaneous excitation of the plurality of word lines for computation operations in the memory, and having a negative voltage level during the simultaneous excitation of the plurality of word lines for computation operations in the memory. The voltage generator circuit includes a voltage boost circuit configured to boost the first modulator bias voltage from ground voltage to the negative voltage level in response to a control signal. The boost of the first modulator bias voltage is provided by a capacitive boost circuit, which includes: A transistor having a source coupled to receive the ground voltage, a drain coupled to the first body bias voltage line of the SRAM cell, and a gate configured to receive the control signal. as well as A capacitor having a first terminal coupled to receive the control signal and a second terminal coupled to the drain.

16. An in-memory computing circuit, comprising: A memory array includes a plurality of static random access memory (SRAM) cells arranged in a matrix having a plurality of rows and a plurality of columns, each row including word lines connected to the SRAM cells in the row, and each column including at least one bit line connected to the SRAM cells in the column. Each SRAM cell includes a first body bias voltage line connected to the body node of a first type of transistor in the SRAM cell. A word line driver circuit for each row, having outputs connected to drive the word lines of said row; The line controller circuit is configured to simultaneously stimulate the plurality of word lines by applying pulses to the word lines via the word line driver circuit for in-memory computation operations; A column processing circuit, connected to the at least one bit line for each column, and configured to process analog voltages formed on the bit lines in response to simultaneous excitation of the plurality of word lines to generate decision outputs for computational operations within the memory; as well as A voltage generator circuit is configured to generate a first modulated body bias voltage applied to the first body bias voltage line, the first modulated body bias voltage having a non-negative voltage level before the simultaneous excitation of the plurality of word lines for computation operations in the memory, and having a negative voltage level during the simultaneous excitation of the plurality of word lines for computation operations in the memory. The voltage generator circuit includes a voltage boost circuit configured to boost the first modulator bias voltage from ground voltage to the negative voltage level in response to a control signal. The boost of the first modulator bias voltage is provided by a capacitive boost circuit, which includes: A transistor having a source coupled to receive the ground voltage, a drain coupled to the first body bias voltage line of the SRAM cell, and a gate configured to receive the control signal; and Multiple switched capacitor circuits are coupled to receive the control signal and further coupled to the drain; The switched capacitor circuit is selectively excited to tune the level of the modulator bias voltage.

17. The in-memory computing circuit of claim 16, wherein the level tuning is performed based on integrated circuit processing conditions.

18. The in-memory computing circuit of claim 16, wherein the level tuning is based on integrated circuit temperature conditions.

19. The in-memory computing circuit of claim 1, wherein the voltage generation circuit further comprises a switching circuit configured to selectively apply one of the negative voltage level and the non-negative voltage level to the first body bias voltage line of the SRAM cell.

20. The in-memory computing circuit of claim 1, wherein the optimal level is selected based on integrated circuit processing conditions.

21. An in-memory computing circuit, comprising: A memory array includes a plurality of static random access memory (SRAM) cells arranged in a matrix having a plurality of rows and a plurality of columns, each row including word lines connected to the SRAM cells in the row, and each column including at least one bit line connected to the SRAM cells in the column. Each SRAM cell includes a first body bias voltage line and a second body bias voltage line. The first body bias voltage line is connected to a first body node of a first type transistor in the SRAM, and the second body bias voltage line is connected to a second body node of a second type transistor in the SRAM. A word line driver circuit for each row, having outputs connected to drive the word lines of said row; The line controller circuit is configured to simultaneously stimulate the plurality of word lines by applying pulses to the word lines via the word line driver circuit for in-memory computation operations; A column processing circuit, connected to the at least one bit line for each column, is configured to process analog voltages generated on the bit lines in response to simultaneous excitation of the plurality of word lines to generate decision outputs for computational operations within the memory. as well as A voltage generator circuit is configured to generate a first modulator bias voltage applied to a first body bias voltage line and to generate a second modulator bias voltage applied to a second body bias voltage line, wherein the voltage generator circuit switches the first modulator bias voltage to a first negative voltage level during the simultaneous excitation of the plurality of word lines for computation operations in the memory, and wherein the voltage generator circuit switches the second modulator bias voltage to a second negative voltage level during the simultaneous excitation of the plurality of word lines for computation operations in the memory. The voltage generator circuit is configured to adjust each of the first negative voltage level and the second negative voltage level according to the integrated circuit and / or temperature conditions; The adjusted first negative voltage level and the second negative voltage level are optimal levels for ensuring that unwanted flips are prevented during in-memory computation operations of the data stored in the SRAM cell.

22. The in-memory computing circuit of claim 21, wherein the first type transistor of the SRAM cell is a p-channel transistor, and wherein the second type transistor of the SRAM cell is an n-channel transistor.

23. The in-memory computing circuit of claim 21, wherein the voltage generator circuit is further configured to apply a non-negative voltage level as the first modulator bias voltage and the second modulator bias voltage before simultaneous excitation of the plurality of word lines for the in-memory computing operation.

24. The in-memory computing circuit of claim 23, wherein the non-negative voltage level is grounded.

25. The in-memory computing circuit of claim 21, wherein the voltage generator circuit is configured to adjust each of the first negative voltage level and the second negative voltage level according to integrated circuit processing conditions.

26. The in-memory computing circuit of claim 25, wherein the adjusted first negative voltage level and the second negative voltage level are optimal levels for ensuring that unwanted flips are prevented during the in-memory computing operation of the data stored in the SRAM cell.

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