Adaptive bit line overdrive control for in-memory compute operations with simultaneous access to multiple rows of static random access memory

Abstract

This disclosure relates to adaptive bit-line overdrive control for in-memory computation operations involving simultaneous access to multiple rows of static random access memory (SRAM). A circuit includes a memory array having SRAM cells connected row-wise by word lines and column-wise by bit lines. Row controller circuitry simultaneously actuates word lines in parallel via word line driver circuitry for each row for in-memory computation operations. Column processing circuitry processes analog voltages generated on the bit lines in response to simultaneous actuation to generate decision outputs for in-memory computation operations. Bit-line precharge circuitry generates a precharge voltage to be applied to each pair of bit lines. When the memory array is operating in a data read / write mode, the precharge voltage has a first voltage level (not greater than the positive supply voltage of the SRAM cell). Before the simultaneous actuation of the word lines for in-memory computation operations, the precharge voltage has a second voltage level (greater than the first voltage level).

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 219,897, filed July 9, 2021, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The embodiments described herein relate to in-memory computing circuitry utilizing an array of static random access memory (SRAM), and more specifically, to performing adaptive bit-line overdrive control during simultaneous access to multiple rows of the SRAM array used for in-memory computing operations. Background Technology

[0004] refer to Figure 1 , Figure 1 A schematic diagram of in-memory computation circuitry 10 is shown. Circuitry 10 utilizes a static random access memory (SRAM) array 12, which is formed by standard 6T SRAM memory cells 14 arranged in a matrix format with N rows and M columns. Alternatively, standard 8T memory cells or other SRAM cells with similar functionality and topology can be used. Each memory cell 14 is programmed to store a bit of a computational weight for in-memory computation operations. In this context, in-memory computation operations are understood as high-dimensional matrix-vector multiplication (MVM) supporting multi-bit weights stored in multiple bits of memory. Groups of bit cells (in the case of multi-bit weights) can be considered as virtual synaptic elements. Each bit of the computational weight has a logic "1" or logic "0" value.

[0005] Each SRAM cell 14 includes a word line WL and a pair of complementary bit lines BLT and BLC. An 8T-type SRAM cell will additionally include a read word line RWL and a read bit line RBT. Cells 14 in a common row of the matrix are connected to each other via a common word line WL (and via a common read word line RWL in the 8T-type embodiment). Cells 14 in a common column of the matrix are connected to each other via a pair of common complementary bit lines BLT and BLC (and via a common read bit line RBL in the 8T-type embodiment). Each word line WL, RWL is driven by a word line driver circuit 16, which can be implemented as a CMOS driver circuit (e.g., a series-connected pair of p-channel and n-channel MOSFET transistors forming a logic inverter circuit). Word line signals applied to the word lines and driven by the word line driver circuit 16 are generated from input to feature data in the in-memory computing circuit 10 and controlled by the row controller circuit 18. Column processing circuit 20 senses analog signal voltages on complementary bit line pairs BLT and BLC (and / or read bit line RBL) of M columns and generates decision outputs for in-memory computation operations based on those analog signal voltages. Column processing circuit 20 can be implemented to support processing that first processes the voltages on the columns individually and then combines multiple column outputs.

[0006] Despite Figure 1 Although not explicitly shown, it should be understood that circuit 10 also includes conventional row decoding circuitry, column decoding circuitry, and read / write circuitry known to those skilled in the art, which are used in conjunction with writing bits of calculated weights to SRAM cells 14 of memory array 12 and reading bits of calculated weights from SRAM cells 14 of memory array 12.

[0007] Now for reference Figure 2Each memory cell 14 includes two cross-coupled CMOS inverters 22 and 24, each inverter including a series-connected pair of p-channel and n-channel MOSFET transistors. The inputs and outputs of inverters 22 and 24 are coupled to form a latch circuit with a true data storage node (QT) and a complementary data storage node (QC), which store complementary logic states of the stored data bits. Cell 14 also includes two transmit (transmission gate) transistors 26 and 28, whose gate terminals are driven by a word line (WL). The source-drain path of transistor 26 connects between the true data storage node (QT) and the node associated with the true bit line (BLT). The source-drain path of transistor 28 connects between the complementary data storage node (QC) and the node associated with the complementary bit line (BLC). The source terminals of p-channel transistors 30 and 32 in each inverter 22 and 24 are coupled to receive a high supply voltage (e.g., Vdd) at the high supply node, while the source terminals of n-channel transistors 34 and 36 in each inverter 22 and 24 are coupled to receive a low supply voltage (e.g., ground (Gnd) reference) at the low supply node. Although Figure 2 Specific to the use of 6T-type cells, but those skilled in the art will recognize that 8T-type cells are similarly configured and will also include signal paths coupled to one of the memory nodes, and transmit (transmission gate) transistors coupled to the read word line RWL and gate-driven by signals on the read word line RWL. The word line driver circuit 16 is also typically coupled to receive a high supply voltage (Vdd) at the high supply node and reference a low supply voltage (Gnd) at the low supply node.

[0008] The line controller circuit 18 selects the word line WL during in-memory computation operations. <0> To WL <n-1>The function determines which word lines will be accessed (or actuated) simultaneously and in parallel, and also controls the application of pulse signals to the word lines based on characteristic data for the computational operation in that memory. Figure 1 The simultaneous actuation of all N word lines using pulse word line signals is illustrated by way of example only. It should be understood that in-memory computation operations can instead utilize simultaneous actuation of fewer than all rows of the SRAM array. The analog signal voltage generated on a given complementary bit line pair BLT and BLC (or on the read bit line RBL in the 8T-type embodiment) depends on the logic state of the bits of computation weight stored in the memory cells 14 of the corresponding columns and the width of one or more pulse word line signals applied to those memory cells 14.

[0009] Figure 1 The embodiment illustrated in the figure shows an example of pulse width modulation (PWM) of the applied word line signal for in-memory computation operations. Using PWM or periodic pulse modulation (PTM) for the applied word line signal is a common technique used for in-memory computation operations based on the vector linearity of multiply-accumulate (MAC) operations. The pulsed word line signal format can further evolve into an encoded pulse train to manage the block sparsity of the feature data for in-memory computation operations. Accordingly, it should be appreciated that any set of encoding schemes for the applied word line signals can be used when multiple word lines are driven simultaneously in response to feature data. Furthermore, in a simpler implementation, it should be understood that all applied word line signals can instead have the same pulse width when simultaneously actuated.

[0010] Bit line precharge circuit 42 is connected to each complementary bit line pair BLT and BLC and operates in response to a precharge off control signal PCHoff to charge two bit lines in each pair to a precharge voltage level (e.g., the level of the high supply voltage Vdd). The bit line precharge operation occurs on word line WL during the computation cycle of an in-memory computation operation. <0> To WL <n-1>The simultaneous access is performed before the normal operation of writing data bits to SRAM cell 14 of memory array 12 and reading data bits from SRAM cell 14 of memory array 12 is also performed.

[0011] Figure 3 This is a timing diagram illustrating the deassertion (logic low) of the precharge disconnect control signal PCHoff, used to charge complementary bit line pairs BLT and BLC to the Vdd voltage level, and then the activation (logic high) of the precharge disconnect control signal PCHoff (used to deactuate the precharge circuitry system of precharge circuitry 42), subsequently applying pulse-width modulated word line signals simultaneously to multiple row memory cells 14 in the SRAM array 12 in response to characteristic data for a computation cycle of a given in-memory computation operation. Analog signal voltages Va,T and Va,C are generated over time on the complementary bit line pairs BLT and BLC, respectively, decreasing from the precharge voltage Vdd in response to the pulse width(s) of those word line signals and the logic state of the bits representing computational weights stored in memory cells 14. The representation of the analog voltage Va level shown is merely an example. After all word line signals are deasserted during the calculation cycle, the precharge disconnect control signal PCHoff is deasserted, thereby actuating the precharge circuit system of precharge circuit 42 and precharging the bit lines back to the precharge voltage level to prepare for the next calculation cycle.

[0012] It should be noted that the analog voltage on at least one of the bit lines BLT and BLC may drop from the precharge (Vdd) voltage to a level that causes an undesirable data flip relative to the data bit value stored in one of the column memory cells 14. For example, a logic "1" state stored in the column cell 14 may be flipped to a logic "0" state. Such a data flip introduces data errors into the computational weights stored in the memory cell, thereby jeopardizing the accuracy of subsequent in-memory computation operations.

[0013] Undesirable data flips due to excessive bit line voltage drops are primarily caused by simultaneous parallel access to word lines in matrix-vector multiplication mode during in-memory computation operations. This problem differs from normal data flips in SRAM bit cells, which are caused by static noise margin (SNM) issues during serial bit cell accesses when the bit lines are close to the supply voltage Vdd. Normal data flips during serial access are caused by ground bounces from the data storage node QT or QC.

[0014] Another concern arises from the expectation of operating SRAM arrays at relatively low supply voltages (e.g., Vdd on the order of 0.5 volts to 1.2 volts). In this scenario, the dynamic range of the swings of the analog signal voltages Va,T and Va,C on each pair of bit lines BLT and BLC during in-memory computation operations is correspondingly constrained. Furthermore, the magnitude of the bit line swings can approach levels that increase the risk of unwanted data flips occurring at these points.

[0015] There is a need in the art for SRAM cells that support in-memory computing circuitry, operate at low power supply voltage levels, prevent unwanted data flips during simultaneous access, and provide increased dynamic range for analog voltages generated on complementary bit line pairs to support higher output accuracy. Summary of the Invention

[0016] In one embodiment, a circuit includes: a memory array comprising a plurality of static random access memory (SRAM) cells arranged in a matrix having a plurality of rows and a plurality of columns, each row including word lines connected to the SRAM cells in that row, and each column including at least one bit line connected to the SRAM cells in that column; word line driver circuitry for each row having outputs connected to drive the word lines of that row; row controller circuitry configured to simultaneously actuate a plurality of word lines by applying pulses to the word lines via the word line driver circuitry for in-memory computation operations; and column processing circuitry connected to... The system includes at least one bit line connected to each column and configured to process analog voltages generated on the bit lines in response to simultaneous actuation of multiple word lines to generate decision outputs for in-memory computation operations; and a bit line precharge circuit configured to generate a precharge voltage to be applied to each pair of bit lines, wherein the precharge voltage has a first voltage level not greater than the positive supply voltage for multiple SRAM cells when the memory array is operating in a data read / write mode, and wherein the precharge voltage has a second voltage level greater than the first voltage level before simultaneous actuation of the multiple word lines for in-memory computation operations.

[0017] In one embodiment, a circuit includes: a memory array comprising a plurality of memory cells arranged in a matrix having a plurality of rows and a plurality of columns, each row including word lines connected to the memory cells in that row, and each column including bit lines connected to the memory cells in that column; word line driver circuitry for each row having outputs connected to drive the word lines of that row; row controller circuitry configured to simultaneously actuate the plurality of word lines by applying pulses to the word lines via the word line driver circuitry for in-memory computation operations; column processing circuitry connected to the bit lines of each column and configured to process analog voltages generated on the bit lines in response to the simultaneous actuation of the plurality of word lines to generate decision outputs for in-memory computation operations; and bit line precharge circuitry configured to generate a precharge voltage for applying to each bit line prior to the simultaneous actuation of the plurality of word lines for in-memory computation operations, the precharge voltage having a voltage level greater than the positive supply voltage for the memory cells. Attached Figure Description

[0018] To better understand the embodiments, reference will now be made to the accompanying drawings by way of example only, in which:

[0019] Figure 1 This is a schematic diagram of the in-memory computing circuit;

[0020] Figure 2 yes Figure 1 The circuit diagram shown is of the standard 6T static random access memory (SRAM) cells used by the memory array of the in-memory computing circuit.

[0021] Figure 3 It's a diagram. Figure 1 Timing diagram of in-memory computation operations for the circuit;

[0022] Figure 4 This is a schematic diagram of an in-memory computing circuit that utilizes adaptive bit line overdrive.

[0023] Figure 5 It's a diagram. Figure 4 Timing diagram of in-memory computation operations for the circuit;

[0024] Figure 6A and Figure 6B Timing diagrams for memory read and memory write operations are shown;

[0025] Figure 7 This is a circuit diagram of an embodiment of a circuit used to provide bit line overdrive voltage;

[0026] Figure 8 This is a circuit diagram of another embodiment of a circuit used to provide bit line overdrive voltage;

[0027] Figure 9 This is a circuit diagram of yet another embodiment of a circuit used to provide bit line overdrive voltage;

[0028] Figure 10 The diagram illustrates the combination. Figure 9 Timing diagram of in-memory computation operations in an embodiment;

[0029] Figure 11 This is a circuit diagram of another embodiment of a circuit for providing bit line overdrive voltage;

[0030] Figure 12 It's a flowchart;

[0031] Figure 13 This is a circuit diagram of an embodiment of a circuit for providing overdrive voltage and access to time-division multiplexed bit lines;

[0032] Figure 14 Is using Figure 13 The circuit diagram shown illustrates the 6T SRAM cells used in the memory array for the in-memory computing circuitry; and

[0033] Figure 15 It's a diagram. Figure 13 The timing diagram of the in-memory computation operation of the circuit. Detailed Implementation

[0034] Now for reference Figure 4 , Figure 4 A schematic diagram of an in-memory computing circuit 110 is shown, which uses adaptive bit line overdrive to precharge complementary bit line pairs BLT and BLC. Figure 1 and Figure 4 The same reference numerals refer to the same or similar components and will not be described again (see the description above). Circuit 110 differs from circuit 10 in that the bit line overdrive precharge circuit 142 connected to each complementary bit line pair BLT and BLC operates for each computation cycle of the in-memory computation operation to precharge the bit lines BLT and BLC to an overdrive voltage Vod exceeding the positive supply voltage Vdd (which powers the memory cells 14 of array 12). The operation of the bit line overdrive precharge circuit 142 in conjunction with the execution of the computation cycle of the in-memory computation operation is as follows: The failure (logic low) of the precharge disconnect control signal PCHoff causes the precharge circuit system of the bit line overdrive precharge circuit 142 to charge the two bit lines in each pair to the high supply voltage Vdd level. Then, the precharge disconnect control signal PCHoff is activated to disable the precharge circuitry from charging the Vdd level, and the bit line boost signal BLboost (logic high) causes the boost circuitry within the bit line overdrive precharge circuitry 142 to charge two bit lines in each pair to the overdrive voltage Vod level (where Vod > Vdd). Subsequently, word lines are simultaneously activated in parallel to perform in-memory computation operations.

[0035] Figure 5 This is a timing diagram showing the deactivation (logic low) of the precharge disconnect control signal PCHoff at time ta, causing the precharge circuitry of the bit line overdrive precharge circuitry 142 to charge each complementary bit line pair BLT and BLC to the Vdd voltage level. At this time, the bit line rise signal BLboost is deactivated to prevent activation of the boost circuitry in the bit line overdrive precharge circuitry 142. Next, at time tb, both the precharge disconnect control signal PCHoff and the bit line rise signal BLboost are activated (logic high). At this time, the precharge circuitry is disabled, and the boost circuitry is enabled to charge the complementary bit line pairs BLT and BLC to the overdrive Vdd voltage level. Subsequently, at time tc, for a given in-memory computation operation, pulse width modulated word line signals (in response to feature data) are simultaneously applied to multiple rows of memory cells 14 in the SRAM array 12. Analog signal voltages Va,T and Va,C are generated over time on complementary bit line pairs BLT and BLC, respectively, decreasing from the overdrive voltage Vod level in response to the pulse width(s) of the word line signals and the logic state of the bits with computational weights stored in memory cell 14. The representation of the analog voltage Va level shown is merely an example. It should be noted that the sampling of analog signal voltages Va,T and Va,C is typically performed by column processing circuitry 20 at any appropriate time thereafter (e.g., see time ts). After all word line signals are deactivated for a computation cycle, the precharge disconnect control signal PCHoff and the bit line rise signal BLboost are deactivated to actuate the precharge circuitry system in bit line overdrive precharge circuitry 142 and restore the bit line precharge to the precharge voltage level Vdd in preparation for the next computation cycle. Applying a higher overdrive Vod voltage level to the bit line before in-memory computation helps ensure a higher margin for the analog voltage swing of the bit line and further minimizes the risk that the analog voltage level will drop to a point where an undesirable data flip occurs relative to the data bit value stored in one of the column memory cells 14.

[0036] It should be noted that when writing and reading the calculated weights to SRAM cell 14, the operation of the rise circuitry system that precharges the complementary bit line pairs BLT and BLC to the overdrive voltage Vod level will affect the normal read / write execution of SRAM array 12. Therefore, when SRAM array 12 is operating in normal (regular) data read / write mode, the operation of the rise circuitry system within bit line overdrive precharge circuitry 142, which generates the overdrive voltage Vod level for bit line precharge, is disabled. In the case of performing a read / write operation on the memory, the precharge circuitry system within bit line overdrive precharge circuitry 142 is enabled so that a precharge voltage not exceeding the power supply voltage Vdd for the memory cell (and in a preferred embodiment, may be equal to the power supply voltage Vdd) takes effect. Bit line overdrive precharge circuitry 142 may, for example, receive an enable signal EN. r / w When the enable signal EN is activated r / w When active (e.g., logic low), the operation of raising the circuitry to precharge to the overdrive voltage Vod level is disabled, and the precharge circuitry is allowed to precharge only to a voltage level less than or equal to the supply voltage Vdd level.

[0037] Figure 6A and Figure 6B Timing diagrams for memory read and memory write operations are shown separately, using bit line precharge to the supply voltage Vdd level, because the bit line overdrive precharge circuit 142's rise circuit system has already passed the enable signal EN. r / w It is disabled when set to logically low. Note here that... Figure 3 and Figure 5 The contrast between the in-memory computation operations shown is that, during memory read and memory write operations, only a single word line (here, for example, word line WL) is activated by a pulsed word line signal. <0> (This will take effect.) Note that the explanation of bit line discharge to ground is for illustrative purposes only.

[0038] Now for reference Figure 7 , Figure 7 A circuit diagram is shown of an embodiment of a bit line overdrive precharge circuit 142 for selectively providing a bit line overdrive voltage Vod in response to signals PCHoff and BLboost. Circuit 142 includes a precharge circuit system 300 comprising a first p-channel MOSFET device 302 and a second p-channel MOSFET device 306. The first p-channel MOSFET device 302 has a source coupled (preferably directly connected) to a power supply voltage Vdd node and a drain coupled (preferably directly connected) to at least one real bit line (preferably multiple real bit lines, if not all) in the real bit line (BLT). The second p-channel MOSFET device 306 has a source coupled (preferably directly connected) to a power supply voltage Vdd node and a drain coupled (preferably directly connected) to at least one supplementary bit line (preferably multiple supplementary bit lines, if not all) in the supplementary bit line (BLC). The gates of transistors 302 and 306 are coupled to receive a precharge disconnect control signal PCHoff.

[0039] Circuit 142 further includes a boost circuit system 310, which includes a first capacitor 304 and a second capacitor 308. A first terminal of the first capacitor 304 is coupled to receive a bit line boost signal BLboost, and a second terminal is coupled in series with a switching circuit 305 (which may be implemented by a transistor device) to one or more true bit lines BLT. Similarly, a first terminal of the second capacitor 308 is coupled to receive the bit line boost signal BLboost, and a second terminal is coupled in series with a switching circuit 309 (which may be implemented by a transistor device) to one or more supplementary bit lines BLC. The first and second switching circuits 305 and 309 are enabled by an EN signal. r / w control.

[0040] Circuit 142 operates as follows. The enable signal EN is activated when a normal read / write operation is performed on the SRAM array 12. r / w When the precharge disconnect control signal PCHoff fails (logic low), the first and second switching circuits 305 and 309 are disconnected. When the precharge disconnect control signal PCHoff fails (logic low), transistors 302 and 306 are turned on, and the true bit line BLT and the supplementary bit line BLC are precharged to the Vdd level. Then, the following can be executed: Figure 6A and Figure 6B The image shows the normal operation for reading / writing.

[0041] However, when used for in-memory computation operations, the enable signal EN is activated. r / w When activated (logic high), the second terminals of capacitors 304 and 308 are connected to the actual bit line BLT and the supplementary bit line BLC via switches 305 and 309, respectively. The bit line boost signal BLboost is logic low at the first terminals of capacitors 304 and 308. When the precharge disconnect control signal PCHoff is deactivated (logic low), transistors 302 and 306 are turned on, and the boosted voltage is stored across the first and second capacitors 304 and 308. At this time, the voltages on the complementary bit line pair BLT and BLC are also precharged to the Vdd level. Subsequently, when the precharge disconnect control signal PCHoff is activated (logic high), transistors 302 and 306 are turned off to disconnect the power supply voltage Vdd from the actual bit line BLT and the supplementary bit line BLC. Subsequently, when the bit line boost signal BLboost is activated (logic high), the voltages on the complementary bit line pair BLT and BLC are boosted to the bit line overdrive voltage Vod level by the boosted voltage stored on the first and second capacitors 304 and 308.

[0042] Now for reference Figure 8 , Figure 8 A circuit diagram of an embodiment of a bit line overdrive precharge circuit 142 for selectively providing a bit line overdrive voltage Vod is shown. Circuit 142 includes a precharge circuit system 320 comprising a first p-channel MOSFET device 322 and a second p-channel MOSFET device 326. The first p-channel MOSFET device 322 has a source coupled (preferably, directly connected) to a power supply voltage Vdd node and a drain coupled (preferably, directly connected) to at least one true bit line (preferably multiple true bit lines, if not all) of the true bit lines BLT. The second p-channel MOSFET device 326 has a source coupled (preferably, directly connected) to a power supply voltage Vdd node and a drain coupled (preferably, directly connected) to at least one supplementary bit line (preferably multiple supplementary bit lines, if not all) of the supplementary bit lines BLC. The gates of transistors 322 and 326 are coupled to receive a precharge disconnect control signal PCHoff.

[0043] Circuit 142 also includes a boost circuit system 330, which includes multiple switched capacitor circuits 314 connected in parallel and coupled between the node receiving the bit line boost signal BLboost and one or more actual bit lines BLT, and multiple switched capacitor circuits 318 connected in parallel and coupled between the node receiving the bit line boost signal BLboost and one or more supplementary bit lines BLC. Each switched capacitor circuit 314, 318 includes a capacitor C connected in series with a switch S (which may be implemented by a transistor device). Digital control circuit 340 generates a multi-bit digital control signal Csel, which, in combination with pre-charging the bit line to a Vdd voltage and generating and selectively applying a bit line overdrive voltage Vod level, selectively actuates one or more switches in the switches S of the switched capacitor circuits 314 and 318.

[0044] Circuit 142 operates as follows. The enable signal EN is activated when a normal read / write operation is performed on the SRAM array 12. r / w When the logic is low (failure occurs), the digital control circuit 340 controls all switches S of the switched capacitor circuits 314 and 318 to open. When the precharge disconnect control signal PCHoff fails (logic low), transistors 322 and 326 are turned on, and the true bit line BLT and the supplementary bit line BLC are precharged to the Vdd level. Then, the following can be executed: Figure 6A and Figure 6B The image shows the normal operation for reading / writing.

[0045] However, when used for in-memory computation operations, the enable signal EN is activated. r / w When active (logic high), the digital control circuit 340 enables selective actuation of switches S in switched capacitor circuits 314 and 318 to support modulation of the bit line overdrive voltage Vod level. The bit line boost signal BLboost is logic low. When the precharge disconnect control signal PCHoff is deactivated (logic low), transistors 322 and 326 are turned on, and the boost voltage is stored across each capacitor C, whose corresponding switch S has been actuated (selected) by the digital control circuit 340. At this time, the voltages on the complementary bit line pairs BLT and BLC are also precharged to the Vdd level. Subsequently, when the precharge disconnect control signal PCHoff is active (logic high), transistors 322 and 326 are turned off to disconnect the power supply voltage Vdd from the actual bit line BLT and the complementary bit line BLC. Subsequently, when the bit line boost signal BLboost is active (logic high), the voltages on the complementary bit line pairs BLT and BLC are boosted to the bit line overdrive voltage Vod level by the boost voltage stored on one or more selected capacitors C.

[0046] Selective actuation of switch S provides flexibility in the level of the modulated bit line overdrive voltage Vod. This offers the opportunity to program the overdrive voltage level in response to operating conditions such as: setting the overdrive level in response to write interference issues during multi-line access; adjusting the overdrive level up or down depending on the number of word lines being accessed to optimize power without sacrificing output accuracy; and controlling the overdrive level depending on process conditions and / or temperature to set desired power, performance, and area (PPA) characteristics.

[0047] Regarding the modulation of the bit line overdrive voltage Vod level, which depends on integrated circuit process information, process data can be provided to the digital control circuit 340. This process data pertains to whether the MOSFET devices of memory cell 12 are at a fast-slow (where NMOS is faster and PMOS is slower) or fast-fast (where NMOS is faster and PMOS is faster) process corner. In response to this information, the digital control circuit 340 can activate a bit of the multi-bit digital control signal Csel to control the selection of switched capacitor circuits 314 and 318, thereby providing a relatively high voltage level for the bit line overdrive voltage Vod. Similarly, regarding the modulation of the bit line overdrive voltage Vod level, which depends on integrated circuit temperature information, data about the current temperature conditions can be provided to the digital control circuit 340. In response to this information, the digital control circuit 340 can activate the bits of the multi-bit digital control signal Csel to control the selection of the switched capacitor circuits 314 and 318, thereby adjusting the level of the bit line overdrive voltage Vod to mitigate write interference problems during multi-line access and / or optimize operation at the desired PPA point.

[0048] Now for reference Figure 9 , Figure 9 A circuit diagram of an embodiment of a bit line overdrive precharge circuit 142 for providing a bit line overdrive voltage Vod is shown. Circuit 142 includes a voltage generator circuit 350 configured to generate the bit line overdrive voltage Vod. The voltage generator circuit 350 may, for example, include a voltage regulator circuit (such as a low-dropout (LDO) regulator) that generates the bit line overdrive voltage Vod from an input voltage. Alternatively, the voltage generator circuit 350 may, for example, include a charge pump circuit that generates the bit line overdrive voltage Vod from a supply voltage Vdd. The output of the voltage generator circuit 350 is selectively coupled to an intermediate power node 352 via a first switch S1. The supply voltage Vdd is selectively coupled to an intermediate power node 354 via a second switch S2. When in-memory compute operation mode, the first switch S1 is closed and the second switch S2 is open. When in normal memory read / write operation mode, the first switch S1 is open and the second switch S2 is closed. Switches S1 and S2 (which may be implemented by transistor devices) may be enabled, for example, by an enable signal EN. r / w The logic is inverted for control, so that when the enable signal EN is activated... r / w When enabled (e.g., logic low), switch S1 is open and switch S2 is closed, and when the enable signal EN is activated... r / w In the event of a failure (e.g., logic high), switch S1 closes and switch S2 opens. Circuit 142 also includes a first p-channel MOSFET device 354 having a source coupled (preferably, directly connected) to intermediate power node 352 and a drain coupled (preferably, directly connected) to one or more true bit lines BLT. The gate of transistor 354 is coupled to receive a level-shifted version of the precharge disconnect control signal PCHoff. A second p-channel MOSFET device 356 has a source coupled (preferably, directly connected) to intermediate power node 352 and a drain coupled (preferably, directly connected) to one or more supplementary bit lines BLC. The gate of transistor 356 is also coupled to receive a level-shifted version of the precharge disconnect control signal PCHoff.

[0049] Circuit 142 operates as follows. If the enable signal EN is activated because the memory array is operating in read / write mode... r / w When the precharge disconnect control signal PCHoff is enabled (logic low), switch S2 closes, switch S1 opens, and the power supply voltage Vdd is applied to intermediate power node 352. When the precharge disconnect control signal PCHoff is disabled (logic low), transistors 354 and 356 are turned on, and complementary bit line pairs BLT and BLC are precharged to the power supply voltage Vdd. When the precharge disconnect control signal PCHoff is subsequently enabled (logic high) in conjunction with a read or write operation related to memory array 12, transistors 354 and 356 are turned off. Conversely, if the enable signal EN is enabled because the in-memory computing circuit is performing an in-memory computing operation... r / w When the precharge disconnect control signal PCHoff is disabled (logic high), switch S1 closes, switch S2 opens, and the bit line overdrive voltage Vod output from voltage generator circuit 350 is applied to intermediate power node 352. When the precharge disconnect control signal PCHoff is disabled (logic low), transistors 354 and 356 are turned on, and complementary bit line pairs BLT and BLC are precharged to the bit line overdrive voltage Vod level. When the precharge disconnect control signal PCHoff is subsequently enabled (logic high) in conjunction with an in-memory computation operation performed with respect to memory array 12, transistors 354 and 356 are turned off, and analog voltage levels are allowed to be generated on bit lines BLT and BLC.

[0050] Figure 9 The timing of this operation of circuit 142 and Figure 5 The illustration is slightly different, and alternatively, refer to... Figure 10 , Figure 10 The relationship between the precharge disconnect control signal PCHoff and the logic states of overdrive voltage bit line precharge and in-memory computation operations is illustrated. The activation of signal S1 charges complementary bit line pairs BLT and BLC to the precharge voltage level Vdd. At time ta, the deactivation of signal S1 (logic low) along with the activation of signal S2 (logic high) allows the charge on the bit lines to be changed to the overdrive voltage level Vod. The precharge disconnect control signal PCHoff controls the conductivity of transistors 354 and 356 to allow Vdd and Vod voltages to charge the bit lines. The subsequent activation of the precharge turn-off control signal PCHoff (logic high) turns off transistors 354 and 356. At time tb, in response to characteristic data for a given in-memory computation operation, pulse-width modulated word line signals are simultaneously applied to multiple row memory cells 14 in the SRAM array 12. Analog signal voltages Va,T and Va,C are generated over time on complementary bit line pairs BLT and BLC, respectively, decreasing from the overdrive voltage Vod level in response to the pulse width(s) of the word line signal and the logic state of the bits with calculated weights stored in memory cell 14. The representation of the analog voltage Va level shown is merely an example. It should be noted that the sampling of analog signal voltages Va,T and Va,C is typically performed by column processing circuitry 20 at any appropriate time thereafter (e.g., see time ts). After sampling, the precharge disconnect control signal PCHoff is deactivated to turn on transistors 154 and 356, and the switch signal S1 is activated to cause the precharge circuitry to charge the bit lines BLT and BLC back to the precharge voltage level Vdd. The higher overdrive Vod voltage level on the bit lines helps ensure a higher margin for the analog voltage swing of the bit lines and further minimizes the risk that the analog voltage level will drop to a point where an undesirable data flip occurs relative to the data bit value stored in one of the memory cells 14 of the column.

[0051] Now for reference Figure 11 , Figure 11 A circuit diagram of an embodiment of a bit line overdrive precharge circuit 142 for providing bit line overdrive voltage Vod is shown. Figure 9 and Figure 11 The same reference markers refer to the same or similar components, and their descriptions will not be repeated (see the description above). Figure 11 The circuits in Figure 9 The difference in the circuit is that the level of the bit line overdrive voltage Vod is modulated depending on the integrated circuit process and / or temperature conditions.

[0052] Voltage generator circuit 350 receives a control signal Vsel. In one embodiment, signal Vsel is a digital control signal; however, it should be understood that an analog control signal may be used alternatively. The digital value of the bits of control signal Vsel selects the level of the bit line overdrive voltage Vod output by voltage generator circuit 350. Control signal Vsel is generated by control circuit 114 in response to integrated circuit process and / or temperature information, and therefore the level of bit line overdrive voltage Vod is modulated in a manner dependent on the integrated circuit process and / or temperature information.

[0053] Integrated circuit process information is represented by digital codes stored in memory M within control circuitry 114. These digital codes represent the centering of a process batch and are generated by a circuit system such as a ring oscillator (RO), the output frequency of which varies depending on the integrated circuit process. Therefore, the output frequency of the RO circuit represents the process centering and can be easily converted into digital codes (e.g., using a counter circuit). Process monitoring circuitry 116 within control circuitry 114 can generate a digital value for a control signal Vsel based on the stored digital codes specific to the integrated circuit process. For example, process monitoring circuitry 116 may include a lookup table (LUT) that associates each digital code with a digital value for the control signal Vsel to provide a specific level of the bit line overdrive voltage Vod, which will produce optimal performance for in-memory computation operations for the integrated circuit process corner, for example, limiting a wide range of levels in the sensing circuitry before output and limiting power losses due to bit line switching, regardless of process and / or temperature. The control circuit 114 outputs a digital value of the control signal Vsel associated with the stored digital code, and the voltage generator circuit 350 responds by generating a corresponding level for the bit line overdrive voltage Vod.

[0054] Temperature information is generated by temperature sensing circuit 118 and represents the current temperature of the integrated circuit. Temperature sensing circuit 118 can select, modify, or adjust the digital value of control signal Vsel based on the sensed temperature. For example, temperature sensing circuit 118 may include a lookup table (LUT) that specifies a (positive or negative) adjustment to the digital value of control signal Vsel to provide a corresponding tuning for a specific level of bit line overdrive voltage Vod, which will produce optimal performance given the integrated circuit process corner and current temperature conditions.

[0055] Now for reference Figure 12 , Figure 12 It shows the use of Figure 11 The flowchart describes the operation of the control circuit 114 and the process monitoring circuit 116 of the circuit. In step 240, the stored digital code for the integrated circuit process is read from the memory M. In one embodiment, the digital code for the integrated circuit process is loaded into the memory M at the factory, and this digital code is based on the identified integrated circuit process characteristics (fast / slow angle, etc.) for the integrated circuit manufacturing batch (e.g., source wafer), from which the integrated circuit is obtained. Next, in step 242, it is determined whether the read digital code for the integrated circuit process indicates that the MOSFET device of the memory cell 12 is at a certain integrated circuit process angle. If so, then in step 244, a digital value for the control signal Vsel is selected, corresponding to the read digital code, and will cause the voltage generator circuit 350 to generate a higher degree of bit line overdrive (i.e., the level used for adaptive bit line overdrive voltage Vod will be higher than the nominal (or default) level). The effect of the increased bit line overdrive voltage Vod level, higher than the nominal (or default) level, during multi-line access ensures that the bit line discharge level does not exceed the write interference level and also ensures higher headroom availability for bit line sway to support higher output accuracy. If step 242 is negative, then in step 246 it is determined whether the read digital code for the integrated circuit process indicates that the MOSFET device of memory cell 12 is in another integrated circuit process corner. If yes, then in step 248 a digital value for the control signal Vsel is selected, which corresponds to the read digital code and will cause the voltage generator circuit 350 to generate a lower level of bit line overdrive (i.e., the level used for adaptive bit line overdrive voltage Vod will be lower than the nominal (or default) level). The effect of reducing the bit line overdrive voltage Vod level to be lower than the nominal (or default) level is to ensure bit line level optimization to limit a wide range of levels of the sensing circuit system before output and to limit power loss due to bit line switching, regardless of process / temperature conditions. If step 246 is negative, then in step 250 a digital value for the control signal Vsel is selected, which corresponds to the read digital code and will cause the voltage generator circuit 350 to generate a bit line overdrive voltage Vod level equal to the nominal (or default) level.

[0056] although Figure 12 The process envisions three levels of voltage control (above, below, and equal to nominal), but it should be understood that this is merely an example. Additional test steps can be added. Figure 12 During the process, other integrated circuit process corners or process-related conditions are tested, where each test has an associated digital code and a digital value of the control signal Vsel to set the corresponding level of the bit line overdrive voltage Vod generated by the voltage generator circuit 350.

[0057] Now for reference Figure 13 , Figure 13 A schematic diagram of an in-memory computing circuit 210 is shown, which uses adaptive bit line overdrive to precharge complementary bit line pairs BLT and BLC. Figure 4 and Figure 13 The same reference numerals in the diagram indicate the same or similar components, and their description will not be repeated (see the description above). The difference between circuit 210 and circuit 110 is that the word line access control for the true side and complement side of each SRAM cell has been split, as shown below. Figure 14 As shown in more detail below. Each cell 14 includes a first transfer (transmission gate) transistor 26 for the true side of the latch, the transistor 26 having a gate terminal driven by a first word line WL1. The transistor 26 is source-drain connected between the true data storage node QT and the node associated with the true bit line BLT. Each cell 14 also includes a second transfer (transmission gate) transistor 28 for the supplementary side of the latch, the transistor 28 having a gate terminal driven by a second word line WL2. The transistor 28 is source-drain connected between the supplementary data storage node QC and the node associated with the supplementary bit line BLC. With this configuration, word line access to each side of the memory cell 14 can be controlled independently. The circuit also supports a phase (first phase p1) of performing in-memory computation operations associated only with the actuation of the first word line WL1 in response to accessing / reading feature data on the true side of the latch, and another phase (second phase p2) of performing in-memory computation operations associated only with the actuation of the second word line WL2 in response to accessing / reading feature data on the supplementary side of the latch. The first and second word lines WL1 and WL2 will have word line signals generated from the same feature data, and therefore have the same pulse width.

[0058] The difference between circuit 210 and circuit 110 lies in that the bit line overdrive precharge circuit 142 connected to each complementary bit line pair BLT and BLC operates to independently precharge the bit lines BLT and BLC to the overdrive voltage Vod used for in-memory computation operations. In response to the failure (logic low) of the first precharge disconnect control signal PCHoff_T, the precharge circuitry of bit line overdrive precharge circuit 142 charges the actual bit line BLT in each pair to the high supply (precharge) voltage Vdd level. Then, in response to the activation (logic high) of the first precharge disconnect control signal PCHoff_T, combined with the execution of one phase of the in-memory computation operation associated only with the actuation of the first word line WL1, the rise circuitry of bit line overdrive precharge circuit 142 charges the actual bit line BLT in each pair to the overdrive voltage Vod level. Similarly, in response to the failure (logic low) of the second precharge disconnect control signal PCHoff_C, the precharge circuitry of the bit line overdrive precharge circuitry 142 charges the supplementary bit line BLC in each pair to the high power supply (precharge) voltage Vdd level. Then, in response to the activation (logic high) of the second precharge disconnect control signal PCHoff_C, combined with the execution of another phase of the in-memory computation operation associated only with the actuation of the second word line WL2, the rise circuitry of the bit line overdrive precharge circuitry 142 charges the supplementary bit line BLC in each pair to the overdrive voltage Vod level.

[0059] Figure 15 This is a timing diagram illustrating the circuitry of a computation cycle for an in-memory computation operation performed in a time-multiplexed manner on the true and supplementary sides of a latch for a given column of SRAM cells in the array. Both the true bit line BLT and the supplementary bit line BLC respond to the failure (logic low) state of the first and second precharge disconnect control signals PCHoff_T and PCHoff_C, and are precharged to the desired voltage level by the bit line precharge circuitry at time ta (here, by example, precharged to the Vdd voltage level, but other voltage levels can be selected). In the first phase p1 of the computation cycle for the in-memory computation operation, at time tb1, the first precharge disconnect control signal PCHoff_T is activated (logic high), and the raised circuitry charges the true bit line BLT to the overdrive Vod voltage level. Then, for a given in-memory computation operation, in response to the characteristic data, pulse-width modulated word line signals are simultaneously applied to the first word lines WL1 of multiple rows of memory cells 14 in the SRAM array 12. The analog signal voltage Va,T is generated over time on the actual bit line BLT, decreasing from the overdrive voltage Vod in response to the pulse width(s) of those word line signals and the logic state of the bits with calculated weights stored on the actual side of memory cell 14. The representation of the analog voltage Va,T level shown is merely an example.

[0060] In the second phase p2 of the computation cycle used for in-memory computation operations, at time tb2, the second precharge disconnect control signal PCHoff_C is activated (logic high), and the raised circuitry charges the supplementary bit line BLC to the overdrive voltage level Vod. In response to the feature data, word line signals of the same pulse width modulated for a given in-memory computation operation are then simultaneously applied to the second word lines WL2 of the plurality of row memory cells 14 in the SRAM array 12. Analog signal voltage Va,C is generated on the supplementary bit line BLC over time, decreasing from the overdrive voltage Vod in response to the pulse width(s) of those word line signals and the logic state of the bits with computational weights stored on the supplementary side of the memory cell 14. The representation of the analog voltage Va,C level shown is merely an example.

[0061] After all word line signals are disabled, the first and second precharge disconnect control signals PCHoff_T and PCHoff_C are disabled at the end of the calculation cycle to cause the precharge circuit system in the bit line overdrive precharge circuit 142 to be overcharged, and the actual bit line and supplementary bit line are precharged back to the precharge voltage level. In one embodiment, the first precharge disconnect control signal PCHoff_T can be disabled after all the first word line signals are disabled, and the second precharge disconnect control signal PCHoff_C can be disabled after all the second word line signals are disabled.

[0062] The column processing circuit 20 senses analog signal voltages on complementary bit line pairs BLT and BLC for M columns and generates decision outputs for in-memory computation operations based on those analog signal voltages. It should be noted that the sampling of analog signal voltages Va,T and Va,C is typically performed by the column processing circuit 20 at two separate times. The first time is associated with the simultaneous application of pulse-width modulated word line signals to the first word line WL1 during a first phase p1 (at time ts1), where the true side of the latch circuit is accessed, and the second time is associated with the simultaneous application of pulse-width modulated word line signals to the second word line WL1 during a second phase p2 (at time ts2), where the supplementary side of the latch circuit is accessed.

[0063] The foregoing description has provided a complete and informative description of exemplary embodiments of the invention by way of exemplary and non-limiting examples. However, various modifications and adaptations may become apparent to those skilled in the art when read in conjunction with the accompanying drawings and appended claims, given the foregoing description. Nevertheless, all such modifications and similar alterations to the teachings of the invention will still fall within the scope of the invention as defined in the appended claims.

Claims

1. A circuit comprising: A memory array comprising a plurality of static random access memory cells arranged in a matrix having a plurality of rows and a plurality of columns, each row comprising a word line connected to the static random access memory cells of the row, and each column comprising at least one bit line connected to the static random access memory cells of the column. A word line driver circuit for each row, the word line driver circuit having an output connected to drive the word line of the row; A row controller circuit configured to simultaneously actuate the plurality of word lines by applying pulses to the word lines via the word line driver circuit for in-memory computation operations; A column processing circuit, connected to the at least one bit line for each column, and configured to process analog voltages generated on the bit lines in response to the simultaneous actuation of the plurality of word lines to generate a decision output for the in-memory computation operation; as well as Bit line precharge circuit, configured to generate a precharge voltage to be applied to each pair of bit lines, wherein when the memory array operates in a data read / write mode, the precharge voltage has a first voltage level not greater than the positive supply voltage for the plurality of static random access memory cells, and wherein the precharge voltage has a second voltage level greater than the first voltage level prior to the simultaneous actuation of the plurality of word lines for the in-memory computation operation.

2. The circuit of claim 1, wherein the bit line precharge circuit includes a voltage boosting circuit configured to boost the precharge voltage from the first voltage level to the second voltage level in response to a control signal generated in response to the end of precharge to the first voltage level.

3. The circuit according to claim 2, wherein the increase in pre-charge voltage is provided by a capacitive voltage boosting circuit, the capacitive voltage boosting circuit comprising: A capacitor having a first terminal coupled to receive the control signal and a second terminal coupled to the bit line; A switch, wherein the switch is coupled in series with the capacitor between the control signal and the bit line; as well as A control circuit configured to selectively actuate the switch.

4. The circuit of claim 3, wherein the control circuit selectively actuates the switch in response to information about the integrated circuit process and / or temperature conditions in order to set the second voltage level.

5. The circuit of claim 3, wherein the control circuit de-actuates the switch in response to operation of the memory array in a data read / write mode.

6. The circuit of claim 2, wherein the increase in pre-charge voltage is provided by a capacitive voltage boosting circuit, the capacitive voltage boosting circuit comprising: Multiple switched capacitor circuits are connected in parallel and coupled between the control signal and the bit line, and each switched capacitor circuit includes a capacitor coupled in series with a switch. as well as A control circuit configured to selectively actuate the switches in the plurality of switched capacitor circuits.

7. The circuit of claim 6, wherein the control circuit selectively actuates certain switches of the switches in response to information about the integrated circuit process and / or temperature conditions in order to set the second voltage level.

8. The circuit of claim 6, wherein the control circuit de-actuates the switch in response to operation of the memory array in a data read / write mode.

9. The circuit of claim 1, wherein the bit line pre-charge circuit comprises: A voltage generator circuit, the voltage generator circuit being configured to generate the second voltage level of the pre-charge voltage; as well as A switching circuit configured to selectively apply one of the first voltage level and the second voltage level to the bit line in response to a first control signal.

10. The circuit of claim 9, wherein the first control signal indicates whether the memory array is operated to perform the in-memory computation operation or to operate in the data read / write mode, wherein in the in-memory computation operation the switching circuit selectively applies the second voltage level to the intermediate node, and in the data read / write mode the switching circuit selectively applies the first voltage level to the intermediate node.

11. The circuit of claim 10, wherein the bit line precharge circuit further comprises a transistor having a source-drain path coupled between the intermediate node and the bit line, the transistor having a gate configured to receive a second control signal indicating actuation of a precharge operation on the bit line.

12. The circuit of claim 1, wherein the bit line precharge circuit includes a voltage generator circuit configured to generate the precharge voltage, wherein the voltage generator circuit is controlled to generate the second voltage level, and the bit line precharge circuit further includes a control circuit configured to generate a control signal for application to the voltage generator circuit.

13. The circuit of claim 12, wherein the control signal is configured to cause modulation of the second voltage level away from the nominal level in response to the applicable integrated circuit process corner of the transistor device of the static random access memory cell.

14. The circuit of claim 13, wherein the applicable integrated circuit process corner is indicated by programming code stored in the control circuit, and wherein the control circuit includes a lookup table that correlates the programming code with the value of the control signal.

15. The circuit of claim 13, wherein the control circuit further comprises a temperature sensor, and wherein the control signal is configured to cause temperature-dependent tuning of the second voltage level in response to an applicable integrated circuit process corner.

16. The circuit of claim 15, wherein the control circuit includes a lookup table that correlates the sensed integrated circuit temperature with a tuning level for the value of the control signal.

17. The circuit of claim 12, wherein the control circuit further comprises a temperature sensor, and wherein the control signal is configured to modulate a second voltage level away from a nominal level in response to an integrated circuit temperature sensed by the temperature sensor.

18. The circuit of claim 17, wherein the control circuit includes a lookup table that correlates the sensed integrated circuit temperature with the value of the control signal.

19. The circuit of claim 1, wherein the at least one bit line comprises a pair of bit lines, and wherein the word line connected to the static random access memory cell of the row comprises: A first word line, configured to drive a first transmission gate transistor of the static random access memory cell coupled between a first data node and a bit line in the bit line pair; The second word line is configured to drive the second transmission gate transistor of the static random access memory cell coupled between the second data node and another line in the bit line pair; The row controller circuit is configured to simultaneously actuate the first word line in the first phase of the in-memory computation operation, and then simultaneously actuate the second word line in the second phase of the in-memory computation operation.

20. The circuit of claim 19, wherein the bit line precharge circuit is configured to: Prior to the first phase of the in-memory computation operation, a precharge voltage at the second voltage level is generated for application to one bit line in each pair of bit lines; and Prior to the second phase of the in-memory computation operation, a precharge voltage at the second voltage level is generated for application to the other bit in each pair of bit lines.

21. The circuit of claim 20, wherein the bit line precharge circuit is further configured to hold the other bit of each pair of bit lines to the first voltage level prior to the first phase of the in-memory computation operation.

22. A circuit comprising: A memory array comprising a plurality of memory cells arranged in a matrix having a plurality of rows and a plurality of columns, each row comprising word lines connected to memory cells in the row, and each column comprising bit lines connected to memory cells in the column. A word line driver circuit for each row, the word line driver circuit having an output connected to drive the word line of the row; A row controller circuit configured to simultaneously actuate the plurality of word lines by applying pulses to the word lines via the word line driver circuit for in-memory computation operations; A column processing circuit connected to the bit line of each column and configured to process analog voltages generated on the bit lines in response to the simultaneous actuation of the plurality of word lines to generate a decision output for the in-memory computation operation; as well as Bit line precharge circuitry is configured to generate a precharge voltage to be applied to each bit line prior to the simultaneous actuation of the plurality of word lines for the in-memory computation operation, the precharge voltage having a voltage level greater than the positive power supply voltage for the memory cell.

23. The circuit of claim 22 further includes a voltage generator circuit configured to generate the precharge voltage, wherein the voltage level of the precharge voltage depends on information regarding the integrated circuit process and / or temperature conditions.

24. The circuit according to claim 22, further comprising: A boost circuit is configured to generate the precharge voltage, wherein the voltage level of the precharge voltage depends on information about the integrated circuit process and / or temperature conditions.

25. The circuit of claim 22, wherein the bit line precharge circuit includes a voltage generator circuit configured to generate the precharge voltage, wherein the voltage generator circuit is controlled to generate the voltage level, and the bit line precharge circuit further includes a control circuit configured to generate a control signal for application to the voltage generator circuit.

26. The circuit of claim 25, wherein the control signal is configured to cause modulation of the voltage level away from the nominal level in response to the applicable integrated circuit process corner of the transistor device of the memory cell.

27. The circuit of claim 26, wherein the applicable integrated circuit process corner is indicated by programming code stored in the control circuit, and wherein the control circuit includes a lookup table that correlates the programming code with the value of the control signal.

28. The circuit of claim 26, wherein the control circuit further comprises a temperature sensor, and wherein the control signal is configured to cause temperature-dependent tuning of the voltage level in response to an applicable integrated circuit process corner.

29. The circuit of claim 28, wherein the control circuit includes a lookup table that correlates the sensed integrated circuit temperature with a tuning level of the value of the control signal.

30. The circuit of claim 25, wherein the control circuit further comprises a temperature sensor, and wherein the control signal is configured to modulate the voltage level away from the nominal level in response to an integrated circuit temperature sensed by the temperature sensor.

31. The circuit of claim 30, wherein the control circuit includes a lookup table that correlates the sensed integrated circuit temperature with the value of the control signal.

32. The circuit of claim 22, wherein the bit line precharge circuit is further configured to read data from or write data to the memory cells in conjunction with the operation of the memory array to generate the precharge voltage for applying to each bit line, the precharge voltage having a voltage level not greater than the positive power supply voltage of the memory cell.

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