Parallel programming of multiple cells of a non-volatile memory device

Abstract

Techniques are disclosed herein for programming the same data pattern in parallel in multiple groups of non-volatile memory cells. A voltage is applied to bit lines according to a data pattern. A select voltage is applied to drain select gates of multiple groups of NAND strings. While the select voltage is applied to the drain select gates of the multiple groups of NAND strings and the voltage is applied to the multiple bit lines, the system applies a program pulse in parallel to control gates of different groups of selected memory cells in each respective group of the multiple groups of NAND strings to program the data pattern in parallel into each group of selected memory cells.

Description

[0001] Priority Claim

[0002] This application is a partial continuation-in-place of U.S. Patent Application No. 17 / 227,820, filed April 12, 2021, entitled "Concurrent Programming of Multiple Cells for Non-Volatile Memory Devices," which is a divisional application of U.S. Patent Application No. 16 / 024,002, filed June 29, 2018, also entitled "Concurrent Programming of Multiple Cells for Non-Volatile Memory Devices." Both applications are incorporated herein by reference in their entirety. Technical Field

[0003] In various embodiments, this disclosure relates to storage devices, and more particularly, to systems and methods for parallel programming of multiple cells of a non-volatile storage device. Background Technology

[0004] Many data storage devices, such as flash memory devices, store data in non-volatile media cells. The physical characteristics of each cell, such as stored charge, voltage, material phase, resistance, magnetization, etc., can be varied to encode the data. The physical characteristics of a cell can vary within a range, which can be divided into discrete states, such that different states correspond to different data values. Sensing whether the physical characteristics of a cell meet one or more read thresholds (e.g., voltage threshold, resistivity threshold, etc.) within its range determines the state of the cell, thereby allowing the recovery of the stored data value.

[0005] Non-volatile memory types include, but are not limited to, ReRAM, memristor memory, programmable metallized cell memory, phase-change memory (PCM, PCME, PRAM, PCRAM, bidirectional unified memory, chalcogenide RAM, or C-RAM), NAND flash memory (e.g., 2D NAND flash memory, 3D NAND flash memory), NOR flash memory, nanoscale random access memory (nanoRAM or NRAM), nanocrystalline wire-based memory, silicon oxide-based sub-10nm process memory, graphene memory, silicon-oxide-nitride-oxide-silicon (SONOS), programmable metallized cell (PMC), conductive bridged RAM (CBRAM), magnetoresistive RAM (MRAM), spin-transfer torque (STT) MRAM, spin-orbit torque (SOT) MRAM, magnetic storage media (e.g., hard disks, magnetic tapes), optical storage media, and so on. In non-volatile memory types used to encode information in retained charge, various charging and / or charge retention techniques can be used, including, but not limited to, floating gate and charge trapping techniques.

[0006] In many of the aforementioned techniques, storage cells within different blocks are programmed through individual operations. In some instances, multiple copies of the data are temporarily written to corresponding groups of storage cells before being stored in a multi-level cell (MLC). Examples of multi-level cells include two-level cells, three-level cells (TLC), four-level cells (QLC), five-level cells (PLC), and so on. If the temporarily stored data is written to cells of different capacities, such as single-level cells (SLC), cell compression operations (folding operations) can be used to combine multiple bits of the temporarily stored data in the SLC cell to provide the value to be encoded into the MLC cell. The traditional method of writing and verifying temporary copies individually increases the time and number of steps required to encode the MLC cell. Summary of the Invention

[0007] Presents apparatus and methods for parallel programming of multiple memory cells of one or more nonvolatile memory elements.

[0008] Apparatus and methods are presented for parallel programming of a plurality of memory cells of one or more nonvolatile memory elements. In one example, the memory die includes: a set of nonvolatile memory cells arranged in a first block containing a first string of memory cells intersecting a first word line at a first memory cell and a second block containing a second string of memory cells intersecting a second word line at a second memory cell; bit lines electrically connected to the first string and the second string; and a controller configured to apply programming pulses in parallel to the first word line and the second word line to program the first and second memory cells in parallel to a common target threshold voltage.

[0009] In another instance, the controller is further configured to: after applying the programming pulse in parallel to the first word line and the second word line, apply a verification pulse in parallel to the first word line and the second word line, sense the current flowing through one of the first memory cell and the second memory cell in response to the application of the verification pulse to determine that one of the first memory cell and the second memory cell is not correctly programmed, and initiate separate programming of the first memory cell and the second memory cell in response to determining that one of the first memory cell and the second memory cell is not correctly programmed.

[0010] In one example embodiment, the separate programming of the first storage unit and the second storage unit includes: applying a regular programming operation to the first storage unit, and applying a regular programming operation to the second storage unit after verifying that the first storage unit has been correctly programmed.

[0011] In one example, the controller is further configured to: after applying the conventional programming pulse to the second cell, apply a second verification pulse to the first cell, sense the current flowing through one of the first and second cell in response to the application of the second verification pulse to determine that the first cell is correctly programmed, and after applying the second verification pulse to the first cell, apply a third verification pulse to the second cell, and sense the current flowing through one of the first and second cell in response to the application of the third verification pulse to determine that the second cell is correctly programmed.

[0012] In another instance, the controller is further configured to: determine that the first storage unit is correctly programmed, read data from the first storage unit in response to determining that the first storage unit is correctly programmed, and overwrite the first storage unit and the second storage unit after reading the data from the first storage unit.

[0013] In one example embodiment, the controller is further configured to read data from one of the first and second memory cells and program a multi-level cell using the data through a cell compression operation. Generally, a cell compression (also known as memory cell compression) operation is an operation that acquires data values ​​stored in an original memory cell holding one or more data values ​​and moves those data values ​​to a cell capable of holding more data values ​​than the number held in the original memory cell. For example, in one embodiment, the cell compression operation is SLC-TLC cell compression, meaning that data values ​​in a memory cell holding a single data value are moved by storing them in a combinatorial encoding to a single memory cell holding three data values. In other instances, as those skilled in the art will understand, the cell compression is SLC-MLC, MLC-QLC, TLC-QLC, SLC-QLC, etc.

[0014] In another embodiment, the second block and the first block are located in different physical portions of the set of non-volatile memory cells.

[0015] In one example, a device includes: a set of non-volatile memory cells arranged in a first block and a second block, each block being electrically connected to a set of bit lines, the first block including a first word line and the second block including a second word line; selection circuitry configured to electrically select a first set of memory cells in the first block and a second set of memory cells in the second block; and programming circuitry configured to apply programming pulses to the first and second word lines at an increased voltage to write the same data in parallel to the first and second sets of memory cells in a single pulse.

[0016] In another example, the device further includes verification circuitry configured to: apply verification pulses in parallel to the first word line and the second word line; sense current flowing through corresponding memory cells connected to the set of bit lines in response to the application of the verification pulses to determine that one of the first set of memory cells and the second set of memory cells is not correctly programmed; and, in response to determining that one of the first set of memory cells and the second set of memory cells is not correctly programmed, program the first set of memory cells and the second set of memory cells individually.

[0017] In another example embodiment, the second block is physically shifted relative to the first block.

[0018] In one example, a system includes: a set of non-volatile memory cells arranged in a string, the string being connectable to bit lines and including a word line for each memory cell; and a controller configured to write data in parallel to two memory cells in the string by: electrically selecting the bit lines by setting a select gate transistor, electrically connecting a first word line corresponding to a first memory cell in the string to a second word line corresponding to a second memory cell in the string, and applying programming pulses in parallel to the connected word lines to write the data in parallel to the first memory cell and the second memory cell.

[0019] In another instance, the controller is further configured to: after applying the programming pulse in parallel to the first word line and the second word line, apply a verification pulse in parallel to the first word line and the second word line, sense the current flowing through one of the first memory cell and the second memory cell in response to the application of the verification pulse to determine in parallel that one of the first memory cell and the second memory cell is not correctly programmed, and in response to determining that one of the first memory cell and the second memory cell is not correctly programmed, program the first memory cell and the second memory cell individually.

[0020] In another example embodiment, the controller is further configured to: determine that the first storage unit is correctly programmed, read data from the first storage unit in response to determining that the first storage unit is correctly programmed, and overwrite the first storage unit and the second storage unit after reading the data from the first storage unit.

[0021] In one instance, the controller is further configured to read data from one of the first and second storage units and use the data to program the other unit via the unit-to-unit compression operation described herein.

[0022] In another instance, the first storage unit and the second storage unit are consecutive storage units in the string.

[0023] In one example embodiment, a method includes: electrically selecting bit lines arranged to a set of non-volatile memory cells in two erase blocks, the bit lines being connectable to memory cells in each of the two blocks; electrically connecting individual word lines, including a first word line corresponding to one of the memory cells in a first block of the two blocks and a second word line corresponding to one of the memory cells in a second block of the two blocks; and applying programming pulses in parallel to the connected word lines to program the memory cells corresponding to the first word line and the second word line in the two blocks to a common target threshold voltage in parallel.

[0024] In one example, the method further includes: after applying the programming pulse in parallel to the connected word lines, applying a verification pulse in parallel to the connected word lines, sensing the current flowing through the bit lines in response to the application of the verification pulse to determine that one of the memory cells has not been correctly programmed, and in response to determining that one of the memory cells has not been correctly programmed, programming the memory cell individually.

[0025] In one example embodiment, the method further includes: determining that a first storage cell in the storage unit is correctly programmed; reading the first storage cell in the storage unit in response to determining that the first storage cell in the storage unit is correctly programmed; and overwriting the first storage cell in the storage unit and the second storage cell in the storage unit after reading the first storage cell in the storage unit.

[0026] In another example embodiment, the method further includes: reading data from one of the first storage cell of the storage unit in the first block of the two blocks and the second storage cell of the storage unit in the second block of the two blocks, and using the data to program the other cell through a cell compression operation.

[0027] In one instance, the first of the two blocks is physically separated from the second of the two blocks.

[0028] In another example, an apparatus includes: a component for electrically selecting bit lines of memory cells arranged in a set of nonvolatile memory cells in two blocks, the bit lines being connectable to a first string of memory cells in a first block and a second string of memory cells in a second block, each of the first string and the second string including a set of word lines; a component for electrically connecting a first word line contained in the first string to a second word line contained in the second string, the first word line and the second word line corresponding to a first memory cell contained in the first string and a second memory cell contained in the second string, respectively; and a component for applying a single programming pulse to the connected word lines to program the first memory cell in the first string and the second memory cell in the second string in parallel to a common target threshold voltage. Attached Figure Description

[0029] The following description contains more specific details with reference to the particular embodiments illustrated in the accompanying drawings. It should be understood that these drawings depict only certain embodiments of this disclosure and are therefore not intended to limit the scope of the disclosure. The disclosure is described and explained with additional specificity and detail using the accompanying drawings, in which:

[0030] Figure 1AThis is a block diagram of one embodiment of a system that includes a parallel programming component of a non-volatile memory device.

[0031] Figure 1B An embodiment of a non-volatile memory device that may include one or more memory dies or chips is shown.

[0032] Figure 2A Depicting Figure 1B An instance of a memory array configured as a 2D memory cell block.

[0033] Figure 2B Describing as Figure 2A A cross-sectional view of an instance charge-capture memory cell in a NAND string containing an instance of a memory cell.

[0034] Figure 2C Depicting Figure 2B A cross-sectional view of the structure.

[0035] Figure 2D Describe the instance memory unit.

[0036] Figure 3 It is a perspective view of a memory device comprising a set of blocks in an example 3D configuration of the memory array shown in Figure 1.

[0037] Figure 4 Depicting Figure 3 A cross-sectional view of a portion of a block.

[0038] Figure 5 Depicting Figure 4 A close-up view of a certain area of ​​the stack.

[0039] Figure 6 Depicting and presenting Figure 4 A view of instances of NAND strings in sub-blocks with a consistent 3D configuration.

[0040] Figure 7 Depicting Figure 6 Additional details for sub-blocks SB0-SB3.

[0041] Figure 8 Describe the waveform of the example programming operation.

[0042] Figure 9 Depicting Figure 5 A portion of the memory cell MC is shown, illustrating the electron injection into the charge trapping region during weak programming.

[0043] Figure 10 A top view depicting a series of blocks according to an example embodiment.

[0044] Figure 11This is a diagram of programming and verification pulses based on an example embodiment.

[0045] Figure 12 An embodiment of two blocks according to an example embodiment is described.

[0046] Figure 13 An embodiment of a method for describing cells of a parallel programmable memory array.

[0047] Figure 14 Another embodiment of a method for describing cells for parallel programming of a memory array.

[0048] Figure 15A , 15B Figures 15C and 15D show the Vt distribution of memory cells programmed with different numbers of bits per cell.

[0049] Figure 16 This is a flowchart of one embodiment of the process of parallel programming different groups of memory units.

[0050] Figure 17 This is a flowchart of an embodiment of the process of parallel programming of memory cells of NAND strings in different erase blocks.

[0051] Figure 18 This is a flowchart of an embodiment of the process of programming memory cells in multiple erase blocks in parallel through a multi-level unit programming process.

[0052] Figure 19 This is a flowchart of one embodiment of the process of parallel programming of memory cells in multiple erase blocks.

[0053] Figure 20A and 20B It is a block diagram of a circuit system used to provide voltage during parallel programming of each group of memory cells.

[0054] Figure 21 Depicting Figure 20A and 20B Further details on how the circuitry can be electrically connected to the conductive areas connected to the control gates of the memory cells.

[0055] Figure 22 This is a flowchart of one embodiment of the process of providing voltage during parallel programming.

[0056] Figure 23 Describe an example of a multistage charge pump. Detailed Implementation

[0057] This document discloses techniques for parallel programming of the same data pattern across multiple groups of nonvolatile memory cells. In embodiments, the same data pattern is programmed in parallel across three or more groups of nonvolatile memory cells. In embodiments, memory cells are programmed in parallel with one bit per cell. In embodiments, memory cells are programmed in parallel with two bits per cell. In embodiments, memory cells are programmed in parallel with three bits per cell. In embodiments, memory cells are programmed in parallel with four bits per cell. In embodiments, memory cells are programmed in parallel with five bits per cell. Each group of nonvolatile memory cells may be part of a different group of NAND strings. In embodiments, the different groups of NAND strings are associated with the same bit lines. For example, the NAND strings may reside in the same plane containing several bit lines. As an example, n copies of a data pattern may be programmed in parallel into “n” groups of memory cells, where n is an integer greater than 1.

[0058] In this embodiment, data patterns are applied to bit lines by applying a programming enable voltage or programming disable voltage to each corresponding bit line. In this embodiment, a selection voltage is applied to the drain-select gate of n groups of NAND strings, where n is an integer greater than 1. Therefore, each selection bit line is connected to one of the n selected NAND strings. Furthermore, each selection bit line is connected to a different NAND string in each of the n groups of NAND strings. When a selection bit line is connected to the corresponding n selected NAND strings, the system applies programming pulses in parallel to the control gates of the n groups of memory cells and applies a programming enable voltage to the selection bit line to program the data pattern in parallel to each of the n groups of memory cells. For example, each of the n groups of memory cells is programmed in parallel to a threshold voltage distribution associated with the data state.

[0059] In some embodiments, the control gate of each group of memory cells is connected via conductive regions. Each of these conductive regions can be quite large, such as conductive plates in a three-dimensional NAND memory array. Therefore, large RC loads may be associated with the conductive regions. In an embodiment, multiple voltage generators are used to provide a common voltage to multiple conductive regions during parallel programming. In another embodiment, the system enables several voltage generators based on the number of conductive regions to receive the same magnitude of voltage during programming operations that program the same data pattern to n groups of memory cells in parallel. This solves the aforementioned technical problem of RC loads.

[0060] Various aspects of this disclosure may be embodied in an apparatus, system, method, or computer program product. These aspects may take the form of an all-hardware embodiment, an all-software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects, all of which are collectively referred to herein as “circuit,” “module,” “apparatus,” or “system.” Furthermore, various aspects of this disclosure may take the form of a computer program product embodied in one or more non-transitory computer-readable storage media storing computer-readable and / or executable program code.

[0061] Many of the hardware units described in this specification are labeled as circuits to more specifically emphasize their implementation independence. For example, a circuit may be a custom VLSI circuit or gate array, all or part of off-the-shelf semiconductors such as logic chips, transistors, or another discrete component. Circuits may also be implemented in programmable hardware devices, such as field-programmable gate arrays, programmable array logic, programmable logic devices, etc. It is worth noting that in cases where multiple circuits are described, in some instances they may share hardware elements; therefore, two distinct circuits may be embodied as a single hardware entity configured, via software or different hardware elements, to perform the functions of the two circuits.

[0062] Computer program code used to implement the operations of various aspects of this disclosure may be written in any combination of one or more programming languages, including: object-oriented programming languages ​​such as Python, Java, Smalltalk, C++, C#, Objective C, etc.; conventional programming languages ​​such as the "C" programming language, scripting programming languages, and / or another similar programming language. The program code may be executed, partially or completely, on a user's computer and / or on a remote computer or server via a data network, etc.

[0063] As used herein, a component is a tangible, physically non-transitory device. For example, a component may be implemented as hardware logic circuitry having a custom VLSI circuitry, gate array, or another integrated circuit; off-the-shelf semiconductors, such as logic chips, transistors, or another discrete device; and / or another mechanical or electrical device. Components may also be implemented in programmable hardware devices, such as field-programmable gate arrays, programmable array logic, programmable logic devices, etc. A component may comprise one or more silicon integrated circuit devices (e.g., chips, dies, die planar packages) or another discrete electrical device electrically connected to one or more other components via wires on a printed circuit board (PCB). In some embodiments, each module described herein may alternatively be embodied or implemented as a component.

[0064] Throughout this specification, references to "an embodiment," "an embodiment," "an example embodiment," or similar language mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of this disclosure. Therefore, unless expressly stated otherwise, the phrases "in an embodiment," "in an embodiment," and similar language throughout this specification may, but do not necessarily, refer to the same embodiment, but rather to "one or more, but not all, embodiments." Unless expressly stated otherwise, the terms "comprising," "including," "having," and variations thereof mean "comprising but not limited to." Unless expressly stated otherwise, the list of items does not imply that any or all items are mutually exclusive and / or mutually inclusive. Unless expressly stated otherwise, the terms "a / an" and "described" also mean "one or more."

[0065] The following description refers to schematic flowcharts and / or schematic block diagrams of methods, apparatuses, systems, and computer program products according to embodiments of the present disclosure. It should be understood that each block and combination of blocks in the schematic flowcharts and / or schematic block diagrams may be implemented by computer program instructions. These computer program instructions may be provided to a processor of a computer or another programmable data processing apparatus to produce a machine, such that the instructions, which execute via said processor or other programmable data processing apparatus, form elements for implementing the functions and / or actions specified in one or more blocks of the schematic flowcharts and / or schematic block diagrams.

[0066] It should also be noted that in some alternative embodiments, the functions marked in the boxes may not conform to the order in which they are marked in the figures. For example, two boxes shown consecutively may actually be executed substantially in parallel, or these boxes may sometimes be executed in reverse order, depending on the functions involved. Other steps and methods that are functionally, logically, or effectively equivalent to one or more boxes or portions thereof in the illustrated figures are conceivable. Although various arrow types and line styles may be used in flowcharts and / or block diagrams, it is understood that they do not limit the scope of the corresponding embodiments. For example, arrows may indicate waiting or monitoring periods of unspecified duration between enumerated steps of the depicted embodiment.

[0067] In the following detailed description, reference is made to the accompanying drawings, which form part of the description. The above overview is illustrative only and is not intended to be limiting in any way. Other aspects, embodiments, and features will become apparent from the accompanying drawings and the following detailed description, in addition to the illustrative aspects, embodiments, and features described above. Descriptions of elements in each figure may refer to elements in previous figures. Similar numerals may refer to similar elements in the figures, including alternative embodiments containing similar elements.

[0068] Figure 1AThis is a block diagram of one embodiment of a system 100 having a parallel programming component 150 with a non-volatile memory device 120. The parallel programming component 150 may be a non-volatile memory media controller 126 (such as...). Figure 1A The parallel programming component 150 may operate on the non-volatile memory system 102 of the computing device 110, which may include a processor 111, volatile memory 112, and a network interface 113. The processor 111 may include one or more central processing units, one or more general-purpose processors, one or more dedicated processors, one or more virtual processors (e.g., the computing device 110 may be a virtual machine operating within a host computer), one or more processor cores, etc. The network interface 113 may include one or more network interfaces configured to communicatively couple the computing device 110 and / or the non-volatile memory media controller 126 to a communication network 115, such as an Internet Protocol (IP) network, a storage area network (SAN), a wireless network, a wired network, etc.

[0069] In various embodiments, the non-volatile memory device 120 may be located at one or more different locations relative to the computing device 110. In one embodiment, the non-volatile memory device 120 includes one or more non-volatile memory elements 123, such as semiconductor chips or other integrated circuit devices packaged or mounted on one or more printed circuit boards, storage housings, and / or other mechanical and / or electrical support structures. For example, the non-volatile memory device 120 may include one or more direct inline memory module (DIMM) cards, one or more expansion cards and / or daughter cards, solid-state drives (SSDs) or other hard disk drive devices, and / or may have another memory and / or storage form factor. The non-volatile memory device 120 may be integrated with and / or mounted on the motherboard of the computing device 110, mounted in a port and / or slot of the computing device 110, mounted on another computing device 110 and / or dedicated storage device on a communication network 115, communicate with the computing device 110 via an external bus (e.g., an external hard disk drive), and so on.

[0070] In one embodiment, the non-volatile memory device 120 may be located on the memory bus of the processor 111 (e.g., on the same memory bus as the volatile memory 112, on a different memory bus than the volatile memory 112, in place of the volatile memory 112, etc.). In another embodiment, the non-volatile memory device 120 may be located on the peripheral bus of the computing device 110, such as a Peripheral Component Interconnect High Speed ​​(PCI Express or PCIe) bus, a Serial Advanced Technology Attachment (SATA) bus, a Parallel Advanced Technology Attachment (PATA) bus, a Small Computer System Interface (SCSI) bus, a FireWire bus, a Fibre Channel connection, a Universal Serial Bus (USB), a PCIe Advanced Switching (PCIe-AS) bus, etc. In another embodiment, the non-volatile memory device 120 may be located on a communication network 115, such as an Ethernet network, an Infiniband network, a SCSI RDMA over the communication network 115, a Storage Area Network (SAN), a Local Area Network (LAN), a Wide Area Network (WAN) such as the Internet, another wired and / or wireless network, etc.

[0071] The computing device 110 may further include a non-transitory computer-readable storage medium 114. The computer-readable storage medium 114 may have executable instructions configured to cause the computing device 110 (e.g., processor 111) to perform steps of one or more methods disclosed herein. Alternatively or additionally, the parallel programming component 150 may be embodied as one or more computer-readable instructions stored on the computer-readable storage medium 114.

[0072] In the depicted embodiment, the non-volatile memory system 102 includes a parallel programming component 150. As will be further described, the parallel programming component 150 can be configured to electrically select bit lines of a group of non-volatile memory cells arranged in the same block or two different blocks, electrically connect individual word lines corresponding to the memory cells, and apply programming pulses to the connected word lines to program the memory cells corresponding to the individual word lines in parallel to a common target threshold voltage. The memory cells may optionally be located in two different blocks that may be physically separated from each other within the memory array to minimize the probability that an error occurring in one memory cell will also exist in the other memory cell. As used herein, “electrically select” includes applying a potential that allows a current source to be transferred to the other component. In one example, electrically selecting a bit line includes setting up one or more hardware components to connect the bit line to the other component.

[0073] The parallel programming component 150 can program individual cells in a separate block in parallel using the same data and program them to a common target threshold voltage. In some embodiments, writing the same data in parallel to separate blocks provides improved performance because if one block fails to store the written data, the data can be recovered from another block without requesting data from the non-volatile memory media controller 126 again. This allows the system 100 to move to other operations more quickly because fewer requests are required from the non-volatile memory media controller 126.

[0074] Furthermore, in some embodiments, cell compression operations using two copies of the same data can utilize the same data in a single block, eliminating the need for the non-volatile memory media controller 126 to write a separate copy of the data. This simplifies the operations performed by the non-volatile memory media controller 126, which is involved in MLC, TLC, QLC programming, and so on.

[0075] In one example embodiment, the parallel programming component 150 writes the same data to blocks located in physically separate regions. These separate regions can be defined by distance, the number of blocks between selected blocks, etc. As those skilled in the art will understand, NAND cell arrays may fail in specific physical locations or regions. Writing the same data to physically distant regions of the NAND array provides greater fault protection because if a specific portion of the NAND array fails, a second copy of the data residing in a different physical location may not be affected. As described herein, in some embodiments, this benefit does not require additional operations (e.g., writing the same data to a second cell requires no additional time compared to writing data to a first cell) because the parallel programming component 150 writes two copies of the same data in parallel.

[0076] In another example embodiment, the parallel programming component 150 writes the same data to two separate cells within the same string. Parallel programming of multiple cells within a string to a common target threshold voltage provides similar benefits to writing to a single block. In addition to the benefits previously described, parallel programming of two consecutive cells within a string to a common target threshold voltage reduces electrical interference because the two word lines corresponding to the same programmed cell are simultaneously subjected to the same voltage bias. Furthermore, word line-to-word line capacitance is reduced in this case. The parallel programming component 150 can write the same data to cells at different locations within the string to provide physical separation, as previously described in conjunction with parallel writing to a single block.

[0077] In another embodiment, after verifying that the first unit has been correctly programmed, the parallel programming component 150 may discard the data in the second unit. The parallel programming component 150 may achieve this by erasing the second unit, marking it for reuse, or overwriting the second unit with other data. Alternatively, the data in both units may be retained, for example, until a unit compression operation is performed, in which the data is combined with other data and stored in a multi-level cell (MLC), etc. (e.g., TLC, QLC, etc.).

[0078] In some embodiments, an SLC-TLC compression operation (an example of cell compression) can be used after data for a multilevel cell (MLC), such as a three-level cell (TLC), has been temporarily stored in a series of SLC cells. In some embodiments, three pairs of SLC cells can be used to store data for the TLC, wherein each pair stores the same version of data for a single bit to be stored in the TLC for data redundancy purposes. In SLC-TLC compression, data from at least one SLC cell in each of the three pairs of SLC cells can be read and encoded into bits within the TLC, such that three bits are encoded on the TLC. The bits encoded in the TLC can optionally be compared with those of the three pairs of SLC cells to confirm that the TLC has been correctly programmed. The SLC can then be erased after the TLC has been correctly programmed. The same SLC cells can then be used as a buffer for TLC programming, with temporary data redundancy built in.

[0079] After a cell compression operation, both the first and second cells can be erased. A new programming operation can be used to program the cell with new data, for example, for another SLC-TLC compression operation. The combination of erasing data from a cell and programming the cell with new data (or determining an unprogrammed cell in cases where the new data to be stored involves the retention of a cell in an erased or unprogrammed state) is called "overwriting" the cell's contents.

[0080] As used herein, a “block” comprises a set of word lines, each word line being connected to a set of memory cells. In one exemplary embodiment, a “block” comprises a portion of an array of memory cells (e.g., non-volatile memory elements) connected in a manner that allows all memory cells in the block to be erased in a single operation. Those skilled in the art will recognize that a block is the smallest unit of memory cells that can be erased using a single memory erase command, and may be referred to as an “erase block” in some embodiments. In some embodiments, a “block” comprises a string of non-volatile memory elements.

[0081] As used herein, a “NAND string” includes a group of NAND memory cells electrically connected in series to bit lines via NAND channels. A “NAND channel” includes electrical connections that connect the memory cells in a NAND string to their respective bit lines and source lines (e.g., ...). Figure 5 (Channel 665). The control gate of a memory cell on a NAND string can be connected to a conductive region, allowing voltage to be applied to the control gate. As used herein, a "bit line" comprises a conductive material line that can be connected to a voltage source and to the end of the NAND string (e.g., via the NAND channel). In one example, a block contains 64 strings, and a separate bit line can be connected to each of the 64 strings. In another example, bit lines pass through multiple blocks and can be connected to the corresponding string in each block.

[0082] As used herein, “intersection” includes two components (e.g., word lines, bit lines, memory cells, etc.) physically arranged such that they can electrically influence each other. An intersection of a word line and a memory cell means that the word line is electrically connected to the memory cell, such that applying a programming pulse to the word line programs the memory cell.

[0083] As used herein, “electrically connectable” includes two components (e.g., word lines, bit lines, memory cells, etc.) configured and / or positioned to facilitate connection to allow current to flow between them. Electrical connectability may involve connecting the electrically connectable components using secondary components. In one example, a gate transistor may be configured to electrically connect a word line to a voltage source. Thus, the word line and the voltage source are electrically connectable to each other, but they are not electrically connected to each other unless a gate transistor connects them.

[0084] As used herein, "concurrently program" or "concurrently programming," "applying programming pulses in parallel," etc., means applying programming pulses to two or more individual memory cells substantially simultaneously. "Substantially simultaneously" means that the two or more cells are programmed by the same programming pulse, but due to physical location or electrical distance, the memory cells may not receive the programming pulse at exactly the same time. In one example, due to the physical distance from the programming pulse source, the first memory cell may receive the programming pulse before the second memory cell. In another example embodiment, the two or more memory cells receive the programming pulse simultaneously, but the first memory cell is successfully programmed before the second memory cell. Furthermore, programming multiple memory cells in parallel to a common target threshold voltage means applying a common voltage to each of the memory cells substantially simultaneously. Of course, as those skilled in the art will understand, this does not necessarily mean that the memory cells are successfully programmed to the target threshold voltage due to the same pulse.

[0085] In one embodiment, the parallel programming component 150 may include logic hardware of one or more non-volatile memory devices 120, such as a non-volatile memory media controller 126, a non-volatile memory element 123, a device controller, a field-programmable gate array (FPGA) or other programmable logic, firmware for the FPGA or other programmable logic, microcode for execution on a microcontroller, an application-specific integrated circuit (ASIC), and so on. In another embodiment, the parallel programming component 150 may include executable software code, such as a device driver, stored on a computer-readable storage medium 114 for execution on a processor 111. In yet another embodiment, the parallel programming component 150 may include a combination of both executable software code and logic hardware.

[0086] In one embodiment, the parallel programming component 150 is configured to receive storage requests from a device driver or other executable application via a bus 125. The parallel programming component 150 may be further configured to transfer data to / from the device driver and / or storage client 116 via the bus 125. Accordingly, in some embodiments, the parallel programming component 150 may include or communicate with one or more direct memory access (DMA) modules, remote DMA modules, bus controllers, bridges, buffers, etc., to facilitate the transfer of storage requests and associated data. In another embodiment, the parallel programming component 150 may receive storage requests such as API calls, IO-CTL commands, etc., from the storage client 116.

[0087] According to various embodiments, a non-volatile memory media controller 126, communicating with one or more program sequencing components 140, can manage one or more non-volatile memory devices 120 and / or non-volatile memory elements 123. The non-volatile memory device 120 may include recording, memory, and / or storage devices, such as solid-state storage devices and / or semiconductor storage devices, arranged and / or partitioned into multiple addressable media storage locations. As used herein, a media storage location refers to any physical unit of memory (e.g., any number of physical storage media on the non-volatile memory device 120). Memory units may include, but are not limited to, pages, memory partitions, blocks, sectors, sets or groups of physical storage locations (e.g., logical pages, logical blocks), etc.

[0088] In some embodiments, the device driver and / or non-volatile memory media controller 126 may present a logical address space 134 to the storage client 116. As used herein, the logical address space 134 refers to a logical representation of a memory resource. The logical address space 134 may contain multiple (e.g., a series) logical addresses. As used herein, a logical address refers to any identifier used to reference a memory resource (e.g., data), including but not limited to: logical block address (LBA), cylinder / head / sector (CHS) address, filename, object identifier, inode, universally unique identifier (UUID), globally unique identifier (GUID), hash code, signature, index entry, range, degree, etc.

[0089] The device driver of the non-volatile memory device 120 may maintain metadata 135, such as a logical-to-physical address mapping structure, to map logical addresses in the logical address space 134 to media storage locations on the non-volatile memory device 120. The device driver may be configured to provide storage services to one or more storage clients 116. Storage clients 116 may include local storage clients operating on the computing device 110 and / or remote storage clients 116 accessible via the communication network 115 and / or the network interface 113. Storage clients 116 may include, but are not limited to, operating systems, file systems, database applications, server applications, kernel-level processes, user-level processes, applications, etc.

[0090] The device driver can communicatively couple to one or more non-volatile memory devices 120. The one or more non-volatile memory devices 120 may include different types of non-volatile memory devices, including, but not limited to, solid-state storage devices, semiconductor storage devices, SAN storage resources, etc. The one or more non-volatile memory devices 120 may include one or more corresponding non-volatile memory media controllers 126 and non-volatile memory media 122. The device driver can provide access to the one or more non-volatile memory devices 120 via a conventional block I / O interface 131. Additionally, the device driver can provide access to enhanced features via an SCM interface 132. Metadata 135 can be used to manage and / or track data operations performed through any of the block I / O interface 131, SCM interface 132, cache interface 133, or other relevant interfaces.

[0091] The cache interface 133 can expose cache-specific features that can be accessed via the device driver of the non-volatile memory device 120. Furthermore, in some embodiments, the SCM interface 132 presented to the storage client 116 provides access to data transformations implemented by the one or more non-volatile memory devices 120 and / or the one or more non-volatile memory media controllers 126.

[0092] The device driver may present a logical address space 134 to the storage client 116 through one or more interfaces. As discussed above, the logical address space 134 may contain multiple logical addresses, each corresponding to a specific media location of the one or more non-volatile memory devices 120. The device driver may maintain metadata 135, including arbitrary mappings between logical addresses and media locations, etc.

[0093] The device driver may further include a non-volatile memory device interface 139 configured to transmit data, commands, and / or queries to and / or communicate with the one or more non-volatile memory devices 120 via bus 125, said bus may include, but is not limited to: processor 111 memory bus, peripheral component interconnect high-speed (PCI Express or PCIe) bus, Serial Advanced Technology Attachment (ATA) bus, parallel ATA bus, small computer system interface (SCSI), FireWire, Fibre Channel, universal serial bus (USB), PCIe Advanced Switching (PCIe-AS) bus, communication network 115, Infiniband, SCSI RDMA, etc. The non-volatile memory device interface 139 may communicate with the one or more non-volatile memory devices 120 using input-output control (IO-CTL) commands, IO-CTL command extensions, remote direct memory access, etc.

[0094] Network interface 113 may include one or more network interfaces configured to communicatively couple computing device 110 and / or nonvolatile memory media controller 126 to communication network 115 and / or one or more remote network-accessible storage clients 116. Storage client 116 may include a local storage client operating on computing device 110 and / or a remote storage client 116 accessible via communication network 115 and / or network interface 113. Nonvolatile memory media controller 126 is part of and / or communicates with one or more nonvolatile memory devices 120. Although Figure 1A A single non-volatile memory device 120 is depicted, but this disclosure is not limited in this respect and can be adapted to incorporate any number of non-volatile memory devices 120.

[0095] The non-volatile memory device 120 may include one or more non-volatile memory elements 123 of a non-volatile memory medium 122, which may include, but is not limited to: ReRAM, memristor memory, programmable metallized cell memory, phase change memory (PCM, PCME, PRAM, PCRAM, bidirectional unified memory, chalcogenide RAM or C-RAM), NAND flash memory (e.g., 2D NAND flash memory, 3D NAND flash memory), NOR flash memory, nanoscale random access memory (nanoRAM or NRAM), nanocrystal wire-based memory, silicon oxide-based sub-10 nanometer process memory, graphene memory, silicon-oxide-nitride-oxide-silicon (SONOS), programmable metallized cell (PMC), conductive bridge RAM (CBRAM), magnetoresistive RAM (MRAM), spin-transfer torque (STT) MRAM, spin-orbit torque (SOT) MRAM, magnetic storage media (e.g., hard disk, magnetic tape), optical storage media, etc. In some embodiments, the one or more non-volatile memory elements 123 of the non-volatile memory medium 122 include storage class memory (SCM). The examples herein refer to NAND memory, or more specifically, SLC NAND memory; however, the systems and methods provided herein can be applied to other memory types, including but not limited to those listed above.

[0096] While conventional technologies such as NAND flash memory can be block and / or page addressable, in one embodiment, the memory class memory is byte addressable. In other embodiments, the memory class memory can be faster and / or have a longer lifespan (e.g., endurance) than NAND flash memory; can have lower cost, lower power consumption, and / or higher storage density compared to DRAM; or offer one or more other benefits or improvements compared to other technologies. For example, the memory class memory may include one or more of the following non-volatile memory elements 123: ReRAM, memristor memory, programmable metallized cell memory, phase-change memory, nanoRAM, nanocrystal wire-based memory, silicon oxide-based sub-10nm process memory, graphene memory, SONOS memory, MANOS memory, PMC memory, CBRAM, MRAM, and / or variations thereof.

[0097] Although the non-volatile memory medium 122 is referred to herein as "memory medium," in various embodiments, the non-volatile memory medium 122 may more generally include one or more non-volatile recording media capable of recording data, and may be referred to as non-volatile memory medium, non-volatile storage medium, etc. Furthermore, in various embodiments, the non-volatile memory device 120 may include a non-volatile recording device, a non-volatile memory device, a non-volatile storage device, etc.

[0098] The non-volatile memory medium 122 may include one or more non-volatile memory elements 123, which may include, but are not limited to, chips, packages, planes, dies, etc. The non-volatile memory medium controller 126 may be configured to manage data operations on the non-volatile memory medium 122 and may include one or more processors, programmable processors (e.g., FPGAs), ASICs, microcontrollers, etc. In some embodiments, the non-volatile memory medium controller 126 is configured to store data on and / or read data from the non-volatile memory medium 122, transfer data to / from the non-volatile memory device 120, etc.

[0099] The nonvolatile memory media controller 126 can be communicatively coupled to the nonvolatile memory media 122 via bus 127. Bus 127 may include an I / O bus for transferring data to / from the nonvolatile memory element 123. Bus 127 may further include a control bus for transmitting addressing and other command and control information to the nonvolatile memory element 123. In some embodiments, bus 127 may communicatively couple the nonvolatile memory elements 123 to the nonvolatile memory media controller 126 in parallel. This parallel access allows the nonvolatile memory elements 123 to be managed as a group, thereby forming logical memory elements 129. Logical memory elements may be divided into corresponding logical memory cells (e.g., logical pages) and / or logical memory partitions (e.g., logical blocks). Logical memory cells can be formed by logically combining the physical memory cells of each nonvolatile memory element.

[0100] In some embodiments, the non-volatile memory media controller 126 may organize blocks of word lines within the non-volatile memory element 123 using word line addresses, such that the word lines are logically organized into a monotonically increasing sequence (e.g., decoding and / or converting word line addresses into a monotonically increasing sequence, etc.). In another embodiment, the word lines of a block within the non-volatile memory element 123 may be physically arranged according to a monotonically increasing sequence of word line addresses, wherein consecutively addressed word lines are also physically adjacent (e.g., WL0, WL1, WL2, ..., WLN).

[0101] The non-volatile memory media controller 126 may include and / or communicate with a device driver executing on and / or with the computing device 110. The device driver may provide storage services to the storage client 116 via one or more interfaces 131, 132, and / or 133. In some embodiments, the device driver provides a block I / O interface 131 or a device interface for the storage client 116 to perform block-level I / O operations. Alternatively or additionally, the device driver may provide a storage class memory (SCM) interface 132 that provides other storage services to the storage client 116. In some embodiments, the SCM interface 132 may include extensions to the block I / O interface 131 (e.g., the storage client 116 can access the SCM interface 132 through extensions or additions to the block I / O interface 131). Alternatively or additionally, the SCM interface 132 may be provided as a separate API, service, and / or library. The device driver may be further configured to provide a cache interface 133 for caching data using the non-volatile memory system 102.

[0102] The device driver may further include a non-volatile memory device interface 139 configured to transmit data, commands, and / or queries to the non-volatile memory media controller 126 via bus 125, as described above.

[0103] Figure 1B An embodiment of a non-volatile memory device 210, which may include one or more memory dies 212 or chips, is illustrated. In some embodiments, the memory die 212 includes a memory array 200 (two-dimensional or three-dimensional) of memory cells, a die controller 220, and read / write circuitry 230A / 230B. In one embodiment, access to the memory array 200 by the various peripheral circuits is implemented symmetrically on opposite sides of the array, such that the density of access lines and circuitry on each side is halved. In another embodiment, the read / write circuitry 230A / 230B includes a plurality of sensing blocks 250 that allow memory cell pages to be read or programmed in parallel.

[0104] In various embodiments, the memory array 200 can be addressed via word lines through row decoders 240A / 240B and via bit lines through column decoders 242A / 242B. In some embodiments, the controller 244 and the one or more memory dies 212 are contained within the same non-volatile storage device 210 (e.g., a removable memory card or package). Commands and data are transmitted between the host and the controller 244 via line 232, and between the controller and the one or more memory dies 212 via line 234. One embodiment may include multiple memory dies 212.

[0105] The die controller 220 may share a die with the memory array 200, thus constituting a "die-on" controller. The die controller 220 may have any form known in the art, including but not limited to a microprocessor, microcontroller unit (MCU), finite state machine (FSM), central processing unit (CPU), graphics processing unit (GPU), etc.; "die-on controller" or "controller" may refer to any of these.

[0106] In one embodiment, die controller 220 cooperates with read / write circuitry 230A / 230B to perform memory operations on memory array 200. In some embodiments, die controller 220 includes parallel programming component 150, state machine 222, and on-chip address decoder 224. In one embodiment, state machine 222 forms part of parallel programming component 150. In another embodiment, controller 244 forms part of parallel programming component 150. Controller 244 may optionally be located on one or more memory dies 212, or may be on a die separate from memory die 212.

[0107] In some embodiments, each memory array 200 may be an SLC (Single-Level Cell) NAND array, wherein each non-volatile memory element 123 or “non-volatile memory cell” can be programmed via a programming pulse applied across the cell. Each memory array 200 may further utilize single-pulse programming, thereby providing speeds close to the theoretical limits of programmable NAND. As known in the art, each non-volatile memory element 123 may have an electrically insulating element, such as a gate oxide layer or tunnel oxide layer, through which electrons can selectively move, providing gate functionality by allowing the cell to be programmed with charge and retaining the charge used for programming. The “insulating element” or “insulating layer” may comprise any structure designed to selectively allow charge to enter and / or leave the non-volatile memory cell.

[0108] The phrase "programming pulse" refers to an electrical pulse applied to the non-volatile memory element 123 to cause it to enter or move towards a programmed state. This can be a peak voltage value, a root mean square ("RMS") voltage value, an average voltage of the pulse, the voltage value of a specific pulse in a pulse sequence, etc. In another embodiment, the programming pulse includes an applied current, including a peak current, an RMS current value, an average current of the pulse, or a specific current sequence, etc. The "programming pulse" is not limited to NAND memory, but can be applied to any non-volatile memory that is programmed by applying a potential. Therefore, programming settings, such as programming pulses, can be adjusted using the systems and methods of this disclosure for non-volatile memory types that include, but are not limited to, the types of non-volatile memory listed in the background section above.

[0109] The phrase "verification pulse" refers to an electrical pulse applied to non-volatile memory element 123 (e.g., a memory cell) and thereby indicating whether the memory cell has been adequately programmed. The verification pulses for different memory cells may be the same or different.

[0110] Similarly, various "sensing settings" can be used to sense the contents of one or more non-volatile memory elements 123 of the memory array 200. The term "sensing" refers not only to a non-volatile memory structure with cells that hold charge, but also to a type of non-volatile memory that uses different storage mechanisms. For example, in some non-volatile memory types, voltage and / or current are used to sense the resistance level of the cells (rather than the stored charge). In other non-volatile memory types, the current flowing through the cells is detected; current levels above or below a certain threshold indicate that the cells are programmed. This can be referred to as "reading" the cells when determining the contents of individual cells. However, "sensing" the contents of a non-volatile memory array can include reading the contents of individual cells, or detecting individual or collective characteristics of the cells, such as whether the voltage or resistance of the cells is above or below a predetermined threshold.

[0111] In some embodiments, modifying the programming settings may include reducing the number of times the programming voltage is applied across the non-volatile memory element 123 during the operating lifetime of the non-volatile memory device 120, thereby extending the lifetime of the non-volatile memory device 120 and reducing the likelihood of erroneous data reads due to cell overprogramming.

[0112] In one embodiment, state machine 222 provides chip-level control for memory operations. On-chip address decoder 224 provides an address interface for translating between addresses used by a host or memory controller and hardware addresses used by decoders 240A, 240B, 242A, 242B. In some embodiments, state machine 222 includes an embodiment of parallel programming component 150.

[0113] In one embodiment, one or any combination of the die controller 220, parallel programming component 150, on-chip address decoder 224, state machine 222, decoder 242A, decoder 242B, decoder 240A, decoder 240B, read / write circuitry 230A, read / write circuitry 230B, and / or controller 244 may be referred to as one or more management circuits. In one example embodiment, the die controller 220 includes any one of selection circuitry 282, programming circuitry 284, and verification circuitry 286.

[0114] In another example embodiment (in) Figure 1B (Not depicted in the original text), selection circuit 282, programming circuit 284, and verification circuit 286 are implemented as part of controller 244. In yet another example embodiment, die controller 220 includes one or more of circuits 282, 284, and 286, and controller 244 includes one or more of circuits 282, 284, and 286. Therefore, it is not necessary to implement each of the circuits 282, 284, and 286 on die controller 220 or controller 244.

[0115] Selection circuit 282 can be configured to electrically select a first set of memory cells in a first erase block and a second set of memory cells in a second erase block. In one example, non-volatile memory media controller 126 is configured to write data to the first erase block at a given depth of memory cells (e.g., the top row or another row of memory cells in the block). In another example embodiment, parallel programming component 150 provides a set of select gate transistors to connect bit lines of the string containing the memory cells and to connect programming pulse sources to word lines corresponding to the memory cells. Furthermore, selection circuit 282 can also connect word lines in the second erase block to a voltage source, such that when the voltage source is applied, voltages are applied in parallel to the first word lines in the first erase block and the second word lines in the second erase block. In a particular example, selection circuit 282 provides one or more select gate transistors to connect word lines to a source select gate and a drain select gate.

[0116] In some embodiments, the selection circuit 282 selects word lines corresponding to the same row in the first erase block and the same row in the second erase block. However, this may not be the case in practice, as the selection circuit 282 can select any word line in the block.

[0117] In another embodiment, programming circuitry 284 is configured to apply programming pulses to memory cells of the first word line and the second word line under a boosted voltage to write the same data in parallel to memory cells in the first erase block and the second erase block in a single pulse. In some embodiments, the first word line and the second word line are separate word lines located at different physical locations. In other embodiments, the first word line and the second word line are the same physical word line. In one instance, the first erase block and the second erase block may include adjacent erase blocks and share the same physical word line when the memory cells being programmed in parallel have different memory channels.

[0118] In another embodiment, the programming circuit 284 is configured to program memory cells in three or more erase blocks in parallel. In this embodiment, the programming circuit 284 is configured to apply programming pulses at an increased voltage to memory cells connected to a first word line in a first erase block, memory cells connected to a second word line in a second erase block, and memory cells connected to a third word line in a third erase block, to write the same data in parallel to memory cells in the first erase block, the second erase block, and the third erase block in a single pulse. In another embodiment, the programming circuit 284 is configured to program memory cells in four erase blocks in parallel.

[0119] In some embodiments, programming circuitry 284 is configured to program memory cells in different erase blocks in parallel as one bit per memory cell (SLC). In some embodiments, programming circuitry 284 is configured to program memory cells in different erase blocks in parallel as two bits per memory cell. In some embodiments, programming circuitry 284 is configured to program memory cells in different erase blocks in parallel as three bits per memory cell. In some embodiments, programming circuitry 284 is configured to program memory cells in different erase blocks in parallel as four bits per memory cell. In some embodiments, programming circuitry 284 is configured to program memory cells in different erase blocks in parallel as five bits per memory cell. In some embodiments, parallel programming of memory cells in different erase blocks is performed without verification.

[0120] In one example embodiment, verification circuit 286 is configured to apply a verification pulse to the currently programmed word line. For example, verification circuit 286 is configured to apply verification pulses to word lines in different erase blocks currently being programmed. In one embodiment, verification circuit 286 is configured to apply verification pulses to a first word line and a second word line. However, in the case of parallel programming of memory cells connected to more than two word lines, verification circuit 286 may apply verification pulses to more than two word lines.

[0121] Verification circuit 286 prepares sensing block 250 connected to the bit line for verification operations. Verification circuit 286 then senses the amount of current flowing from the sensing amplifier through the memory cell that received the programming pulse. In one embodiment, if current flows through any of a plurality of cells being programmed and connected to the same bit line in response to the application of the verification pulse, then the threshold voltage of one of the cells has not yet reached the target level. For example, in the case of programming two cells to the same target level, if current flows in either of the two cells in response to the application of the verification pulse, then the threshold voltage of one or both cells has not yet reached the target level. Therefore, at least one of the cells is not sufficiently programmed. If one or more of the cells have not reached the target level, then verification circuit 286 may initiate another programming procedure, as described herein. In one example embodiment, sensing the amount of current includes determining whether current is flowing. In one example embodiment, sensing the amount of current includes charging a sensing capacitor to a sensing voltage, connecting the sensing capacitor to the bit line for a sensing period (integration time) to allow bit line current (if present) to drain from the sensing capacitor, and then sensing the voltage across the sensing capacitor. If the voltage on the sensing capacitor has dropped below the threshold voltage, then the threshold voltage of at least one of the indicating units has not yet reached the target level.

[0122] In another example embodiment, sensing the current includes measuring the current and determining whether the measured current is above a threshold current amount (e.g., 0 amperes). In one example, sensing the current includes sensing the current connected to a bit line of a NAND string containing the memory cell being programmed. In this example embodiment, although current may flow through the bit line, it may not be known which NAND string the current is flowing through because the bit line may be connected to multiple NAND strings.

[0123] In another instance, the sensed current includes sensing the current at a current sensing component attached to the NAND string. In yet another embodiment, the sensed current includes sensing the current at the corresponding memory cell. Of course, those skilled in the art will understand that various different architectures exist, and the sensed current can be implemented in different ways.

[0124] In one example embodiment, programming circuit 284 programs the first memory cell in response to current sensing as a response to the application of a verification pulse, and separately programs the second memory cell.

[0125] As those skilled in the art will understand, a separate programming procedure may include applying a programming cycle to a first memory cell at progressively increasing voltages. In another example embodiment, a separate programming procedure includes applying a programming cycle to a second memory cell after applying a programming cycle to the first memory cell and verifying that the first cell is correctly programmed. An “increased” programming pulse indicates that previous programming pulses were insufficient to correctly program a particular memory cell, so an “increased” (e.g., at a higher voltage) programming pulse re-attempts to program the memory cell. Therefore, “correctly programmed” means that the programming pulses applied cause the threshold voltage level of the particular memory cell to be above a threshold or within a threshold range. A specific example of this series of programming pulses is... Figure 8 It is depicted in the text and will be described below.

[0126] In another embodiment, the parallel programming component 150 is configured to determine whether the first and / or second memory cell is correctly programmed, and in response to determining that the first and / or second memory cell is correctly programmed, to initiate an overwrite of the first and / or second memory cell. In some instances, the parallel programming component 150 marks the second memory cell for reuse, initiates an erase of the second memory cell, repurposes the second memory cell, etc.

[0127] In one example embodiment, the parallel programming component 150 is configured to read data from one of the first and second storage units and use said data to program a multi-level cell via an SLC-TLC compression operation. As previously described, having two copies of the same data allows the parallel programming component 150 to perform the multi-level cell SLC-TLC compression operation without having to copy the data stored in the cell. Therefore, the data stored in the first and second storage units is available for temporary use. Having two copies of the data helps prevent data loss during the time between the initial storage of the data in the memory array 200 and its use in the SLC-TLC compression operation.

[0128] In another example embodiment, the parallel programming component 150 uses two memory cells along a single NAND string. In this example embodiment, the NAND string comprises a set of memory cells. The NAND string may be connected to bit lines and intersect with individual word lines of each of the two memory cells along the NAND string. Similarly, as previously described, the parallel programming component 150 may select two individual word lines corresponding to the two individual memory cells along the NAND string for parallel programming to a common target threshold voltage.

[0129] In one embodiment, the selected word lines may optionally be separated from each other, such that they are located at different positions along the NAND string. For example, the selected word lines may be at opposite ends of the NAND string. As previously described, such displacement can help reduce the risk of data loss by decreasing the likelihood of memory cells being affected by common interruptions.

[0130] In another embodiment, the parallel programming component 150 connects individual word lines in more than two different erase blocks, thereby applying programming pulses to memory cells in each of the different erase blocks by applying programming pulses to the connected word lines.

[0131] In this exemplary embodiment, as those skilled in the art will understand, the selection circuit 282 electrically selects the bit line by turning on a selection gate transistor or by using one or more other components. The selection circuit 282 then electrically connects a first word line corresponding to a first memory cell in the NAND string to a second word line corresponding to a second memory cell in the NAND string. Next, the programming circuit 284 applies programming pulses to the connected word lines to write the data in parallel to the first and second memory cells in the NAND string.

[0132] In another embodiment, after programming circuitry 284 applies programming pulses in parallel to the first and second word lines, verification circuitry 286 applies verification pulses to the first and second word lines to determine whether the first and / or second memory cells are correctly programmed. In response to the current flowing through the NAND string, verification circuitry 286 determines that one or more of the first and second memory cells are not fully programmed (e.g., insufficient threshold voltage). Then, in response to this determination, verification circuitry 286 may begin the subsequent programming process for each memory cell in any of the manner described herein.

[0133] In some embodiments, instead of determining whether any particular memory cell has been correctly programmed, verification circuit 286 determines that one of the memory cells has not been correctly programmed by sensing the current in the bit line shared by the two memory cells. In response to this determination, programming circuit 284 reprograms the first and second memory cells. Because both memory cells have been programmed, it may not be necessary to determine which one or more memory cells have not been correctly programmed.

[0134] In one example embodiment, the first and second memory cells in the NAND string are contiguous memory cells in the NAND string. While there is an advantage to physical displacement between memory cells storing duplicate data, it is also beneficial to program consecutive word lines on the NAND string in parallel to a common target threshold voltage. In some embodiments, two word lines storing the same data are less likely to interfere with each other electromagnetically.

[0135] Figure 2A Depicting Figure 1B The memory array 200 is configured with memory cell blocks in instance 2D. The memory array 200 may contain multiple blocks. Each instance block 202, 204 contains several NAND strings and corresponding bit lines, such as BL0, BL1, ..., which are shared within the block. One end of each NAND string is connected to the drain select gate (SGD), and the control gate of the drain select gate is connected via a common SGD line. The other end of the NAND string is connected to the source select gate (SGS), which is in turn connected to a common source line 206. Sixteen word lines extend between the source select gate and the drain select gate, such as WL0-WL15.

[0136] In some cases, dummy word lines without user data can also be used in memory arrays adjacent to the select-gate transistor (SGS / SGD). These dummy word lines can shield edge data word lines, protecting them from certain edge effects. In some instances, the dummy word lines are positioned adjacent to the SGD and SGS lines. Therefore, in Figure 2A In an exemplary embodiment, dummy word line WLD0 is positioned adjacent to the SGS line of each of blocks 202, 204, and dummy word line WLD1 is positioned adjacent to the SGD line of each of blocks 202, 204. In other instances, multiple (e.g., two or three) dummy word lines are positioned between word lines WL0 to WL15 and each of the SGD and SGS lines. In some embodiments, the dummy word lines are not erased using the remainder of blocks 202, 204 to which they belong. Therefore, all data stored on the dummy word lines is retained after an erase operation normally used to erase user data and can only be modified by programming the bits of dummy word lines that have not yet been programmed.

[0137] like Figure 2A As illustrated, bit lines BL0, BL1, ... define the word line columns for each block 202, 204. In addition to the bit lines BL0, BL1, ... that store user data, each block 202, 204 also has multiple spare columns SC0, SC1, ... which can be used for various purposes, such as replacing bit lines BL0, BL1, ... that are no longer available or have become unusable. Therefore, in some instances, the spare columns do not store user data.

[0138] Each word line in the memory array 200 may have a word line driver 208 for decoding and / or otherwise processing data from said word line. Therefore, in Figure 2A In this context, word lines WL0 to WL15 may have a word line driver 208, as shown. The word line driver 208 may be included in... Figure 1B The line decoders 240A / 240B shown in the figure.

[0139] The non-volatile memory element 123 may comprise any of various technologies, including, but not limited to, all non-volatile memory types mentioned in the background section above. One type of non-volatile memory that can be provided in a memory array is a charge-trapping memory cell. Other types of non-volatile memory may also be used. For example, a charge-trapping memory cell may use a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner. In an example, a three-layer dielectric formed of silicon oxide, silicon nitride, and silicon oxide (“ONO”) is sandwiched between a conductive control gate and a semiconductor. The cell is programmed by injecting electrons from the cell channel into the nitride, where electrons are trapped and stored in a limited area. The stored charge then detectably alters the threshold voltage of a portion of the cell channel. The cell is erased by injecting a hot hole into the nitride. A similar cell may be provided in a split-gate configuration, wherein a doped polysilicon gate extends over a portion of the memory cell channel to form a separate selection transistor.

[0140] In another approach, NROM cells are used. For example, two bits are stored in each NROM cell, where an ONO dielectric layer extends across a channel between the source and drain. The charge of one data bit is located in the dielectric layer near the drain, and the charge of the other data bit is located in the dielectric layer near the source. Multi-state data storage is achieved by individually reading the binary states of the spatially separated charge storage regions inherent in the dielectric. Other types of non-volatile memories are also known.

[0141] Figure 2B Describing as Figure 2A A cross-sectional view of an instance charge-capture memory cell within a NAND string, representing an instance of a memory cell. This view is situated as... Figure 1B The 2D instance of a memory cell in the memory array 200 is shown in the word line direction of the memory cell, including a planar control gate and a charge trapping region. Charge trapping memory can be used in NOR and NAND flash memory devices. Compared to floating-gate MOSFET technology, which uses conductors such as doped polysilicon to store electrons, this technology uses insulators such as SiN films to store electrons. As an example, word lines (WL) 423 extend across NAND strings containing corresponding channel regions 406, 416, and 426. A portion of the word line provides control gates 402, 412, and 422. Below the word line are polysilicon interlayer dielectric (IPD) layers 428, charge trapping layers 404, 414, and 424, polysilicon layers 405, 415, and 425, and tunneling layers 409, 407, and 408. Each charge trapping layer extends continuously within the corresponding NAND string.

[0142] Memory cell 400 includes a control gate 402, a charge trapping layer 404, a polysilicon layer 405, and a portion of a channel region 406. Memory cell 410 includes a control gate 412, a charge trapping layer 414, a polysilicon layer 415, and a portion of a channel region 416. Memory cell 420 includes a control gate 422, a charge trapping layer 421, a polysilicon layer 425, and a portion of a channel region 426.

[0143] One advantage of planar control gates is that the charge trapping layer can be fabricated to be thinner than that of floating gates. Additionally, memory cells can be placed closer together.

[0144] Figure 2C Depicting Figure 2B The structure is shown in a cross-sectional view along line 429. This view shows a NAND string 430 with a planar control gate and a charge trapping layer. The NAND string 430 includes an SGS transistor 431, instance memory cells 400, 433, ..., 434 and 435, and an SGD transistor 436.

[0145] NAND strings can be formed on a substrate including a p-type substrate region 455, an n-type well 456, and a p-type well 457. N-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7 are formed in the p-type well 457. A channel voltage Vch can be directly applied to the channel region of the substrate. The memory cell 400 includes a control gate 402 and an IPD layer 428 above a charge trapping layer 404, a polysilicon layer 405, a tunneling layer 409, and a channel region 406.

[0146] For example, the control gate layer can be polysilicon, and the tunneling layer can be silicon oxide. The IPD layer can be a stack of high-k dielectrics such as AlOx or HfOx, which helps increase the coupling ratio between the control gate layer and the charge trap or charge storage layer. For example, the charge trap layer can be a mixture of silicon nitride and silicon oxide.

[0147] SGD and SGS transistors have the same configuration as memory cells, but with a longer channel length to ensure that current is cut off in the suppressed NAND string.

[0148] In this example, layers 404, 405, and 409 extend continuously within the NAND string. In another approach, portions of layers 404, 405, and 409 between control gates 402, 412, and 422 may be removed, thereby exposing the top surface of channel region 406.

[0149] Figure 2DExample memory cell 500 is depicted. The memory cell includes a control gate CG that receives word line voltage Vwll0, a drain at voltage Vd, a source at voltage Vs, and a channel at voltage Vch.

[0150] Figure 3 This is a perspective view of a memory device 600 comprising a set of blocks in an example 3D configuration of the memory array 200 shown in FIG. 1. On the substrate are example blocks BLK0, BLK1, BLK2, and BLK3 of memory cells (memory elements), and a peripheral region 604 having a circuitry for use by said blocks. For example, said circuitry may include a voltage driver 605 connectable to a control gate layer of the block. In one approach, control gate layers at a common height within the blocks are driven together. The substrate 601 may also carry the circuitry beneath these blocks, as well as one or more lower metal layers patterned in conductive paths to carry signals of the circuitry. The blocks are formed in a middle region 602 of the memory device. In an upper region 603 of the memory device, one or more upper metal layers are patterned in conductive paths to carry signals of the circuitry. Each block includes a stacked region of memory cells, wherein alternating stacked levels represent word lines. In one possible approach, each block has opposing layered sides from which vertical contacts extend upwards to the upper metal layers to form connections with the conductive paths. Although four blocks are depicted as examples, two or more blocks can be used, extending in the x and / or y directions.

[0151] In one possible approach, the plane length in the x-direction represents the direction in which the signal path to the word line extends within the one or more upper metal layers (word line or SGD line direction), and the plane width in the y-direction represents the direction in which the signal path to the bit line extends within the one or more upper metal layers (bit line direction). The z-direction represents the height of the memory device.

[0152] Figure 4 Depicting Figure 3 A cross-sectional view of a portion of a block. The block comprises a stack 610 of alternating conductive and dielectric layers. In this example, the conductive layers include two SGD layers, two SGS layers, and four dummy word line layers (or word lines) WLD1, WLD2, WLD3, and WLD4, as well as data word line layers (or word lines) WLL0-WLL10. The dielectric layers are labeled DL0-DL19. Furthermore, a stacked region including NAND strings NS1 and NS2 is depicted. Each NAND string surrounds a memory hole 618 or 619, which is filled with a material forming a memory cell adjacent to the word line. Figure 5 The stacked region 622 is shown in more detail below.

[0153] The stack includes a substrate 611, an insulating film 612 on the substrate, and a portion of a source line SL. NS1 has a source terminal 613 at the bottom 614 of the stack and a drain terminal 615 at the top 616 of the stack. Metal-filled slots 617 and 620 can be periodically provided across the stack as interconnects extending through the stack to connect the source line to a line above the stack. The slots can be used during word line formation and are subsequently filled with metal. A portion of a bit line BL0 is also depicted. A conductive via 621 connects the drain terminal 615 of NS1 to BL0. The connection of NS2 to its bit line is... Figure 4 It is not depicted in the text.

[0154] Figure 5 Depicting Figure 4 A close-up view of region 622 of the stack. Memory cells are formed at different levels of the stack at the intersection of word line layers and memory vias. In this example, SGD transistors 680 and 681 are disposed above dummy memory cells 682 and 683 and data memory cell MC. Several layers may be deposited along the sidewalls (SW) of memory via 630 and / or within each word line layer, for example, using atomic layer deposition. For example, each column (e.g., a pillar formed by material within the memory via) may include a charge trapping layer 663 or a thin film such as SiN or other nitrides, a tunneling layer 664, a channel 665 (e.g., including polysilicon), and a dielectric core 666. The word line layer may include a blocking oxide / blocking high-k material 660, a blocking metal 661, and a conductive metal 662, such as tungsten, as a control gate. For example, control gates 690, 691, 692, 693, and 694 are provided. In this example, all layers except the metal and the barrier oxide / barrier high-k material 660 are disposed within the memory vias. In other methods, additional layers may be present in the control gate layer. Similarly, additional pillars are formed in the different memory vias. The pillars may form pillared active regions (AA) of the NAND string.

[0155] When a memory cell is programmed, electrons are stored in a portion of the charge trapping layer associated with the memory cell. These electrons enter the charge trapping layer from the channel through a tunneling layer. The Vth of the memory cell increases proportionally to the amount of charge stored (e.g., as the amount of charge stored increases). During an erase operation, the electrons return to the channel.

[0156] Each memory via may be filled with multiple annular layers, including a barrier oxide layer, a charge trapping layer, a tunneling layer, and a channel layer. The core region of each memory via is filled with a host material, and in each memory via, the multiple annular layers are located between the core region and the word line.

[0157] NAND strings can be viewed as having floating channels because this section of the channel is not formed on the substrate. Furthermore, NAND strings are provided by multiple word line layers stacked on top of each other and separated by dielectric layers.

[0158] Figure 6 Depicting and presenting Figure 4 A consistent 3D configuration of instance views of NAND strings within sub-blocks. Each sub-block contains multiple NAND strings, with one instance NAND string depicted. For example, SB0, SB1, SB2, and SB3 include instance NAND strings 700n, 710n, 720n, and 730n, respectively. The NAND strings have... Figure 4 Consistent data word lines, dummy word lines, and select gate lines. Within a block BLK, each sub-block comprises a set of NAND strings extending along the x-direction and sharing a common SGD line. NAND strings 700n, 710n, 720n, and 730n are located in sub-blocks SB0, SB1, SB2, and SB3, respectively. Block programming can be performed one sub-block at a time. Within each sub-block, a word line programming order can be followed, for example, starting with the source-side word line WL0 and advancing one word line at a time until the drain-side word line WLL10. As previously described, a sub-block may contain multiple strings, while in other embodiments, a sub-block contains a single string.

[0159] NAND strings 700n, 710n, 720n and 730n have channel regions 700a, 710a, 720a and 730a, respectively.

[0160] Additionally, the NAND string 700n includes SGS transistors 700 and 701, dummy memory cells 702 and 703, data memory cells 704, 705, 706, 707, 708, 709, 710, 711, 712, 713 and 714, dummy memory cells 715 and 716, and SGD transistors 717 and 718.

[0161] The NAND string 710n includes SGS transistors 720 and 721, dummy memory cells 722 and 723, data memory cells 724, 725, 726, 727, 728, 729, 730, 731, 732, 733 and 734, dummy memory cells 735 and 736, and SGD transistors 737 and 738.

[0162] The NAND string 720n includes SGS transistors 740 and 741, dummy memory cells 742 and 743, data memory cells 744, 745, 746, 747, 748, 749, 750, 751, 752, 753 and 754, dummy memory cells 755 and 756, and SGD transistors 757 and 758.

[0163] The NAND string 730n includes SGS transistors 760 and 761, dummy memory cells 762 and 763, data memory cells 764, 765, 766, 767, 768, 769, 770, 771, 772, 773 and 774, dummy memory cells 775 and 776, and SGD transistors 777 and 778.

[0164] Figure 7 Depicting Figure 6 Additional details of sub-blocks SB0-SB3 are shown. Instance memory cells extending in the x-direction along word lines within each sub-block are depicted. For simplicity, each memory cell is depicted as a cube. SB0 contains NAND strings 700n, 701n, 702n, and 703n. SB1 contains NAND strings 710n, 711n, 712n, and 713n. SB2 contains NAND strings 720n, 721n, 722n, and 723n. SB3 contains NAND strings 730n, 731n, 732n, and 733n. Bit lines are connected to multiple sets of NAND strings. For example, bit line BL0 is connected to NAND strings 700n, 710n, 720n, and 730n; bit line BL1 is connected to NAND strings 701n, 711n, 721n, and 731n; bit line BL2 is connected to NAND strings 702n, 712n, 722n, and 732n; and bit line BL3 is connected to NAND strings 703n, 713n, 723n, and 733n. Sensing circuitry can be connected to each bit line. For example, sensing circuitry systems 780, 781, 782, and 783 are connected to bit lines BL0, BL1, BL2, and BL3.

[0165] During programming operations, the final Vth distribution can be achieved using one or more programming cycles. Multi-pulse programmed memory devices can be programmed using multiple programming cycles. Conversely, single-pulse programmed memory devices can be programmed via a single programming cycle or via a single programming pulse without a verification step. For multi-pulse programming, each subsequent cycle may use an increasing number of programming pulses. In some embodiments, during a programming cycle, a programming verification iteration is performed against a selected word line. The programming verification iteration includes a programming step / stage of applying a programming voltage to the word line, followed by a verification step / stage of performing one or more verification tests. Each programmed state may include a verification pulse used in the verification test for said state.

[0166] Figure 8 Describe the waveforms of typical programming operations in the example. More precisely, Figure 8This depicts a multi-pulse programming operation, in which step programming pulses are applied to program one or more memory cells. The horizontal axis depicts the number of programming cycles (PLs), and the vertical axis depicts the memory cell control gate, also known as the word line voltage. Typically, a programming operation may involve applying a sequence of pulses to a selected word line, wherein the pulse sequence comprises multiple programming cycles or programming verification iterations. The programming portion of a programming verification iteration includes a programming voltage, and the verification portion of a programming verification iteration includes one or more verification pulses.

[0167] In one approach, each programming cycle comprises two steps. Furthermore, this example uses Incremental Step Pulse Programming (ISPP), where the programming voltage is stepped in each successive programming cycle using a fixed or varying step size.

[0168] Waveform 800 includes a series of programming voltages 852, 854, and 856 applied to a selected word line for programming and an associated set of non-volatile memory cells. After each programming voltage, as an example, one or more verification pulses may be provided based on the verified target data state. 0V may be applied to the selected word line between the programming and verification pulses. For example, parallel programming component 150 may apply a first programming pulse 852, apply a verification pulse 860, apply a second programming pulse 854, apply another verification pulse 860, and then apply a third programming pulse 856. In another example embodiment, the triggering condition includes the memory cell being programmed to a target voltage threshold. In this example embodiment, in response to determining that both the first and second memory cells have reached the target threshold voltage, parallel programming component 150 may abort the pulse programming sequence, for example, after the first programming pulse 852 or after the second programming pulse 854. Additional examples of single-pulse programming phases are described in U.S. Patent No. 8,134,871, which is incorporated herein by reference.

[0169] In other example embodiments, using a "single pulse" to program the memory cell involves applying a single programming pulse at an increased voltage to program the cell to a target threshold voltage, rather than as... Figure 8 The execution of a continuous programming cycle is depicted. In one example, programming circuitry 284 applies a single programming pulse at Vpgm3, but not Vpgm1 or Vpgm2. In another example, programming circuitry 284 applies 20 volts to the word line of the memory cell and applies a lower limit voltage difference to the bit line of the memory cell. In this example, the voltage difference between the word line and the bit line is applied to the memory cell. In some embodiments, the "rise voltage" includes a voltage level higher than the initial normal programming cycle in normal programming operation. In one example, the "rise voltage" is 18 volts. In another example embodiment, the "rise voltage" is between 16 and 20 volts.

[0170] In other example embodiments, the parallel programming component 150 first applies a single-pulse programming sequence, followed by a multi-stage programming sequence in response to one of the first and second memory cells not being correctly programmed. Specifically, in one such embodiment, programming circuitry 284 first applies single-pulse programming to program the first and second memory cells in parallel to a common target threshold voltage, and then verification circuitry 286 simultaneously verifies the programming levels of the first and second memory cells. If verification circuitry 286 determines that one of the first and second memory cells is not correctly programmed, then in one embodiment, programming circuitry 284 may apply multi-pulse programming to program the first and second memory cells individually, as those skilled in the art will understand. This programming step of the first and second memory cells may be completed at different times (e.g., by programming the first memory cell first, then programming the second memory cell). Next, verification circuitry 286 verifies the correct programming of the first and second memory cells. This may be done in parallel for the first and second memory cells or at different times (e.g., by verifying the correct programming of the first memory cell first, then verifying the correct programming of the second memory cell).

[0171] In another embodiment, the first and second memory cells are independently programmed in a single programming operation through a series of regular programming verification iterations. After each programming iteration is completed, the parallel programming component 150 independently verifies that each memory cell is correctly programmed.

[0172] Those skilled in the art will recognize that various alternative cell programming methods can be used to program multiple memory cells individually. Single-pulse programming, multi-pulse programming, and / or combinations thereof can be applied. Additional examples of single-pulse programming are illustrated in U.S. Patent 9,343,141, which is incorporated herein by reference.

[0173] Figure 9 Depicting Figure 5 A portion of a memory cell MC is shown, illustrating electron injection into the charge trapping region during programming. The memory cell includes a control gate 694, a barrier metal 661a, a barrier oxide 660a, a charge trapping layer 663, a tunneling layer 664, a channel 665, and a dielectric core 666. Due to the increased word line voltage, an electric field (E) is generated that attracts electrons from the channel 665 (see example electron 650) into the charge trapping layer 663, thereby increasing Vth. This programming is likely caused by the Fowler-Nordheim tunneling effect, a type of electron tunneling through a trap.

[0174] Figure 10This is a top view of a memory cell array 1000 including a set of bit lines 1050 and an S / A data latch 1010. In this example embodiment, the bit lines 1050 are set according to data received at the S / A data latch 1010, and the data is written to specific memory cells corresponding to selected word lines as described herein.

[0175] In one example embodiment, bit line 1050 is set according to the data to be written to memory cells corresponding to the selected bit line and in each string of memory cells in the first erase block 1020. Parallel programming component 150 selects another word line (in) the memory cell located in the second erase block 1030. Figure 10 (Not shown in the image). As previously described, in this example embodiment, the parallel programming component 150 is electrically connected to the word lines of the first erase block 1020 and the second erase block 1030, whereby, in response to the application of a programming pulse on one of the word lines, memory cells in the two blocks 1020, 1030 can be programmed in parallel to a common target threshold voltage. Therefore, memory cells in each block 1020, 1030 are programmed in parallel according to the bit pattern set for bit line 1050.

[0176] In some embodiments, the parallel programming component 150 selects the first erase block 1020 and the second erase block 1030 as at least one block spaced apart from each other. In other words, at least one block may exist between the first erase block 1020 and the second erase block 1030. In other embodiments, the parallel programming component 150 selects two blocks that are at least physically separated from each other. For example, the minimum distance is 50 nanometers, but of course, this disclosure is not limited in this respect.

[0177] As previously described, by physically separating the first erase block 1020 from the second erase block 1030, a physical failure of the memory cell array is unlikely to simultaneously affect both the first erase block 1020 and the second erase block 1030. In one example embodiment, the parallel programming component 150 divides the memory cell array into separate physical partitions or portions. In one example, the parallel programming component 150 divides the array into four portions by vertically halving the array and horizontally halving the array. Of course, other partitioning or physical separation techniques can be used, and this disclosure is not limited in this respect. Thus, as described herein, a "physical portion" includes a sub-portion of the memory cell array that is physically different from other memory cells in the array. In some instances, physical portions are defined using logical boundaries. Therefore, there may be no physical differences between the various physical portions.

[0178] Figure 11This is a diagram of programming and verification pulses according to an example embodiment. In this example embodiment, to perform parallel programming operations, the parallel programming component 150 sets the voltage of the unselected location line (data "1") to a high voltage (e.g., 2.5 volts) and the voltage of the selected location line (data "0") to a low voltage (e.g., 0 volts), sets the drain select gate (SGD) in each block 1020, 1030 to VSGD (e.g., 2.5 volts), sets the selected word line in the first erase block 1020 and the second erase block 1030 to a programming pulse (VPGM, e.g., 18 volts), sets the unselected word line in each block 1020, 1030 to a raised voltage (VPASS, e.g., 10 volts), sets the source select gate to 0 volts, and sets the source line (CELSRC) voltage to PROGGRC (e.g., 2 volts).

[0179] In another example embodiment, in order to perform the parallel verification operation, the parallel programming component 150 sets the bit lines to the bit line clamp voltage (VBLC), sets the SGD to the select gate voltage (VSG), sets each selected word line in each block to the verification pulse (Vverify), sets each unselected word line to the read voltage (Vread), sets the SGS to the select gate voltage VSG, and sets the source line (CELSRC) voltage to VCELSRC (e.g., 1 volt).

[0180] Figure 12 Depicting portions of two blocks according to one example embodiment. Bit lines 1210a, 1210b, and 1210c are set according to the data to be written to the memory cells in each block. In this example embodiment, the blocks include a first erase block 1220 and a second erase block 1230. Although in Figure 12 The diagram depicts three bit lines 1210, but of course, a memory cell array can contain many more bit lines. Furthermore, although two blocks are depicted, one or more additional copies can optionally be made, for example, on a third block (not shown), a fourth block (not shown), and so on.

[0181] In one example embodiment, the parallel programming component 150 electrically selects bit lines to program cells in a NAND string connected to bit line 1210. In this particular example, the parallel programming component 150 selects bit line 1210c. The parallel programming component 150 also connects a first word line 1250 corresponding to a first memory cell 1221 and a second word line 1240 corresponding to a second memory cell 1231. For example, the parallel programming component 150 may select gate transistors to simultaneously electrically connect the first word line 1250 and the second word line 1240 to a common connection. Specifically, the first erase block 1220 includes a first NAND string 1260 intersecting with the first word line 1250 at the first memory cell 1221, and the second erase block 1230 includes a second string 1261 intersecting with the second word line 1240 at the second memory cell 1231. The parallel programming component 150 applies programming pulses to the connected word lines 1240 and 1250, thereby applying programming pulses to the first memory cell 1221 and the second memory cell 1231.

[0182] In another embodiment, after applying programming pulses in parallel to the first word line and the second word line, the parallel programming component 150 applies verification pulses to the first word line and the second word line. Specifically, the parallel programming component 150 applies verification pulses to the first word line and the second word line. Figure 11 The voltage described in the verification operation. In this example embodiment, the parallel programming component 150, in response to the application of the verification pulse, then senses the current flowing through one of the first memory cell 1221 and the second memory cell 1231 (e.g., by sensing the current at the end of the memory cell or NAND string) to determine in parallel whether one of the first memory cell 1221 and the second memory cell 1231 is not correctly programmed. In one embodiment, the parallel programming component 150 then senses the current flowing through a bit line connected to the NAND string containing the memory cell being programmed in parallel. In another example embodiment, the parallel programming component 150, in response to sensing the current flowing through one of the first memory cell 1221 and the second memory cell 1231, programs the first memory cell and the second memory cell individually, as previously described. As previously described, individual programming can be performed in the same manner as the initial programming of the first memory cell 1221 and the second memory cell 1231, or individual programming can be performed in a different manner, such as by individually programming the first memory cell 1221 and the second memory cell 1231, and / or by programming with a different programming pulse structure, such as by conventional programming or via multi-pulse programming, etc.

[0183] Figure 13An embodiment of a method 1309 for parallel programming of cells in a memory array is depicted. Method 1309 can be performed each time one or more of the non-volatile memory elements 123 are to be programmed. Method 1309 can be performed by a die controller 220, for example, by using... Figure 1B The various circuits described herein. In alternatives, method 1309 can be implemented using different hardware, such as... Figure 1B Controller 244 and / or Figure 1A The non-volatile memory media controller 126.

[0184] As shown, method 1309 may begin 1310 at step 1312, where a bit line corresponding to the memory cell to be programmed (e.g., non-volatile memory element 123 of memory array 200) is selected. In one example embodiment, parallel programming component 150 receives a command to program one or more non-volatile memory elements 123 in memory array 200. This command may be received, for example, in die controller 220. Such commands may be received in programming circuitry 284 of die controller 220.

[0185] In step 1314, word lines of memory cells in two different blocks or, in an alternative embodiment, within a common NAND string in the same block are selected. In one example embodiment, word lines in separate blocks are electrically connected, as previously described.

[0186] In step 1316, programming pulses are applied to the connected word lines to program the memory cells in the two different blocks in parallel. This can be accomplished by programming circuitry 284, which can apply programming pulses in parallel across two selected word lines, thereby programming the first memory cell 1221 and the second memory cell 1231.

[0187] In step 1320, verification pulses are applied in parallel to the connected word lines. This can be accomplished, for example, by verification circuit 286.

[0188] In step 1322, the current flowing through one of the first and second memory cells is sensed to determine whether the first memory cell 1221 and the second memory cell 1231 are correctly programmed. As previously described, if the memory array 200 is a NAND array with a conventional architecture, then the current flowing through the bit line in response to the application of a verification pulse can indicate that the first memory cell and / or the second memory cell is not correctly programmed.

[0189] In one example embodiment, the "sensing" current includes a charged capacitor connected to the bit line after a voltage pulse is applied to the word line. In response, if the memory cell has a threshold voltage at or below the voltage level on the word line, the memory cell will conduct current, which can flow from the bit line to the current drain. In this example embodiment, the sensing current can simply determine the amount of discharge of the capacitor when connected to the bit line.

[0190] In response to both the first and second storage cells being correctly programmed, method 1309 proceeds to step 1318. In step 1318, data written to one of the first and second storage cells 1221 in step 1316 is read and used to program the multilevel cell via an SLC-TLC compression operation (folding operation). The SLC-TLC compression operation can be implemented according to any method known in the art. In some embodiments, data is retrieved from the first storage cell 1221 and / or the second storage cell 1231 and then combined with other data (e.g., repeating bits stored in the third and fourth storage cells) to provide a value (e.g., 0, 1, or 2) to be stored in the multilevel cell. The value is then written to the multilevel cell.

[0191] The method continues to step 1324: the parallel programming component 150 overwrites the second memory cell. As used herein, "overwrite" includes the parallel programming component 150 storing another data value in the memory cell in a subsequent programming operation (which may occur after the second memory cell has been erased first). In other instances, at step 1324, the second memory cell is marked for reuse, the second memory cell is erased, or the second memory cell is otherwise prepared for storing other data. Then, method 1309 ends at 1350.

[0192] In response to one of the first and second memory cells not being correctly programmed, method 1309 proceeds to step 1326: the programming circuit programs the first and second memory cells individually. As previously mentioned, the individual programming of the first memory cell 1221 and the second memory cell 1231 can be performed using the same single-pulse method used in step 1316. Alternatively, the first memory cell 1221 and the second memory cell 1231 can be programmed individually, and / or programmed using different methods such as multi-pulse programming.

[0193] After completing the separate programming procedure at step 1326, the method proceeds to step 1320: applying a verification pulse to the memory cell again. The verification pulse can optionally be applied in the previous iteration of step 1320, i.e., by applying verification pulses in parallel to the word lines corresponding to the first memory cell 1221 and the second memory cell 1231. Alternatively, as an alternative to step 1320, a modified verification operation can be applied, wherein the correct programming of the first memory cell 1221 and the second memory cell 1231 is evaluated separately, for example, by applying a verification pulse only to the word line of the first memory cell 1221, reading the current through bit line 1210c, and then applying a verification pulse only to the word line of the second memory cell 1231, again reading the current through bit line 1210c.

[0194] Figure 14 An embodiment of step 1326 for individually programming cells of a memory array is described. Step 1326 can be performed each time the first memory cell and / or the second memory cell fails to be programmed correctly. In some embodiments, it may be unknown whether the first memory cell 1221 or the second memory cell 1231 is not programmed correctly; therefore, step 1326 may require individually programming the first memory cell 1221 and the second memory cell 1231. Step 1326 can be performed by a die controller 220, for example by using... Figure 1B The various circuits described herein. In alternative solutions, step 1326 can be performed using different hardware, such as... Figure 1B Controller 244 and / or Figure 1A The non-volatile memory media controller 126.

[0195] As shown in the figure, step 1326 may begin with step 1412, in which a standard verification pulse is applied to the first memory cell 1221. In this example embodiment, it may be unknown which of the two memory cells 1221, 1231 has failed to be correctly programmed. Therefore, in this example embodiment, each of the two memory cells 1221, 1231 is programmed independently. Therefore, the first memory cell 1221 and the second memory cell 1231 are not electrically coupled to perform steps 1412 and 1420 (described below). If necessary, the reprogramming of the first memory cell 1221 and the reprogramming of the second memory cell 1231 can be performed in parallel by independently and in parallel applying programming voltages between corresponding word lines of the first memory cell 1221 and the second memory cell 1231.

[0196] In step 1414, it is determined whether the first memory cell is correctly programmed. In one instance, current is sensed at a sensing component attached to either end of the NAND string containing the first memory cell, and in response to the current flowing through the first memory cell, it is determined that the first memory cell has not been successfully programmed.

[0197] In response to the current sensing at step 1414, the method proceeds to step 1416: applying an increasing programming pulse, as described herein. Any suitable increment of the programming pulse can be used. In some embodiments, a lookup table of programming pulses or increments is used; each iteration of step 1414 sets the programming pulse to the next programming pulse or increments the programming pulse by the next increment in the lookup table.

[0198] At step 1418, as part of a regular programming operation, an increased programming pulse is applied to the first memory cell, and step 1326 proceeds to step 1412, as previously described. In this example embodiment of the method, steps 1414, 1416, 1418, and 1412 may be repeated multiple times. In response to the first memory cell being correctly programmed, method 1309 proceeds to step 1420. It is worth noting that if the first memory cell 1221 meets certain criteria, such as exceeding a threshold number of programming pulses, then in order to achieve correct programming, the first memory cell 1221 may be marked for reduced use or not used in the future. If needed, the first memory cell 1221 can still be used for current storage operations. Alternatively, the first memory cell 1221 may not be used, and data to be written to the first memory cell 1221 may alternatively be written to a different memory cell (potentially a third block different from the first erase block 1220 and the second erase block 1230).

[0199] At step 1420, a verification pulse is applied to the second memory cell 1231. In step 1426, it is determined whether the second memory cell 1231 is correctly programmed. In one example, current is sensed at one of the first and second memory cells, and in response to the current flowing through the bit line, it is determined that the second memory cell has not been successfully programmed. As described in conjunction with step 1412, the first memory cell 1221 and the second memory cell 1231 may optionally be electrically decoupled to perform step 1420, such that the programming of the second memory cell 1231 can be verified separately.

[0200] In response to the current sensing at step 1426, method 1309 proceeds to step 1424: adding a programming pulse, as described herein. Any suitable method can be used to calculate the new programming pulse. As in step 1416, a lookup table, etc., can be used.

[0201] At step 1422, an additional programming pulse is applied to the second memory cell 1231, and step 1326 continues to step 1420, as previously described. Steps 1426, 1424, 1422, and 1420 can be repeated multiple times, as with steps 1412, 1414, 1416, and 1418. In response to the second memory cell being correctly programmed, method 1309 continues to step 1320.

[0202] The embodiments include programming the same data in parallel into different groups of memory cells. In the embodiments, all the different groups of memory cells are associated with the same set of bit lines. In the embodiments, all the different groups of memory cells are in the same plane. The bit line voltage can be set according to a data pattern, wherein "n" copies of the data pattern are programmed in parallel into n groups of memory cells, where n is an integer greater than 1.

[0203] Parallel programming can be used when programming memory cells as one bit per cell (SLC), two bits per cell, three bits per cell (TLC), four bits per cell (QLC), five bits per cell (QLC), and so on. Figures 15A-15D The diagram illustrates the threshold voltage (Vt) distribution obtained after parallel programming to different numbers of bits per cell. Figure 15 shows the Vt distribution for SLC programming. First, the memory cell is erased to the erase state (“1”). An erase verification voltage (Vev) is used to verify that the memory cell has been sufficiently erased. Then, the same data is programmed in parallel to different groups of memory cells. In this embodiment, selected memory cells are programmed in parallel from the erase state to the data state (“0”). Optionally, a verification voltage (Vv) can be used to verify that the Vt of the memory cell has reached the data state. A read voltage (Vr) can be used to distinguish between the erase state and the data state.

[0204] Figure 15B The Vt distribution can be depicted through a process of programming memory cells in parallel to two bits per cell. First, the memory cells are erased to the erase state (“Er”). Then, the memory cells can be programmed in parallel to various data states (state A, state B, state C). Optionally, verification voltages (Vva, VvB, VvC) can be used to determine whether the Vt of the memory cells has reached their corresponding target data states. Read voltages (VrA, VrB, VrC) can be used to distinguish these states.

[0205] Figure 15CThe distribution of Vt can be depicted through a process of programming memory cells in parallel to three bits per cell. First, the memory cells are erased to the erase state (“Er”). Then, the memory cells can be programmed in parallel to various data states (state A, state B, state C, state D, state E, state F, state G). Optionally, verification voltages (Vva, VvB, VvC, VvD, VvE, VvF, VvG) can be used to determine whether the Vt of the memory cells has reached their respective target data states. Read voltages (VrA, VrB, VrC, VrD, VrE, VrF, VrG) can be used to distinguish these states.

[0206] Figure 15D The Vt distribution can be depicted through a process of programming memory cells in parallel to four bits per cell. First, the memory cells are erased to the erase state (“S0”). Then, the memory cells can be programmed in parallel to various data states (S0-S15). Read voltages (Vr1-Vr15) can be used to distinguish these states.

[0207] Figure 16 This is a flowchart of one embodiment of a process 1600 for parallel programming of different groups of memory cells. In this embodiment, each group is in a different erase block. Hereinafter, the term "selected erase block" refers to an erase block in which memory cells are to be programmed. In some embodiments, there are three or more selected erase blocks in process 1600. Process 1600 can be used to program memory cells as one bit per cell (SLC), two bits per cell, three bits per cell (TLC), four bits per cell (QLC), five bits per cell (PLC), or some other number of bits per cell.

[0208] Step 1602 includes applying a voltage to the bit line according to the data pattern to be programmed. In an embodiment, the voltage applied to the bit line is set according to the data received at the S / A data latch 1010. In one embodiment, a programming enable voltage (e.g., 0V) is used to enable programming of selected memory cells on a selected NAND string, and a programming disable voltage (e.g., 2.5V) is used to disable programming on an unselected NAND string. The bit line to which the programming enable voltage is applied is referred to as the selected bit line. The bit line to which the programming disable voltage is applied is referred to as the programming disable bit line or the unselected bit line.

[0209] In some embodiments, a data pattern corresponds to a data state. For example, for SLC, a memory cell will remain in an erased state (“1”) or be programmed to a data state (“0”). Therefore, a data pattern may include 0 for those cells to be programmed to a data state and 1 for those cells to remain erased. If ultimately two bits are to be programmed into each cell, then the cell may eventually end up in one of an erased state, state A, state B, or state C. Therefore, the data pattern in step 1602 may identify, for example, those cells to be programmed to state A.

[0210] In step 1604, the system applies selection voltages in parallel to the drain select gates of n groups of NAND strings. In an embodiment, the selection voltage is applied to a common SGD line connecting the drain select gates of a group of NAND strings. In an embodiment, there are several conductive regions associated with each group of NAND strings. Each conductive region is connected to the control gate of a memory cell on each NAND string in the group. In an embodiment, each group of NAND strings resides in a different selected erase block. Step 1604 may include applying selection voltages in parallel to the SGD line in each erase block. The selection voltage connects the selected NAND string to its corresponding select line by turning on the drain select gate of the selected NAND string. However, the selection voltage does not turn on the drain select gate of unselected NAND strings. For example, the selection voltage may be 2.5V, the programming enable voltage on the select line may be 0V, and the programming disable voltage on the unselected line may be 2.5V.

[0211] In step 1606, the system applies programming voltages in parallel to the control gates of the n selected memory cells. The programming voltages are applied when a selection voltage is applied to the drain select gate of the NAND string and when a voltage is applied to the bit line. Therefore, data patterns are programmed in parallel into each selected memory cell group. Thus, n copies of the data pattern can be stored in parallel. In this embodiment, each selected memory cell group resides in a different selected erase block.

[0212] In step 1608, the system determines whether there is another data pattern to be programmed in parallel. For example, if process 1600 is used to program two bits per unit in parallel, then steps 1602-1606 can be repeated to program state B after parallel programming for state A. Therefore, in this example, the first data pattern programs state A in parallel, the second data pattern programs state B in parallel, and the third data pattern programs state C in parallel. In this way, two or more bits per unit can be programmed in parallel.

[0213] In some embodiments, the system verifies the programming of memory cells programmed in parallel in process 1600. For example, the system may verify (for each memory cell to be programmed to a target data state) whether the Vt of the memory cell has reached the Vt associated with the target data state, which may be referred to herein as “verifying the data state”. In some embodiments, the system does not verify the programming of memory cells programmed in parallel in process 1600.

[0214] Figure 17 This is a flowchart of one embodiment of the process 1700 for parallel programming of memory cells on a NAND string in different erase blocks. Step 1702 includes applying a programming enable voltage to the selected location line according to the data pattern to be programmed. It should be noted that a programming disable voltage (e.g., 2.5V) may be applied to an unselected location line. In this embodiment, the programming enable voltage (and programming disable voltage) applied to the location line is set based on the data received at the S / A data latch 1010.

[0215] In step 1704, the system connects each selectable line in parallel to n selected NAND strings. In one embodiment, each selectable line is connected to two selected NAND strings. In one embodiment, each selectable line is connected to three selected NAND strings. In one embodiment, each selectable line is connected to four selected NAND strings. Each selectable line may be connected to five or more selected NAND strings. In an embodiment, the system applies a select voltage to the drain select gate on the NAND string to connect the selectable line to the selected NAND string.

[0216] In step 1706, the system applies programming voltages in parallel to the control gates of n selected memory cells. The programming voltages are applied when the selectable line is connected to the selected NAND string and when a programming enable voltage is applied to the selectable line. Therefore, data patterns are programmed in parallel into each selected memory cell group. Thus, n copies of the data pattern can be stored. In this embodiment, each selected memory cell group resides in a different selected erase block.

[0217] In step 1708, the system verifies each group of memory cells. In an embodiment, a verification voltage is applied to the control gate of all currently programmed memory cells. For each selected bit line, the system can sense the current that can flow in the bit line in response to the verification voltage. In an embodiment, the system charges a sensing capacitor and then connects the sensing capacitor to the bit line (after the verification voltage is applied). The system then allows the bit line current (if present) to discharge the sensing capacitor for a predetermined time. In an embodiment, if any selected memory cell associated with the bit line does not reach its target data state, the memory cell will conduct a significant current. Therefore, in an embodiment, if at least one selected memory cell does not reach its target data state, the sensing capacitor voltage will drop below a threshold voltage.

[0218] In step 1710, the system determines whether all groups of memory cells have passed verification. This determination is based on sensing bit lines. In an embodiment, if no more than a certain number of bit lines correspond to a failed programming case, then the system considers all groups to have passed. An error correction algorithm is capable of handling a certain number of errors in such cases. If all groups have passed, then the process ends. If all groups have failed, then in step 1712, the system verifies each group of memory cells individually. All groups that have failed verification can be further programmed. In some embodiments, steps 1708-1712 are not performed; in this case, the memory cells are not verified.

[0219] In some embodiments, the system programs n copies of the data pattern in parallel into the corresponding n sets of memory cells through a multi-level cell programming process. Figure 18 This is a flowchart of an embodiment of process 1800, which involves parallel programming n copies of a data pattern into n sets of memory units through a multi-level unit programming process. Process 1800 is... Figure 16 One embodiment of the process. Step 1802 includes applying a programming enable voltage (e.g., 0V) to the selected bit lines according to state A. For example, all bit lines associated with the memory cell to be programmed to state A receive the programming enable voltage. All other bit lines receive a programming disable voltage (e.g., 2.5V).

[0220] Step 1804 involves connecting each selectable line in parallel to n selected NAND strings. In one embodiment, each selectable line is connected to two selected NAND strings. In one embodiment, each selectable line is connected to three selected NAND strings. In one embodiment, each selectable line is connected to four selected NAND strings. Each selectable line may be connected to five or more selected NAND strings. In an embodiment, the system applies a select voltage to the drain select gate on the NAND string to connect the selectable line to the selected NAND string.

[0221] Step 1804 may further include connecting each selected line in parallel to different NAND strings in the n groups of NAND strings. In one embodiment, each group of selected NAND strings resides in a different erase block. In one embodiment, there are two selected erase blocks. In one embodiment, there are three selected erase blocks. In one embodiment, there are four selected erase blocks. In one embodiment, there are more than four selected erase blocks. In an embodiment, the system connects each selected line to one selected NAND string in each selected erase block.

[0222] In step 1806, the system applies an A-state programming voltage in parallel to the control gates of n selected groups of memory cells. In an embodiment, each group of memory cells resides in a different selected erase block. In an embodiment, the system selects a value for the programming voltage used for the A-state, the value of which depends on Vt associated with the A-state. In an embodiment, the value of the A-state programming voltage is sufficient to cause almost all memory cells to reach Vt associated with the A-state using a single programming pulse. In some embodiments, a certain number of memory cells may fail to reach Vt associated with the A-state, and an error correction algorithm is used during the read process to handle such underprogrammed memory cells. In an embodiment, the A-state programming voltage will increase the Vt of the memory cells from the erase state to the Vt associated with the A-state. For example, the value may be selected such that most memory cells will experience a Vt increase from the erase state to above VvA (e.g., see...). Figure 15B Or 15B).

[0223] In an embodiment, process 1800 is used for a fuzzy-fine programming process. During fuzzy-fine programming, a first memory cell is programmed to a final Vt close to the state, but may have a Vt slightly lower than the final Vt of the state. Then, a fine programming phase can be used to complete the programming of the memory cell to the final Vt of the state. In an embodiment, the fine programming phase is performed individually on each group of memory cells (as opposed to parallel programming of each group of memory cells). In an embodiment, the A-state programming voltage will increase the Vt of the memory cell from the erase state to a Vt close to the final Vt of state A; if necessary, the fine programming phase can be used to further increase Vt. For example, regarding... Figure 15A The target Vt of state A used for parallel programming may be slightly lower than VvA, and programming to at least VvA can be completed using the fine programming phase. Those skilled in the art will understand that even if some memory cells fail to reach a Vt close to the final Vt of state A during parallel programming, the fine programming phase can still program such cells to the final Vt of state A.

[0224] Steps 1808, 1810, and 1812 are similar to their counterparts 1802, 1804, and 1806, but are applied to state B. The difference lies in step 1812, where a state B voltage is applied to the control gate of the selected memory cell. In this embodiment, the state B programming voltage has a larger magnitude than the state A programming voltage. In this embodiment, the magnitude of the state B programming voltage is sufficient to program almost all memory cells to the Vt associated with state B using a single programming pulse. In this embodiment, the state B programming voltage will increase the Vt of the memory cell from the erase state to the final Vt associated with state B. In the fuzzy-fine embodiment, the state B programming voltage will increase the Vt of the memory cell from the erase state to a Vt close to the final Vt of state B; if necessary, a fine-tuning stage can be used to further increase Vt.

[0225] Steps 1814, 1816, and 1818 are similar to their corresponding steps 1802, 1084, and 1806, but are applied to the C state. The difference lies in that, in step 1818, a C-state voltage is applied to the control gate of the selected memory cell. In an embodiment, the C-state programming voltage has a larger magnitude than the B-state programming voltage (and therefore also larger than the A-state programming voltage). In an embodiment, the magnitude of the C-state programming voltage is sufficient to program almost all memory cells to the final Vt associated with the C state using a single programming pulse. In an embodiment, the C-state programming voltage will increase the Vt of the memory cell from the erase state to the final Vt associated with the C state. In a fuzzy-fine embodiment, the C-state programming voltage will increase the Vt of the memory cell from the erase state to a Vt close to the final Vt associated with the C state; if necessary, a fine-tuning stage can be used to further increase Vt.

[0226] In one embodiment, process 1800 is used for the initial programming phase of QLC programming. For example, a memory cell ending at any of S4-S7 is programmed to state A via process 1800, a memory cell ending at any of S8-S11 is programmed to state B via process 1800, and a memory cell ending at any of S12-S15 is programmed to state C via process 1800. In this embodiment, the final programming phase leading to the final states (S4-S15) programs and verifies each group of memory cells individually.

[0227] In some embodiments, the multi-level cell parallel programming process programs memory cells as three bits per cell. Figure 19This is a flowchart of one embodiment of a process 1900 for parallel programming of memory cells in multiple erase blocks. Process 1900 describes D-state programming (steps 1902, 1904, 1906), E-state programming (steps 1908, 1910, 1912), F-state programming (steps 1914, 1916, 1918), and G-state programming (steps 1920, 1922, 1924). In one embodiment, process 1900 is executed after process 1800. Process 1900 is similar to process 1800 and will not be described in detail. In this embodiment, the programming voltage gradually increases for data states with higher Vt. In this embodiment, the D-state programming voltage is greater than the C-state programming voltage, the E-state programming voltage is greater than the D-state programming voltage, the F-state programming voltage is greater than the E-state programming voltage, and the G-state programming voltage is greater than the F-state programming voltage. Process 1900 can be used for fuzzy-fine programming processes, as described in conjunction with process 1800.

[0228] It should be noted that neither process 1800 nor process 1900 explicitly describes the verification operation. In some embodiments, process 1800 does not use programming verification. In some embodiments, process 1900 does not use programming verification. Optionally, programming verification may be used in conjunction with process 1800 or 1900. Such verification operations may be parallel verification of n groups of memory cells, as already described herein. This programming verification can be used for any or all data states. If all groups of memory cells pass the programming verification, then programming can end. If the condition "all groups of memory cells pass the programming verification" is not met, then each group of memory cells can be verified individually.

[0229] The concepts in processes 1800 and 1900 can be extended to more than three bits per memory cell. In the QLC programming implementation, the programming voltage gradually increases for data states with higher Vt.

[0230] Applying voltages such as programming voltages to more than one group of memory cells can generate a large RC load. This is because the control gate of each group of memory cells can be connected to a different conductive region (or conductive plate). In one embodiment, each group of memory cells is connected to a different word line residing in a different erase block. In another embodiment, the system selects several voltage generators (e.g., charge pumps) based on the number of memory cell groups being programmed in parallel. Figure 20A This is a block diagram of a circuit system for supplying voltage to the erase block. Voltage generators 2002(1)-2002(N) are depicted. Each voltage generator 2002 may contain a charge pump. Each voltage generator 2002 is configured to generate the same voltage. Figure 20AIn this context, the voltage is referred to as VGEN and has the same magnitude for each voltage generator 2002. In one embodiment, VGEN is the programming voltage (e.g., Vpgm). In another embodiment, VGEN is the channel rise voltage (e.g., Vpass). The channel rise voltage raises the channel potential of an unselected NAND string to prevent or reduce programming interference. Each voltage generator 2002 can be selectively connected to an erase block via a switch 2004. Each switch 2004 may contain one or more transistors, etc.

[0231] Figure 20A A plane 2006 is also shown, containing several memory cell erase blocks (BLK0-BLKn) (erase block BLK6 is selected). A sense amplifier (S / A) 2010 is associated with the plane. A bit line 2050 associated with the plane is also depicted. The voltage on bit line 2050 is set according to the data received at the data latch in S / A 2010.

[0232] Voltage generator 2002(1) is enabled, wherein switch 2004(1) is closed to electrically connect voltage generator 2002(1) to a selected erase block (BLK6). In an embodiment, voltage generator 2002(1) is connected to a conductive area (or plate) in the erase block that is connected to the control gate of a selected memory cell.

[0233] Figure 20B Showing with Figure 20A The same circuit system is used, but in this example, three erase blocks (BLK2, BLK4, BLK6) are selected. Voltage generators 2002(1), 2002(2), and 2002(3) are all enabled. In this example, switches 2004(1), 2004(2), and 2004(3) are all closed, such that each of voltage generators 2002(1), 2002(2), and 2002(3) provides VGEN to the common line 2005 connected to each selected erase block (BLK2, BLK4, BLK6). Optionally, each voltage generator can be used to provide its VGEN to a separate selected erase block. For example, voltage generator 2002(1) can provide its VGEN to BLK6, voltage generator 2002(2) can provide its VGEN to BLK4, and voltage generator 2002(3) can provide its VGEN to BLK2.

[0234] Figure 21 Depicting Figure 20A and 20B Other details regarding how the circuitry can be electrically connected to the conductive areas in the corresponding erase block. Figure 21The diagram depicts portions of two sets of NAND strings 2120 and 2130. In this embodiment, each set of NAND strings resides in a different erase block. Bit lines 2110a, 2110b, and 2110c are associated with each set of NAND strings 2120 and 2130. The two sets of NAND strings 2120 and 2130 are in the same plane. NAND string set 2130 contains NAND strings 2161, 2162, 2163, and... Figure 21 Other NAND strings not depicted. NAND string group 2120 contains similar NAND strings, allowing cells in different blocks to be programmed in parallel. Several memory cells 2121, 2122, 2123, 2124, 2125, and 2126 are circled to indicate cells that can be programmed in parallel. For example, the same data can be programmed in parallel in cells 2121 and 2124; the same data can be programmed in parallel in cells 2122 and 2125; and the same data can be programmed in parallel in cells 2123 and 2126. Each of these memory cells has a control gate electrically connected to a conductive region in the corresponding block. For example, the respective control gates of cells 2121, 2122, and 2123 are electrically connected via a selected conductive region 2140. The respective control gates of cells 2124, 2125, and 2126 are electrically connected via a selected conductive region 2150. The term "selected" is used to indicate that the memory cells connected to these lines are selected for programming.

[0235] The voltages on bit lines 2210a-2210c are set according to the data to be written to the memory cells in each NAND string group 2120, 2130. Although in Figure 21 Three bit lines 2210 are depicted, but of course, the memory cell array can contain many more bit lines. Furthermore, although two NAND string groups are depicted, one or more additional copies can optionally be programmed, for example, in a third NAND string group (not shown), a fourth NAND string group (not shown), and so on.

[0236] As previously combined Figure 20A and 20B The voltage generators 2002(1)-2002(N) can be enabled separately and can be connected to line 2005 via switches 2004(1)-2004(N). Figure 21The diagram illustrates an example of providing a programming voltage (VPGM) to a NAND string group. Specifically, voltage generators 2002(1) and 2002(2) are both enabled, each generating VPGM. Switches 2004(1) and 2004(2) are closed to provide VPGM to line 2005. Switch 2102 is configured to electrically connect line 2005 to both selected conductive regions 2140 and 2150. Switch 2102 may contain transistors, etc. Thus, VPGM is provided to selected conductive regions 2140 and 2150. Thus, VPGM is provided to the control gates of memory cells 2121-2126. Optionally, switch 2102 may be used to provide VPGM from voltage generator 2002(1) to selected conductive region 2150 and VPGM from voltage generator 2002(2) to selected conductive region 2140, instead of providing VPGM to line 2005.

[0237] If additional NAND string groups are to be included in parallel programming, an additional voltage generator 2002 can be used to supply the VPGM. In one embodiment, there is a one-to-one correspondence between the voltage generator 2002 and the NAND string groups. That is, in one embodiment, one voltage generator 2002 is enabled for each NAND string group. However, a one-to-one correspondence is not required.

[0238] Figure 21 An example is depicted where a VPGM is provided to selected conductive regions connected to different groups of NAND strings. Each group of NAND strings may reside in a different erase block. A voltage generator 2002 may be used to provide additional voltages (e.g., Vpass) to unselected conductive regions. The term "unselected" is used to indicate that memory cells connected to these lines are not selected for programming. In one embodiment, a channel rise voltage (Vpass) is provided to the control gate of an unselected memory cell connected to an unselected conductive region.

[0239] Figure 22 This is a flowchart of one embodiment of a process 2200 for providing voltage during parallel programming. This process can be used to provide voltage (e.g., VPGM, Vpass) during the various processes described herein. For example, process 2200 can be used in steps 1606, 1806, 1812, 1818, 1906, 1912, 1918, and / or 1924. In step 2202, the system enables several voltage generators 2002 based on the number of NAND string groups involved in the parallel programming. In one embodiment, the system enables one voltage generator 2002 for each NAND string group. In one embodiment, the system enables several voltage generators 2002 based on the number of erase blocks involved in the parallel programming. In one embodiment, the system enables one voltage generator 2002 for each selected erase block.

[0240] In step 2204, the system connects the enabled voltage generator 2002 in parallel to a conductive region. The conductive region is connected to the control gate of a memory cell in the corresponding NAND string group. In step 2204, the system may control switch 2004 and / or switch 2102. In one embodiment, the system connects the enabled voltage generator 2002 in parallel to multiple selected conductive regions (e.g., 2140, 2150) to provide VPGM. In one embodiment, the system connects the enabled voltage generator 2002 in parallel to one or more unselected conductive regions in each erase block to provide Vpass.

[0241] Figure 23 An example of a multi-stage charge pump 2300 is depicted. The charge pump 2300 can be used in a voltage generator 2002. Vin is provided at the input node 2302, such that Vout is obtained at the output node 2326. As an example, three stages 2308, 2316, and 2324 are provided. Two or more stages can be used. For example, each stage may contain a switch and one or more flying capacitors. At the input, capacitor Cin 2304 is connected to ground node 2306 at one of its conductive layers. At node 2310, located between the first stage 2308 and the second stage 2316, capacitor Ca 2312 is connected to ground node 2314 at one of its conductive layers. At node 2318, located between the second stage 2316 and the third stage 2324, capacitor Cb 2320 is connected to ground node 2322 at one of its conductive layers. Finally, at the output node 2326, output capacitor Cout 2328 is connected to ground node 2330 at one of its conductive layers. Multistage charge pumps offer greater flexibility in providing a wider range of output voltages. Furthermore, each stage can include one or more capacitors for even greater flexibility.

[0242] The multi-stage charge pump 2300 operates under the control of a regulating and control circuitry 2317 for controlling the switches in each stage. It should be noted that, alternatively, a regulating and control circuitry may also be provided in each stage. Charge is transferred from the input node 2302 of the first stage to a flying capacitor (not shown) in the first stage 2308, and from the flying capacitor of the first stage to node 2310. Charge is then transferred from node 2310 of the second stage to a flying capacitor (not shown) in the second stage, and from the flying capacitor of the second stage to node 2318. Charge is then transferred from node 2318 to a flying capacitor (not shown) in the third stage, and from the flying capacitor of the third stage to the output node 2326 (assuming no other stages exist).

[0243] As can be seen from the above description, one aspect includes a device comprising multiple sets of NAND strings. Each NAND string includes a memory cell. Each memory cell has a control gate. Each NAND string includes a drain-select gate. The device includes a plurality of bit lines associated with the multiple sets of NAND strings. Each bit line is associated with a different NAND string in each set of NAND strings. The device includes one or more management circuits connected to the multiple sets of NAND strings and the plurality of bit lines. The one or more management circuits are configured to apply a voltage to the plurality of bit lines according to a data pattern, apply a selection voltage to the drain-select gate of the multiple sets of NAND strings, and, while the selection voltage is applied to the drain-select gate of the multiple sets of NAND strings and the voltage is applied to the plurality of bit lines, apply programming pulses in parallel to the control gate of a different set of selected memory cells in each corresponding set of the multiple sets of NAND strings to program the data pattern in parallel into each set of selected memory cells.

[0244] In another aspect, the multiple sets of NAND strings include at least three sets of NAND strings.

[0245] In another aspect, the one or more management circuits are configured to apply programming pulses in parallel to the control gates of selected memory cells in different groups within each of the multiple groups of NAND strings to program each selected memory cell as a single bit per cell.

[0246] In another aspect, the data mode defines whether the selected memory cell will be programmed into one of a plurality of data states. The one or more management circuits are configured to select the magnitude of the programming pulse based on which of the plurality of data states is currently undergoing parallel programming.

[0247] In another aspect, the data pattern corresponds to a first data state among multiple data states. The programming pulse is a first programming pulse applied by the one or more management circuits to program a selected memory cell targeting the first data state in parallel.

[0248] In another aspect, the one or more management circuits are further configured to: apply a voltage to the plurality of bit lines according to a second data mode, wherein the second data mode corresponds to a second data state among the plurality of data states; apply the selection voltage in parallel to the drain-select gates of the plurality of NAND strings; and when the selection voltage is applied to the drain-select gates of the plurality of NAND strings and the voltage is applied to the bit lines, apply a second programming pulse in parallel to the control gate of the selected memory cell in each corresponding group of the plurality of NAND strings to program the second data mode in parallel into each selected memory cell.

[0249] In another aspect, the device further includes a plurality of voltage generators. The one or more management circuits are further configured to enable several voltage generators based on the number of selected groups of memory cells to be programmed in parallel. The one or more management circuits are configured to connect the enabled voltage generators to the control gate of the selected group of memory cells in each of the plurality of NAND strings to apply programming pulses to the control gate in parallel.

[0250] In another aspect, the one or more management circuits are further configured to enable a separate voltage generator for each selected group of memory cells to be programmed in parallel.

[0251] One aspect is a method comprising: i) applying a programming enable voltage to a select line according to a data state to which "n" groups of nonvolatile memory cells are to be programmed in parallel, where n is an integer greater than 1; ii) connecting each select line in parallel to n selected NAND strings, including connecting each select line in parallel to different NAND strings in the n groups of NAND strings; iii) when the select line is connected to the corresponding n selected NAND strings and the programming enable voltage is applied to the select line, applying programming pulses in parallel to the control gates of the n groups of memory cells to program each of the n groups of memory cells in parallel to a threshold voltage distribution associated with the data state; and iv) repeating ii) and iii) for zero or more additional data states.

[0252] One aspect includes a system comprising: multiple sets of NAND strings, each NAND string including a non-volatile memory cell, each memory cell having a control gate. The system includes multiple conductive regions, each conductive region connected to the control gate of a memory cell in each of the multiple sets of NAND strings. The system includes multiple bit lines associated with the multiple sets of NAND strings, each bit line associated with a different NAND string in each set of NAND strings. The system includes multiple voltage generators. The system includes one or more management circuitry connected to the multiple sets of NAND strings, the multiple conductive regions, the multiple bit lines, and the multiple voltage generators. The one or more management circuitry are configured to enable several voltage generators based on the number of conductive regions to receive the same magnitude of voltage during a programming operation that programs the same data pattern in parallel into n sets of memory cells. Each set of memory cells resides in a different set of the multiple sets of NAND strings, where n is an integer greater than 1. The one or more management circuits are configured to connect an enabled voltage generator to the plurality of conductive regions to apply the same magnitude of voltage to the plurality of conductive regions in parallel when the same data pattern is programmed in parallel into n sets of memory cells.

[0253] In various embodiments, the components for electrically connecting the first word line and the second word line may include a parallel programming component 150, a die controller 220, a programming circuit 284, a non-volatile memory device interface 139, a non-volatile memory media controller 126, a device driver, a controller (e.g., a device driver, etc.) executing on the host computing device 110, a processor 111, or other logic hardware.

[0254] In various embodiments, the components for electrically selecting bit lines may include a parallel programming component 150, a die controller 220, a programming circuit 284, a non-volatile memory device interface 139, a non-volatile memory media controller 126, a host computing device 110, a bus 127, a communication network 115, a device driver, a controller (e.g., a device driver, etc.) executing on the host computing device 110, a processor 111, other logic hardware, and / or other executable code stored on a computer-readable storage medium.

[0255] In various embodiments, the components for applying a single programming pulse to a connected word line may include a parallel programming component 150, a die controller 220, a programming circuit 284, a non-volatile memory device interface 139, a non-volatile memory media controller 126, a storage client 116, a host computing device 110, a bus 127, a communication network 115, a device driver, a controller (e.g., a device driver, etc.) executing on the host computing device 110, a processor 111, other logic hardware, and / or other executable code stored on a computer-readable storage medium.

[0256] This disclosure may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The described embodiments are to be regarded in all respects as illustrative and not limiting. Therefore, the scope of this disclosure is indicated by the appended claims rather than the foregoing description. All modifications within the equivalent meaning and scope of the claims should be included within the scope of the claims.

Claims

1. An apparatus comprising: Multiple NAND strings, each NAND string includes a memory cell, each memory cell has a control gate, and each NAND string includes a drain-select gate. Multiple bit lines associated with the multiple sets of NAND strings, each bit line being associated with a different NAND string in each set of NAND strings; and One or more management circuits are connected to the plurality of NAND strings and the plurality of bit lines, the one or more management circuits being configured to: A voltage is applied to the plurality of bit lines according to a certain data pattern; A selection voltage is applied to the drain-select gate of the plurality of NAND strings; and While the selection voltage is applied to the drain selection gate of the plurality of NAND strings and the voltage is applied to the plurality of bit lines, programming pulses are applied in parallel to the control gate of a group of selected memory cells in each of the plurality of NAND strings to program the data pattern in parallel to each group of selected memory cells.

2. The device according to claim 1, wherein the plurality of NAND strings comprises at least three NAND strings.

3. The device of claim 1, wherein the one or more management circuits are configured to apply the programming pulses in parallel to the control gate of the selected memory cells in each of the plurality of NAND strings to program each selected memory cell as a single bit per cell.

4. The device of claim 1, wherein the data mode defines whether the selected memory cell will be programmed into a certain data state among a plurality of data states, and the one or more management circuits are configured to: The magnitude of the programming pulse is selected based on which of the plurality of data states is currently undergoing parallel programming.

5. The device of claim 1, wherein the data mode corresponds to a first data state among a plurality of data states, and the programming pulse is a first programming pulse applied by the one or more management circuits to program a selected memory cell targeting the first data state in parallel.

6. The device of claim 5, wherein the one or more management circuits are further configured to: A voltage is applied to the plurality of bit lines according to a second data mode, wherein the second data mode corresponds to a second data state among the plurality of data states; The selection voltage is applied in parallel to the drain-select gate of the multiple NAND strings; and When the selection voltage is applied to the drain selection gate of the plurality of NAND strings and the voltage is applied to the bit line, a second programming pulse is applied in parallel to the control gate of the selected memory cell in each corresponding group of the plurality of NAND strings to program the second data mode in parallel to each selected memory cell.

7. The device of claim 1, further comprising a plurality of voltage generators, wherein the one or more management circuits are further configured to: Several voltage generators are enabled based on the number of selected memory cell groups to be programmed in parallel; and An enabled voltage generator is connected to the control gate of a selected set of memory cells in each of the multiple sets of NAND strings to apply the programming pulses to the control gates in parallel.

8. The device of claim 7, wherein the one or more management circuits are further configured to enable a separate voltage generator for each selected group of memory cells to be programmed in parallel.

9. A method comprising: i) Apply a programming enable voltage to the selected positioning line according to the data state to which n sets of non-volatile memory cells are programmed in parallel, where n is an integer greater than 1; ii) Connect each selected positioning line in parallel to n selected NAND strings, including connecting each selected positioning line in parallel to different NAND strings in n groups of NAND strings; iii) When the select line is connected to the corresponding n selected NAND strings and the programming enable voltage is applied to the select line, programming pulses are applied in parallel to the control gates of the n groups of nonvolatile memory cells to program each of the n groups of nonvolatile memory cells in parallel to a threshold voltage distribution associated with the data state; as well as iv) For zero or more additional data states, repeat steps i), ii), and iii).

10. The method of claim 9, wherein repeating i), ii), and iii) for zero or more additional data states comprises: Repeat steps i), ii), and iii) for at least three additional data states.

11. The method of claim 9, wherein repeating i), ii), and iii) for zero or more additional data states comprises: Repeat statements i), ii), and iii) for at least three additional data states without verifying any of the data states.

12. The method of claim 11, further comprising: After the n groups of non-volatile memory cells are programmed in parallel to the data state, a fine-grained programming phase is performed individually on each of the n groups of non-volatile memory cells.

13. The method of claim 9, wherein repeating i), ii), and iii) for zero or more additional data states comprises: The magnitude of the programming pulse is selected for each corresponding data state, and the magnitude depends on the threshold voltage associated with the data state.

14. The method of claim 9, wherein repeating i), ii), and iii) for zero or more additional data states comprises: Repeat steps i), ii), and iii) for the three additional data states to program each of the n sets of nonvolatile memory cells in parallel as two bits per cell.

15. The method of claim 14, further comprising: After programming the n groups of non-volatile memory cells in parallel to two bits per cell, each of the n groups of non-volatile memory cells is programmed individually to four bits per cell.

16. A system comprising: Multiple NAND strings, each NAND string including a non-volatile memory cell, each memory cell having a control gate; Multiple conductive regions, each conductive region being connected to the control gate of the memory cell of each NAND string in a set of NAND strings; Multiple bit lines associated with the multiple sets of NAND strings, each bit line being associated with a different NAND string in each set of NAND strings; Multiple voltage generators; as well as One or more management circuits are connected to the plurality of NAND strings, the plurality of conductive regions, the plurality of bit lines, and the plurality of voltage generators, the one or more management circuits being configured to: Several voltage generators are enabled based on the number of conductive regions that need to receive the same voltage magnitude during the programming operation, which programs the same data pattern in parallel into n groups of memory cells, each group of memory cells residing in a different group among the multiple groups of NAND strings, where n is an integer greater than 1; and An enabled voltage generator is connected to the plurality of conductive regions to apply the same magnitude of voltage to the plurality of conductive regions in parallel when the same data pattern is programmed into the n sets of memory cells in parallel.

17. The system according to claim 16, wherein: The voltage of the same magnitude is the programming voltage; and The plurality of conductive regions are n selected conductive regions, and each group of memory cells is connected to one of the n selected conductive regions.

18. The system according to claim 17, wherein: The one or more management circuits are configured to select one of the voltage generators for each of the selected conductive regions.

19. The system according to claim 16, wherein: The same voltage value is an increased voltage; and The aforementioned conductive regions are unselected conductive regions.

20. The system of claim 16, wherein the one or more management circuits are configured to perform the following operations when an enabled voltage generator is connected to the plurality of conductive regions: Based on the data state to which the n sets of memory cells are to be programmed in parallel, a programming enable voltage is applied to the selected positioning line; and Each selected positioning line is connected in parallel to n selected NAND strings, including connecting each selected positioning line in parallel to different NAND strings in n groups of NAND strings.

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