Multilayer ceramic capacitor

Abstract

The present disclosure provides a multilayer ceramic capacitor including a main body including dielectric layers and first and second internal electrodes having different sizes from each other, and having a first surface and a second surface opposite to each other in a stacking direction, a third surface and a fourth surface connected to the first and second surfaces and opposite to each other, and a fifth surface and a sixth surface connected to the first and second surfaces and connected to the third and fourth surfaces and opposite to each other, and first and second external electrodes. When an edge of the first internal electrode in a length direction is b and an edge of the second internal electrode in the length direction is a, a ratio a / b of the edge a of the second internal electrode in the length direction to the edge b of the first internal electrode in the length direction is 0.33 or more (wherein a>0 and b>0).

Description

[0001] This application is a divisional application of the invention patent application "Multilayer Ceramic Capacitor" filed on April 2, 2020, with application number 202010254779.5. Technical Field

[0002] This disclosure relates to a multilayer ceramic capacitor. Background Technology

[0003] Multilayer ceramic capacitors (MLCCs) are passive components that control electrical signals in circuits. The main function of such MLCCs is to accumulate charge in their electrodes, block direct current (DC) signals, and allow alternating current (AC) signals to pass through. In other words, MLCCs play a role in stabilizing IC operation by bypassing AC noise and removing AC noise from the power lines.

[0004] When the electromagnetic distance between each layer is reduced, MLCC devices may experience performance degradation due to crosstalk.

[0005] Specifically, compared to simply connecting individual components in parallel, the problem is that the electric field characteristics are more likely to be weakened when using a single integrated chip. Summary of the Invention

[0006] One aspect of this disclosure is to prevent the degradation of electric field characteristics due to crosstalk.

[0007] Another aspect of this disclosure is to significantly reduce the effect of the edge field applied to the internal electrode.

[0008] Another aspect of this disclosure is to reduce noise caused by unwanted electric field signals.

[0009] According to one aspect of this disclosure, a multilayer ceramic capacitor includes: a body comprising a dielectric layer and a first inner electrode and a second inner electrode having different dimensions from each other, and the body having a first surface and a second surface opposite to each other in a stacking direction, a third surface and a fourth surface connected to the first surface and the second surface and opposite to each other, and a fifth surface and a sixth surface connected to the first surface and the second surface and connected to the third surface and the fourth surface and opposite to each other; and a first outer electrode and a second outer electrode, wherein when the edge of the first inner electrode in the length direction is b and the edge of the second inner electrode in the length direction is a, the ratio a / b of the edge a of the second inner electrode in the length direction to the edge b of the first inner electrode in the length direction can be 0.33 or greater (where a > 0 and b > 0).

[0010] According to another embodiment of this disclosure, a multilayer ceramic capacitor includes: a body comprising a dielectric layer and a first inner electrode and a second inner electrode having different dimensions from each other, and the body having a first surface and a second surface opposite to each other in a stacking direction, a third surface and a fourth surface connected to the first surface and the second surface and opposite to each other, and a fifth surface and a sixth surface connected to the first surface and the second surface and connected to the third surface and the fourth surface and opposite to each other; and a first outer electrode and a second outer electrode, wherein when the edge of the first inner electrode in the width direction is d and the edge of the second inner electrode in the width direction is c, the ratio c / d of the edge of the second inner electrode in the width direction to the edge of the first inner electrode in the width direction can be 0.33 or greater (where c > 0 and d > 0).

[0011] According to another aspect of this disclosure, a multilayer ceramic capacitor includes: a body including a first inner electrode and a second inner electrode having a size different from that of the first inner electrode, the first inner electrode and the second inner electrode being stacked along a thickness direction and a dielectric layer disposed between the first inner electrode and the second inner electrode; and a first outer electrode connected to the first inner electrode and a second outer electrode connected to the second inner electrode. The value of a / b and c / d is greater than 0.33 or both, where a is the shortest distance between the end of the second inner electrode and the end of the dielectric layer in a length direction perpendicular to the thickness direction, b is the shortest distance between the end of the first inner electrode and the end of the dielectric layer in the length direction, c is the shortest distance between the end of the second inner electrode and the end of the dielectric layer in a width direction perpendicular to both the thickness direction and the length direction, and d is the shortest distance between the end of the first inner electrode and the end of the dielectric layer in the width direction, wherein all of a, b, c, and d are greater than zero. Attached Figure Description

[0012] The above and other aspects, features and advantages of this disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 This is a schematic perspective view of a multilayer ceramic capacitor according to an embodiment of the present disclosure;

[0014] Figure 2 yes Figure 1 A schematic perspective view of the main body of a multilayer ceramic capacitor;

[0015] Figure 3 and Figure 4 This shows the applications respectively. Figure 1A plan view of the first and second internal electrodes of a multilayer ceramic capacitor.

[0016] Figure 5 It is applied to Figure 1 A plan view of the stacked first and second internal electrodes of a multilayer ceramic capacitor.

[0017] Figure 6 This is a schematic perspective view of a multilayer ceramic capacitor according to another embodiment of the present disclosure;

[0018] Figure 7 It is shown Figure 6 A schematic perspective view of the main body of a multilayer ceramic capacitor;

[0019] Figure 8 It is applied to Figure 6 A plan view of the stacked first and second internal electrodes of a multilayer ceramic capacitor.

[0020] Figure 9 This is a schematic perspective view of a multilayer ceramic capacitor according to another embodiment of the present disclosure;

[0021] Figure 10 This is a schematic perspective view of a multilayer ceramic capacitor according to another embodiment of the present disclosure;

[0022] Figure 11 It is shown Figure 9 and Figure 10 A schematic perspective view of the main body of a multilayer ceramic capacitor;

[0023] Figure 12 This makes the embodiments applicable to Figure 9 and Figure 10 A plan view of the stacked first and second internal electrodes of a multilayer ceramic capacitor.

[0024] Figure 13 This makes another embodiment applicable to Figure 9 and Figure 10 A plan view of the stacked second and third internal electrodes of a multilayer ceramic capacitor;

[0025] Figure 14 This shows the application to Figure 9 and Figure 10 A plan view of the second internal electrode of a multilayer ceramic capacitor;

[0026] Figure 15 This makes another embodiment applicable to Figure 9 and Figure 10 A plan view of the stacked first and second internal electrodes of a multilayer ceramic capacitor; and

[0027] Figure 16It is a graph showing the crosstalk level (S21 parameter) of the multilayer ceramic capacitor according to the present disclosure in the ratio of the edges in the length and / or width direction of the multilayer ceramic capacitor. Detailed Implementation

[0028] In the following description, embodiments of the present disclosure will be illustrated with reference to the accompanying drawings. However, the present disclosure may be exemplified in many different forms and should not be construed as limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Therefore, for clarity of description, the shapes and dimensions of the elements in the drawings may be exaggerated, and elements indicated by the same reference numerals in the drawings are the same elements.

[0029] Throughout this specification, unless otherwise expressly stated, when a component is referred to as “including” or “contains”, it means that the component may also include other components, without excluding other components.

[0030] In the following text, when defining the orientation of the capacitor body 110 to clearly illustrate the embodiments of this disclosure, X, Y, and Z shown in the figures represent the length direction (second direction), width direction (third direction), and thickness direction (first direction) of the capacitor body 110, respectively. Furthermore, in this embodiment, the Z direction may conceptually be the same as the stacking or lamination direction along which the dielectric layers are stacked or laminated.

[0031] Figure 1 This is a schematic perspective view of a multilayer ceramic capacitor according to an embodiment of the present disclosure. Figure 2 yes Figure 1 A schematic perspective view of the main body of a multilayer ceramic capacitor. Figure 3 and Figure 4 This shows the applications respectively. Figure 1 A plan view of the first and second internal electrodes of a multilayer ceramic capacitor. Figure 5 It is applied to Figure 1 A plan view of the stacked first and second internal electrodes of a multilayer ceramic capacitor.

[0032] Reference Figures 1 to 5According to an embodiment of the present disclosure, a multilayer ceramic capacitor includes a body 110 and a first external electrode 131 and a second external electrode 132. The body 110 includes a dielectric layer 111 and a first internal electrode 121 and a second internal electrode 122 having different sizes from each other. The body 110 has a first surface S1 and a second surface S2 that are opposite to each other in the stacking direction, a third surface S3 and a fourth surface S4 that are connected to the first surface S1 and the second surface S2 and opposite to each other, and a fifth surface S5 and a sixth surface S6 that are connected to the first surface S1 and the second surface S2 and connected to the third surface S3 and the fourth surface S4 and opposite to each other.

[0033] In this case, when the edge of the first inner electrode 121 in the length direction is b and the edge of the second inner electrode 122 in the length direction is a, the ratio a / b of the edge a of the second inner electrode 122 in the length direction to the edge b of the first inner electrode 121 in the length direction can be 0.33 or greater (where a > 0 and b > 0).

[0034] In the multilayer ceramic capacitor according to this disclosure, crosstalk that may occur due to the fringing effect, as described later, can be prevented when the ratio of the edges in the length direction (a / b) and / or the ratio of the edges in the width direction (c / d, described later) falls within a predetermined range, thereby preventing degradation of the electric field characteristics. The fringing effect refers to the effect caused by the circular diffusion and convergence of electric field lines at the terminals of a parallel-plate capacitor, which can cause crosstalk when unwanted electric field signals are transmitted to another port. This phenomenon is likely to occur when multiple small plates are mounted in a narrow area, or when several components are combined into a single plate. The multilayer ceramic capacitor of this disclosure solves this problem. The size of the fringing field can be reduced by using multiple internal electrodes as a compensating pattern for each other, thereby preventing degradation of the electric field characteristics and the generation of noise.

[0035] In this specification, "edge" can mean the dimensional difference between the dielectric layer and the inner electrode, and can also mean the distance between the end of the inner electrode and the end of the dielectric layer. Furthermore, in this specification, "edge in the length direction" can mean the shortest distance from the end of the inner electrode in the length direction (second direction, X direction) to the end of the dielectric layer in the length direction (second direction, X direction), and can also mean the shortest distance from the end of the inner electrode in the length direction (second direction, X direction) to the third surface S3 or the fourth surface S4 of the aforementioned body. In this specification, "edge in the width direction" can mean the shortest distance from the end of the inner electrode in the width direction (third direction, Y direction) to the end of the dielectric layer in the width direction (third direction, Y direction), and can also mean the shortest distance from the end of the inner electrode in the width direction (third direction, Y direction) to the fifth surface S5 or the sixth surface S6 of the aforementioned body.

[0036] Figure 12 This is a cross-sectional view of a multilayer ceramic capacitor in which a first internal electrode 321 and a second internal electrode 322 are disposed. (Refer to...) Figure 12 The edge b of the first inner electrode 321 in the length direction refers to the shortest distance from position l1 to position l3, and the edge a of the second inner electrode 322 in the length direction refers to the shortest distance from position l2 to position l3. Additionally, the edge d of the first inner electrode 321 in the width direction refers to the shortest distance from position w1 to position w3, and the edge c of the second inner electrode 322 in the width direction refers to the shortest distance from position w2 to position w3.

[0037] The capacitor body 110 is formed by laminating multiple dielectric layers 111 in the Z direction and then firing the multiple dielectric layers 111. The boundary between adjacent dielectric layers 111 of the capacitor body 110 can be integrated, making it difficult to confirm the boundary without using a scanning electron microscope (SEM).

[0038] The specific shape of the body is not particularly limited, but as shown, the body can be formed into a hexahedral shape or a similar shape. Due to the shrinkage of the ceramic powder contained in the body during the firing process, although the body does not have a perfectly linear hexahedral shape, it can have a generally hexahedral shape. In addition, the shape and size of the capacitor body 110 and the number of layers of the dielectric layer 111 are not limited to those shown in the figures of this embodiment.

[0039] In this embodiment, for ease of explanation, the two surfaces of the capacitor body 110 that are opposite to each other in the Z direction are defined as the first surface S1 and the second surface S2, the two surfaces connected to the first surface S1 and the second surface S2 and opposite to each other in the X direction are defined as the third surface S3 and the fourth surface S4, and the two surfaces connected to the first surface S1 and the second surface S2 and connected to the third surface S3 and the fourth surface S4 and opposite to each other in the Y direction are defined as the fifth surface S5 and the sixth surface S6.

[0040] According to embodiments of this disclosure, there are no particular limitations on the raw materials used to form the dielectric layer 111, as long as sufficient electrostatic capacitance can be obtained. For example, the raw materials used to form the dielectric layer 111 can be barium titanate (BaTiO3), lead composite perovskite, strontium titanate (SrTiO3), etc.

[0041] Additionally, for the purposes of this disclosure, materials used to form the dielectric layer 111 (various ceramic additives, organic solvents, plasticizers, binders, dispersants, etc.) can be added to powders such as barium titanate (BaTiO3).

[0042] Transition metal oxides or transition metal carbides, rare earth elements, magnesium (Mg), aluminum (Al), etc., can be used as ceramic additives.

[0043] In the examples of this disclosure, a plurality of inner electrodes 121 and 122 with different sizes may be alternately arranged with a dielectric layer 111 between them. In this case, the first inner electrode 121 and the second inner electrode 122 may be electrically isolated from each other by the dielectric layer 111 disposed in the middle.

[0044] There are no particular limitations on the materials used to form the first internal electrode 121 and the second internal electrode 122, and conductive pastes including, for example, silver (Ag), palladium (Pd), gold (Au), platinum (Pt), nickel (Ni), copper (Cu), tin (Sn), tungsten (W), palladium (Pd), titanium (Ti), and alloys thereof can be used to form the conductive paste. Screen printing or gravure printing can be used as printing methods for the conductive paste, but this disclosure is not limited thereto.

[0045] The average thickness of the first inner electrode 121 and the second inner electrode 122 can be 0.4 μm or less. The average thickness of the inner electrodes can be the average of values ​​measured at five different locations on the fired inner electrodes. There is no particular limitation on the lower limit of the average thickness of the first and second inner electrodes, but it can be, for example, 0.01 μm or greater.

[0046] In embodiments of this disclosure, the ratio a / b of the length-direction edge a of the second inner electrode 122 to the length-direction edge b of the first inner electrode 121 can be 0.33 or greater. When the ratio a / b of the length-direction edge a of the second inner electrode 122 to the length-direction edge b of the first inner electrode 121 is 0.33 or greater, the second inner electrode effectively serves as a compensation pattern and can reduce crosstalk. When the ratio a / b is less than 0.33, the distance to the outer electrode may be too close and a short circuit may occur.

[0047] In the example, there is no particular upper limit to the ratio a / b of the length-direction edge a of the second inner electrode 122 to the length-direction edge b of the first inner electrode 121; however, it may be less than 1, for example. When the ratio a / b is 1, the second inner electrode 122 may not be usable as a compensation pattern. The ratio (a / b) of the length-direction edge a of the second inner electrode to the length-direction edge b of the first inner electrode may be less than 1, for example, 0.95 or less, 0.85 or less, 0.80 or less, 0.75 or less, or 0.67 or less. The ratio a / b of the length-direction edge a of the second inner electrode to the length-direction edge b of the first inner electrode satisfies the above range, thereby significantly reducing the influence of the edge field applied to the end of the inner electrode and significantly reducing crosstalk.

[0048] In embodiments according to this disclosure, the difference (ba) between the length-direction edge a of the second inner electrode and the length-direction edge b of the first inner electrode can be 10 μm or greater. The difference (ba) between the length-direction edge b of the first inner electrode and the length-direction edge a of the second inner electrode can represent the difference in length between the length of the length-direction edge b of the first inner electrode and the length of the length-direction edge a of the second inner electrode, and can represent the difference in length in the X direction. By making the difference (ba) between the length-direction edge b of the first inner electrode and the length-direction edge a of the second inner electrode 10 μm or greater, the noise of the multilayer ceramic capacitor can be effectively reduced.

[0049] The difference (ba) between the length-direction edge b of the first inner electrode and the length-direction edge a of the second inner electrode can be, for example, 10 μm or greater, 14 μm or greater, 18 μm or greater, 22 μm or greater, 26 μm or greater, or 30 μm or greater, and there is no particular upper limit; for example, it can be 500 μm or less. When the difference (ba) between the length-direction edge b of the first inner electrode and the length-direction edge a of the second inner electrode satisfies the above range, the noise removal effect can be maximized.

[0050] In another embodiment of this disclosure, when the edge of the first inner electrode in the width direction is d and the edge of the second inner electrode in the width direction is c, the ratio c / d of the edge c of the second inner electrode in the width direction to the edge d of the first inner electrode in the width direction can be 0.33 or greater (where c > 0 and d > 0). Crosstalk can be reduced within the range where the ratio c / d of the edge c of the second inner electrode in the width direction to the edge d of the first inner electrode in the width direction is 0.33 or greater. When the ratio c / d is less than 0.33, the distance to the outer electrode may be too close, and a short circuit may occur.

[0051] In the example, there is no particular upper limit to the ratio c / d of the width-direction edge c of the second inner electrode to the width-direction edge d of the first inner electrode, but it can be, for example, less than 1. When the ratio c / d is 1, the second inner electrode may not be usable as a compensation pattern. The ratio c / d of the width-direction edge d of the first inner electrode to the width-direction edge c of the second inner electrode can be less than 1, 0.95 or less, 0.85 or less, 0.80 or less, 0.75 or less, 0.70 or less, or 0.67 or less. The fact that the ratio c / d of the width-direction edge c of the second inner electrode to the width-direction edge d of the first inner electrode satisfies the above ranges makes it possible to significantly reduce the influence of the edge field applied to the end of the inner electrode and to significantly reduce crosstalk.

[0052] In embodiments according to this disclosure, the difference (dc) between the edge d of the first inner electrode in the width direction and the edge c of the second inner electrode in the width direction can be 10 μm or greater. The difference (dc) between the edge d of the first inner electrode in the width direction and the edge c of the second inner electrode in the width direction can mean the difference between the width of the edge d of the first inner electrode in the width direction and the width of the edge c of the second inner electrode in the width direction, and can mean the difference in width in the Y direction. By making the difference (dc) between the edge d of the first inner electrode in the width direction and the edge c of the second inner electrode in the width direction 10 μm or greater, the noise of the multilayer ceramic capacitor can be effectively reduced.

[0053] The difference (dc) between the width-direction edge d of the first inner electrode and the width-direction edge c of the second inner electrode can be, for example, 10 μm or greater, 14 μm or greater, 18 μm or greater, 22 μm or greater, 26 μm or greater, or 30 μm or greater, and its upper limit is not particularly limited, but can be, for example, 500 μm or less. When the difference (dc) between the width-direction edge d of the first inner electrode and the width-direction edge c of the second inner electrode satisfies the above range, the noise removal effect can be maximized.

[0054] The first external electrode 131 and the second external electrode 132 may be configured to contact the first internal electrode and the second internal electrode, respectively. The contact between the first external electrode and the second external electrode with the first internal electrode and the second internal electrode respectively implies that the first internal electrode is connected to the first external electrode through a portion exposed to the outside of the body, and that the second internal electrode is connected to the second external electrode through a portion exposed to the outside of the body. The first external electrode 131 and the second external electrode 132 may extend and be disposed on portions of four surfaces that contact the exposed surfaces of the first internal electrode and the second internal electrode.

[0055] The method for forming the first external electrode 131 and the second external electrode 132 is not particularly limited. For example, the first external electrode 131 and the second external electrode 132 can be formed by immersing the substrate in a paste comprising conductive metal and glass, or by transferring a dry film obtained by drying the metal paste onto the substrate.

[0056] In embodiments of this disclosure, the first external electrode 131 and the second external electrode 132 may be one or more of silver (Ag), palladium (Pd), gold (Au), platinum (Pt), nickel (Ni), copper (Cu), tin (Sn), tungsten (W), palladium (Pd), titanium (Ti), and alloys thereof. Additionally, to improve mountability with the substrate, plating layers may be formed on the first external electrode 131 and the second external electrode 132.

[0057] In embodiments of this disclosure, the first inner electrode and the second inner electrode may be respectively configured to be exposed on the third and fourth surfaces of the body. The exposure of the first and second inner electrodes on the third and fourth surfaces of the body implies that the first and second inner electrodes are stacked in the Z direction and exposed on the third and fourth surfaces of the body. In this case, the first outer electrode 131 and the second outer electrode 132 may be respectively disposed on the third and fourth surfaces of the body to contact the first inner electrode 121 and the second inner electrode 122, respectively.

[0058] Figures 1 to 5 A multilayer ceramic capacitor according to an embodiment is shown. (Refer to...) Figures 1 to 5 In the multilayer ceramic capacitor 100 according to this embodiment, the first inner electrode 121 and the second inner electrode 122, stacked in the Z direction (thickness direction, first direction), can be exposed on the third surface S3 and the fourth surface S4 of the body 110, respectively. Additionally, the first outer electrode 131 and the second outer electrode 132 can be disposed on the third surface S3 and the fourth surface S4 of the body 110, respectively, to be connected to the first inner electrode 121 and the second inner electrode 122. When the multilayer ceramic capacitor according to this embodiment has the above structure, the multilayer ceramic capacitor has an appearance similar to that of a conventional MLCC.

[0059] In another embodiment of this disclosure, the first inner electrode and the second inner electrode may be configured to be exposed on the fifth and sixth surfaces of the body. The exposure of the first inner electrode and the second inner electrode on the fifth and sixth surfaces of the body means that the first inner electrode and the second inner electrode are stacked in the Z direction and exposed on the fifth and sixth surfaces of the body. In this case, the first outer electrode and the second outer electrode may be disposed on the fifth and sixth surfaces of the body, respectively. The first outer electrode and the second outer electrode may be disposed on the fifth and sixth surfaces of the body to contact the first inner electrode and the second inner electrode, respectively.

[0060] Figures 6 to 8 A multilayer ceramic capacitor according to an embodiment is shown. (Refer to...) Figures 6 to 8 In the multilayer ceramic capacitor 200 according to this embodiment, the first inner electrode 221 and the second inner electrode 222, stacked in the Z direction (thickness direction, first direction), can be exposed on the fifth surface S5 and the sixth surface S6 of the body 210, respectively. Furthermore, the first outer electrode 231 and the second outer electrode 232 can be respectively disposed on the fifth surface S5 and the sixth surface S6 of the body 210, such that the first outer electrode 231 and the second outer electrode 232 can be connected to the first inner electrode 221 and the second inner electrode 222, respectively. When the multilayer ceramic capacitor according to this embodiment has the above structure, the multilayer ceramic capacitor can have an appearance similar to that of a low-inductance chip capacitor (LICC).

[0061] In another embodiment of this disclosure, the multilayer ceramic capacitor may further include a third external electrode, and a first internal electrode may be exposed on a third or fourth surface of the body, and a second internal electrode may be exposed on a fifth and sixth surface of the body. In this case, the first external electrode may be disposed on the third surface of the body, the second external electrode may be disposed on the fourth surface of the body, and the third external electrode may be connected to the second internal electrode and may be disposed on the first, second, fifth, and sixth surfaces of the body.

[0062] Figures 9 to 14 A multilayer ceramic capacitor according to this embodiment is shown. (Refer to...) Figures 9 to 14In the multilayer ceramic capacitor 300 according to this embodiment, the first inner electrode 321 may be exposed on the third surface S3 or the fourth surface S4 of the body 310, and the second inner electrode 322 may be exposed on the fifth surface S5 and the sixth surface S6 of the body 310. Furthermore, the first outer electrode 331 and the second outer electrode 332 may be respectively disposed on the third surface S3 and the fourth surface S4 of the body 310 to connect to the first inner electrode 321. The third outer electrode 333 may be disposed on the first surface S1, the second surface S2, the fifth surface S5, and the sixth surface S6 of the body 310. In this case, the second inner electrode 322, which is disposed exposed on the fifth surface S5 and the sixth surface S6 of the body 310, may have the following characteristics: Figure 13 The shape shown can be, for example, a "+" shape.

[0063] like Figure 9 As shown, the third external electrode 333 can be disposed on the first surface S1, the second surface S2, the fifth surface S5, and the sixth surface S6 of the main body 310, as follows: Figure 10 As shown, the third external electrode 333 may include a break located on the first surface S1 and the second surface S2, or it may not be provided on the first surface S1 and the second surface S2 of the body 310, but is not limited thereto.

[0064] In the example, the multilayer ceramic capacitor may further include a third internal electrode. In this case, the first internal electrode may be configured to be exposed on a third surface of the body and in contact with a first external electrode, and the third internal electrode may be configured to be exposed on a fourth surface of the body and in contact with a second external electrode.

[0065] Reference Figures 9 to 14 In the above embodiments, the multilayer ceramic capacitor 310 may have a multilayer structure depending on the positions of the first internal electrode 321 and the third internal electrode 323. For example, the multilayer ceramic capacitor 310 according to this embodiment may have the following stacked structure: Figure 12 The plurality of first internal electrodes 321 and the plurality of second internal electrodes 322 shown are alternately stacked and as... Figure 13 The diagram shows a stacked structure of multiple second internal electrodes 322 and multiple third internal electrodes 323. In this case, the structure can be appropriately adjusted according to the intended use of the capacitor. Figure 12 The number of stacks in the structure and Figure 13 The number of stacks of the structure.

[0066] In the above embodiments, although Figure 12 The stacked structure of the first internal electrode 321 is disposed at the bottom. Figure 13 The stacked structure of the third internal electrode 323 is positioned on top, but conversely, Figure 12 The stacked structure of the first internal electrode 321 is disposed on top and Figure 13The stacked structure of the third inner electrode 323 is naturally included in the above example. When the multilayer ceramic capacitor according to this embodiment has the above structure, the multilayer ceramic capacitor may be a three-terminal capacitor, and one of the outer electrodes may be used as a ground electrode.

[0067] In another embodiment of this disclosure, the multilayer ceramic capacitor according to this disclosure further includes a third external electrode. A first internal electrode may be configured to expose the third and fourth surfaces of the body, and a second internal electrode may be configured to expose the fifth and sixth surfaces of the body. In this case, the first external electrode may be disposed on the third surface of the body, the second external electrode may be disposed on the fourth surface of the body, and the third external electrode may be connected to the second internal electrode and may be disposed on the first, second, fifth, and sixth surfaces of the body.

[0068] Figure 15 This is a cross-sectional view of a multilayer ceramic capacitor according to another embodiment. (Refer to...) Figure 15 The first inner electrode 421 may be exposed on the third surface S3 and the fourth surface S4 of the body, and may be in contact with the first outer electrode 431 and the second outer electrode 432. In addition, the second inner electrode 422 may be exposed on the fifth surface S5 and the sixth surface S6 of the body, and may be in contact with the third outer electrode 433.

[0069] When a multilayer ceramic capacitor includes a third inner electrode and a third outer electrode, the description of the third inner electrode and the third outer electrode will be omitted because their thickness and forming method are the same as those of the first inner electrode and the first outer electrode, as well as the second inner electrode and the second outer electrode.

[0070] Table 1 below shows the scattering coefficients (S21 parameters) based on the ratio a / b or the ratio c / d.

[0071] [Table 1]

[0072] S21[dB]@10MHz -41.66 -45.58 -49.41 -59.4 -67.85 -78.39 Reduction rate 0％ 9％ 19％ 43％ 63％ 88％

[0073] Referring to Table 1, when the ratio a / b or c / d is 1, it can be confirmed that the same result is obtained as without applying the compensation pattern, and the reduction rate increases as the ratio a / b or c / d decreases. Specifically, it can be confirmed that a sharp numerical change occurs when the ratio a / b or c / d is 0.667. Furthermore, it can be confirmed that a very high reduction rate occurs when the ratio a / b or c / d is 0.333. This is in Figure 16 The text further illustrates that, Figure 16 A graph showing the crosstalk level (S21 parameter) of a multilayer ceramic capacitor according to the present disclosure is displayed, representing the ratio of the edges in the length and / or width directions of the multilayer ceramic capacitor.

[0074] Based on Table 1 above, in the multilayer ceramic capacitor according to this disclosure, it can be confirmed that by using the second inner electrode as a compensation pattern, the influence of the edge field applied to the end of the inner electrode can be significantly reduced and the degradation of the electric field characteristics due to crosstalk can be prevented, and noise caused by unwanted electric field signals can be reduced.

[0075] As described above, embodiments of the present disclosure can prevent the degradation of electric field characteristics due to crosstalk.

[0076] According to another embodiment of this disclosure, the effect of the edge field applied to the end of the inner electrode can be minimized.

[0077] According to another embodiment of this disclosure, a multilayer ceramic capacitor capable of reducing noise caused by unwanted electric field signals can be provided.

[0078] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the invention as defined by the appended claims.

Claims

1. A multilayer ceramic capacitor, comprising: The body includes a dielectric layer and a first inner electrode and a second inner electrode having different sizes from each other, and the body has a first surface and a second surface opposite to each other in a stacking direction, a third surface and a fourth surface connected to the first surface and the second surface and opposite to each other, and a fifth surface and a sixth surface connected to the first surface and the second surface and connected to the third surface and the fourth surface and opposite to each other; as well as First external electrode and second external electrode Wherein, when the edge of the first inner electrode in the length direction is b and the edge of the second inner electrode in the length direction is a, the ratio a / b is 0.33 or greater and less than 1.0, where a > 0 and b > 0, and Wherein, the edge dimension of the first inner electrode near at least one of the fifth and sixth surfaces in the width direction is greater than the edge dimension of the second inner electrode near at least one of the fifth and sixth surfaces in the width direction.

2. A multilayer ceramic capacitor, comprising: The body includes a dielectric layer and a first inner electrode and a second inner electrode having different sizes from each other, and the body has a first surface and a second surface opposite to each other in a stacking direction, a third surface and a fourth surface connected to the first surface and the second surface and opposite to each other, and a fifth surface and a sixth surface connected to the first surface and the second surface and connected to the third surface and the fourth surface and opposite to each other; as well as First external electrode and second external electrode Wherein, when the edge of the first inner electrode in the length direction is b and the edge of the second inner electrode in the length direction is a, the ratio a / b is 0.33 or greater and less than 1.0, where a > 0 and b > 0, and The width of the first inner electrode is smaller than the width of the second inner electrode.

3. The multilayer ceramic capacitor according to any one of claims 1 and 2, wherein, It is 0.67 or less than a / b.

4. The multilayer ceramic capacitor according to any one of claims 1 and 2, wherein, The difference ba between edge b and edge a is 10µm or greater.

5. The multilayer ceramic capacitor according to any one of claims 1 and 2, wherein, When the edge of the first inner electrode near at least one of the fifth and sixth surfaces in the width direction is d and the edge of the second inner electrode near at least one of the fifth and sixth surfaces in the width direction is c, the ratio c / d is 0.33 or greater, where c > 0 and d > 0.

6. The multilayer ceramic capacitor according to any one of claims 1 and 2, wherein, The first internal electrode and the second internal electrode are respectively exposed on the fifth surface and the sixth surface of the body, and The first external electrode and the second external electrode are respectively disposed on the fifth surface and the sixth surface of the main body, so as to contact the first internal electrode and the second internal electrode respectively.

7. A multilayer ceramic capacitor, comprising: The body includes a dielectric layer and a first inner electrode and a second inner electrode having different sizes from each other, and the body has a first surface and a second surface opposite to each other in a stacking direction, a third surface and a fourth surface connected to the first surface and the second surface and opposite to each other, and a fifth surface and a sixth surface connected to the first surface and the second surface and connected to the third surface and the fourth surface and opposite to each other; as well as First external electrode and second external electrode Wherein, when the edge of the first inner electrode near at least one of the fifth and sixth surfaces in the width direction is d and the edge of the second inner electrode near at least one of the fifth and sixth surfaces in the width direction is c, the ratio c / d is 0.33 or greater and less than 1.0, where c > 0 and d > 0, and Wherein, the edge dimension of the first inner electrode in the length direction is greater than the edge dimension of the second inner electrode in the length direction.

8. A multilayer ceramic capacitor, comprising: The body includes a dielectric layer and a first inner electrode and a second inner electrode having different sizes from each other, and the body has a first surface and a second surface opposite to each other in a stacking direction, a third surface and a fourth surface connected to the first surface and the second surface and opposite to each other, and a fifth surface and a sixth surface connected to the first surface and the second surface and connected to the third surface and the fourth surface and opposite to each other; as well as First external electrode and second external electrode Wherein, when the edge of the first inner electrode near at least one of the fifth and sixth surfaces in the width direction is d and the edge of the second inner electrode near at least one of the fifth and sixth surfaces in the width direction is c, the ratio c / d is 0.33 or greater and less than 1.0, where c > 0 and d > 0, and The length of the first inner electrode is less than the length of the second inner electrode.

9. The multilayer ceramic capacitor according to any one of claims 7 and 8, wherein, It is less than c / d of 0.

67.

10. The multilayer ceramic capacitor according to any one of claims 7 and 8, wherein, The difference dc between edge d and edge c is 10µm or greater.

11. The multilayer ceramic capacitor according to any one of claims 1, 2, 7 and 8, wherein, The average thickness of the first inner electrode and the second inner electrode is 0.4 μm or less.

12. The multilayer ceramic capacitor according to any one of claims 1, 2, 7 and 8, wherein, The first internal electrode and the second internal electrode are respectively exposed on the third surface and the fourth surface of the body, and The first external electrode and the second external electrode are respectively disposed on the third surface and the fourth surface of the main body, so as to contact the first internal electrode and the second internal electrode respectively.

13. The multilayer ceramic capacitor according to any one of claims 1, 2, 7, and 8, wherein the multilayer ceramic capacitor further comprises a third external electrode. in, The first internal electrode is exposed on the third or fourth surface of the body. The second internal electrode is configured to be exposed to the fifth and sixth surfaces of the body. The first external electrode is disposed on the third surface of the main body. The second external electrode is disposed on the fourth surface of the main body, and The third external electrode is connected to the second internal electrode and is disposed on the first surface, the second surface, the fifth surface, and the sixth surface of the body.

14. The multilayer ceramic capacitor according to claim 13, wherein the multilayer ceramic capacitor further comprises a third internal electrode. in, The first inner electrode is exposed on the third surface of the body and is configured to contact the first outer electrode, and The third inner electrode is exposed on the fourth surface of the body and is configured to contact the second outer electrode.

15. The multilayer ceramic capacitor according to claim 8, wherein the multilayer ceramic capacitor further comprises a third external electrode. in, The first internal electrode is exposed on the third and fourth surfaces of the body. The second internal electrode is configured to be exposed to the fifth and sixth surfaces of the body. The first external electrode and the second external electrode are respectively disposed on the third surface and the fourth surface of the main body, and are connected to the first internal electrode. The third external electrode is connected to the second internal electrode and is disposed on the first surface, the second surface, the fifth surface, and the sixth surface of the body.

16. The multilayer ceramic capacitor according to any one of claims 7 and 8, wherein, When the edge of the first inner electrode in the length direction is b and the edge of the second inner electrode in the length direction is a, the ratio of a / b is 0.33 or greater, where a > 0 and b > 0.

17. A multilayer ceramic capacitor, comprising: The main body includes a first inner electrode and a second inner electrode having a different size from the first inner electrode, the first inner electrode and the second inner electrode being stacked along the thickness direction and a dielectric layer disposed between the first inner electrode and the second inner electrode; and A first external electrode connected to the first internal electrode and a second external electrode connected to the second internal electrode. Among them, the ratio of one or both of a / b and c / d is 0.33 or greater and less than 1.

0. in, 'a' is the shortest distance between the end of the second inner electrode and the end of the dielectric layer, taken in the length direction perpendicular to the thickness direction. b is the shortest distance between the end of the first inner electrode and the end of the dielectric layer, obtained along the length direction. c is the shortest distance between the end of the second inner electrode and the end of the dielectric layer, taken in the width direction perpendicular to the thickness direction and the length direction. d is the shortest distance between the end of the first inner electrode and the end of the dielectric layer, obtained in the width direction. Among them, all of a, b, c, and d are greater than zero, and Where c is less than d, and Where a is less than b.

18. A multilayer ceramic capacitor, comprising: The main body includes a first inner electrode and a second inner electrode having a different size from the first inner electrode, the first inner electrode and the second inner electrode being stacked along the thickness direction and a dielectric layer disposed between the first inner electrode and the second inner electrode; and A first external electrode connected to the first internal electrode and a second external electrode connected to the second internal electrode. Among them, the ratio of one or both of a / b and c / d is 0.33 or greater and less than 1.

0. in, 'a' is the shortest distance between the end of the second inner electrode and the end of the dielectric layer, taken in the length direction perpendicular to the thickness direction. b is the shortest distance between the end of the first inner electrode and the end of the dielectric layer, obtained along the length direction. c is the shortest distance between the end of the second inner electrode and the end of the dielectric layer, taken in the width direction perpendicular to the thickness direction and the length direction. d is the shortest distance between the end of the first inner electrode and the end of the dielectric layer, obtained in the width direction. Among them, all of a, b, c, and d are greater than zero, and Wherein, the width of the first inner electrode is smaller than the width of the second inner electrode. The length of the first inner electrode is less than the length of the second inner electrode.

19. The multilayer ceramic capacitor according to any one of claims 17 and 18, wherein, The average thickness of the first inner electrode and the second inner electrode is 0.4 μm or less.

20. The multilayer ceramic capacitor according to any one of claims 17 and 18, wherein, The ratio of one or both of a / b and c / d is in the range of 0.33 to 0.

67.

21. The multilayer ceramic capacitor according to any one of claims 17 and 18, wherein, One or both of ba and dc are 10 μm or larger.

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