Silicon-based pin diode planarization preparation method and silicon-based pin diode
By etching grooves on the passivation layer to prepare multiple cathode pads, the silicon-based PIN diode is planarized, solving the problem that vertical silicon-based PIN diodes cannot be stacked with other circuit components, thus achieving high-density integration and miniaturization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- THE 13TH RES INST OF CHINA ELECTRONICS TECH GRP CORP
- Filing Date
- 2022-10-12
- Publication Date
- 2026-07-31
AI Technical Summary
Existing silicon-based PIN diodes have a vertical structure, which cannot be stacked with other circuit components, resulting in large electronic device size and low integration, failing to meet the requirements of miniaturization and high integration of electronic devices.
By etching multiple grooves up to the N+ layer on the passivation layer, multiple cathode pads are fabricated, making multiple pads and anode pads on the same surface, thus realizing the planarization of silicon-based PIN diodes and supporting stacking integration with other circuit components.
It enables the planarization of silicon-based PIN diodes, supports high-density integration, reduces the size of electronic devices, and improves integration.
Smart Images
Figure CN115602539B_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of semiconductor technology, and in particular relates to a planar fabrication method for silicon-based PIN diodes and silicon-based PIN diodes. Background Technology
[0002] Silicon-based PIN diodes (PIN diodes) are characterized by high thermal conductivity and high voltage withstand capability, making them widely used in electronic devices. However, silicon-based PIN diodes have a vertical structure, meaning they are discrete devices and cannot be stacked with other circuit components. This limits the use of vertically structured silicon-based PIN diodes to hybrid integration processes, preventing monolithic integration. Consequently, devices using vertically structured silicon-based PIN diodes are larger and have lower integration density, failing to meet the miniaturization and high integration requirements of electronic devices. Therefore, there is an urgent need for a planar fabrication method for vertically structured silicon-based PIN diodes, enabling their application in high-density integration, reducing device size, and increasing integration density. Summary of the Invention
[0003] This application provides a planar fabrication method for silicon-based PIN diodes and a silicon-based PIN diode, enabling the planar silicon-based PIN diodes to be applied in high-density integration, reducing the size of electronic devices and improving integration.
[0004] This application is achieved through the following technical solution:
[0005] In a first aspect, embodiments of this application provide a planar fabrication method for a silicon-based PIN diode, comprising: P+ doping on the upper surface of a silicon wafer substrate to form a P+ layer with a first predetermined diameter; N+ doping on the lower surface of the silicon wafer substrate to form an N+ layer; etching an I layer, wherein the I layer is located between the P+ layer and the N+ layer, and retaining an I layer region with a second predetermined diameter below the P+ layer; the first predetermined diameter being larger than the second predetermined diameter; thinning the lower surface of the N+ layer to a predetermined thickness; fabricating a passivation layer on the upper surface of the N+ layer excluding the I layer region and the P+ layer region; fabricating an anode pad on the upper surface of the P+ layer; etching multiple grooves on the upper surface of the passivation layer down to the N+ layer, and fabricating multiple cathode pads based on the multiple grooves.
[0006] In one possible implementation of the first aspect, the anode pad is prepared on the upper surface of the P+ layer, comprising: performing gold plating on the upper surface of the P+ layer to form the anode pad; the corresponding first gold plating thickness is 1 to 5 μm.
[0007] In one possible implementation of the first aspect, multiple cathode pads are prepared based on multiple grooves, including: performing gold plating in the multiple grooves to form multiple cathode pads; the corresponding second gold plating thickness is 5 to 10 μm.
[0008] In one possible implementation of the first aspect, the lifetime of the injected carriers during P+ doping and N+ doping is less than or equal to 100 ns.
[0009] Secondly, embodiments of this application provide a silicon-based PIN diode, obtained by applying the silicon-based PIN diode planarization fabrication method as described in any of the first aspects; the silicon-based PIN diode includes: an N+ layer of a predetermined thickness; an I layer region of a second predetermined diameter disposed on the upper surface of the N+ layer; a P+ layer of a first predetermined diameter disposed on the upper surface of the I layer region; an anode pad disposed on the upper surface of the P+ layer; and a plurality of cathode pads, wherein a plurality of grooves are provided on the upper surface of the N+ layer, and each cathode pad is disposed in each groove.
[0010] In conjunction with the second aspect, in some possible implementations, the silicon-based PIN diode further includes: a passivation layer disposed on the upper surface of the N+ layer, excluding the I layer region, the P+ layer, and the region of multiple cathode pads; the thickness of the passivation layer is 0.5–2 μm.
[0011] In conjunction with the second aspect, in some possible implementations, the preset thickness is 100 μm, and the thickness of the I layer region is 3 to 5 μm.
[0012] In conjunction with the second aspect, in some possible implementations, the first preset diameter is larger than the second preset diameter; the first preset diameter is 50 to 100 μm.
[0013] In conjunction with the second aspect, in some possible implementations, the diameter of the anode pad is 5–50 μm.
[0014] In conjunction with the second aspect, in some possible implementations, the diameter of each groove is 50–100 μm.
[0015] It is understandable that the beneficial effects of the second aspect mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here.
[0016] The beneficial effects of the embodiments in this application compared with the prior art are:
[0017] The silicon-based PIN diode planarization fabrication method provided in this application involves etching multiple grooves up to the N+ layer on a passivation layer and fabricating multiple cathode pads based on these grooves. This allows the multiple cathode pads and anode pads to be on the same surface, thus planarizing the vertically structured silicon-based PIN diode. This planarized silicon-based PIN diode can be stacked with other circuit components, such as using a flip-chip bonding integration method. It can be applied to high-density integration fields, thereby enabling electronic devices using planarized silicon-based PIN diodes to reduce their size and increase their integration density.
[0018] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description
[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0020] Figure 1 This is a cross-sectional view of a silicon-based PIN diode provided in an embodiment of this application;
[0021] Figure 2 This is a top view of a silicon-based PIN diode provided in an embodiment of this application;
[0022] Figure 3 This application provides a planar fabrication method for silicon-based PIN diodes according to one embodiment. Detailed Implementation
[0023] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.
[0024] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.
[0025] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.
[0026] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."
[0027] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0028] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.
[0029] Furthermore, the term "multiple" mentioned in the embodiments of this application should be interpreted as two or more.
[0030] Figure 1 This is a cross-sectional view of a silicon-based PIN diode provided in an embodiment of this application. Figure 2 This is a top view of a silicon-based PIN diode provided in an embodiment of this application. Figure 1 As shown, this silicon-based PIN diode is obtained using a silicon-based PIN diode planarization fabrication method, including:
[0031] An N+ layer 1 of preset thickness; an I layer region 2 of second preset diameter, disposed on the upper surface of the N+ layer 1; a P+ layer 3 of first preset diameter, disposed on the upper surface of the I layer region 2; an anode pad 4, disposed on the upper surface of the P+ layer 3; and multiple cathode pads 5, wherein multiple grooves are provided on the upper surface of the N+ layer 1, and each cathode pad 5 is disposed in each groove.
[0032] Wherein, the first preset diameter is larger than the second preset diameter, and based on Figure 1 As shown, the projection area of layer P+3 in the vertical direction includes the projection area of layer I region 2 in the vertical direction.
[0033] Optionally, the above-described planarization fabrication method for silicon-based PIN diodes can be any of the planarization fabrication methods for silicon-based PIN diodes provided in any of the embodiments described later in this application.
[0034] For example, the preset thickness is 100 μm, and the thickness of layer I region 2 is 3–5 μm. The first preset diameter is larger than the second preset diameter, and the first preset diameter is 50–100 μm. The diameter of the anode pad 4 is 5–50 μm, and the diameter of each groove is 50–100 μm.
[0035] Optionally, the silicon-based PIN diode may further include: a passivation layer 6 disposed on the upper surface of the N+ layer 1, excluding the I layer region 2, the P+ layer 3 and the plurality of cathode pads 5; the thickness of the passivation layer 6 is 0.5 to 2 μm.
[0036] It should be noted that there are no specific limitations on the thickness and diameter mentioned above, and they can be set according to specific needs.
[0037] The following combination Figure 1 The planarization fabrication method of silicon-based PIN diodes according to embodiments of this application will be described in detail.
[0038] Figure 3 This application provides a planar fabrication method for a silicon-based PIN diode according to an embodiment. (Refer to...) Figure 3 The method is described in detail below:
[0039] Step 101: P+ doping is performed on the upper surface of the silicon wafer substrate to form a P+ layer with a first predetermined diameter.
[0040] Step 102: Perform N+ doping on the lower surface of the silicon wafer substrate to form an N+ layer.
[0041] Step 103: Etch the I layer, which is located between the P+ and N+ layers, and retain the I layer region with a second preset diameter under the P+ layer.
[0042] Steps 101 to 103 define the process for fabricating a PN junction based on a silicon wafer substrate. The first preset diameter is larger than the second preset diameter.
[0043] For example, P+ doping is performed on the upper surface of a silicon wafer substrate using carrier injection to obtain a P+ layer, which is the anode of the silicon-based PIN diode. The first predetermined diameter of the P+ layer can be 50–100 μm. N+ doping is performed on the lower surface of the silicon wafer substrate using carrier injection to obtain an N+ layer, which is the cathode of the silicon-based PIN diode. The carriers injected during P+ and N+ doping are different, and the lifetime of the carriers in both processes is less than or equal to 100 ns.
[0044] Optionally, an I layer exists between the P+ and N+ layers, where the I layer is an undoped region, and its thickness can be 3–5 μm. The I layer is etched to retain only the second, predetermined I layer region beneath the P+ layer, thereby reducing the junction capacitance of the final fabricated silicon-based PIN diode.
[0045] Step 104: Thin the lower surface of the N+ layer to the preset thickness.
[0046] For example, the preset thickness can be 100 μm. Thinning the N+ layer can reduce the forward voltage drop of the final silicon-based PIN diode and increase the current density.
[0047] Step 105: Prepare a passivation layer on the upper surface of the N+ layer, excluding the regions of the I layer and the P+ layer.
[0048] Optionally, a passivation layer can be prepared on the surface of the N+ layer, excluding the I-layer and P+ layer regions, using methods such as thermal oxidation growth or chemical deposition for protection. The thickness of the passivation layer is 0.5–2 μm.
[0049] Step 106: Prepare an anode pad on the upper surface of the P+ layer.
[0050] For example, step 106 may specifically include: performing gold plating on the upper surface of the P+ layer to form an anode pad. The corresponding first gold plating thickness is 1–5 μm.
[0051] Optionally, the diameter of the anode pad can be 5 to 50 μm.
[0052] Step 107: Etch multiple grooves on the upper surface of the passivation layer to the N+ layer, and fabricate multiple cathode pads based on the multiple grooves.
[0053] For example, multiple cathode pads can be fabricated based on multiple grooves, which may specifically include: performing gold plating within the multiple grooves to form multiple cathode pads. The corresponding second gold plating thickness is 5–10 μm.
[0054] Optionally, etching is performed on the upper surface of the passivation layer until the N+ layer is exposed, then etching is stopped to form multiple grooves. These grooves can be evenly distributed around the P+ layer, and the diameter of each groove can be 50–100 μm. Gold plating is then performed within each of these grooves to form multiple cathode pads, wherein the diameter of each cathode pad is larger than the diameter of the corresponding groove.
[0055] In practical applications, an 8-inch silicon wafer substrate is used, which can be used to fabricate multiple planar silicon-based PIN diodes on the same silicon wafer substrate. The silicon wafer substrate can be diced as needed, for example, according to the chip outline size, to finally obtain multiple independent planar silicon-based PIN diodes.
[0056] The silicon-based PIN diode planarization fabrication method provided in this application involves etching multiple grooves up to the N+ layer on a passivation layer and fabricating multiple cathode pads based on these grooves. This allows the multiple cathode pads and anode pads to be on the same surface, thus planarizing the vertically structured silicon-based PIN diode. This planarized silicon-based PIN diode can be stacked with other circuit components, such as using a flip-chip bonding integration method. It can be applied to high-density integration fields, thereby enabling electronic devices using planarized silicon-based PIN diodes to reduce their size and increase their integration density.
[0057] In one possible implementation, after steps 101-102 above, steps 104 and 106 can be executed directly, as well as the following steps:
[0058] Step 108: Etch multiple grooves into the N+ layer on the upper surface of the I layer located between the P+ layer and the N+ layer, and fabricate multiple cathode pads based on the multiple grooves.
[0059] Step 109: Prepare a passivation layer on the upper surface of layer I, excluding the bonding sites.
[0060] For example, the bonding locations described above are the locations of the anode pads and multiple cathode pads.
[0061] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.
[0062] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. A method for planarizing a silicon-based PIN diode, comprising: include: P+ doping is performed on the upper surface of a silicon wafer substrate to form a P+ layer with a first predetermined diameter; N+ doping is performed on the lower surface of the silicon wafer substrate to form an N+ layer; wherein the lifetime of injected carriers during the P+ and N+ doping processes is less than or equal to 100 ns; the I layer is etched, the I layer being located between the P+ layer and the N+ layer, and the I layer region with a second preset diameter under the P+ layer is retained; the first preset diameter is greater than the second preset diameter. The lower surface of the N+ layer is thinned to a preset thickness; A passivation layer is prepared on the upper surface of the N+ layer, excluding the regions of the I layer and the P+ layer. An anode pad is prepared on the upper surface of the P+ layer; Multiple grooves are etched onto the upper surface of the passivation layer to the N+ layer, and multiple cathode pads are fabricated based on the multiple grooves.
2. The planar fabrication method for silicon-based PIN diodes according to claim 1, characterized in that, The process of preparing an anode pad on the upper surface of the P+ layer includes: Gold plating is performed on the upper surface of the P+ layer to form an anode pad; the corresponding first gold plating thickness is 1~5μm.
3. The planar fabrication method for silicon-based PIN diodes according to claim 1, characterized in that, The process of fabricating multiple cathode pads based on the multiple grooves includes: Gold plating is performed in the multiple grooves to form multiple cathode pads; the corresponding second gold plating thickness is 5~10μm.
4. A silicon-based PIN diode, characterized in that, The silicon-based PIN diode is obtained by the planarization fabrication method according to any one of claims 1 to 3; the silicon-based PIN diode comprises: N+ layers with a preset thickness; A second preset diameter I layer region is disposed on the upper surface of the N+ layer; A P+ layer of a first preset diameter is disposed on the upper surface of the I layer region; An anode pad is disposed on the upper surface of the P+ layer; Multiple cathode pads are provided, and multiple grooves are provided on the upper surface of the N+ layer, with each cathode pad disposed in each of the grooves.
5. The silicon-based PIN diode according to claim 4, characterized in that, Also includes: A passivation layer is disposed on the upper surface of the N+ layer, excluding the I layer region, the P+ layer, and the region of the plurality of cathode pads; The thickness of the passivation layer is 0.5~2μm.
6. The silicon-based PIN diode according to claim 4, characterized in that, The preset thickness is 100 μm, and the thickness of the I layer region is 3~5 μm.
7. The silicon-based PIN diode according to claim 4, characterized in that, The first preset diameter is larger than the second preset diameter; the first preset diameter is 50~100μm.
8. The silicon-based PIN diode according to claim 4, characterized in that, The diameter of the anode pad is 5~50μm.
9. The silicon-based PIN diode according to claim 4, characterized in that, The diameter of each groove is 50~100μm.