Method for preparing double buried oxide silicon-on-insulator dsoi wafer

Abstract

The application discloses a double buried oxygen silicon-on-insulator (DSOI) wafer preparation method, which comprises the following steps: providing a plurality of original wafers; preparing a bottom wafer by using the original wafers; performing specified area P doping and metal deposition treatment on the bottom wafer to obtain an intermediate wafer with a PNP structure; performing thermal oxidation and hydrogen injection treatment on the original wafer to obtain a top wafer; and preparing a double buried oxygen silicon-on-insulator wafer with a floating body PNP structure by using the top wafer and the intermediate wafer with the PNP structure. The application can solve the problems of occupying on-chip area and wasting on-chip resources in traditional ESD protection in the prior art.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating silicon-on-insulator (DSOI) wafers with double buried oxide insulation. Background Technology

[0002] Electrostatic discharge (ESD) is the process by which two objects with different electrostatic potentials transfer charges and cancel out the potential difference due to direct contact or electrostatic induction. It is often accompanied by a strong spike current.

[0003] ESD commonly affects microelectronic devices (semiconductor devices) in two main ways: First, friction between the body and clothing during activity generates triboelectric charge. When the body comes into contact with ESD-sensitive components before releasing static electricity, this triboelectric charge can impact and damage the components. Second, charges generated during automated production processes can damage devices when discharged through low-resistance areas, or they can induce charge on the metal parts of ESD-sensitive devices, causing damage. Damage to components is often accompanied by thermal failure due to high heat from peak currents, or dielectric breakdown caused by high voltage induced by ESD. This process also generates large currents, leading to thermal failure. Therefore, ESD protection is essential in microelectronic devices.

[0004] Currently, traditional ESD protection needs to be deployed on the device layer, such as on the top silicon layer of double silicon on insulator (DSOI). In practice, it has been found that traditional ESD protection circuits occupy a significant amount of on-chip area, wasting on-chip resources. Summary of the Invention

[0005] This application provides a method for fabricating silicon-on-a-chip (DSOI) wafers with a floating PNP structure, which solves the problem that traditional ESD protection requires on-chip area and wastes on-chip resources in the prior art. This application achieves ESD protection by designing a floating PNP structure, thereby saving on-chip area while achieving ESD protection.

[0006] On one hand, this application provides a method for fabricating a silicon-on-insulator (DSOI) wafer with double buried oxide insulation through one embodiment of the application, the method comprising:

[0007] Provides multiple original wafers;

[0008] The underlying wafer is prepared using the original wafer;

[0009] The bottom wafer is subjected to P-doping and metal deposition in a designated area to obtain an intermediate wafer with a PNP structure.

[0010] The original wafer is subjected to thermal oxidation and hydrogen implantation to obtain the top layer wafer;

[0011] Using the top-layer wafer and the intermediate wafer with the PNP structure, a silicon-on-insulator (DSOI) wafer with a floating PNP structure is prepared.

[0012] Optionally, the step of preparing the underlying wafer using the original wafer includes:

[0013] A processed wafer is prepared using the original wafer;

[0014] The original wafer is bonded to the surface of the processed wafer to obtain a bonded wafer;

[0015] The bonded wafer is subjected to thermal oxidation to obtain the treated bottom wafer.

[0016] Optionally, the process of obtaining a processed wafer using the original wafer includes:

[0017] The original wafer is subjected to thermal oxidation and hydrogen implantation to obtain a first wafer;

[0018] The first wafer is flipped over and bonded to the original wafer to obtain a second wafer;

[0019] The excess upper layer wafer on the second wafer is cut off using a layer transfer process to obtain the cut processed wafer.

[0020] Optionally, the step of performing P-doping and metal deposition on the bottom wafer in a designated area to obtain an intermediate wafer with a PNP structure includes:

[0021] An etching mask is applied to the bottom wafer to obtain two voids on the bottom wafer;

[0022] Two voids on the bottom wafer are P-doped and N-region etched to obtain a doped wafer.

[0023] The doped wafer is etched with metal wiring regions to obtain an etched wafer with a PNP structure.

[0024] Metal deposition and metal contact line extraction are performed on the etched wafer with the PNP structure to obtain the intermediate wafer with the PNP structure.

[0025] Optionally, the step of fabricating a DSOI wafer with a floating PNP structure using the top-layer wafer and the intermediate wafer with the PNP structure includes:

[0026] The top wafer is flipped over and bonded to the middle wafer to obtain a bonded wafer;

[0027] The bonding wafer is subjected to layer transfer and etching deposition processes to obtain the DSOI wafer with the floating PNP structure.

[0028] Optionally, the step of performing layer transfer and etching deposition on the bonding wafer to obtain the DSOI wafer with the floating PNP structure includes:

[0029] The excess upper layer wafer on the bonding wafer is cut off using a layer transfer process to obtain the cut-off remaining wafer;

[0030] The top layer wafer and the intermediate layer wafer of the cut remaining wafer are etched to expose the first P-type metal via, the N-type metal via and the second P-type metal via on the cut remaining wafer;

[0031] Metal via deposition is performed on the first P-type metal via, the N-type metal via, and the second P-type metal via on the remaining wafer after dicing, thereby obtaining the DSOI wafer with the floating PNP structure.

[0032] Optionally, the DSOI wafer with the floating PNP structure is stacked sequentially from bottom to top as follows: a substrate, a second buried oxide layer BOX2, a second silicon film SOI2, a first buried oxide layer BOX1, and a first silicon film SOI1; wherein the substrate, the second buried oxide layer BOX2, and the second silicon film SOI2 are all provided for the bottom wafer, and the first buried oxide layer BOX1 and the first silicon film SOI1 are provided for the intermediate wafer and the top wafer.

[0033] Optionally, the floating PNP structure is disposed in the second layer of silicon film SOI2.

[0034] Optionally, the floating PNP structure allows for voltage clamping to achieve corresponding electrostatic discharge (ESD) protection.

[0035] Optionally, the DSOI wafer with a floating PNP structure supports bidirectional electrostatic discharge (ESD) protection.

[0036] Optionally, the ESD protection capability of the floating PNP structure is related to the size and doping concentration of the floating PNP structure.

[0037] Optionally, a DSOI device with a floating PNP structure is fabricated on the double buried oxide insulator silicon-on-displacement (DSOI) wafer with the floating PNP structure.

[0038] One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages: This application provides multiple raw wafers, uses the raw wafers to prepare a bottom wafer, performs P-doping and metal deposition on the bottom wafer in a specified area to obtain an intermediate wafer with a PNP structure; performs thermal oxidation and hydrogen implantation on the raw wafers to obtain a top wafer; and uses the top wafer and intermediate wafers to prepare a DSOI wafer with a floating PNP structure. This utilizes the floating PNP structure to achieve ESD protection, effectively solving the problems of occupying on-chip area and wasting on-chip resources caused by the traditional ESD protection settings at the device layer, thereby saving on-chip area and resources. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 It is a logic circuit deployment diagram for traditional ESD protection provided by existing technology.

[0041] Figure 2 This is a logic circuit deployment diagram for ESD protection provided in an embodiment of this application.

[0042] Figure 3 This is a schematic diagram of the snapback curve corresponding to a PNP structure provided in an embodiment of this application.

[0043] Figure 4 This application provides a method for fabricating a DSOI wafer with a floating PNP structure.

[0044] Figure 5 This is a schematic diagram of the fabrication process of a DSOI wafer with a floating PNP structure in a second layer of silicon film SOI2, provided in an embodiment of this application.

[0045] Figure 6 This is a schematic diagram of a simulated PNP structure provided in an embodiment of this application.

[0046] Figure 7 This is a schematic diagram of a simulated floating body PNP structure provided in an embodiment of this application.

[0047] Figure 8 This is a schematic diagram of a transfer characteristic curve and two key voltages versus the P-doping width provided in an embodiment of this application.

[0048] Figure 9 This is a schematic diagram of a transfer characteristic curve and the variation curves of two key voltages and N-doping width provided in the embodiments of this application.

[0049] Figure 10 This is a schematic diagram of a transfer characteristic curve and two key voltages versus the thickness of the second silicon film, provided in an embodiment of this application.

[0050] Figure 11 This is a schematic diagram of a transfer characteristic curve and two key voltages versus the P doping concentration in the second silicon film, provided in an embodiment of this application.

[0051] Figure 12 This is a schematic diagram of the transfer characteristic curve of a PNP structure under the action of positive and negative pulse signals provided in the embodiments of this application. Detailed Implementation

[0052] During the process of filing this application, it was discovered that: dual buried oxide DSOIs have independent back-gate adjustment capability, which can suppress threshold voltage drift caused by the total dose effect (such as the threshold voltage V of N-channel devices under irradiation conditions). th (Reduces) However, when other devices that do not require threshold voltage adjustment, such as capacitors, resistors, diodes, and bipolar transistors, are placed on the top silicon layer, the second silicon layer loses its function. Furthermore, it is understood that the current principle for achieving ESD protection using PNP structures is the snapback phenomenon. This snapback phenomenon specifically refers to the voltage clamping phenomenon that occurs in PNP bipolar transistors under the action of pulse current, and its corresponding snapback curve is as follows: Figure 3 As shown, details will be provided below. Based on this, the applicant can utilize the area of ​​the second silicon film by modifying the existing DSOI process flow to add doping and metal wiring processes to the second silicon film, fabricating a PNP bipolar transistor structure in this area, and utilizing the snapback phenomenon to achieve ESD protection for the circuitry deployed on the top silicon film.

[0053] Please see Figure 1 This diagram illustrates a logic circuit design for a prior art on-chip PNP type ESD protection circuit. (Example:) Figure 1 The circuit diagram shown includes both ESD protection and protected circuits. Traditional ESD protection places both protection circuits on the same layer, specifically on the top silicon film of the device layer. This provides ESD protection for parallel circuits. When a high pulse current arrives, it flows into the low-resistance ESD circuit. When a large amount of charge accumulates on the drain side (where the PNP device receives the current pulse), the voltage rises to V. t When the device gain is turned on, the drain voltage drops, charge is discharged, and the transfer characteristic curve (I) d -Vd (curve) as Figure 3 The snapback curve shown can be used to measure the voltage signal of parallel logic and digital circuits at V when a pulse current is applied to the device. t The following measures are taken to protect digital and logic circuits from gate dielectric damage.

[0054] Based on the fundamental principles of traditional ESD protection, please refer to Figure 2 This document illustrates a logic circuit diagram of an on-chip PNP type ESD protection circuit design provided in an embodiment of this application. Figure 2 The circuit shown includes an ESD protection layer and a protected circuit layer. From the perspective of the device's operating logic circuit diagram, there is no difference. However, this application changes the traditional on-layer relationship between the ESD protection circuit and the protected circuit by deploying the ESD protection layer on the second silicon film of the DSOI wafer, and deploying the protected circuit layer on the top silicon layer of the DSOI wafer. Based on the DSOI process, a PNP structure is fabricated using the second silicon film (SOI2) of DSOI, achieving a voltage clamping effect similar to the traditional structure. Under the action of a large pulse current (e.g., a pulse current below 0.5A), the voltage of the parallel circuit can be clamped at V. t Within this range, the specific snapback curve corresponding to its PNP structure is as follows: Figure 3 As shown, it will not be elaborated further here.

[0055] Based on this, the embodiments of this application provide a method for fabricating DSOI wafers with a floating PNP structure, which solves the technical problems of traditional ESD deployment occupying on-chip area and wasting on-chip resources in the prior art.

[0056] The technical solution of this application embodiment is to solve the above-mentioned technical problems. The overall idea is as follows: providing multiple raw wafers; using the raw wafers to prepare a bottom wafer; performing P-doping and metal deposition treatment on the bottom wafer in a specified area to obtain an intermediate wafer with a PNP structure; performing thermal oxidation and hydrogen implantation treatment on the raw wafers to obtain a top wafer; using the top wafer and the intermediate wafer with the PNP structure to prepare a double buried oxide insulator-on-silicon (DSOI) wafer with a floating PNP structure.

[0057] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0058] First, it should be clarified that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0059] Please see Figure 4 This is a schematic flowchart of a DSOI wafer fabrication method with a floating PNP structure provided in an embodiment of this application. Figure 4 The method shown includes the following implementation steps:

[0060] S401 provides multiple original wafers 401.

[0061] S402. The underlying wafer 406 is prepared using the original wafer 401.

[0062] In one specific embodiment, please refer to Figure 5 A schematic flow chart of a DSOI wafer fabrication process with a floating PNP structure is shown. Figure 5 As shown, this application uses the original wafer 401 to prepare a processed wafer 404. Optionally, this application can perform thermal oxidation and hydrogen implantation on one of the original wafers 401 to obtain a first wafer 402; then, the first wafer 402 is flipped over and bonded to another original wafer 401 to form a second wafer 403. Subsequently, a layer transfer process (e.g., a Smartcut process) can be used to cut away the excess upper layer wafer on the second wafer 403 to obtain the cut processed wafer 404.

[0063] Further, a layer of the original wafer 401 is bonded or grown on the surface of the processed wafer 404 to obtain a bonded wafer 405; the bonded wafer 405 is subjected to thermal oxidation treatment to obtain the processed bottom wafer 406.

[0064] S403. Perform P-doping and metal deposition on the bottom wafer 406 in a designated area to obtain an intermediate wafer 410 with a PNP structure.

[0065] like Figure 5 As shown, in a specific embodiment, this application can perform an etching mask on the bottom wafer 406 to create a mask layer on its surface and etch two voids 407 on the bottom wafer 406. Further, the two voids on the bottom wafer are P-doped, for example, by implanting boron (B), and the N-region or N-contact is etched to obtain a doped wafer 408. Then, the doped wafer 408 is etched with metal wiring regions, i.e., metal wiring regions are etched on the doped wafer 408 to etch an etched wafer 409 with a PNP structure. Finally, metal deposition and metal contact line outlining are performed on the etched wafer to create metal line outlining points in the P, N, and P regions, i.e., outlining the P, N, and P metal contacts, thereby obtaining an intermediate wafer 410 with a PNP structure.

[0066] S404. The original wafer 401 is subjected to thermal oxidation and hydrogen injection treatment to obtain the top layer wafer 411.

[0067] S405. Using the top wafer 411 and the intermediate wafer 410 with the PNP structure, a DSOI wafer 414 with a floating PNP structure is prepared.

[0068] This application allows for the thermal oxidation and hydrogen implantation of another original wafer 401 to obtain a top layer wafer 411. The top layer wafer 411 is then flipped and bonded to the intermediate wafer 410 to obtain a bonded wafer 412. Further, a layer transfer process (e.g., Smartcut process) is used to cut away the excess upper layer wafer on the bonded wafer 412, resulting in a cut-off wafer 413. The top layer wafer and intermediate layer wafer (specifically, the top layer Si and the intermediate layer SiO2) are then etched to expose PNP vias, which can be referred to as a first P-type via, an N-type via, and a second P-type via, respectively. Finally, AI deposition is used to fill the vias, thereby fabricating a DSOI wafer 414 with an introduced floating PNP structure. This wafer 414 can be used to fabricate DSOI circuits on the top silicon layer, with the PNP-doped region of the second silicon film SOI2 used as an ESD protection circuit.

[0069] In an optional embodiment, this application can employ conventional DSOI fabrication processes to fabricate a corresponding DSOI device with a floating PNP structure on the DSOI wafer 414 with the floating PNP structure. Please refer to [link to relevant documentation]. Figure 6 and Figure 7 These are schematic diagrams of a simulated (traditional) PNP structure and a simulated floating PNP structure, respectively, as provided in the embodiments of this application. Figure 6 The simulated PNP structure shown includes, from bottom to top, a substrate (Sub) 601, a second buried oxide layer (BOX2) 602, a second silicon film (SOI2) 603, and a source 604, a gate 605, and a drain 606 formed on the second silicon film (SOI2).

[0070] like Figure 7 This diagram illustrates another method for fabricating a floating PNP structure on a second layer of silicon film SOI2 according to this application. Figure 7 The simulated floating PNP structure shown includes, from bottom to top, the following layers stacked sequentially: a substrate (Sub) 701, a second buried oxide layer BOX2 702, a second silicon insulated film SOI2 703, a first buried oxide layer BOX1 704, a first silicon insulated film SOI1 705, and a source 706, a gate 707, and a drain 708 formed on the first buried oxide layer 704 and the first silicon insulated film 705. Wherein... Figure 6 and Figure 7 As shown, P-doped and N-doped materials are implanted into the second silicon film SOI2 to form the corresponding PNP structure.

[0071] By implementing this application, we propose a method to achieve ESD protection by using a second layer of silicon film SOI2 prepared by DSOI process to prepare a floating PNP structure without occupying on-chip area. This method saves on-chip area and reduces the metal interconnect distance between the ESD protection circuit and the protected circuit, thereby improving the three-dimensional integration density.

[0072] To achieve the above objectives, this application also utilizes existing DSOI technology and a computer numerical simulation platform (Technology Computer Aided Design, TCAD) to verify, through simulation, the fabrication of a floating PNP structure on the second silicon film SOI2 in the DSOI wafer structure for ESD protection. The effects of different sizes and doping concentrations on ESD protection capability were compared, and the protection capability of the PNP structure against both positive and negative pulse currents was also verified. Please refer to [link to relevant documentation]. Figures 3-12 The legend shown is explained below. Figure 3 The snapback curve of the PNP structure shown is crucial for achieving ESD protection in this application. The snapback phenomenon includes two key voltages: clamping voltage V. t and holding voltage V hold To verify that a snapback phenomenon can occur in a floating PNP structure, this application can set... Figure 6 and Figure 7 Simulation experiments were conducted on the corresponding simulated PNP structure to obtain a similar result. Figure 3 The snapback curve shown.

[0073] To compare the critical voltage (V) under different sizes and doping conditions, as shown in Figure 3. t and V hold To achieve better ESD protection, this application explored PNP structures with different PNP structure sizes and P doping concentrations, and the simulated transfer characteristic curves (I... d -V d )like Figure 8-12 As shown. It should be noted that the initial set values ​​of the simulation control variables used in this application are as follows: W p =100nm, W n =150nm, P dop =1e20cm -3 Hsoi2 = 50nm. W p This refers to the width of region P, W n This refers to the width of region N, P dopHsoi2 refers to the P doping concentration, and Hsoi2 refers to the thickness of the second silicon film SOI2.

[0074] Please refer to Figure 8, which shows a snapback curve and V. t V hold With the P-doping width W p A schematic diagram of the change curve. (See example...) Figure 8 In the diagram, curve 1 represents W. p The first curve is the snapback curve for 150nm, and curve 2 represents W. p This is the snapback curve for 100nm, curve 3 represents W. p This is the snapback curve corresponding to 50nm. (From...) Figure 8 It can be seen that when the width of region P is W p When the clamping voltage V increases, t Decrease, maintain voltage V hold The difference between the two decreases; while when W... p When the size is reduced to 50nm, it can be seen that as the input current of the drain P region increases, a very frequent snapback phenomenon occurs. Considering that this will generate AC signals that interfere with the protected circuit, this application should avoid this situation in the size design.

[0075] like Figure 9 A snapback curve with V is shown. t V hold With N-doped width W n A schematic diagram of the change curve. (See example...) Figure 9 In the diagram, curve 1 represents W. n This is the snapback curve for 200nm, and curve 2 represents W. n This is the snapback curve for 150nm, curve 3 represents W. n This is the snapback curve corresponding to 100nm. (From...) Figure 9 It can be seen that when the width of region N is W n When the clamping voltage V increases, t It will increase, while maintaining voltage V hold It will not follow W n Change with change.

[0076] like Figure 10 A snapback curve with V is shown. t V hold A schematic diagram showing the variation of Hsoi2 with the thickness of the second silicon film SOI2. (See diagram for example.) Figure 10In the diagram, curve 1 represents the snapback curve for Hsoi2 at 150nm, curve 2 represents the snapback curve for Hsoi2 at 100nm, and curve 3 represents the snapback curve for Hsoi2 at 50nm. Figure 10 It can be seen that as the thickness Hsoi2 of the second silicon film SOI2 increases, the clamping voltage V... t Keep it unchanged, while maintaining the voltage V. hold The difference between the two increases and decreases.

[0077] like Figure 11 The snapback curve and V are shown without changing the N doping concentration in the second silicon film. t V hold A schematic diagram showing the change in P doping concentration in the second silicon film. (Example) Figure 11 In the diagram, curve 1 represents P. dop 1e20cm -3 The corresponding snapback curve, curve 2 represents P dop 1e19cm -3 The corresponding snapback curve, curve 3 represents P dop 1e18cm -3 The corresponding snapback curve. For example... Figure 11 It can be seen that when the thickness Hsoi2 of the second silicon film SOI2 increases, without changing the N doping concentration in the second silicon film, the clamping voltage V increases as the P doping concentration is changed from small to large. t First decrease, then increase, maintaining voltage V hold The voltage first decreases and then increases, while the difference between the two remains constant, and the range of the corresponding current values ​​increases. This is a relatively good trend for reducing the clamping voltage and maintaining voltage difference and increasing the withstand current range under the action of a large current pulse. From the above... Figures 8-11 As shown, the ESD protection capability of the PNP structure is related to the PNP structure size and the P doping concentration.

[0078] To verify that the floating PNP structure of this application possesses bidirectional ESD protection functionality, i.e., it can achieve ESD protection against both positive and negative pulse currents, +1A and -1A current pulse signals were input to the drain side of the floating PNP structure. The specific snapback curves under the action of positive and negative pulse signals can be found in [reference needed]. Figure 12 As shown, the PNP structure provides bidirectional protection. Figure 12 Curve 1 represents the snapback curve under a drain input of 1A, and curve 2 represents the snapback curve under a drain input of -1A.

[0079] The technical solutions in the embodiments of this application described above have at least the following technical effects or advantages compared to the prior art: Existing processes often utilize the area on the wafer that is on the same layer as the device to fabricate ESD protection circuits, occupying a large amount of on-chip area; while this application proposes a solution: based on DSOI wafer technology, local P-doping is performed on the second silicon film (N-doped) to form a PNP structure, realizing ESD protection for the circuit on the top silicon layer, greatly reducing the area occupied by ESD protection on the chip, saving on-chip area, and reducing the metal interconnect distance between the ESD protection circuit and the protected circuit, thereby improving the three-dimensional integration density. In addition, through simulation, this application also compares the influence of doping concentration and size process parameters on key electrical parameters of ESD protection, such as clamping voltage V. t and holding voltage V hold .

[0080] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0081] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A method for fabricating a silicon-on-insulator (DSOI) wafer with double buried oxide insulator, characterized in that, The method includes: Provides multiple original wafers; The underlying wafer is prepared using the original wafer; The bottom wafer is subjected to P-doping and metal deposition in a designated area to obtain an intermediate wafer with a PNP structure. The original wafer is subjected to thermal oxidation and hydrogen implantation to obtain the top layer wafer; Using the top-layer wafer and the intermediate wafer with the PNP structure, a double buried oxide insulator-on-silicon (DSOI) wafer with a floating PNP structure is prepared. The double buried oxide insulator silicon-on-insulator (DSOI) wafer with floating PNP structure is stacked from bottom to top as follows: substrate, second buried oxide layer BOX2, second silicon film SOI2, first buried oxide layer BOX1 and first silicon film SOI1. The floating PNP structure is disposed in the second silicon film SOI2, which allows voltage clamping and is used to achieve electrostatic discharge (ESD) protection; the first silicon film SOI1 is used to arrange the protected circuit and does not have an ESD protection structure. The process of preparing the underlying wafer using the original wafer includes: A processed wafer is prepared using the original wafer; The original wafer is bonded to the surface of the processed wafer to obtain a bonded wafer; The bonded wafer is subjected to thermal oxidation to obtain the treated bottom wafer; The process of obtaining a processed wafer using the original wafer includes: The original wafer is subjected to thermal oxidation and hydrogen implantation to obtain a first wafer; The first wafer is flipped over and bonded to the original wafer to obtain a second wafer; The excess upper layer wafer on the second wafer is cut off using a layer transfer process to obtain the cut processed wafer.

2. The method according to claim 1, characterized in that, The step of performing P-doping and metal deposition in a designated area on the bottom wafer to obtain an intermediate wafer with a PNP structure includes: An etching mask is applied to the bottom wafer to obtain two voids on the bottom wafer; Two voids on the bottom wafer are P-doped and N-region etched to obtain a doped wafer. The doped wafer is etched with metal wiring regions to obtain an etched wafer with a PNP structure. Metal deposition and metal contact line extraction are performed on the etched wafer with the PNP structure to obtain the intermediate wafer with the PNP structure.

3. The method according to claim 1, characterized in that, The process of fabricating a silicon-on-insulator (DSOI) wafer with a floating PNP structure using the top-layer wafer and the intermediate wafer with a PNP structure includes: The top wafer is flipped over and bonded to the middle wafer to obtain a bonded wafer; The bonded wafer is subjected to layer transfer and etching deposition processes to obtain the silicon-on-insulator (DSOI) wafer with a floating PNP structure.

4. The method according to claim 3, characterized in that, The process of performing layer transfer and etching deposition on the bonding wafer to obtain the silicon-on-insulator (DSOI) wafer with a floating PNP structure includes: The excess upper layer wafer on the bonding wafer is cut off using a layer transfer process to obtain the cut-off remaining wafer; The top layer wafer and the intermediate layer wafer of the cut remaining wafer are etched to expose the first P-type metal via, the N-type metal via and the second P-type metal via on the cut remaining wafer; Metal via deposition is performed on the first P-type metal via, the N-type metal via, and the second P-type metal via on the remaining wafer after dicing, thereby obtaining the DSOI wafer with the floating PNP structure.

5. The method according to any one of claims 1-4, characterized in that, The substrate, the second buried oxide layer BOX2, and the second silicon insulated film SOI2 are provided for the preparation of the bottom wafer, and the first buried oxide layer BOX1 and the first silicon insulated film SOI1 are provided for the preparation of the intermediate wafer and the top wafer.

6. The method according to any one of claims 1-4, characterized in that, The silicon-on-oxide (DSOI) wafer with a floating PNP structure supports bidirectional electrostatic discharge (ESD) protection.

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