Semiconductor device with mom capacitor and method of manufacturing the same

Abstract

This invention provides a semiconductor device with MOM capacitors and a method for fabricating the same. The method includes the following steps: providing a substrate; forming conductive plugs within the substrate; forming an insulating layer on the substrate; photolithographically etching the insulating layer to form a plurality of spaced-apart first trenches, the first trenches exposing the conductive plugs; filling the first trenches with a first metal layer, the first metal layer being electrically connected to the conductive plugs; removing the insulating layer located in the MOM capacitor region to form a plurality of second trenches located between the first metal layers, the second trenches exposing the substrate, the MOM capacitor region located on one side of the conductive plugs; forming a high-k dielectric layer extending outward from the bottom of the second trenches to the surface of the first metal layer and the conductive plugs; forming a second metal layer to fill the remaining space in the second trenches; and forming an electrical lead-out layer. This invention facilitates the fabrication of high-density, high-precision MOM capacitors, contributing to device miniaturization.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor device with MOM capacitors and its fabrication method. Background Technology

[0002] MOM capacitors (short for metal-oxide-metal), also known as finger capacitors, are capacitors formed by the oxide layer between two metal routes on the same metal layer. Limited by the feature size (metal CD) / overlay variability and space dimension of the metal layer, as well as the characteristics of low-K dielectric materials, MOM capacitors suffer from low density and poor precision, limiting their application to circuits with relatively low capacitance requirements. Currently, multi-layer MOM capacitors are typically stacked to increase capacitance density and reduce area, but this still falls short of meeting the demands of increasingly sophisticated device integration. Summary of the Invention

[0003] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor device with MOM capacitors and a method for fabricating the same, in order to solve the problems that the prior art generally increases capacitance density and reduces area by stacking multiple MOM capacitors, but still cannot meet the needs of the increasing integration of current devices.

[0004] To achieve the above and other related objectives, the present invention provides a method for fabricating a semiconductor device with a MOM capacitor, comprising the following steps:

[0005] A substrate is provided, and a conductive plug is formed within the substrate;

[0006] An insulating layer is formed on the substrate;

[0007] The insulating layer is photolithographically etched to form a plurality of spaced first trenches within the insulating layer, the first trenches exposing the conductive plug;

[0008] A first metal layer is filled into the first trench, and the first metal layer is electrically connected to the conductive plug.

[0009] The insulating layer located in the MOM capacitor region is removed to form a plurality of second trenches located between the first metal layers, the second trenches exposing the substrate, the MOM capacitor region being located on one side of the conductive plug;

[0010] A high-K dielectric layer is formed, which extends outward from the bottom of the second trench to the surface of the first metal layer and the conductive plug;

[0011] A second metal layer is formed, which fills the remaining space of the second trench. The high-k dielectric layer, together with the first and second metal layers located on both sides thereon, constitutes a MOM capacitor.

[0012] An electrical lead-out layer is formed, the electrical lead-out layer including a plurality of contact holes and a low-k dielectric layer located between the contact holes, and then a planarization process is performed to make the upper surfaces of the first metal layer, the second metal layer, the high-k dielectric layer and the conductive plug flush, the contact holes being electrically connected to the conductive plug, the first metal layer and the second metal layer.

[0013] Optionally, a transistor is formed within the substrate, and the conductive plug is electrically connected to the transistor.

[0014] Alternatively, the substrate includes a base layer and an interlayer dielectric layer located on the base layer, the source and drain electrodes of the transistor are located within the base layer, the gate of the transistor is located within the interlayer dielectric layer, and the conductive plug is electrically connected to the source and drain electrodes of the transistor and exposed upward on the surface of the interlayer dielectric layer.

[0015] Optionally, the high-K dielectric layer may be made of one or more of SiO2, Si3N4, and HfO2.

[0016] Optionally, the lateral dimension of the high-K dielectric layer located between the first metal layer and the second metal layer is 1 nm to 100 nm.

[0017] Optionally, the step of forming the first metal layer includes:

[0018] A diffusion barrier layer is formed on the structural surface obtained after the formation of the first trench, the diffusion barrier layer extending from the bottom of the first trench to the surface of the insulating layer;

[0019] A metal seed layer is formed on the surface of the diffusion barrier layer;

[0020] An electroplated copper layer is formed on the surface of the metal seed layer, and the electroplated copper layer fills the first trench and extends outward;

[0021] A surface planarization process is performed to expose the insulating layer and conductive plug, so that the upper surface of the electroplated copper layer and the upper surface of the insulating layer are flush.

[0022] Optionally, the step of forming the second metal layer includes:

[0023] A diffusion barrier layer is formed on the surface of the high-k dielectric layer;

[0024] An electroplated copper layer is formed on the surface of the diffusion barrier layer, the electroplated copper layer fills the remaining space of the second trench and extends outward above the insulating layer and the conductive plug;

[0025] A surface planarization process is performed to expose the insulating layer and conductive plug, so that the upper surface of the electroplated copper layer and the upper surface of the insulating layer are flush.

[0026] The present invention also provides a semiconductor device having a MOM capacitor, comprising:

[0027] A substrate in which conductive plugs are formed;

[0028] Multiple MOM capacitors, wherein the MOM capacitors include a high-k dielectric layer and a first metal layer and a second metal layer located on both sides of the high-k dielectric, and the high-k dielectric layer extends from the side of the second metal layer to the bottom of the second metal layer in a U-shaped structure;

[0029] An electrical lead-out layer includes a plurality of contact holes and a low-k dielectric layer located between the contact holes, wherein the contact holes are electrically connected to the conductive plug, the first metal layer and the second metal layer.

[0030] Optionally, the semiconductor device further includes a transistor formed within the substrate and electrically connected to the conductive plug.

[0031] Optionally, the lateral dimension of the high-K dielectric layer located between the first metal layer and the second metal layer is 1 nm to 100 nm.

[0032] As described above, the semiconductor device with MOM capacitor and its fabrication method of the present invention have the following beneficial effects: The improved process and structural design of the present invention form the electrode metals (first metal layer and second metal layer) of the MOM capacitor in two steps, depositing a thinner high-k dielectric material as an insulating layer between the electrodes, shortening the distance between the two electrodes, and increasing the dielectric constant of the material between the electrodes, thereby forming a high-density, high-precision MOM capacitor. Compared with a single-layer conventional MOM capacitor structure of the same area, the MOM capacitor of the present invention doubles the electrode area, reduces the electrode distance by more than 90%, changes the dielectric between the electrodes from ULK (ultra-low K) to HK (high K), increases the dielectric constant by approximately 10 times, and has a capacitance density approximately 200 times that of a single-layer conventional MOM capacitor structure. Compared with the MIM capacitor structure, which also requires an additional mask, even when using a high-k material of the same thickness and K value as the dielectric material between the electrodes, the MOM capacitor of the present invention has a greater capacitance density than the MIM capacitor structure when the aspect ratio is greater than 1 (for example, when the aspect ratio is 3, its capacitance density is 3 times that of the MIM capacitor). This allows the size of the semiconductor device provided by the present invention to be further reduced. Attached Figure Description

[0033] Figure 1-10 The diagram shows the cross-sectional structure of a semiconductor device with MOM capacitor prepared according to the preparation method of the present invention at each step.

[0034] Component designation explanation

[0035] 11 Basal layer

[0036] 12 interlayer dielectric layer

[0037] 13 Conductive plugs

[0038] 14 Insulation layer

[0039] 15 First trench

[0040] 16 First metal layer

[0041] 17 Second trench

[0042] 18 High-K dielectric layer

[0043] 19 Second metal layer

[0044] 20 Contact Holes

[0045] 21 Low-K dielectric layer

[0046] 22 Photoresist layers

[0047] 231 Source / Drain Electrodes

[0048] 232 gate

[0049] 233 Side Wall

[0050] 24. Isolation Structure Detailed Implementation

[0051] The following specific examples illustrate the embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. For ease of explanation, when detailing the embodiments of the present invention, the cross-sectional views showing the device structure are partially enlarged, not according to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0052] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0053] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0054] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components related to the present invention and are not drawn according to the actual number, shape, and size of the components in the actual implementation. In the actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex. To keep the illustrations as concise as possible, not all structures are shown in the figures.

[0055] Traditional MOM capacitors suffer from drawbacks such as low density and poor precision, limiting their application to circuits with relatively low capacitance requirements. Currently, the common approach is to increase capacitance density and reduce area by stacking multiple layers of MOM capacitors, but this still falls short of meeting the demands of increasingly sophisticated device integration. In response, the inventors of this case have proposed an improved solution through extensive creative work over a long period.

[0056] Specifically, this invention proposes a method for fabricating a semiconductor device with MOM capacitors, comprising the following steps:

[0057] A substrate is provided, and a conductive plug 13 is formed within the substrate; a prefabricated structure may be formed within the substrate, such as... Figure 1As shown, a transistor is formed within the substrate, and the conductive plug 13 is electrically connected to the transistor. In a further example, the substrate includes a base layer 11 and an interlayer dielectric layer 12 located on the base layer 11. The base layer 11 includes, but is not limited to, a silicon layer, a germanium layer, a germanium-silicon layer, or other semiconductor material layers, and multiple isolation structures 24 may be formed within the base layer 11. The interlayer dielectric layer 12 (ILD) includes, but is not limited to, any one or both of silicon oxide and silicon nitride layers. The source / drain electrodes 231 of the transistor are located within the base layer 11, and the gate 232 of the transistor (e.g., a polysilicon gate) is located within the interlayer dielectric layer 12. Sidewalls 233 may also be formed on the side of the gate. The conductive plug 1313 is electrically connected to the source / drain electrodes of the transistor and is exposed upward on the surface of the interlayer dielectric layer 12. The conductive plug 13 includes, but is not limited to, copper pillars. The structure obtained after this step is as follows: Figure 1 As shown;

[0058] An insulating layer 14 is formed on the substrate. The insulating layer 14 includes, but is not limited to, one or a combination of silicon oxide and silicon nitride layers. The method for forming the insulating layer 14 includes, but is not limited to, vapor deposition. The thickness of the insulating layer 14 determines the plate height of the MOM capacitor and therefore needs to be set as required. The structure obtained after this step is as follows: Figure 2 As shown;

[0059] The insulating layer 14 is photolithographically etched to form a plurality (e.g., two or more) spaced first trenches 15 within the insulating layer 14, the first trenches 15 exposing the conductive plug 13; specifically, this step may include first forming a photoresist layer 22 on the insulating layer 14, and then exposing and developing the photoresist layer 22 to define the desired pattern (the resulting structure is as shown in the image). Figure 3 (As shown), then using the remaining photoresist as a mask, the insulating layer 14 is etched to obtain the result shown. Figure 4 The structure shown;

[0060] A first metal layer 16 is filled into the first trench 15, and the first metal layer 16 is electrically connected to the conductive plug 13. Specifically, this step may include: forming a diffusion barrier layer on the surface of the structure obtained after forming the first trench 15 using a vapor deposition process, including but not limited to a titanium nitride layer, the diffusion barrier layer extending upward from the bottom of the first trench 15 along the sidewall of the first trench 15 to the surface of the insulating layer 14 (or the diffusion barrier layer is located at the bottom, sidewall, and surface of the insulating layer 14 of the first trench 15); forming a metal seed layer, such as a copper seed layer, on the surface of the diffusion barrier layer using a sputtering process, including but not limited to a sputtering process; then forming an electroplated copper layer on the surface of the metal seed layer, the electroplated copper layer filling the first trench 15 and extending outward; performing surface planarization to expose the insulating layer 14 and the conductive plug 13, so that the upper surface of the electroplated copper layer is flush with the upper surface of the insulating layer 14 (i.e., the first metal layer 16 completely fills the first trench 15); the structure obtained after this step is as follows. Figure 5 As shown;

[0061] The insulating layer 14 located in the MOM capacitor region is removed to form a plurality of second trenches 17 located between the first metal layers 16, the second trenches 17 exposing the substrate, the MOM capacitor region being located on one side of the conductive plug 13; this step may include first forming a photoresist layer 22 on the surface of the conductive plug 13 as a protective layer (see reference). Figure 6 (As shown), then etching is performed to remove the insulating layer 14 located in the MOM capacitor region. The position and size of the MOM capacitor region can be defined as needed and are not specifically limited; the structure obtained after this step is as follows. Figure 7 As shown;

[0062] A high-k dielectric layer 18 is formed using processes including, but not limited to, vapor deposition. The high-k dielectric layer 18 extends outward from the bottom of the second trench 17 to the surface of the first metal layer 16 and the conductive plug 13. The resulting structure is as follows: Figure 8 As shown;

[0063] A second metal layer 19 is formed, filling the remaining space of the second trench 17. Afterwards, a planarization process is performed to make the upper surfaces of the first metal layer 16, the second metal layer 19, the high-K dielectric layer 18, and the conductive plug 13 flush. The high-K dielectric layer 18, together with the first metal layer 16 and the second metal layer 19 located on either side of it, constitutes a MOM capacitor. Due to the formation of multiple second grooves, the first metal layer, the high-K dielectric layer, and the second metal layer are alternately stacked in the lateral direction to form multiple MOM capacitors arranged laterally. Specifically, the second metal layer 19 is formed... The process for forming the second metal layer 19 can be the same as that for forming the first metal layer 16. For example, the steps for forming the second metal layer 19 may include: forming a diffusion barrier layer on the surface of the high-K dielectric layer 18; forming an electroplated copper layer on the surface of the diffusion barrier layer, the electroplated copper layer filling the remaining space of the second trench 17 and extending outward above the insulating layer 14 and the conductive plug 13; performing surface planarization to expose the insulating layer 14 and the conductive plug 13, so that the upper surface of the electroplated copper layer is flush with the upper surface of the insulating layer 14; the structure obtained after this step is as follows: Figure 9 As shown;

[0064] An electrical lead-out layer is formed, comprising a plurality of contact holes 20 and a low-k dielectric layer 21 located between the contact holes 20. The contact holes 20 are electrically connected to the conductive plug 13, the first metal layer 16, and the second metal layer 19. This step may specifically include: firstly, forming the low-k dielectric layer 21 on the surface of the structure obtained in the aforementioned step using a process including but not limited to vapor deposition; then, photolithographically etching the low-k dielectric layer 21 to form a plurality of through holes corresponding to the conductive plug 13, the first metal layer 16, and the second metal layer 19; and finally, filling the through holes with metal using a process including but not limited to sputtering to form the contact holes 20. The final structure is as follows: Figure 10 As shown.

[0065] Depending on the specific needs, transistors or other electrical connection structures can be formed on the electrical lead-out layer after its formation. Furthermore, in addition to the first metal layer 16 and the second metal layer 19, the semiconductor device with MOM capacitors may also include a third metal layer and even a fourth metal layer. These metal layers are separated by the high-k dielectric layer 18, forming a multilayer metal stack MOM capacitor combined with an HK dielectric, thereby further increasing the capacitance density.

[0066] As an example, the material of the high-K dielectric layer 18 includes, but is not limited to, one or more of SiO2 (porous silicon dioxide), Si3N4 (silicon nitride) and HfO2, and the lateral dimension of the high-K dielectric layer 18 located between the first metal layer 16 and the second metal layer 19 is preferably 1nm to 100nm (including the endpoint values; unless otherwise specified, all numerical ranges mentioned in this specification include the endpoint values), and more preferably 10 to 50nm.

[0067] The present invention also provides a semiconductor device with a MOM capacitor, which can be fabricated using any of the aforementioned methods; therefore, the foregoing content is incorporated herein by reference in its entirety. Specifically, the semiconductor device with a MOM capacitor includes:

[0068] A substrate in which a conductive plug 13 is formed;

[0069] Multiple MOM capacitors (e.g., two or more) are arranged in a horizontal direction. Each MOM capacitor includes a high-K dielectric layer 18 and a first metal layer 16 and a second metal layer 19 located on both sides of the high-K dielectric. The high-K dielectric layer 18 extends from the side of the second metal layer 19 to the bottom of the second metal layer 19 in a U-shaped structure (i.e., the side and bottom of the second metal layer 19 are covered by the high-K dielectric layer 18).

[0070] An electrical lead-out layer includes a plurality of contact holes 20 and a low-K dielectric layer 21 located between the contact holes 20. The contact holes 20 are electrically connected to the conductive plug 13, the first metal layer 16 and the second metal layer 19.

[0071] As an example, the semiconductor device further includes a transistor formed within the substrate and electrically connected to the conductive plug 13, or the semiconductor device may also have a transistor or other electrical connection structure connected to the electrical lead-out layer and / or the first metal layer 16 and / or the second metal layer 19.

[0072] The dielectric constant of the high-k dielectric layer 18 is greater than that of the low-k dielectric layer 21. The material of the high-k dielectric layer 18 includes, but is not limited to, one or more of SiO2 (porous silicon dioxide), Si3N4 (silicon nitride), and HfO2.

[0073] As an example, the lateral dimension of the high-K dielectric layer 18 located between the first metal layer 16 and the second metal layer 19 is 1 nm to 100 nm, preferably 10 to 50 nm.

[0074] The semiconductor device with MOM capacitor may also include a third metal layer or even a fourth metal layer, with each metal layer separated by the high-k dielectric layer 18, forming a multilayer metal stack MOM capacitor and HK dielectric combination scheme to further improve capacitance density.

[0075] For a more detailed description of the semiconductor device with MOM capacitor, please refer to the foregoing content, which will not be repeated for the sake of brevity.

[0076] In summary, this invention provides a semiconductor device with MOM capacitors and a method for fabricating the same. The fabrication method includes the following steps: providing a substrate and forming a conductive plug within the substrate; forming an insulating layer on the substrate; performing photolithography on the insulating layer to form a plurality of spaced first trenches within the insulating layer, the first trenches exposing the conductive plug; filling the first trenches with a first metal layer, the first metal layer being electrically connected to the conductive plug; removing the insulating layer located in the MOM capacitor region to form a plurality of second trenches located between the first metal layers, the second trenches exposing the substrate, the MOM capacitor region being located on one side of the conductive plug; forming a high-k dielectric layer, the high-k dielectric layer extending outward from the bottom of the second trench to the surface of the first metal layer and the conductive plug; forming a second metal layer, the second metal layer filling the remaining space of the second trench, the high-k dielectric layer and the first metal layer and second metal layer located on both sides thereon forming a MOM capacitor; forming an electrical lead-out layer, the electrical lead-out layer including a plurality of contact holes and a low-k dielectric layer located between the contact holes, the contact holes being electrically connected to the conductive plug, the first metal layer and the second metal layer. This invention, through an improved process and structural design, forms the electrode metals of a MOM capacitor (a first metal layer and a second metal layer) in two steps. A thinner high-k dielectric material is deposited as the insulating layer between the electrodes, shortening the distance between the two electrodes and increasing the dielectric constant of the material between the electrodes, thereby forming a high-density, high-precision MOM capacitor. Compared to a conventional single-layer MOM capacitor structure of the same area, the MOM capacitor of this invention doubles the electrode area, reduces the electrode distance by more than 90%, changes the dielectric between the electrodes from ULK (ultra-low k) to HK (high k), increases the dielectric constant by approximately 10 times, and achieves a capacitance density approximately 200 times that of a conventional single-layer MOM capacitor structure. Compared to MIM capacitor structures, which also require additional masks, even using the same thickness and k-value of high-k material as the dielectric material between the electrodes, the MOM capacitor of this invention has a higher capacitance density than the MIM capacitor structure when the aspect ratio is greater than 1. Therefore, this invention contributes to the further miniaturization of semiconductor devices. Thus, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0077] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method of fabricating a semiconductor device having a MOM capacitor, characterized by, Including the following steps: A substrate is provided, and a conductive plug is formed within the substrate; A transistor is formed in the substrate, and the conductive plug is electrically connected to the transistor. An insulating layer is formed on the substrate; The insulating layer is photolithographically etched to form a plurality of spaced first trenches within the insulating layer, the first trenches exposing the conductive plug; A first metal layer is filled into the first trench, and the first metal layer is electrically connected to the conductive plug. The insulating layer located in the MOM capacitor region is removed to form a plurality of second trenches located between the first metal layers, the second trenches exposing the substrate, the MOM capacitor region being located on one side of the conductive plug; A high-K dielectric layer is formed, which extends outward from the bottom of the second trench to the surface of the first metal layer and the conductive plug; A second metal layer is formed, which fills the remaining space of the second trench. Then, a planarization process is performed to make the upper surfaces of the first metal layer, the second metal layer, the high-K dielectric layer and the conductive plug flush. The high-K dielectric layer, together with the first metal layer and the second metal layer located on both sides thereon, constitutes a MOM capacitor. An electrical lead-out layer is formed, the electrical lead-out layer including a plurality of contact holes and a low-k dielectric layer located between the contact holes, the contact holes being electrically connected to the conductive plug, the first metal layer and the second metal layer; The step of forming the first metal layer includes: A diffusion barrier layer is formed on the structural surface obtained after the formation of the first trench, the diffusion barrier layer extending from the bottom of the first trench to the surface of the insulating layer; A metal seed layer is formed on the surface of the diffusion barrier layer; An electroplated copper layer is formed on the surface of the metal seed layer, and the electroplated copper layer fills the first trench and extends outward; A surface planarization process is performed to expose the insulating layer and the conductive plug, so that the upper surface of the electroplated copper layer and the upper surface of the insulating layer are flush. The steps for forming the second metal layer include: A diffusion barrier layer is formed on the surface of the high-k dielectric layer; An electroplated copper layer is formed on the surface of the diffusion barrier layer, the electroplated copper layer fills the remaining space of the second trench and extends outward above the insulating layer and the conductive plug; A surface planarization process is performed to expose the insulating layer and conductive plug, so that the upper surface of the electroplated copper layer and the upper surface of the insulating layer are flush.

2. The production method according to claim 1, characterized by, The substrate includes a base layer and an interlayer dielectric layer located on the base layer. The source and drain electrodes of the transistor are located in the base layer, and the gate electrode of the transistor is located in the interlayer dielectric layer. The conductive plug is electrically connected to the source and drain electrodes of the transistor and is exposed upward on the surface of the interlayer dielectric layer.

3. The preparation method according to claim 1, characterized in that, The high-K dielectric layer is made of one or more of SiO2, Si3N4, and HfO2.

4. The preparation method according to claim 1, characterized in that, The lateral dimension of the high-K dielectric layer located between the first metal layer and the second metal layer is 1nm~100nm.

5. A semiconductor device with MOM capacitors, characterized in that, The semiconductor device with MOM capacitance is prepared by the fabrication method according to any one of claims 1 to 4, comprising: A substrate in which conductive plugs are formed; Multiple MOM capacitors are arranged laterally. Each MOM capacitor includes a high-K dielectric layer and a first metal layer and a second metal layer located on both sides of the high-K dielectric. The high-K dielectric layer extends from the side of the second metal layer to the bottom of the second metal layer in a U-shaped structure. An electrical lead-out layer includes a plurality of contact holes and a low-k dielectric layer located between the contact holes, wherein the contact holes are electrically connected to the conductive plug, the first metal layer and the second metal layer.

6. The semiconductor device with MOM capacitor according to claim 5, characterized in that, The semiconductor device further includes a transistor formed within the substrate and electrically connected to the conductive plug.

7. The semiconductor device with MOM capacitor according to claim 5, characterized in that, The lateral dimension of the high-K dielectric layer located between the first metal layer and the second metal layer is 1nm~100nm.

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