Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, the method comprising: in a first device region and a second device region, removing channel stack layers on both sides of a dummy gate structure and a side wall as a mask to form a first recess in the channel stack layers; laterally etching a part of a sacrificial layer exposed by a side wall of the first recess in a direction parallel to a substrate and perpendicular to an extending direction of the dummy gate structure to form a second recess surrounded by adjacent channel layers and the remaining sacrificial layer, or a second recess surrounded by the substrate, the channel layers adjacent to the substrate, and the remaining sacrificial layer; forming an inner wall layer in the second recess; forming a first type source / drain doped layer in the first recess; removing the first type source / drain doped layer in the second device region to expose the first recess; forming a second type source / drain doped layer in the first recess of the second device region, the second type source / drain doped layer having a same conductive type of dopant ions as a channel of a second type transistor. The method simplifies process steps and accordingly reduces process cost.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration, and semiconductor process nodes are continuously shrinking in accordance with Moore's Law. Transistors, as the most basic semiconductor devices, are currently widely used. Therefore, as the component density and integration of semiconductor devices increase, the channel length of transistors must be continuously shortened to adapt to the shrinking process nodes.

[0003] To better adapt to the requirements of proportionally shrinking device dimensions, semiconductor technology has gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as gate-all-around (GAA) transistors. In a GAA transistor, the gate surrounds the channel area from all sides. Compared with planar transistors, GAA transistors have stronger control over the channel and can better suppress short-channel effects. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which helps to simplify process steps and reduce process costs.

[0005] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, on which one or more longitudinally stacked channel layers are formed, each channel layer including a sacrificial layer and a channel layer located on the sacrificial layer; forming a dummy gate structure on the substrate that spans the channel layers and covers a portion of the top and a portion of the sidewalls of the channel layers; the sidewalls of the dummy gate structure forming sidewalls; the substrate including a first device region for forming a first type transistor and a second device region for forming a second type transistor; in the first device region and the second device region, using the dummy gate structure and the sidewalls as masks, removing the channel layers on both sides of the dummy gate structure to form a first groove in the channel layers, the first groove exposing the top of the substrate; after forming the first groove, along a direction parallel to the substrate and perpendicular to the extension direction of the dummy gate structure... The process involves: 1) laterally etching a portion of the sacrificial layer exposed on the sidewall of the first groove to form a second groove surrounded by an adjacent channel layer and the remaining sacrificial layer; 2) forming a second groove surrounded by a substrate, a channel layer adjacent to the substrate, and the remaining sacrificial layer; 3) forming an inner wall layer in the second groove; 4) forming a first type source / drain doped layer in the first groove within the first and second device regions, wherein the conductivity type of the doped ions in the first type source / drain doped layer is the same as the channel conductivity type of the first type transistor; 5) removing the first type source / drain doped layer in the second device region to expose the first groove; 6) removing the first type source / drain doped layer in the second device region and forming a second type source / drain doped layer in the first groove of the second device region, wherein the conductivity type of the doped ions in the second type source / drain doped layer is the same as the channel conductivity type of the second type transistor.

[0006] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0007] This invention provides a method for forming a semiconductor structure. A first groove and a second groove are simultaneously formed in a first device region and a second device region. Positions for forming a first-type source / drain doped layer, a second-type source / drain doped layer, and an inner wall layer are defined. Then, the first-type source / drain doped layer and the inner wall layer are simultaneously formed in the first and second device regions. Next, the first-type source / drain doped layer in the second device region is removed, and then the second-type source / drain doped layer is formed in the second device region. Compared to the current method of first forming the inner wall layer and the first-type source / drain doped layer in the first device region, and then forming the inner wall layer and the second-type source / drain doped layer in the second device region, this invention forms the inner wall layer in both the first and second device regions in the same step, reducing the number of steps required to form the inner wall layer, thus simplifying the process and correspondingly reducing process costs.

[0008] In the optional solution, the step of forming the first groove in the channel stack includes: using the pseudo gate structure and sidewalls as masks, and employing a maskless etching process to etch away the channel stack on both sides of the pseudo gate structure; since the first groove is formed simultaneously in the first device region and the second device region, no additional photomask is required to block the second device region during the formation of the first groove, thereby saving photomasks and reducing process costs accordingly. Attached Figure Description

[0009] Figures 1 to 13 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0010] Currently, the number of process steps for forming the inner wall layer and source / drain doped layers in fully enclosed gate transistors still needs to be reduced. Specifically, in current fully enclosed gate transistors, the inner wall layer and first-type source / drain doped layer are first formed in the first device region, and then the inner wall layer and second-type source / drain doped layer are formed in the second device region. Therefore, the inner wall layer is formed in the first device region and the second device region in different steps, which increases the process steps for forming the inner wall layer and correspondingly increases the process cost.

[0011] To address the technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, on which one or more longitudinally stacked channel layers are formed, each channel layer including a sacrificial layer and a channel layer located on the sacrificial layer; forming a dummy gate structure on the substrate that spans the channel layers and covers a portion of the top and a portion of the sidewalls of the channel layers; the sidewalls of the dummy gate structure forming sidewalls; the substrate including a first device region for forming a first type transistor and a second device region for forming a second type transistor; in the first device region and the second device region, using the dummy gate structure and the sidewalls as masks, removing the channel layers on both sides of the dummy gate structure to form a first groove in the channel layers, the first groove exposing the top of the substrate; after forming the first groove, along a direction parallel to the substrate and perpendicular to the extension direction of the dummy gate structure... The first groove sidewall is etched upwards and laterally to expose a portion of the sacrificial layer, forming a second groove surrounded by an adjacent channel layer and the remaining sacrificial layer, or a second groove surrounded by a substrate, a channel layer adjacent to the substrate, and the remaining sacrificial layer; an inner wall layer is formed in the second groove; after forming the inner wall layer, a first type source / drain doped layer is formed in the first groove in the first device region and the second device region, wherein the conductivity type of the doped ions in the first type source / drain doped layer is the same as the channel conductivity type of the first type transistor; the first type source / drain doped layer in the second device region is removed to expose the first groove; after removing the first type source / drain doped layer in the second device region, a second type source / drain doped layer is formed in the first groove in the second device region, wherein the conductivity type of the doped ions in the second type source / drain doped layer is the same as the channel conductivity type of the second type transistor.

[0012] In this embodiment of the invention, a first groove and a second groove are simultaneously formed in a first device region and a second device region, defining the positions for forming a first type source / drain doped layer, a second type source / drain doped layer, and an inner wall layer. Then, the first type source / drain doped layer and the inner wall layer are simultaneously formed in the first device region and the second device region. Next, the first type source / drain doped layer in the second device region is removed, and then the second type source / drain doped layer is formed in the second device region. Compared with the current scheme of first forming the inner wall layer and the first type source / drain doped layer in the first device region, and then forming the inner wall layer and the second type source / drain doped layer in the second device region, this embodiment of the invention forms the inner wall layer in the first device region and the second device region in the same step, reducing the steps of forming the inner wall layer, that is, simplifying the process steps and correspondingly reducing the process cost.

[0013] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0014] Figures 1 to 13 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0015] refer to Figures 1 to 2 The substrate provides a substrate on which one or more longitudinally stacked channel stacks 104 are formed. Each channel stack 104 includes a sacrificial layer 103 and a channel layer 102 located on the sacrificial layer 103. A pseudo-gate structure 105 is formed on the substrate, which spans the channel stack 104 and covers a portion of the top and a portion of the sidewalls of the channel stack 104. The sidewalls of the pseudo-gate structure 105 are formed with sidewalls 107. The substrate includes a first device region 100A for forming a first type transistor and a second device region 100B for forming a second type transistor.

[0016] The substrate provides a process platform for forming gate-all-around (GAA) transistors.

[0017] In this embodiment, the substrate is a three-dimensional substrate, which includes a substrate 100 and a fin 101 protruding from the substrate 100.

[0018] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0019] In this embodiment, the fin 101 is made of the same material as the substrate 100, which is silicon. In other embodiments, the fin can also be made of semiconductor materials suitable for forming fins, such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, and the material of the fin can also be different from that of the substrate.

[0020] In this embodiment, the channel stack 104 is located on the top of the fin 101, and the extension direction of the channel stack 104 is the same as the extension direction of the fin 101.

[0021] In this embodiment, when there are multiple channel stacks 104, the stacking direction of the multiple stacked channel stacks 104 is perpendicular to the surface of the substrate 100. In this embodiment, there are two channel stacks 104. In other embodiments, the number of channel stacks 104 may be other numbers.

[0022] Each channel stack 104 includes a sacrificial layer 103 and a channel layer 102 located on the sacrificial layer 103. The channel stack 104 provides a process basis for the subsequent formation of the channel layer 102 with a spaced-out arrangement. Specifically, the sacrificial layer 103 supports the channel layer 102, thereby providing a process basis for the subsequent realization of the spaced-out arrangement of the channel layer 102, which provides a conductive channel that fully surrounds the gate transistor.

[0023] Correspondingly, when there are multiple channel layers 104, there are also multiple channel layers 102, and the multiple channel layers 102 are arranged at intervals. In this embodiment, there are two channel layers 102.

[0024] In this embodiment, the channel layer 102 is made of Si, and the sacrificial layer 103 is made of SiGe. During the subsequent removal of the sacrificial layer 103, the etching selectivity of SiGe and Si is relatively high. Therefore, by setting the material of the sacrificial layer 103 to SiGe and the material of the channel layer 102 to Si, the impact of the sacrificial layer 103 removal process on the channel layer 102 can be effectively reduced, thereby improving the quality of the channel layer 102 and thus contributing to improved device performance. In other embodiments, the channel layer may also be made of SiGe, and the sacrificial layer may also be made of Si.

[0025] In this embodiment, a pseudo-gate structure 105 is formed on the substrate 100, spanning the channel stack 104 and the fin 101. The pseudo-gate structure 105 covers part of the top and part of the sidewalls of the channel stack 104.

[0026] In this embodiment, the dummy gate structure 105 provides spatial location for the subsequent formation of the device gate structure. The dummy gate structure 105 includes a dummy gate layer, and the material of the dummy gate layer includes polysilicon.

[0027] In this embodiment, the step of forming the pseudo-gate structure 105 includes: forming a gate material layer (not shown) on the channel stack 104; forming a gate mask layer 106 on the gate material layer; using the gate mask layer 106 as a mask, removing the gate material layer exposed by the gate mask layer 106, and the remaining gate material layer on the channel stack 104 as the pseudo-gate structure 105.

[0028] The gate mask layer 106 is used as an etching mask when forming the dummy gate structure 105, and the gate mask layer 106 can also protect the top of the dummy gate structure 105 in subsequent processes.

[0029] In this embodiment, the material of the gate mask layer 106 is silicon nitride.

[0030] In this embodiment, before forming the pseudo-gate structure 105, the method for forming the semiconductor structure further includes forming a gate oxide layer (not shown) on the top surface of the channel stack 104.

[0031] The gate oxide layer is used to protect the channel stack 104. The gate oxide layer can also be used as a stop layer in the subsequent step of removing the dummy gate structure 105, which helps to reduce the damage to the channel stack 104 caused by the process of removing the dummy gate structure 105.

[0032] In this embodiment, the gate oxide layer is made of silicon oxide.

[0033] In this embodiment, the sidewalls of the pseudo-gate structure 105 are formed with sidewalls 107.

[0034] The sidewall 107 is used as an etching mask for subsequent etching processes to define the formation region of the source and drain doped layers. The sidewall 107 is also used to protect the sidewall of the dummy gate structure 105.

[0035] In this embodiment, the sidewall 107 is a single-layer structure, and the material of the sidewall 107 is silicon nitride. In other embodiments, the sidewall may be made of other materials, and the sidewall may also be a layered structure.

[0036] In this embodiment, the first device region 100A is used to form a first type transistor, and the second device region 100B is used to form a second type transistor. The first type transistor and the second type transistor have different channel conductivity types.

[0037] In this embodiment, the first type transistor is an NMOS transistor, and the second type transistor is a PMOS transistor. In other embodiments, the first type transistor is a PMOS transistor, and the second type transistor is an NMOS transistor.

[0038] refer to Figure 3In the first device region 100A and the second device region 100B, using the pseudo gate structure 105 and the sidewall 107 as masks, the channel stack 104 on both sides of the pseudo gate structure 105 is removed, and a first groove 111 is formed in the channel stack 104, with the first groove 111 exposing the top of the substrate.

[0039] The first groove 111 provides space for the subsequent formation of the first type source / drain doped layer and the second type source / drain doped layer.

[0040] Since the first groove 111 is formed simultaneously in the first device region 100A and the second device region 100B, the first groove 111 can be formed without using a photomask to block the second device region 100B, thereby saving the photomask and reducing the process cost accordingly.

[0041] In this embodiment, the step of forming the first groove 111 in the channel stack 104 includes: using the pseudo gate structure 105 and the sidewall 107 as a mask, and employing a maskless etching process to etch away the channel stack on both sides of the pseudo gate structure 105.

[0042] Specifically, the materials of the sidewall 107 and the gate mask layer 106 have an etching selectivity ratio with the material of the channel stack 104. Therefore, the pseudo gate structure 105 and the sidewall 107 are directly used as masks, and a maskless etching process is adopted to etch and remove the channel stack on both sides of the pseudo gate structure 105, thereby simplifying the process steps and reducing the process cost.

[0043] In this embodiment, the process of etching away the channel stacks on both sides of the pseudo gate structure 105 includes a dry etching process.

[0044] Specifically, the dry etching process is an anisotropic dry etching process. The anisotropic dry etching process has better profile control, which is beneficial to improving the profile quality of the first groove 111. Moreover, the dry etching process has high process controllability, which is beneficial to accurately control the depth of the first groove 111. In addition, by selecting anisotropic dry etching process, it is beneficial to achieve a higher etching selectivity, thereby reducing the probability of mis-etching other film layers.

[0045] refer to Figure 4 After forming the first groove 111, the exposed portion of the sacrificial layer 103 on the sidewall of the first groove 111 is laterally etched along a direction parallel to the substrate and perpendicular to the extension direction of the pseudo gate structure 105, forming a second groove 112 surrounded by the adjacent channel layer 102 and the remaining sacrificial layer 103, or a second groove 112 surrounded by the substrate, the channel layer 102 adjacent to the substrate, and the remaining sacrificial layer 103.

[0046] The second groove 112 provides space for the subsequent formation of the inner wall layer. After the formation of the first type source / drain doped layer, the second type source / drain doped layer, and the device gate structure at the location of the sacrificial layer 103, in the first device region, the inner wall layer is located between the first type source / drain doped layer and the device gate structure, and in the second device region, the inner wall layer is located between the second type source / drain doped layer and the device gate structure. The inner wall layer can isolate the first type source / drain doped layer and the device gate structure, as well as the second type source / drain doped layer and the device gate structure. This helps to increase the distance between the first type source / drain doped layer and the second type source / drain doped layer and the device gate structure, thereby helping to reduce the parasitic capacitance between the first type source / drain doped layer and the second type source / drain doped layer and the device gate structure.

[0047] In this embodiment, the process of laterally etching the exposed portion of the sacrificial layer 103 on the sidewall of the first groove 111 includes a wet etching process.

[0048] Wet etching is an isotropic etching process, which allows the sacrificial layer 103 to be etched along a direction parallel to the substrate and perpendicular to the extension direction of the pseudo gate structure 105. Wet etching is also easy to achieve a large etching selectivity, which helps to reduce the difficulty of etching the sacrificial layer 103 and reduce the probability of damage to other film structures.

[0049] In this embodiment, the sacrificial layer 103 is made of SiGe, and the channel layer 102 is made of Si. The exposed sacrificial layer 103 is wet-etched using HCl vapor. The etching rate of HCl vapor on SiGe is much higher than that on Si. Therefore, using HCl vapor to etch the exposed portion of the sacrificial layer 103 on the sidewall of the first groove 111 can effectively reduce the probability of damage to the channel layer 102.

[0050] In other embodiments, when the channel layer material is SiGe and the sacrificial layer material is Si, the etching solution used in the wet etching process is tetramethylammonium hydroxide (TMAH) solution. The etching rate of TMAH solution on Si material differs significantly from that on SiGe material; therefore, using TMAH solution to etch the sacrificial layer can effectively reduce the probability of channel layer damage.

[0051] It should be noted that the lateral dimension of the second groove 112 should not be too large or too small. If the lateral dimension of the second groove 112 is too large, the remaining sacrificial layer 103 will occupy too little space, resulting in a decrease in the control capability of the device gate structure formed at the location of the remaining sacrificial layer 103 over the channel, thereby affecting the structural performance of the semiconductor. If the lateral dimension of the second groove 112 is too small, the size of the subsequently formed inner wall layer will be too small, reducing the non-isolation effect of the inner layer on the subsequently formed source / drain doped layers and device gate structure, thereby affecting the structural performance of the semiconductor. Therefore, in this embodiment, the lateral direction is defined as the direction parallel to the substrate and perpendicular to the extension direction of the dummy gate structure 105, and the lateral dimension of the second groove 112 is 2 nanometers to 8 nanometers. For example, the lateral dimension of the second groove 112 is 5 nanometers.

[0052] refer to Figures 5 to 6 An inner wall layer 113 is formed in the second groove 112.

[0053] The inner wall layer 113 can isolate the first type source / drain doped layer and the device gate structure, as well as the second type source / drain doped layer and the device gate structure, which helps to increase the distance between the first type source / drain doped layer and the second type source / drain doped layer and the device gate structure, thereby helping to reduce the parasitic capacitance between the first type source / drain doped layer and the second type source / drain doped layer and the device gate structure.

[0054] It should be noted that in this embodiment, an inner wall layer 113 is formed in the first device region 100A and the second device region 100B in the same step, which reduces the steps of forming the inner wall layer 113, that is, simplifies the process steps and correspondingly reduces the process cost.

[0055] In this embodiment, the step of forming the inner wall layer 113 in the second groove 112 includes: forming an inner wall material layer 160 on the sidewall of the exposed channel stack 104, the sidewall and top of the pseudo-gate structure 105, and the bottom of the first groove 111, and the inner wall material layer 160 also fills the second groove 112; removing the inner wall material layer 160 from the sidewall and top of the pseudo-gate structure 105, and the sidewall and bottom of the first groove 111, and retaining the remaining inner wall material layer 160 in the second groove 112 as the inner wall layer 113.

[0056] The process for forming the inner wall material layer 160 includes atomic layer deposition (ALD) or chemical vapor deposition (CVD), thereby enabling the inner wall material layer 160 to fill the second groove 112 and providing conformal coverage. In this embodiment, the process for forming the inner wall material layer 160 includes atomic layer deposition (ALD).

[0057] In this embodiment, a dry etching process (e.g., anisotropic dry etching process) is used to remove the inner wall material layer 160 of the sidewalls and top of the dummy gate structure 105, and the sidewalls and bottom of the first groove 111. The anisotropic dry etching process has the characteristics of anisotropic etching, and its longitudinal etching rate is much greater than its transverse etching rate. Therefore, during the removal of the inner wall material layer 160 of the sidewalls and top of the dummy gate structure 105, and the sidewalls and bottom of the first groove 111, the probability of transverse etching of the inner wall material layer 160 located in the second groove 112 is low, so that the inner wall material layer 160 located in the second groove 112 can be retained as the inner wall layer 113.

[0058] In this embodiment, the inner wall layer 113 is made of a dielectric material. The material of the inner wall layer 113 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material, or ultra-low-k dielectric material. In this embodiment, the material of the inner wall layer 113 is silicon nitride.

[0059] The dielectric constant k of the low-k dielectric material is between 2.55 and 3.9; the dielectric constant k of the ultra-low-k dielectric material is less than 2.55.

[0060] refer to Figure 7 After the inner wall layer 113 is formed, a first type source / drain doped layer 114 is formed in the first groove 111 in the first device region 100A and the second device region 100B. The conductivity type of the doped ions in the first type source / drain doped layer 114 is the same as the channel conductivity type of the first type transistor.

[0061] The first type source / drain doped layer 114 is used as the source or drain region of a first type transistor.

[0062] In this embodiment, the first type transistor is an NMOS transistor, and the conductivity type of the doped ions in the first type source / drain doped layer 114 is N-type ions. In other embodiments, when the first type transistor is a PMOS transistor, the conductivity type of the doped ions in the second type source / drain doped layer is P-type ions.

[0063] In this embodiment, the process of forming a first type source / drain doped layer 114 in the first groove 111 in the first device region 100A and the second device region 100B includes an epitaxial process.

[0064] Specifically, a semiconductor layer is formed in the first groove 111 by epitaxial growth, and during the formation of the semiconductor layer, N-type ions are self-doped in situ to form a first type source / drain doped layer 114.

[0065] In this embodiment, the first device region 100A is used to form an NMOS transistor. The first type source / drain doped layer 114 is a semiconductor layer doped with N-type ions. The semiconductor layer material can be SiP or SiC, and the N-type ions can be P ions, As ions, or Sb ions. By doping the semiconductor layer with N-type ions, the N-type ions replace the positions of silicon atoms in the crystal lattice. The more N-type ions incorporated, the higher the majority carrier concentration, and the stronger the conductivity. As an example, the material of the first type source / drain doped layer 114 is SiP.

[0066] refer to Figures 8 to 10 In the first device region 100A, a protective layer 115 is formed to conformally cover the top and sidewalls of the first type source / drain doped layer 114, the top and sidewalls of the sidewall 107, and the top of the pseudo gate structure 105.

[0067] The protective layer 115 provides protection for the first type source / drain doped layer 114 in the first device region 100A during the subsequent removal of the first type source / drain doped layer 114 in the second device region 100B.

[0068] In this embodiment, the step of forming the protective layer 115 includes: as follows Figure 8 As shown, in the first device region 100A and the second device region 100B, a protective material layer 160 is formed to conformally cover the top and sidewalls of the first type source / drain doped layer 114, the top and sidewalls of the sidewall 107, and the top of the dummy gate structure 105; as Figures 9 to 10 As shown, after removing the protective material layer 160 of the second device region 100B, the remaining protective material layer 160 in the first device region 100A serves as the protective layer 115.

[0069] In this embodiment, the 160 process for forming the protective material layer includes atomic layer deposition.

[0070] The atomic layer deposition process involves multiple atomic layer deposition cycles, exhibiting good step-fill performance. This improves the thickness uniformity of the protective material layer 160 and ensures that the protective material layer 160 conformally covers the top and sidewalls of the type-1 source / drain doped layer 114, the top and sidewalls of the sidewall 107, and the top of the pseudo-gate structure 105. In other embodiments, the protective material layer 160 can also be formed using chemical vapor deposition (CVD).

[0071] It should be noted that the thickness of the protective layer 115 should not be too large or too small. If the thickness of the protective layer 115 is too large, the thickness of the protective material layer 160 will be too large, increasing the difficulty of removing the protective material layer 160 of the second device region 100B, thereby increasing the probability of damage to the films located below the protective material layer 160 in the second device region 100B. If the thickness of the protective layer 115 is too small, the protective effect of the protective layer 115 on the films in the first device region 100A will decrease during the subsequent removal of the first type source / drain doped layer 114 of the second device region 100B, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the protective layer 115 is 2 nanometers to 20 nanometers in the step of forming the protective layer 115.

[0072] Correspondingly, the thickness of the protective material layer 160 is 2 nanometers to 20 nanometers.

[0073] In this embodiment, the material of the protective layer 115 in the step of forming the protective layer 115 includes one or more of silicon nitride, silicon carbide, silicon oxide and silicon carbonitride.

[0074] The materials silicon nitride, silicon carbide, silicon oxide, and silicon carbonitride are harder than the material of the first type source / drain doped layer 114. Therefore, during the subsequent removal of the first type source / drain doped layer 114 in the second device region 100B, the protective layer 115 in the first device region 100A can provide protection for the layers beneath it. As an example, the material of the protective layer 160 includes silicon nitride.

[0075] refer to Figures 9 to 10 The step of removing the protective material layer 160 of the second device region 100B includes: forming a masking layer 116 on top of the protective material layer 160, the masking layer 116 being located on top of the protective material layer 160 in the first device region 100A; using the masking layer 116 as a mask, etching away the exposed protective material layer 160 in the second device region 100B, and in the first device region 100A, the remaining protective material layer 160 serves as the protective layer 115.

[0076] In this embodiment, the material of the shielding layer 116 is photoresist.

[0077] In this embodiment, the process of etching away the protective material layer 160 exposed in the second device region 100B includes a dry etching process.

[0078] It should be noted that after removing the protective material layer 160 exposed in the second device region 100B, the process also includes removing the shielding layer 116 in the first device region 100A.

[0079] refer to Figure 11Remove the first type source / drain doped layer 114 in the second device region 100B to expose the first groove 111.

[0080] The exposed first groove 111 provides space for the subsequent formation of the second type source / drain doped layer in the second device region 100B.

[0081] In this embodiment, the process of removing the first type source / drain doped layer 114 in the second device region 100B includes a dry etching process.

[0082] Specifically, the dry etching process is an anisotropic dry etching process. The anisotropic dry etching process has better profile control, resulting in a higher profile formation quality for the exposed first groove 111, which is beneficial for the subsequent formation of a second type source / drain doped layer in the first groove 111 in the second device region 100B.

[0083] refer to Figure 12 In the second device region 100B, a portion of the channel layer 102 exposed on the sidewall of the first groove 111 is laterally etched along a direction parallel to the substrate and perpendicular to the extension direction of the pseudo gate structure 105, forming a third groove 118 surrounded by an adjacent inner wall layer 113 and the remaining channel layer 102, or a third groove 118 surrounded by a sidewall layer 107, an inner wall layer 113 adjacent to the sidewall layer 107, and the remaining channel layer 102.

[0084] The third groove 118 provides space for the subsequent formation of the second type source / drain doped layer. The subsequent second type source / drain doped layer will also be formed in the third groove 118, thereby providing greater stress to the channel layer 102 in the second device region 100B and increasing the carrier mobility in the channel layer 102.

[0085] In this embodiment, the process of laterally etching the exposed portion of the channel layer 102 on the sidewall of the first groove 111 includes a wet etching process.

[0086] Wet etching is an isotropic etching process, which enables the etching of the channel layer 102 in a direction parallel to the substrate and perpendicular to the extension direction of the pseudo gate structure 105. Wet etching is also easy to achieve a large etching selectivity, which helps to reduce the difficulty of etching the channel layer 102 and reduce the probability of damage to other film structures.

[0087] In this embodiment, the sacrificial layer 103 is made of SiGe, the channel layer 102 is made of Si, and the etching solution used in the wet etching process is tetramethylammonium hydroxide (TMAH) solution. The etching rate of TMAH solution on Si material differs significantly from that on SiGe material; therefore, using TMAH solution to etch the channel layer 102 can effectively reduce the probability of the sacrificial layer 103 being damaged.

[0088] It should be noted that the lateral dimension of the third groove 118 should not be too large or too small. If the lateral dimension of the third groove 118 is too large, the remaining space occupied by the channel layer 102 will be too small. This will not only result in the lateral dimension of the channel layer 102 subsequently covered by the device gate structure being too small, thus affecting the performance of the semiconductor structure, but also expose part of the top and sidewalls of the sacrificial layer 103. Consequently, this will cause the subsequently formed device gate structure to come into contact with the second type source / drain doped layer, greatly increasing the probability of a short circuit between the device gate structure and the second type source / drain doped layer, thus affecting the performance of the semiconductor structure. If the lateral dimension of the third groove 118 is too small, the distance between the subsequently formed second type source / drain doped layer and the device gate structure will be too large, resulting in a larger parasitic capacitance between the second type source / drain doped layer and the device gate structure, thus affecting the performance of the semiconductor structure. Therefore, in this embodiment, the lateral dimension of the third groove 118 is 2 nanometers to 10 nanometers, with the direction parallel to the substrate and perpendicular to the extension direction of the dummy gate structure 105 being the lateral direction. For example, the lateral dimension of the third groove 118 is 5 nanometers or 7 nanometers.

[0089] It should also be noted that in other embodiments, the third groove may not be formed, depending on the type and performance requirements of the second transistor.

[0090] refer to Figure 13 After removing the first type source / drain doped layer 114 in the second device region 100B, a second type source / drain doped layer 120 is formed in the first groove 111 of the second device region 100B. The conductivity type of the doped ions in the second type source / drain doped layer 120 is the same as the channel conductivity type of the second type transistor.

[0091] The second-type source / drain doped layer 120 is used as the source or drain region of a second-type transistor.

[0092] In this embodiment, the second-type transistor is a PMOS transistor, and the conductivity type of the doped ions in the second-type source / drain doped layer 120 is P-type. In other embodiments, when the second-type transistor is an NMOS transistor, the conductivity type of the doped ions in the second-type source / drain doped layer is N-type.

[0093] In this embodiment, the process of forming the second type source / drain doped layer 120 in the first groove 111 of the second device region 100B includes an epitaxial process.

[0094] Specifically, a semiconductor layer is formed in the first groove 111 by epitaxial growth, and in the process of forming the semiconductor layer, P-type ions are self-doped in situ to form a second type source / drain doped layer 120.

[0095] In this embodiment, the second device region 100B is used to form a PMOS transistor. The material of the second type source / drain doped layer 120 is a semiconductor layer doped with P-type ions. The semiconductor layer material can be Si or SiGe, and the P-type ions can be B ions, Ga ions, or In ions. By doping the semiconductor layer with P-type ions, the P-type ions replace the positions of silicon atoms in the crystal lattice. The more P-type ions incorporated, the higher the majority carrier concentration, and the stronger the conductivity. As an example, the material of the first type source / drain doped layer 120 is SiGeB.

[0096] In this embodiment, during the step of forming a second type source / drain doped layer 120 in the first groove 111 of the second device region 100B, the second type source / drain doped layer 120 is also filled in the third groove 118.

[0097] Specifically, the second device region 100B is a PMOS device region. Since the carrier mobility in the PMOS device region is low, a second type source / drain doped layer 120 is also formed in the third groove 118 to provide greater stress to the channel layer 102 in the second device region 100B and increase the carrier mobility in the channel layer 102.

[0098] It should be noted that in this embodiment, the protective layer 115 is an insulating material. Therefore, after the second type source / drain doped layer 120 is formed, the protective layer 115 is retained in the first device region 100A.

[0099] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided on which one or more longitudinally stacked channel stacks are formed, each channel stack including a sacrificial layer and a channel layer located on the sacrificial layer. A pseudo-gate structure is formed on the substrate, spanning the channel stacks and covering a portion of the top and a portion of the sidewalls of the channel stacks. The sidewalls of the pseudo-gate structure are formed with sidewalls. The substrate includes a first device region for forming a first type transistor and a second device region for forming a second type transistor, wherein the first type transistor is an NMOS transistor and the second type transistor is a PMOS transistor. In the first device region and the second device region, using the pseudo gate structure and sidewalls as masks, the channel stack on both sides of the pseudo gate structure is removed, and a first groove is simultaneously formed in the channel stack in the first device region and the second device region, with the first groove exposing the top of the substrate. After the first groove is formed, the portion of the sacrificial layer exposed on the sidewall of the first groove is laterally etched along a direction parallel to the substrate and perpendicular to the extension direction of the pseudo-gate structure. A second groove is simultaneously formed in the first device region and the second device region. The second groove is surrounded by the adjacent channel layer and the remaining sacrificial layer. Alternatively, the second groove is surrounded by the substrate, the channel layer adjacent to the substrate, and the remaining sacrificial layer. An inner wall layer is simultaneously formed in the second groove in the first device region and the second device region, and the material of the inner wall layer is a dielectric material. After the inner wall layer is formed, a first type source / drain doped layer is simultaneously formed in the first groove in the first device region and the second device region. The conductivity type of the doped ions in the first type source / drain doped layer is the same as the channel conductivity type of the first type transistor. Remove the first type source / drain doped layer in the second device region to expose the first groove; In the first device region and the second device region, after the first type source / drain doped layer is formed in the first groove and before the first type source / drain doped layer in the second device region is removed, the method further includes: forming a protective layer in the first device region that conformally covers the top and sidewalls of the first type source / drain doped layer, the top and sidewalls of the sidewalls, and the top of the pseudo-gate structure. After removing the first type source / drain doped layer in the second device region, a second type source / drain doped layer is formed in the first groove of the second device region. The conductivity type of the doped ions in the second type source / drain doped layer is the same as the channel conductivity type of the second type transistor. After removing the first type source / drain doped layer in the second device region, and before forming the second type source / drain doped layer in the first groove of the second device region, the method further includes: in the second device region, laterally etching a portion of the channel layer exposed on the sidewall of the first groove along a direction parallel to the substrate and perpendicular to the extension direction of the dummy gate structure to form a third groove surrounded by the adjacent inner wall layer and the remaining channel layer, or a third groove surrounded by the sidewall, the inner wall layer adjacent to the sidewall, and the remaining channel layer; in the step of forming the second type source / drain doped layer in the first groove of the second device region, the second type source / drain doped layer also fills the third groove.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming the protective layer includes: forming a protective material layer in the first device region and the second device region that conformally covers the top and sidewalls of the first type source / drain doped layer, the top and sidewalls of the sidewalls, and the top of the pseudo-gate structure; removing the protective material layer in the second device region; and in the first device region, the remaining protective material layer serves as the protective layer.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The process for forming the protective material layer includes atomic layer deposition.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming the inner wall layer in the second groove includes: forming an inner wall material layer on the exposed sidewall of the channel stack, the sidewall and top of the pseudo-gate structure, and the bottom of the first groove, the inner wall material layer also filling the second groove; removing the inner wall material layer from the sidewall and top of the pseudo-gate structure, and the sidewall and bottom of the first groove, and retaining the remaining inner wall material layer in the second groove as the inner wall layer.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The lateral etching process includes wet etching.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for removing the first type source / drain doped layer in the second device region includes a dry etching process.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming the first groove in the channel stack includes: using the pseudo-gate structure and sidewalls as masks, and employing a maskless etching process to etch away the channel stack on both sides of the pseudo-gate structure.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the first device region and the second device region, the process of forming a first type source / drain doped layer in the first groove includes an epitaxial process; The process of forming a second type source / drain doped layer in the first groove of the second device region includes an epitaxial process.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The lateral dimension of the second groove is 2 nanometers to 8 nanometers, which is a direction parallel to the substrate and perpendicular to the extension direction of the pseudo-gate structure.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The lateral dimension of the third groove is 2 nanometers to 10 nanometers, which is a direction parallel to the substrate and perpendicular to the extension direction of the pseudo-gate structure.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming the protective layer, the thickness of the protective layer is 2 nanometers to 20 nanometers.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming the protective layer, the material of the protective layer includes one or more of silicon nitride, silicon carbide, silicon oxide, and silicon carbonitride.

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