Semiconductor packaging structure

Abstract

This invention provides a semiconductor packaging structure that improves heat dissipation efficiency. In one embodiment, the semiconductor packaging structure provided by this invention may include: a base substrate; a first redistribution layer disposed on the base substrate; a semiconductor chip disposed on the first redistribution layer; and a silicon capacitor disposed below the first redistribution layer and electrically coupled to the semiconductor chip, wherein the silicon capacitor includes: a semiconductor substrate; and a plurality of capacitor cells embedded in the semiconductor substrate; the semiconductor packaging structure further includes: a first bump structure disposed between the silicon capacitor and the base substrate. In this embodiment, the semiconductor packaging structure can utilize the silicon capacitor disposed below the first redistribution layer and electrically coupled to the semiconductor chip and the first bump structure to transfer heat from the semiconductor chip, thereby improving the heat dissipation efficiency of the semiconductor packaging structure.

Description

Technical Field

[0001] This invention relates to semiconductor technology, and more particularly to a semiconductor package structure including a capacitor. Background Technology

[0002] Semiconductor packaging structures not only protect semiconductor dies from environmental contamination, but also provide electrical connections between the packaged semiconductor die and the substrate (e.g., a printed circuit board, PCB). Heat is generated during the operation of semiconductor dies. If this heat is not adequately dissipated, the elevated temperature can damage the semiconductor component. However, with the increasing demand for smaller devices capable of performing more functions, thermal management of semiconductor packages is becoming increasingly challenging.

[0003] Furthermore, decoupling capacitors are commonly used as temporary charge storage devices to prevent transient fluctuations in power supply voltage. These decoupling capacitors are increasingly important for reducing power supply noise during the operation of digital circuits, such as microprocessors, which have numerous transistors that alternate between on and off states. However, decoupling capacitors made of ceramic materials can impede heat conduction, thus degrading their thermal performance. Therefore, further improvements to semiconductor packaging structures are needed to enhance their thermal performance. Summary of the Invention

[0004] This invention provides a semiconductor packaging structure that can improve heat dissipation efficiency.

[0005] In one embodiment, the semiconductor packaging structure provided by the present invention may include: a base substrate; a first redistribution layer disposed on the base substrate; a semiconductor chip disposed on the first redistribution layer; and a silicon capacitor disposed below the first redistribution layer and electrically coupled to the semiconductor chip, wherein the silicon capacitor includes: a semiconductor substrate; and a plurality of capacitor cells embedded in the semiconductor substrate; the semiconductor packaging structure further includes: a first bump structure disposed between the silicon capacitor and the base substrate. In this embodiment, the semiconductor packaging structure can utilize the silicon capacitor disposed below the first redistribution layer and electrically coupled to the semiconductor chip and the first bump structure to transfer heat from the semiconductor chip, thereby improving the heat dissipation efficiency of the semiconductor packaging structure.

[0006] In another embodiment, the semiconductor packaging structure provided by the present invention may include: a first redistribution layer; a semiconductor chip disposed on the first redistribution layer; and a silicon capacitor disposed below the first redistribution layer and electrically coupled to the semiconductor chip through the first redistribution layer, wherein the silicon capacitor includes: a semiconductor substrate having a first surface and a second surface opposite thereto; a plurality of capacitor cells extending from the first surface of the semiconductor substrate to the second surface of the semiconductor substrate; a first bump structure disposed on the first surface of the semiconductor substrate and electrically coupled to the plurality of capacitor cells; and a second bump structure disposed on the second surface of the semiconductor substrate and electrically coupled to the first redistribution layer. In this embodiment, the semiconductor packaging structure can utilize the silicon capacitor disposed below the first redistribution layer and electrically coupled to the semiconductor chip to transfer heat from the semiconductor chip, thereby improving the heat dissipation efficiency of the semiconductor packaging structure.

[0007] In another embodiment, the semiconductor packaging structure provided by the present invention may include a first packaging structure, wherein the first packaging structure includes: a first redistribution layer; a semiconductor chip disposed on the first redistribution layer; a second redistribution layer disposed on the semiconductor chip; a silicon capacitor disposed below the first redistribution layer and electrically coupled to the semiconductor chip; and a bump structure disposed below the silicon capacitor. In this embodiment, the semiconductor packaging structure can utilize the silicon capacitor disposed below the first redistribution layer and electrically coupled to the semiconductor chip, and the bump structure, to transfer heat from the semiconductor chip, thereby improving the heat dissipation efficiency of the semiconductor packaging structure.

[0008] In summary, in the various embodiments of the present invention, the semiconductor packaging structure can utilize silicon capacitors and / or bump structures disposed below the first redistribution layer and electrically coupled to the semiconductor chip to transfer the heat of the semiconductor chip, thereby improving the heat dissipation efficiency of the semiconductor packaging structure. Attached Figure Description

[0009] Figure 1 This is a cross-sectional view of a semiconductor package structure 100 according to some embodiments of the present disclosure.

[0010] Figure 2 This is a cross-sectional view of a silicon capacitor 200 with a semiconductor package structure according to some embodiments of the present disclosure.

[0011] Figure 3 This is a cross-sectional view of a silicon capacitor 300 with a semiconductor package structure according to some embodiments of the present disclosure.

[0012] Figure 4 This is a cross-sectional view of a silicon capacitor 400 with a semiconductor package structure according to some embodiments of the present disclosure.

[0013] Figure 5This is a cross-sectional view of a silicon capacitor 500 with a semiconductor package structure according to some embodiments of the present disclosure.

[0014] Figure 6 This is a cross-sectional view of a silicon capacitor 600 with a semiconductor package structure according to some embodiments of the present disclosure. Detailed Implementation

[0015] The following description represents the best intended mode for carrying out the invention. These descriptions are intended to illustrate the general principles of the invention and should not be construed as limiting. The scope of the invention is best determined by referring to the appended claims.

[0016] The invention will be described with reference to specific embodiments and certain accompanying drawings, but is not limited thereto and is defined only by the scope of the claims. The described drawings are merely illustrative and not restrictive. In the drawings, the dimensions of some components may be exaggerated for illustrative purposes and are not drawn to scale. These dimensions and relative dimensions do not correspond to actual dimensions in the practice of the invention.

[0017] The present invention can add additional components to the following embodiments. For example, the description of "forming a first component on a second component" can include embodiments in which the first component and the second component are in direct contact, or embodiments in which an additional component is disposed between the first component and the second component so that the first component and the second component are not in direct contact. Furthermore, the spatial relative relationship between the first component and the second component can change as the device is operated or used in different directions.

[0018] In the following description, the phrase "first component extending through second component" can include embodiments in which the first component is disposed within the second component and extends from one side of the second component to the opposite side of the second component, wherein the surface of the first component may be flush with the surface of the second component, or the surface of the first component may be outside the surface of the second component. Furthermore, the same reference numerals and / or letter designations may be repeated in various embodiments of the invention. This repetition is for simplicity and clarity and does not in itself define a relationship between the various embodiments discussed.

[0019] A semiconductor package structure is described according to some embodiments of this disclosure. The semiconductor package structure includes a silicon capacitor to transfer heat from a semiconductor chip, thereby improving thermal performance. Furthermore, the semiconductor package structure includes bump structures electrically coupled to the silicon capacitor, which further enhances thermal performance.

[0020] Figure 1This is a cross-sectional view of a semiconductor package structure 100 according to some embodiments of the present disclosure. Additional features may be added to the semiconductor package structure 100. For different embodiments, some features described below may be replaced or eliminated. For simplicity, only a portion of the semiconductor package structure 100 is shown.

[0021] Reference Figure 1 According to some embodiments, the semiconductor package structure 100 includes a first package structure 100a and a second package structure 100b vertically stacked on a substrate 102. The substrate 102 can be a coreless / coreless substrate or a printed circuit board (PCB). The substrate 102 can be formed of polypropylene (PP), polyimide, BT / epoxy resin, prepreg, ABF, ceramic materials, or other suitable materials. Any desired semiconductor component can be formed in and on the substrate 102. However, for simplicity, only a flat substrate 102 is shown.

[0022] The first package structure 100a may have a front side and a back side opposite thereto. The first package structure 100a may have a first redistribution layer 104 on its front side and a second redistribution layer 116 on its back side. The first redistribution layer 104 and the second redistribution layer 116 may each include one or more conductive layers and passivation layers, wherein the conductive layers may be disposed within the passivation layers. The conductive layers may include metals, such as copper, titanium, tungsten, aluminum, etc., or combinations thereof. The passivation layers may include polymer layers, such as polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy resin, etc., or combinations thereof. Alternatively, the passivation layers may include dielectric layers, such as silicon oxide, silicon nitride, silicon oxynitride, etc., or combinations thereof.

[0023] like Figure 1 As shown, according to some embodiments, the first redistribution layer 104 includes more conductive and passivation layers than the second redistribution layer 116. Therefore, the first redistribution layer 104 may be thicker than the second redistribution layer 116, but the present invention is not limited thereto. For example, the second redistribution layer 116 may be thicker than the first redistribution layer 104, or substantially the same thickness as the first redistribution layer 104.

[0024] like Figure 1As shown, according to some embodiments, the first package structure 100a includes a plurality of conductive terminals 106 disposed beneath the first redistribution layer 104. The conductive terminals 106 can electrically couple the first redistribution layer 104 to the substrate 102. The conductive terminals 106 can be formed of a conductive material such as a metal or alloy. For example, the conductive terminals 106 can be formed of solder, copper, aluminum, or combinations thereof. In some embodiments, the conductive terminals 106 include microbumps, controlled collapse chip connection (C4) bumps, solder balls, ball grid array (BGA) balls, or combinations thereof.

[0025] like Figure 1 As shown, according to some embodiments, the first package structure 100a includes a silicon capacitor 108 disposed below and electrically coupled to the first redistribution layer 104. The silicon capacitor 108 may have multiple capacitor cells disposed in a semiconductor substrate (e.g., a silicon substrate). Since the silicon capacitor 108 has a higher thermal conductivity than ceramic capacitors (e.g., multi-layer ceramic capacitors (MLCCs)), heat dissipation efficiency can be improved. It should be noted that more than one silicon capacitor 108 may be disposed directly below the semiconductor chip 110 (described below); only one silicon capacitor 108 is shown here for illustrative purposes.

[0026] The silicon capacitor 108 may be disposed adjacent to the conductive terminal 106. The silicon capacitor 108 may have a front side and a back side opposite thereto. The front side of the silicon capacitor 108 may face the first redistribution layer 104, and the back side of the silicon capacitor 108 may face the substrate 102.

[0027] like Figure 1 As shown, according to some embodiments, the first package structure 100a includes a first bump structure 108a disposed on the back side of a silicon capacitor 108. The first bump structure 108a electrically couples the silicon capacitor 108 to a substrate 102. Compared to the underfill material typically used for connecting MLCCs, the first bump structure 108a may have a higher thermal conductivity to improve heat dissipation efficiency. The first bump structure 108a may be formed of a conductive material, such as a metal or alloy. In some embodiments, the first bump structure 108a includes solder balls, solder paste, or a combination thereof.

[0028] like Figure 1As shown, according to some embodiments, the first package structure 100a includes a second bump structure 108b disposed on the front side of the silicon capacitor 108. The second bump structure 108b can electrically couple the silicon capacitor 108 to the first redistribution layer 104. The second bump structure 108b can be formed of a conductive material such as a metal or alloy. In some embodiments, the second bump structure 108b includes solder balls, solder paste, or a combination thereof. It is worth noting that the number and configuration of the first bump structure 108a and the second bump structure 108b are for illustrative purposes only.

[0029] like Figure 1 As shown, the total thickness of the first bump structure 108a, the second bump structure 108b, and the silicon capacitor 108 can be substantially equal to the thickness of the conductive terminal 106. Ultimately, the first bump structure 108a can connect the substrate 102 and the silicon capacitor 108, while the second bump structure 108b can connect the first redistribution layer 104 and the silicon capacitor 108. Therefore, heat from the semiconductor chip 110 (described below) can be transferred to the substrate 102 through the first bump structure 108a, the second bump structure 108b, and the silicon capacitor 108.

[0030] like Figure 1 As shown, according to some embodiments, the first package structure 100a includes a semiconductor chip 110 disposed on a first redistribution layer 104. The semiconductor chip 110 can be electrically coupled to the substrate 102 through the first redistribution layer 104, conductive terminals 106, a first bump structure 108a, a second bump structure 108b, and a silicon capacitor 108.

[0031] According to some embodiments, the semiconductor chip 110 includes a SoC chip, a logic device, a memory device, a radio frequency (RF) device, or any combination thereof. For example, the semiconductor chip 110 may include a micro control unit (MCU) chip, a microprocessor unit (MPU) chip, a power management integrated circuit (PMIC) chip, a global positioning system (GPS) device, an accelerated processing unit (APU) chip, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, an input-output (I / O) chip, a dynamic random access memory (DRAM) controller, a static random access memory (SRAM), a high bandwidth memory (HBM), or any combination thereof.

[0032] According to some embodiments, the first package structure 100a may include more than one semiconductor chip. Furthermore, the first package structure 100a may also include one or more passive components (not shown), such as resistors, capacitors, inductors, or combinations thereof.

[0033] like Figure 1 As shown, according to some embodiments, the first packaging structure 100a includes a plurality of conductive pillars 112 disposed on the first redistribution layer 104. The conductive pillars 112 can electrically couple the second redistribution layer 116 to the first redistribution layer 104. The conductive pillars 112 can be formed of metals such as copper, tungsten, or combinations thereof.

[0034] like Figure 1 As shown, according to some embodiments, the first encapsulation structure 100a includes a molding material 114 disposed between a first redistribution layer 104 and a second redistribution layer 116. The molding material 114 may include a non-conductive material, such as a moldable polymer, epoxy resin, resin, or a combination thereof. Figure 1 As shown, the sidewalls of the molding material 114 can be substantially coplanar with the sidewalls of the first redistribution layer 104 and the second redistribution layer 116.

[0035] The molding material 114 can surround the semiconductor chip 110 and the conductive pillar 112, and can adjoin the sidewalls of the semiconductor chip 110 and the conductive pillar 112. For example... Figure 1 As shown, the molding material 114 can fill the gaps between the conductive pillars 112 and the gaps between the semiconductor chip 110 and the conductive pillars 112. The molding material 114 can protect the semiconductor chip 110 and the conductive pillars 112 from environmental influences, thereby preventing these components from being damaged by, for example, pressure, chemicals and / or moisture.

[0036] like Figure 1 As shown, according to some embodiments, a second packaging structure 100b is disposed on a first packaging structure 100a and electrically coupled to a second redistribution layer 116 via a plurality of conductive terminals 118. The conductive terminals 118 may be similar to the conductive terminals 106, and will not be described in detail here.

[0037] like Figure 1 As shown, according to some embodiments, the second packaging structure 100b includes a substrate 120. The substrate 120 may have a wiring structure. In some embodiments, the wiring structure of the substrate 120 includes a conductive layer, conductive vias, conductive pillars, etc., or combinations thereof. The wiring structure of the substrate 120 may be formed of a metal, such as copper, titanium, tungsten, aluminum, etc., or combinations thereof.

[0038] The wiring structure of substrate 120 can be disposed in an inter-metal dielectric (IMD) layer. In some embodiments, the IMD layer can be formed of an organic material such as a polymer substrate, an organic material such as silicon nitride, silicon oxide, silicon oxynitride, etc., or a combination thereof. Any desired semiconductor component can be formed in and on substrate 120. However, for the sake of simplicity, only a flat substrate 120 is shown.

[0039] like Figure 1 As shown, according to some embodiments, the second package structure 100b includes a molding material 122 disposed on a substrate 120 and one or more semiconductor components (not shown) surrounded by the molding material 122. The molding material 122 may be similar to the molding material 114, and will not be described further here.

[0040] Semiconductor components may include one or more identical or different devices. For example, a semiconductor component may include a memory chip, such as dynamic random access memory (DRAM). The second package structure 100b may also include one or more passive components (not shown), such as resistors, capacitors, inductors, or combinations thereof.

[0041] Figure 2This is a cross-sectional view of a silicon capacitor 200 with a semiconductor package structure according to some embodiments of the present disclosure. The silicon capacitor 200 may include... Figure 1 The silicon capacitor 108 shown has the same or similar components. For simplicity, these components will not be discussed in detail.

[0042] like Figure 2 As shown, according to some embodiments, the silicon capacitor 200 includes a semiconductor substrate 202. The semiconductor substrate 202 can be formed of any suitable semiconductor material such as silicon, and can be doped (e.g., using p-type or n-type dopants) or undoped. The semiconductor substrate 202 may have a first surface and a second surface opposite thereto.

[0043] like Figure 2 As shown, the silicon capacitor 200 may have a plurality of capacitor cells embedded in a semiconductor substrate 202. The capacitor cells may extend from a first surface of the semiconductor substrate 202 to a second surface of the semiconductor substrate 202. In particular, the top of the capacitor cell is disposed in the semiconductor substrate 202, and the bottom of the capacitor cell is disposed below the semiconductor substrate 202 (e.g., disposed on the first surface of the semiconductor substrate 202).

[0044] The capacitor cell may include electrodes 206, which include an upper electrode and a lower electrode, and an interlayer dielectric layer 208 between the upper and lower electrodes. In some embodiments, the electrodes 206 are formed of a conductive material, such as a metal, alloy, polycrystalline silicon, other suitable conductive materials, or combinations thereof. The upper and lower electrodes may be made of the same or different materials. In some embodiments, the interlayer dielectric layer 208 is formed of a high-k dielectric material such as aluminum oxide.

[0045] like Figure 2 As shown, according to some embodiments, the silicon capacitor 200 includes a conductive layer 204 disposed on a first surface of a semiconductor substrate 202. The conductive layer 204 can electrically couple capacitor cells to ground. In particular, the capacitor cells can be electrically coupled to ground on the first surface of the semiconductor substrate 202. In some embodiments, the conductive layer 204 is formed of a conductive material, such as a metal, alloy, polycrystalline silicon, other suitable conductive materials, or combinations thereof.

[0046] like Figure 2 As shown, according to some embodiments, the silicon capacitor 200 includes a dielectric layer 210 covering the sidewalls and bottom surface of the conductive layer 204. In some embodiments, the dielectric layer 210 is formed of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0047] like Figure 2As shown, according to some embodiments, the silicon capacitor 200 includes a conductive via 212 disposed in the dielectric layer 210. The conductive via 212 can penetrate the dielectric layer 210 and can be electrically coupled to a capacitor cell. The conductive via 212 can connect the capacitor cell to a first bump structure 220 (described below), so that the silicon capacitor 200 can be coupled to the substrate 102 (e.g., ...) via the bump. Figure 1 (as shown). In some embodiments, the conductive via 212 is formed of a conductive material, such as a metal, alloy, polysilicon, other suitable conductive material, or a combination thereof.

[0048] like Figure 2 As shown, according to some embodiments, the silicon capacitor 200 includes a wire 214 disposed below a conductive via 212. In some embodiments, the wire 214 is formed of a conductive material, such as a metal, alloy, polycrystalline silicon, other suitable conductive materials, or combinations thereof.

[0049] like Figure 2 As shown, according to some embodiments, the silicon capacitor 200 includes a conductive pad 216 disposed below the conductive line 214. In some embodiments, the conductive pad 216 is formed of a conductive material, such as a metal or alloy. For example, the conductive pad 216 may be formed of nickel, tin, copper, tungsten, or combinations thereof. The conductive layer 204, the conductive via 212, the wire 214, and the conductive pad 216 may be made of the same or different materials.

[0050] like Figure 2 As shown, according to some embodiments, the silicon capacitor 200 includes a solder resist layer 218 that covers the sidewalls and bottom surface of the conductive lines 214 and the sidewalls of the conductive pads 216. Figure 2 As shown, a portion of the sidewall of the conductive pad 216 may be covered by the solder mask 218. Optionally, the entire sidewall of the conductive pad 216 may be covered by the solder mask 218. In some embodiments, the solder mask 218 is formed of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0051] like Figure 2 As shown, according to some embodiments, the silicon capacitor 200 includes a first bump structure 220 disposed below a conductive pad 216. The first bump structure 220 can be electrically coupled to a capacitor cell via the conductive pad 216, a wire 214, and a conductive via 212. Figure 2 As shown, a portion of the sidewall of the conductive pad 216 can be covered by the first bump structure 220. The first bump structure 220 can be similar to... Figure 1 The first bump structure 108a shown is not described in detail here.

[0052] like Figure 2 As shown, according to some embodiments, the silicon capacitor 200 includes a wire 222 disposed on a second surface of the semiconductor substrate 202 and electrically coupled to a capacitor cell. In some embodiments, the wire 222 is formed of a conductive material, such as a metal, alloy, polycrystalline silicon, other suitable conductive materials, or combinations thereof.

[0053] like Figure 2 As shown, according to some embodiments, the silicon capacitor 200 includes a dielectric layer 224 disposed on a conductor 222. In some embodiments, the dielectric layer 224 is formed of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0054] like Figure 2 As shown, according to some embodiments, the silicon capacitor 200 includes a wiring structure 226 disposed on a dielectric layer 224. The wiring structure 226 can be electrically coupled to a capacitor cell. In some embodiments, the wiring structure 226 includes a conductive layer, conductive vias, conductive pillars, or combinations thereof. The wiring structure 226 may be formed of a metal, such as copper, titanium, tungsten, aluminum, or combinations thereof.

[0055] like Figure 2 As shown, the wiring structure 226 can be disposed in the intermetallic dielectric (IMD) layer 228. In some embodiments, the IMD layer 228 can be formed of organic materials (e.g., polymer base materials), inorganic materials (e.g., silicon nitride, silicon oxide, silicon oxynitride, etc.) or combinations thereof.

[0056] like Figure 2 As shown, according to some embodiments, the silicon capacitor 200 includes a second bump structure 230 disposed on a wiring structure 226 and electrically coupled to a capacitor cell via the wiring structure 226 and a wire 222. The second bump structure 230 may be similar to Figure 1 The second bump structure 108b shown is not described in detail here.

[0057] Figure 3 This is a cross-sectional view of a silicon capacitor 300 with a semiconductor packaging structure according to some embodiments of the present disclosure. It should be noted that the silicon capacitor 300 may include... Figure 2 The silicon capacitor 200 shown has the same or similar components. For simplicity, these components will not be discussed in detail. The conductive via 212 is disposed beneath the semiconductor substrate 202. Figure 2 Compared to the previous embodiment, in the following embodiment, the conductive via penetrates the semiconductor substrate 202.

[0058] like Figure 3As shown, according to some embodiments, the silicon capacitor 300 includes a conductive via 302 penetrating the semiconductor substrate 202. The conductive via 302 can be electrically coupled to the wiring structure 226 and can electrically couple a first bump structure 220 to a second bump structure 230. In some embodiments, the conductive via 302 is formed of a conductive material such as a metal, alloy, polysilicon, other suitable conductive materials, or combinations thereof.

[0059] like Figure 3 As shown, a first bump structure 220 and two second bump structures 230 can be disposed on opposite surfaces of the conductive via 302. However, the diagrams illustrating the number and configuration of the first bump structure 220 and the second bump structure 230 are for illustrative purposes only.

[0060] like Figure 3 As shown, according to some embodiments, the silicon capacitor 300 includes a dielectric layer 304 that penetrates the semiconductor substrate 202 and covers the sidewalls of the conductive via 302. The dielectric layer 304 may be similar to... Figure 2 The dielectric layer 210 shown will not be described further. The dielectric layer 304 and the IMD layer 228 can be made of the same material or different materials.

[0061] Figure 4 This is a cross-sectional view of a silicon capacitor 400 with a semiconductor package structure according to some embodiments of the present disclosure. It should be noted that the silicon capacitor 400 may include... Figure 2 The silicon capacitor 200 shown contains components that are the same as or similar to those in the original; for simplicity, these components will not be discussed in detail. The first bump structure 220 is one of the components of the silicon capacitor 200. Figure 2 Compared to the previous embodiment, in the following embodiment, the first bump structure is formed on the substrate 102 (e.g., Figure 1 As shown, but not in Figure 4 (As shown in the image)

[0062] like Figure 4 As shown, according to some embodiments, the bottom surface of the conductive pad 216 is exposed by the solder mask layer 218. A first bump structure may be formed on the substrate 102 (e.g., Figure 1 Above the silicon capacitor 400, and when the silicon capacitor 400 is disposed on the substrate 102, the conductive pad 216 can be connected to the first bump structure (e.g., as shown). Figure 1 The first bump structure 108a in the middle). As a result, from the semiconductor chip 110 (such as Figure 1 The heat (as shown) can be transferred to the substrate 102 through the silicon capacitor 400 and the first bump structure.

[0063] Figure 5 This is a cross-sectional view of a silicon capacitor 500 with a semiconductor package structure according to some embodiments of the present disclosure. It should be noted that the silicon capacitor 500 may include... Figure 3 The silicon capacitor 300 shown contains components that are the same as or similar to those in the original; for simplicity, these components will not be discussed in detail. The first bump structure 220 is one of the components of the silicon capacitor 300. Figure 3 Compared to the previous embodiment, in the following embodiment, the first bump structure is formed on the substrate 102 (e.g., Figure 1 As shown, but not in Figure 5 (As shown in the image)

[0064] like Figure 5 As shown, according to some embodiments, the bottom surface of the conductive pad 216 is exposed by the solder mask layer 218. A first bump structure may be formed on the substrate 102 (e.g., Figure 1 As shown), and when the silicon capacitor 500 is disposed on the substrate 102, the conductive pad 216 can be connected to the first bump structure (e.g., Figure 1 The first bump structure 108a in the middle). As a result, from the semiconductor chip 110 (such as Figure 1 The heat (as shown) can be transferred to the substrate 102 through the silicon capacitor 500 and the first bump structure.

[0065] Figure 6 This is a cross-sectional view of a silicon capacitor 600 with a semiconductor package structure according to some embodiments of the present disclosure. It should be noted that the silicon capacitor 600 may include... Figure 2 The silicon capacitor 200 shown has the same or similar components, which will not be discussed in detail for simplicity. The first bump structure 220 is connected via conductive vias 212, wires 214, and conductive pads 216. Figure 2 Compared to the previous embodiment, in the following embodiment, a conductive layer 602 is used to connect the first bump structure 606.

[0066] like Figure 6 As shown, according to some embodiments, the silicon capacitor 600 includes a conductive layer 602 disposed beneath the solder resist layer 218 and electrically coupled to the capacitor cell. Specifically, the bottom of the silicon capacitor 600 may include the conductive layer 602. In some embodiments, the conductive layer 602 is formed of a conductive material such as a metal or alloy. For example, the conductive layer 602 may be formed of nickel, tin, or a combination thereof. The conductive layer 602 can be formed by electroplating, electroless plating, or the like.

[0067] like Figure 6 As shown, according to some embodiments, the silicon capacitor 600 includes a ground pad 604 disposed on a substrate 102 and electrically coupled to ground. The ground pad 604 may cover a portion of the top surface of the substrate. In some embodiments, the ground pad 604 is formed of a conductive material, such as a metal or alloy. For example, the ground pad 604 may be formed of nickel, tin, or a combination thereof.

[0068] like Figure 6 As shown, according to some embodiments, the silicon capacitor 600 includes a first bump structure 606 disposed on and electrically coupled to a ground pad 604. When the silicon capacitor 600 is disposed on the first bump structure 606, the capacitor cell can be electrically coupled to the substrate 102 through the conductive layer 602 and the first bump structure 606. The first bump structure 606 may be formed of a conductive material, such as a metal or alloy. In some embodiments, the first bump structure 606 includes solder balls, solder paste, or a combination thereof.

[0069] In summary, according to some embodiments, the semiconductor package structure incorporates a silicon capacitor as a decoupling capacitor. The silicon capacitor can be disposed between the semiconductor chip and the substrate. Because silicon capacitors have better thermal conductivity than ceramic capacitors, heat from the semiconductor chip can be transferred to the substrate through the silicon capacitor. As a result, heat dissipation efficiency can be improved.

[0070] Furthermore, according to some embodiments, the bump structure is used to connect the silicon capacitor and the substrate. Since the bump structure has better thermal conductivity than the underfill material, heat from the semiconductor chip can be transferred to the substrate through the silicon capacitor and the bump structure. Therefore, heat dissipation efficiency can be further improved.

[0071] While the invention has been described by way of example and according to preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. Rather, the invention is intended to cover various modifications and similar arrangements of the disclosed embodiments (which will be apparent to those skilled in the art). Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such modifications and similar arrangements.

Claims

1. A semiconductor packaging structure, characterized in that, include: Basic substrate; The first redistribution layer is disposed on the base substrate; A semiconductor chip is disposed on the first redistribution layer; A silicon capacitor is disposed beneath the first redistribution layer and electrically coupled to the semiconductor chip, wherein the silicon capacitor comprises: Semiconductor substrate; and Multiple capacitor cells are embedded in the semiconductor substrate; and The semiconductor packaging structure also includes: A first bump structure is disposed between the silicon capacitor and the base substrate; The silicon capacitor includes a wiring structure disposed above the plurality of capacitor cells and conductive lines disposed below the plurality of capacitor cells. The silicon capacitor also includes a conductive via penetrating the semiconductor substrate, the conductive via being electrically coupled to the wiring structure and the conductive lines disposed below the conductive via.

2. The semiconductor packaging structure as described in claim 1, characterized in that, The silicon capacitor also includes a second bump structure that electrically couples the plurality of capacitor cells to the first redistribution layer.

3. The semiconductor packaging structure as described in claim 2, characterized in that, The wiring structure electrically couples the multiple capacitor units to the second bump structure.

4. The semiconductor packaging structure as described in claim 3, characterized in that, The conductive via electrically couples the wiring structure to the first bump structure.

5. The semiconductor packaging structure as described in claim 1, characterized in that, The silicon capacitor includes a dielectric layer that penetrates the semiconductor substrate and covers the sidewalls and bottom surface of the conductive via, and the dielectric layer is also disposed between the plurality of capacitor cells and the conductive line.

6. The semiconductor packaging structure as described in claim 1, characterized in that, The bottom of the silicon capacitor includes a conductive layer that is electrically coupled to the plurality of capacitor cells.

7. The semiconductor packaging structure as described in claim 1, characterized in that, The top of the plurality of capacitor cells is disposed within the semiconductor substrate, and the bottom of the plurality of capacitor cells is disposed below the semiconductor substrate.

8. The semiconductor packaging structure as described in claim 7, characterized in that, The bottom of the multiple capacitor cells is electrically coupled to the ground terminal.

9. The semiconductor packaging structure as described in claim 1, characterized in that, It also includes a grounding pad disposed between the first bump structure and the base substrate.

10. The semiconductor packaging structure as described in claim 1, characterized in that, Also includes: A second redistribution layer is disposed on the semiconductor chip; and A molding material is disposed between the first redistribution layer and the second redistribution layer and surrounds the semiconductor chip.

11. A semiconductor packaging structure, characterized in that, include: First redistribution layer; A semiconductor chip is disposed on the first redistribution layer; and A silicon capacitor is disposed below a first redistribution layer and electrically coupled to the semiconductor chip through the first redistribution layer, wherein the silicon capacitor comprises: A semiconductor substrate having a first surface and a second surface opposite thereto; Multiple capacitor cells extend from a first surface of the semiconductor substrate to a second surface of the semiconductor substrate; A first bump structure is disposed on a first surface of the semiconductor substrate and electrically coupled to the plurality of capacitor cells; and A second bump structure is disposed on the second surface of the semiconductor substrate and electrically coupled to the first redistribution layer; The silicon capacitor includes a wiring structure disposed above the plurality of capacitor cells and conductive lines disposed below the plurality of capacitor cells. The silicon capacitor also includes a conductive via penetrating the semiconductor substrate, the conductive via being electrically coupled to the wiring structure and the conductive lines disposed below the conductive via.

12. The semiconductor packaging structure as described in claim 11, characterized in that, The wiring structure is disposed between the second bump structure and the semiconductor substrate.

13. The semiconductor packaging structure as described in claim 11, characterized in that, The conductive via electrically couples the first bump structure to the second bump structure.

14. The semiconductor packaging structure as described in claim 11, characterized in that, The conductive via is disposed between the semiconductor substrate and the first bump structure.

15. The semiconductor packaging structure as described in claim 11, characterized in that, The plurality of capacitor cells are electrically coupled to a ground terminal on the first surface of the semiconductor substrate.

16. The semiconductor packaging structure as described in claim 11, characterized in that, Also includes: A base substrate is disposed below the silicon capacitor, wherein the silicon capacitor is electrically coupled to the base substrate through the first bump structure; and Multiple conductive terminals are located adjacent to the silicon capacitor and electrically couple the first redistribution layer to the base substrate.

17. A semiconductor packaging structure, characterized in that, Includes a first packaging structure, wherein the first packaging structure includes: First redistribution layer; A semiconductor chip is disposed on the first redistribution layer; A second redistribution layer is disposed on the semiconductor chip; A silicon capacitor is disposed beneath the first redistribution layer and electrically coupled to the semiconductor chip; and A bump structure is disposed below the silicon capacitor; The silicon capacitor includes a semiconductor substrate, has a plurality of capacitor cells embedded in the semiconductor substrate, includes a wiring structure disposed above the plurality of capacitor cells and conductive lines disposed below the plurality of capacitor cells, and further includes a conductive via penetrating the semiconductor substrate, the conductive via being electrically coupled to the wiring structure and the conductive lines disposed below the conductive via.

18. The semiconductor packaging structure as described in claim 17, characterized in that, The first packaging structure also includes: Conductive pillars are disposed between the first redistribution layer and the second redistribution layer and adjacent to the semiconductor chip; and Molding material surrounds the semiconductor chip and the conductive pillar.

19. The semiconductor packaging structure as described in claim 17, characterized in that, It also includes a second encapsulation structure disposed on the second redistribution layer.

20. The semiconductor packaging structure as described in claim 17, characterized in that, It also includes a base substrate disposed below the first package structure and in contact with the bump structure.

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