A iii-v semiconductor chip

Abstract

A III-V semiconductor chip includes a device region and a doped semiconductor ring region. The doped semiconductor ring region surrounds the device region. At least one active or passive device is formed in the device region.

Description

Technical Field

[0001] This disclosure relates to a III-V group semiconductor chip for detecting chip breakage. Background Technology

[0002] In traditional semiconductor manufacturing processes, chips are individually assembled from a substrate using dicing techniques (such as laser cutting). However, microcracks, such as hairline cracks, can form at the edges or corners of the chip, potentially reducing its reliability. Furthermore, hairline cracks can extend from major cracks, making their detection crucial. Therefore, the industry needs a structure for detecting cracks on chips. Summary of the Invention

[0003] This disclosure provides embodiments of a III-V semiconductor chip, including a device region and a doped semiconductor ring region. The doped semiconductor ring region surrounds the device region. At least one active or passive device is formed in the device region.

[0004] This disclosure provides some embodiments of a III-V semiconductor chip having a device region and a doped semiconductor ring region surrounding the device region. The III-V semiconductor chip includes a substrate, a secondary collector layer, and a protective layer. The secondary collector layer is formed on the substrate. The protective layer is disposed on the secondary collector layer.

[0005] This disclosure allows for the easy detection of cracks formed at the edges of semiconductor chips. Attached Figure Description

[0006] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, many features are not drawn to scale and are only used for illustrative purposes. In fact, the dimensions of the components may be arbitrarily enlarged or reduced to clearly demonstrate the features of this disclosure.

[0007] Figure 1A-Figure 1B , Figures 2A-2B , Figures 3A-3B , Figures 4A-4D This is a top view of the various stages of forming a semiconductor structure in some embodiments disclosed herein.

[0008] According to some embodiments disclosed herein, Figure 1B , Figure 2B , Figure 3B ,as well as Figure 4B They are along Figure 1A , 2A picture, Figure 3A , Figure 4A The cross-sectional view is shown by line segment AA in the diagram.

[0009] According to some embodiments disclosed herein, Figure 4C It is along Figure 4A The cross-sectional view is drawn using line segment BB.

[0010] According to some embodiments disclosed herein, Figure 4D It is an enlarged view of the details of the protective structure.

[0011] According to some embodiments disclosed herein, Figure 5 The semiconductor structures shown in some embodiments of this disclosure are illustrated.

[0012] According to some embodiments disclosed herein, Figure 6 The semiconductor structures shown in some embodiments of this disclosure are illustrated.

[0013] Figure 7A This is a top view of a semiconductor structure disclosed in some embodiments.

[0014] According to some embodiments disclosed herein, Figure 7B It is along Figure 7A The cross-sectional view is shown by line segment AA in the figure.

[0015] According to some embodiments disclosed herein, Figure 7C It is along Figure 7A The cross-sectional view is drawn using line segment BB.

[0016] Figure 8 The semiconductor structures shown in some embodiments of this disclosure are illustrated.

[0017] Figure 9 The semiconductor structures shown in some embodiments of this disclosure are illustrated.

[0018] Attached icon number

[0019] 100A, 100B, 100C, 100D, 100E: Semiconductor Structure

[0020] 101, 103E1, 103E2, 105S3, 105S4: Edges

[0021] 102:Substrate

[0022] 103: Ring element (collector plateau ring)

[0023] 103A: Part One

[0024] 103B: Part Two

[0025] 103C, 103D: Protrusions

[0026] 104A: Secondary collector layer (first doped semiconductor layer)

[0027] 105: Protective Structure

[0028] 105A: First dielectric layer

[0029] 105B: Second dielectric layer

[0030] 105C: Third dielectric layer

[0031] 105D: Fourth dielectric layer

[0032] 105S1, 105S2: Sidewalls (edges)

[0033] 105S5: Staircase Interface

[0034] 106A: Etching Stop Layer

[0035] 108: Collector layer

[0036] 109: Base High Platform Ring

[0037] 110: Base layer

[0038] 112: Emitter layer

[0039] 114: Emitter cap

[0040] 116: Emitter electrode

[0041] 118: Base electrode

[0042] 124: Collector electrode

[0043] 130: Heterojunction bipolar transistor

[0044] 201,202,203,204: Area

[0045] 205A, 205B: Conductive pads

[0046] 206A: First conductivity characteristic

[0047] 206B: Second conductivity characteristic

[0048] AA, BB: line segments

[0049] D1, D2, D3: Distance

[0050] W1: Width Detailed Implementation

[0051] The following discloses many different implementations or examples to implement different features of the provided object. Specific embodiments of the elements and their arrangements are described below to illustrate this disclosure. Of course, these embodiments are merely illustrative and should not be construed as limiting the scope of this disclosure. For example, the specification mentions that a first feature is formed on a second feature, which includes embodiments where the first and second feature are in direct contact. It may also include embodiments where there are other features between the first and second feature, i.e., the first and second feature are not in direct contact.

[0052] Furthermore, repeated reference numerals or designations may be used in different embodiments. These repetitions are merely for the purpose of clearly and simply describing this disclosure and do not represent a specific relationship between the different embodiments and / or structures discussed. Additionally, the formation, connection, and / or coupling to another feature in this disclosure may include embodiments where the feature is formed in direct contact, and may also include embodiments where additional feature elements may be formed to insert into the aforementioned feature, such that the feature elements may not be in direct contact. Furthermore, spatially related terms such as “vertical,” “above,” “up,” “below,” “bottom,” and similar terms (e.g., “downward,” “upward,” etc.) may be used to facilitate the description of the relationship between one element(s) or feature(s) in the illustrations and another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device including the feature.

[0053] Furthermore, the use of ordinal numbers such as "first" and "second" in the specification and the claims to modify the elements of the claims does not imply or represent any prior ordinal number of the claimed element, nor does it represent the order of one claimed element with another claimed element, or the order of manufacturing methods. The use of such ordinal numbers is only to enable a claimed element with a certain name to be clearly distinguished from another claimed element with the same name.

[0054] Here, the terms "about," "approximately," and "substantially" typically indicate within 20% of a given value or range, preferably within 10%, more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. The quantities given here are approximate, meaning that the terms "about," "approximately," and "substantially" are implied even without specific mention of them.

[0055] Some embodiments of this disclosure provide a semiconductor structure (e.g., a III-V semiconductor chip). According to some embodiments of this disclosure, the semiconductor structure includes a ring element surrounding an active region of the semiconductor chip, which can help detect microcracks (e.g., hairline cracks) that occur during chip monolithization.

[0056] Figure 1A , Figure 2A , Figure 3A ,as well as Figure 4A This is a top view of various stages in forming the semiconductor structure 100A according to some embodiments of this disclosure. According to some embodiments of this disclosure, Figure 1B , Figure 2B , Figure 3B ,as well as Figure 4B They are along Figure 1A , Figure 2A , Figure 3A , Figure 4A The cross-sectional view is shown by line segment AA in the diagram.

[0057] like Figure 1A and Figure 1B As shown, a substrate 102 is provided in some embodiments. In some embodiments, the substrate 102 is a semiconductor substrate. Furthermore, the substrate 102 may include a III-V group semiconductor, such as GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, or combinations thereof. In some embodiments, the substrate 102 includes undoped GaAs. Thus, semiconductor structure 100A (see...) Figure 4A It can be a III-V group semiconductor chip.

[0058] Next, as Figure 2A and Figure 2B As shown, according to some embodiments of this disclosure, a secondary collector layer 104A (a first doped semiconductor layer 104A) is formed on a substrate 102. In some embodiments, the secondary collector layer 104A comprises a III-V semiconductor having a first conductivity type. In some other embodiments, the secondary collector layer 104A comprises a III-V semiconductor having a second conductivity type. In some embodiments, the second conductivity type is the opposite of the first conductivity type. In some embodiments, the first conductivity type is n-type. The secondary collector layer 104A may comprise a III-V semiconductor, such as GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, or a combination thereof. In some embodiments, the secondary collector layer 104A is an n-type GaAs layer, which may be doped with Si, Se, and Te. In some embodiments, the doping concentration of the secondary collector layer 104A is 1e18 cm⁻¹. -3 and 1e20cm -3Within this range, at doping concentrations of this order of magnitude, ohmic contacts can be formed relatively easily between the secondary collector layer 104A and the subsequently formed collector electrode. If the doping concentration of the secondary collector layer 104A is too high, the dopant may not be fully activated, and reliability may deteriorate. If the doping concentration of the secondary collector layer 104A is too low, ohmic contacts may not be formed between the secondary collector layer 104A and the subsequently formed collector electrode. In some embodiments, the secondary collector layer 104A may have a thickness between 50 nm and 1500 nm. If the secondary collector layer 104A is too thick, it may be difficult to isolate it by implantation. If the secondary collector layer 104A is too thin, it may increase the collector resistance. In some embodiments, the secondary collector layer 104A is formed on the substrate 102 by molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), hydride vapor phase epitaxy (HVPE), other suitable methods, or combinations thereof. The secondary collector layer 104A can be doped by in-situ doping.

[0059] like Figure 3A and Figure 3B As shown, according to some embodiments of this disclosure, a ring element 103 is formed in a secondary collector layer 104A. In some embodiments, the ring element 103 (or collector mesa ring 103) is a conductive ring made of a doped semiconductor layer. In some embodiments, the ring element 103 includes an n-type doped semiconductor layer, a p-type doped semiconductor layer, or a combination thereof. In some embodiments, the doping concentration in the ring element 103 is between 1E18 cm⁻¹. -3 and 4E19cm -3 between.

[0060] In some embodiments, a implantation process is performed on the secondary collector layer 104A to define a ring element 103 within the secondary collector layer 104A. In some embodiments, boron ions (or helium ions) are implanted into some regions of the n-type doped secondary collector layer 104A. For example, implantation processes may be performed in some regions of regions 203 and 204 to define insulating regions within the secondary collector layer 104A. In some embodiments, region 204 surrounds region 201, region 202 is located between regions 203 and 204, and no implantation is performed in regions 201 and 202. In some embodiments, at least one region of the secondary collector layer 104A without boron ion implantation may serve as the ring element 103, such as the secondary collector layer 104A in region 202. In some embodiments, another implantation process may be performed to adjust the conductivity of the ring element 103. In some embodiments, the ring element 103 may be referred to as a collector mesa ring (CMESA ring). Therefore, the ring element 103 can have a different conductivity than other portions of the secondary collector layer 104A. For example, it can have a better conductivity than other portions of the secondary collector layer 104A in region 203 or region 204. Therefore, the ring element 103 can serve as a conductive region and can be used to detect chip cracks.

[0061] In some embodiments, such as Figure 3A As shown, the annular element 103 includes protrusions 103C and 103D. In some embodiments, protrusions 103C can be connected to a first conductive pad (e.g., vias and / or conductive layers) by means of conductive features (e.g., vias and / or conductive layers) formed in subsequent processes. Figure 4A The conductive pad 205A shown can be used, and the protrusion 103D can be connected to the second conductive pad (e.g., the conductive pad 205A shown). Figure 4A The conductive pad shown is 205B.

[0062] In some embodiments, active and / or passive devices are formed in region 201. Therefore, region 201 can serve as a device region. The active device may include a heterojunction bipolar transistor (HBT), a high electron mobility transistor (HEMT), other suitable semiconductor devices, or combinations thereof. The passive device may include capacitors, resistors, inductors, filters, PIN diodes, other suitable devices, or combinations thereof.

[0063] In some embodiments, the secondary collector layer 104A in region 201 may serve as the secondary collector layer of a heterojunction bipolar transistor in device region 201. In some embodiments, region 202 may be surrounded by region 203 and formed between region 203 and region 204.

[0064] Next, as shown in Figure 4A and Figure 4B As shown, according to some embodiments of this disclosure, a protective structure 105 (or protective layer) is disposed on the secondary collector layer 104A and in region 201. In some embodiments, the protective structure 105 can be used to protect elements in region 201. Subsequently, according to some embodiments of this disclosure, conductive pads 205A and 205B are formed on the protective structure 105 and in region 201 to form a semiconductor structure 100A. In some embodiments, conductive pad 205A is electrically connected to the annular element 103 via a first conductive feature formed between the annular element 103 and conductive pad 205A, and conductive pad 205B is electrically connected to the annular element 103 via a second conductive feature formed between the annular element 103 and conductive pad 205B. In some embodiments, the conductive feature includes vias in the protective structure 105. In some embodiments, the vias directly contact the annular element 103, conductive pad 205A, and / or conductive pad 205B. In some embodiments, the protective structure 105 is further provided with a conductive layer, and the conductive pads 205A and 205B are electrically connected to the annular element 103 through the vias and the conductive layer.

[0065] According to some embodiments disclosed herein, Figure 4C It is along Figure 4A The cross-sectional view is shown by line segment BB. In some embodiments, such as Figure 4CAs shown, conductive pad 205A is electrically connected to protrusion 103C via a first conductive feature (e.g., via) 206A. In some embodiments, conductive pad 205B is electrically connected to protrusion 103D via a second conductive feature (e.g., via) 206B. In some embodiments, the first conductive feature 206A and the second conductive feature 206B are located directly below conductive pad 205A and conductive pad 205B, respectively. In some embodiments, the first conductive feature 206A and the second conductive feature 206B are located directly above protrusion 103C and protrusion 103D, respectively. In some embodiments, the first conductive feature 206A and the second conductive feature 206B are disposed in the protective structure 105, for example, by photolithography (e.g., photoresist coating, soft baking, exposure, post-exposure baking, development, other suitable processes, or combinations thereof), etching (e.g., wet etching, dry etching, other suitable processes, or combinations thereof), other suitable processes, or combinations thereof to dispose of the first conductive feature 206A and the second conductive feature 206B. In some embodiments, the first conductive feature 206A and the second conductive feature 206B include a combination of a via and a conductive layer.

[0066] According to some embodiments disclosed herein, Figure 4D This is an enlarged view of the details of the protective structure 105. In some embodiments, the protective structure 105 may include a first dielectric layer 105A, a second dielectric layer 105B, a third dielectric layer 105C, and a fourth dielectric layer 105D. In some embodiments, the first dielectric layer 105A is disposed on the secondary collector layer 104A, the second dielectric layer 105B is disposed on the first dielectric layer 105A, and the third dielectric layer 105C is disposed on the second dielectric layer 105B and covers the sidewalls 105S1 of the first dielectric layer 105A and the sidewalls 105S2 of the second dielectric layer 105B. In some embodiments, the third dielectric layer 105C is in contact with the secondary collector layer 104A. In some embodiments, the fourth dielectric layer 105D is disposed on the third dielectric layer 105C, and a stepped interface 105S5 is formed between the third dielectric layer 105C and the fourth dielectric layer 105D. In some embodiments, vias and conductive layers (not shown) may be provided between the first dielectric layer 105A, the second dielectric layer 105B, the third dielectric layer 105C and / or the fourth dielectric layer 105D to electrically connect the annular element 103 to the conductive pads 205A and 205B.

[0067] In some embodiments, the protective structure 105 may include SiN x(x can be between 1 and 3, and specifically SiN, Si3N4, Si2N3, or a combination thereof), SiO2, SiON, Al2O3, AlN, polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO), other insulating materials, or combinations thereof. For example, the first dielectric layer 105A, the second dielectric layer 105B, and the third dielectric layer 105C may include SiN, and the fourth dielectric layer 105D may include PBO. The protective structure 105 can be formed by metal-organic chemical vapor deposition, chemical vapor deposition, spin coating, other suitable methods, or combinations thereof.

[0068] In some embodiments, the annular element 103 may be divided into a first portion 103A and a second portion 103B between conductive pads 205A and 205B. In some embodiments, the first portion 103A and the second portion 103B are electrically connected in parallel to conductive pads 205A and 205B. In some embodiments, the first portion 103A has a resistor R1, and the second portion 103B has a resistor R2. In some embodiments, the lengths of the first portion 103A and the second portion 103B may be substantially the same, but this disclosure is not limited thereto. In some embodiments, conductive pads 205A and 205B may be located diagonally across region 201 of the semiconductor structure 100A, so the lengths of the first portion 103A and the second portion 103B, as well as the resistors R1 and R2, may be substantially the same, but this disclosure is not limited thereto.

[0069] In some embodiments, the total resistance RTl between conductive pad 205A and conductive pad 205B can be calculated using the following equation:

[0070] If any crack forms at the edge of semiconductor structure 100A, when the crack propagates to ring element 103, for example to the second part 103B, the second part 103B will be unable to conduct electricity, so that the total resistance RT2 between conductive pad 205A and conductive pad 205B can be expressed as:

[0071] Even if the crack does not propagate through the entire annular element 103, the total resistance will still be affected because the resistance of the first part 103A or the second part 103B will be altered by the crack. Therefore, the presence of a crack can be determined by measuring the resistance between conductive pads 205A and 205B.

[0072] In some embodiments, the annular element 103 (or region 202) has a width W1. In some embodiments, the width W1 is between 2 μm and 10 μm (e.g., 5 μm). In some embodiments, the distance D1 between the edge 101 of the semiconductor structure 100A and the edge 103E1 of the annular element 103 is between 5 μm and 20 μm (e.g., 10 μm). In some embodiments, the ratio of W1 to D1 is between 0.1 and 2. The width W1 and the distance D1 can be adjusted to improve the crack detection sensitivity of the chip.

[0073] In some embodiments, the edge 105S1 of the first dielectric layer 105A is aligned with the edge 105S2 of the second dielectric layer 105B. In some embodiments, the edge 105S3 of the third dielectric layer 105C is aligned with the edge 105S4 of the fourth dielectric layer 105D. In some embodiments, the distance D2 between edge 105S4 and edge 105S2 is between 0.5 μm and 1.5 μm (e.g., 1 μm). In some embodiments, edge 105S1 may be aligned with the edge 103E2 of the annular element 103. In some embodiments, the width D2 of the stepped interface between the third dielectric layer 105C and the fourth dielectric layer 105D may be smaller than the width W1 of region 202.

[0074] Figure 5 The semiconductor structure 100B is shown in some embodiments of this disclosure. For example... Figure 5 As shown, the position of the annular element 103 can be adjusted, for example, the protective structure 105 can partially cover the annular element 103. For instance, a portion of the annular element 103 may be located below and covered by the protective structure 105, while another portion may be exposed to the protective structure to prevent the annular element 103 from being damaged during manufacturing (e.g., etching process).

[0075] In some embodiments, the width W1 is between 2 μm and 10 μm (e.g., 5 μm). In some embodiments, the distance D1 between edge 101 of semiconductor structure 100A and edge 103E1 of ring element 103 is between 5 μm and 20 μm (e.g., 10 μm). In some embodiments, the ratio of W1 to D1 can be between 0.1 and 2. The width W1 and distance D1 can be adjusted to improve the crack detection sensitivity of the chip. In some embodiments, the distance D2 between edge 105S4 and edge 105S2 is between 0.5 μm and 1.5 μm (e.g., 1 μm). In some embodiments, the distance D3 between edge 105S4 and edge 103E1 is between 1 μm and 9 μm (e.g., 4 μm). In some embodiments, the ratio of W1 to D3 is between 1 and 10. The width W1 and distance D3 can be adjusted to improve the reliability of the chip.

[0076] Figure 6 The semiconductor structure 100C is shown in some embodiments of this disclosure. For example... Figure 6 As shown, the position of the annular element 103 can be further adjusted, for example, to be completely covered by the protective structure 105. Therefore, damage to the annular element 103 during manufacturing (e.g., etching processes) can be prevented. In some embodiments, edge 103E1 may be aligned with edge 105S2 facing the annular element 103, but this disclosure is not limited thereto. In some embodiments, width W1 is between 2 μm and 10 μm (e.g., 5 μm). In some embodiments, the distance D1 between edge 101 of semiconductor structure 100A and edge 103E1 of annular element 103 is between 5 μm and 30 μm (e.g., 15 μm). In some embodiments, the ratio of W1 to D1 may be between 1 / 15 and 2.

[0077] Figure 7A This is a top view of the semiconductor structure 100D according to some embodiments of this disclosure. According to some embodiments of this disclosure, Figure 7B It is along Figure 7A The cross-sectional view is shown by line segment AA in the diagram. According to some embodiments of this disclosure, Figure 7C It is along Figure 7A The cross-sectional view is drawn using line segment BB. For example... Figure 7A , Figure 7B and Figure 7C As shown, the position of the annular element 103 can be further adjusted, for example, to be completely covered by the protective structure 105, and the edge 103E1 can be laterally separated from the edge 105S2. Therefore, damage to the annular element 103 during manufacturing processes (e.g., etching processes) can be further prevented. In some embodiments, conductive pads 205A and 205B are electrically connected to the annular element 103 via a first conductive feature (e.g., via) 206A and a second conductive feature (e.g., via) 206B, respectively. In some embodiments, the first conductive feature 206A and the second conductive feature 206B are located directly below the conductive pads 205A and 205B, respectively. In some embodiments, the first conductive feature 206A and the second conductive feature 206B are located directly above the annular element 103. In some embodiments, the first conductive feature 206A and the second conductive feature 206B are formed in the protective structure 105 by photolithography, etching, other suitable processes, or combinations thereof.

[0078] Figure 8 The semiconductor structure 100E is shown in some embodiments of this disclosure. For example... Figure 8As shown, according to some embodiments of this disclosure, a base mesa ring 109 is provided on the annular element 103. In some embodiments, the base mesa ring 109 may include an etch stop layer 106A, a secondary collector layer 104B, a collector layer 108, and a base layer 110. By providing the base mesa ring 109 on the annular element 103, the annular element 103 can be protected, and the sensitivity of crack detection can be further improved.

[0079] In some embodiments, the etch stop layer 106A comprises InGaP, InGaAs, GaAsP, AlGaAs, InAlAs, GaSb, or a combination thereof. In some embodiments, the etch stop layer 106A has a doping concentration on the same order of magnitude as that of the secondary collector layer 104A. In these embodiments, the doping concentration of the etch stop layer 106A is 1e18 cm⁻¹. -3 Up to 1e20cm -3 Within the range between 5 nm and 200 nm. If the doping concentration of the etch stop layer 106A is too high, the dopant may not be fully activated, and reliability may deteriorate. If the doping concentration of the etch stop layer 106A is too low, the collector resistance may increase. In some embodiments, the etch stop layer 106A may have a thickness between 5 nm and 200 nm. If the etch stop layer 106A is too thick, the collector resistance may increase. If the etch stop layer 106A is too thin, it may not be sufficient to stop subsequent etching processes. The etch stop layer 106A can be formed by molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), hydride vapor phase epitaxy (HVPE), other suitable methods, or combinations thereof. The etch stop layer 106A can be doped by in-situ doping.

[0080] In some embodiments, the secondary collector layer 104A may be referred to as the bottom secondary collector layer 104A, and the secondary collector layer 104B may be referred to as the upper secondary collector layer 104B. In some embodiments, the secondary collector layer 104B has a thickness between 50 nm and 1500 nm. In some embodiments, the thickness of the secondary collector layer 104B is substantially the same as the thickness of the bottom secondary collector layer 104A. In some embodiments, the doping concentration of the secondary collector layer 104B is 1e18 cm⁻¹. -3 Up to 1e20cm -3 Within the range between. The materials and processes used to form the secondary collector layer 104B can be similar to or the same as those used to form the secondary collector layer 104A as previously described, and will not be repeated here for the sake of brevity.

[0081] In some embodiments, the collector layer 108 comprises a III-V semiconductor having a first conductivity type. The collector layer 108 may include a III-V semiconductor, such as GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, GaSb, or combinations thereof. In some embodiments, the collector layer 108 is an n-type GaAs layer. The collector layer 108 may be formed by molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), hydride vapor phase epitaxy (HVPE), other suitable methods, or combinations thereof. In some embodiments, the doping concentration of the collector layer 108 is greater than 0 cm⁻¹. -3 And less than or equal to 1e18cm -3 The collector layer 108 can be a multilayer structure with different doping concentrations.

[0082] In some embodiments, the base layer 110 comprises a III-V semiconductor having a second conductivity type. The base layer 110 may include a III-V semiconductor, such as GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, GaSb, or combinations thereof. In some embodiments, the base layer 110 may be a p-type GaAs layer that can be highly doped with C, Mg, Zn, Ca, Be, Sr, Ba, and Ra. The doping concentration of the base layer 110 may be between 1e18 cm⁻¹. -3 up to 1e20cm -3 The range between these parameters. The base layer 110 can be formed by molecular beam epitaxy, metal-organic chemical vapor deposition, chemical vapor deposition, hydride vapor phase epitaxy, another suitable method, or a combination thereof.

[0083] In some embodiments, an active device (e.g., a heterojunction bipolar transistor, a high electron mobility transistor, or a combination thereof) may be provided in region 201. For example, Figure 9 The semiconductor structure 100F is shown in some embodiments of this disclosure. For example... Figure 9 As shown, according to some embodiments of this disclosure, a heterojunction bipolar transistor 130 is formed in region 201. It should be noted that, according to some embodiments of this disclosure, for simplicity, the protective structure 105 is... Figure 9 The image is shown as a single layer. In some embodiments, the etch stop layer 106A, the secondary collector layer 104B, the collector layer 108, and the base layer 110 may be formed simultaneously in the base pedestal ring 109 and the heterojunction bipolar transistor 130. The materials and processes of these components will not be described in detail here.

[0084] In some embodiments, the heterojunction bipolar transistor 130 further includes an emitter layer 112 formed on the base layer 110. In some embodiments, the emitter layer 112 includes a III-V semiconductor having a first conductivity type. The emitter layer 112 may include a III-V semiconductor, such as GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, or a combination thereof. In some embodiments, the emitter layer 112 is an n-type InGaP layer. The emitter layer 112 may be a multilayer structure. In some embodiments, the emitter layer 112 includes an n-type InGaP layer at the bottom and an n-type GaAs layer (not shown) at the top. In some embodiments, the materials of the emitter layer 112 and the base layer 110 are different materials with different band gaps. Therefore, a heterojunction can be formed at the interface between the emitter layer 112 and the base layer 110. The emitter layer 112 may be formed by molecular beam epitaxy, metal-organic chemical vapor deposition, chemical vapor deposition, hydride vapor phase epitaxy, another suitable method, or a combination thereof.

[0085] In some embodiments, the heterojunction bipolar transistor 130 may further include an emitter cap layer 114 formed on the emitter layer 112. In some embodiments, the emitter cap layer 114 includes a III-V semiconductor having a first conductivity type. The emitter cap layer 114 may include a III-V semiconductor, such as GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, or combinations thereof. In some embodiments, the emitter cap layer 114 is a highly doped n-type InGaAs layer, which may facilitate the formation of an ohmic contact between the emitter cap layer 114 and the subsequently formed emitter electrode. The emitter cap layer 114 may be formed by molecular beam epitaxy, metal-organic chemical vapor deposition, chemical vapor deposition, hydride vapor phase epitaxy, another suitable method, or a combination thereof.

[0086] In some embodiments, the heterojunction bipolar transistor 130 may further include an emitter electrode 116 formed on the emitter capping layer 114. The emitter electrode 116 may include Ti, Al, Au, Pd, Pt, Cu, W, other suitable metals, alloys thereof, or combinations thereof. The emitter electrode material may first be formed on the emitter capping layer 114 by electroplating, sputtering, resistance heating evaporation, physical vapor deposition (PVD), chemical vapor deposition, atomic layer deposition, other suitable methods, or combinations thereof. Then, in some embodiments, the electrode material is patterned using optical lithography and etching processes, thus forming the emitter electrode 116.

[0087] In some embodiments, the heterojunction bipolar transistor 130 may further include a base electrode 118 formed on the base layer 110. In some embodiments, the process and materials used to form the base electrode 118 may be the same as or similar to those used to form the emitter electrode 116. For the sake of brevity, these processes and materials will not be described in detail here.

[0088] In some embodiments, the heterojunction bipolar transistor 130 may further include a collector electrode 124 formed on and electrically connected to the secondary collector layer 104B. The collector electrode 124 may include a conductive material, such as Ti, Al, Au, Pd, Pt, Cu, W, other suitable metals, alloys thereof, or combinations thereof. The process for forming the collector electrode 124 may be the same as or similar to the process for forming the emitter electrode 116. For simplicity, these processes will not be described further here. In some embodiments, a protective structure 105 covers the heterojunction bipolar transistor 130, and the collector electrode 124 may be partially exposed from the protective structure 105.

[0089] In some embodiments, the secondary collector layer 104A beneath the heterojunction bipolar transistor 130 may be referred to as a collector mesa, and the etch stop layer 106A, secondary collector layer 104B, collector layer 108, and base layer 110 of the heterojunction bipolar transistor 130 may be referred to as a base mesa. In some embodiments, at least a portion of region 202 (e.g., ring element 103) and the collector mesa is formed in the secondary collector layer 104A. In some embodiments, the ring element 103 may be referred to as the lower portion of region 202, the base mesa ring 109 may be referred to as the upper portion of region 202, and the collector mesa and the lower portion of region 202 are formed in the secondary collector layer 104A. In some embodiments, the base plateau and the upper part of region 202 are formed in the same semiconductor layer disposed on the secondary collector layer 104A (e.g., etch stop layer 106A, secondary collector layer 104B, collector layer 108 and base layer 110).

[0090] In summary, this disclosure provides some embodiments of a III-V group semiconductor chip, including a device region and a doped semiconductor ring region. The doped semiconductor ring region surrounds the device region. At least one active device is formed in the device region. Therefore, cracks formed at the edge of the semiconductor chip can be easily detected.

[0091] While the embodiments and advantages of this disclosure have been disclosed above, it should be understood that any person skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of this disclosure. Furthermore, the scope of protection of this disclosure is not limited to the processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps described in the specific embodiments of the specification. Any current or future processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps can be understood from the content of this disclosure, and can be used according to this disclosure as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of this disclosure also includes combinations of various claim claims and embodiments.

Claims

1. A III-V group semiconductor chip, characterized in that, The III-V semiconductor chip includes a device region and a doped semiconductor ring region surrounding the device region: One substrate; A primary collector layer is formed on the substrate; A protective layer is disposed on the secondary collector layer; and A pair of conductive pads electrically connect the doped semiconductor ring region; One of the heterojunction bipolar transistors is formed in the device region, and the heterojunction bipolar transistor includes a collector platform and a base platform, with the base platform formed on the collector platform. At least a portion of the doped semiconductor annular region and the collector platform are formed in the secondary collector layer.

2. The III-V group semiconductor chip as described in claim 1, characterized in that, The conductive pads are formed diagonally on the III-V semiconductor chip.

3. The III-V group semiconductor chip as described in claim 1, characterized in that, The doped semiconductor ring region includes a first portion and a second portion, which are electrically connected in parallel to the pair of conductive pads.

4. The III-V group semiconductor chip as described in claim 1, characterized in that, The doped semiconductor annular region has a first width, and there is a first distance between an edge of the doped semiconductor annular region and an edge of the III-V semiconductor chip, and the ratio of the first width to the first distance is between 1 / 15 and 2.

5. A III-V group semiconductor chip, characterized in that, The III-V semiconductor chip includes a device region and a doped semiconductor ring conductive region surrounding the device region. One substrate; A primary collector layer is formed on the substrate, wherein the secondary collector layer includes a first insulating region; and A protective layer is disposed on the secondary collector layer, wherein the protective layer at least partially covers the doped semiconductor annular conductive region.

6. The III-V group semiconductor chip as described in claim 5, characterized in that, A heterojunction bipolar transistor is formed in the device region, and the heterojunction bipolar transistor includes a collector platform and a base platform, the base platform being formed on the collector platform.

7. The III-V group semiconductor chip as described in claim 6, characterized in that, At least a portion of the doped semiconductor annular conductive region and the collector plateau are formed in the secondary collector layer.

8. The III-V group semiconductor chip as described in claim 6, characterized in that, The doped semiconductor annular conductive region includes a lower portion and an upper portion, with the upper portion above the lower portion. The collector platform and the lower portion of the doped semiconductor annular conductive region are formed in the secondary collector layer.

9. The III-V group semiconductor chip as described in claim 8, characterized in that, The base plateau and the upper part of the doped semiconductor annular conductive region are formed in a semiconductor layer, which is disposed on the secondary collector layer.

10. The III-V group semiconductor chip as described in claim 5, characterized in that, The doped semiconductor annular conductive region is formed between the first insulating region and a second insulating region of the secondary collector layer.

11. The III-V group semiconductor chip as described in claim 7, characterized in that, The protective layer includes: A first dielectric layer is disposed on the secondary collector layer; A second dielectric layer is disposed on the first dielectric layer; and A third dielectric layer is disposed on the second dielectric layer and covers one sidewall of the first dielectric layer and one sidewall of the second dielectric layer.

12. The III-V group semiconductor chip as described in claim 11, characterized in that, The protective layer further includes a fourth dielectric layer disposed on the third dielectric layer, and a stepped interface is formed between the third dielectric layer and the fourth dielectric layer.

13. The III-V semiconductor chip as described in claim 12, characterized in that, The width of the stepped interface is smaller than the width of the doped semiconductor annular conductive region.

14. The III-V semiconductor chip as described in claim 11, characterized in that, The third dielectric layer contacts the secondary collector layer.

15. The III-V group semiconductor chip as described in claim 5, characterized in that, The protective layer includes a guide hole.

16. The III-V semiconductor chip as described in claim 15, characterized in that, One edge of the doped semiconductor annular conductive region is aligned with one edge of the protective layer.

17. The III-V group semiconductor chip as described in claim 15, characterized in that, It also includes a conductive pad that is electrically connected to the doped semiconductor annular conductive region via the via.

18. The III-V group semiconductor chip as described in claim 17, characterized in that, The conductive pad is located on the protective layer.

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