Display panel and display device
By setting an electrostatic discharge protection unit in the display area, the problem that the bezel width cannot be further reduced in the prior art is solved, realizing an ultra-narrow bezel design for the display panel while ensuring the effectiveness of electrostatic protection.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI TIANMA MICRO ELECTRONICS CO LTD
- Filing Date
- 2022-11-07
- Publication Date
- 2026-06-19
AI Technical Summary
Existing technologies cannot simultaneously meet the requirements of high resolution and electrostatic protection in display panels that strive for extremely narrow bezels, thus preventing further reduction in bezel width.
Electrostatic discharge protection units are installed within the display area of the display panel, avoiding the need for additional bezel width on the edge side to accommodate these units, thereby reducing the bezel width.
It achieves an ultra-narrow bezel design for the display panel while ensuring the effectiveness of electrostatic protection and the ultra-narrow bezel design of the display panel.
Smart Images
Figure CN115602683B_ABST
Abstract
Description
[Technical Field]
[0001] This application relates to the field of display technology, and in particular to a display panel and display device. [Background Technology]
[0002] In recent years, narrow bezel and borderless displays have become important development directions for high-end displays.
[0003] In the pursuit of ultra-narrow bezels, some have attempted to omit the shift register circuitry used to provide signals to the scan lines to reduce bezel width. This approach requires adding gate leads in the same direction as the data lines, but this solution is only suitable for low-resolution displays. Otherwise, the aperture ratio of the display area will be significantly reduced. Furthermore, the resolutions this method can handle do not meet current consumer demands. To further meet current resolution requirements and achieve narrow bezels, flexible organic light-emitting diode (OLED) displays have gained popularity. By bending the circuitry in the bezel area to the back of the display surface, a borderless effect is achieved for the consumer.
[0004] However, flexible organic light-emitting displays are difficult to apply to all current display scenarios due to their high price, short lifespan, poor stability, inability to withstand high temperature and humidity, and poor corrosion resistance. Therefore, pursuing ultra-narrow bezels remains an urgent problem to be solved in the display field.
[0005] [Application Content]
[0006] In view of this, embodiments of this application provide a display panel and a display device to solve the above problems.
[0007] In a first aspect, embodiments of this application provide a display panel, which includes a plurality of sub-pixels and a plurality of electrostatic discharge protection units; wherein, the display panel includes a first edge, and the sub-pixels adjacent to the first edge form a first sub-pixel group, and each sub-pixel in the first sub-pixel group is arranged along a first direction, and an electrostatic discharge protection unit is disposed between at least some of the adjacent two sub-pixels in the first sub-pixel group.
[0008] In one implementation of the first aspect, the display panel includes a second edge disposed opposite to the first edge along a second direction, the second direction intersecting the first direction; the display panel includes pins located on a side near the second edge, the pins being used for electrical connection with a circuit board.
[0009] In one implementation of the first aspect, the sub-pixel includes a light-emitting device; in the first sub-pixel group, the electrostatic discharge protection unit is located between adjacent light-emitting devices.
[0010] In one implementation of the first aspect, the display panel further includes a third edge and a fourth edge disposed opposite to each other along a first direction, and the first sub-pixel group includes sub-pixels adjacent to the third edge; there is no electrostatic discharge protection unit on the side of the first sub-pixel group near the third edge.
[0011] In one implementation of the first aspect, the first sub-pixel group further includes a sub-pixel adjacent to the fourth edge; there is no electrostatic discharge protection unit on the side of the first sub-pixel group near the fourth edge.
[0012] In one implementation of the first aspect, a sub-pixel includes a pixel circuit and a light-emitting device; in the same sub-pixel of the first sub-pixel group, along a second direction, the pixel circuit is located on the side of the light-emitting device away from the first edge, and the second direction intersects the first direction.
[0013] In one implementation of the first aspect, the number of sub-pixels in the first sub-pixel group is Q1, and the number of electrostatic discharge protection units is Q2, where Q1 ≤ Q2; wherein, an electrostatic discharge protection unit is provided between any two adjacent sub-pixels in the first sub-pixel group.
[0014] In one implementation of the first aspect, a sub-pixel includes a pixel circuit and a light-emitting device; in the same sub-pixel of the first sub-pixel group, along the second direction, a portion of the pixel circuit is located on the side of the light-emitting device closer to the first edge, and the second direction intersects with the first direction; in the first sub-pixel group, multiple adjacent sub-pixels form a first pixel unit, and an electrostatic discharge protection unit is located between two adjacent first pixel units.
[0015] In one implementation of the first aspect, the number of sub-pixels in the first sub-pixel group is Q1, and the number of electrostatic discharge protection units is Q2, where Q1 ≤ Q2; wherein an electrostatic discharge protection unit is provided between any two adjacent first pixel units.
[0016] In one implementation of the first aspect, the first pixel unit comprises three adjacent sub-pixels.
[0017] In one implementation of the first aspect, the display panel includes a first voltage signal line, and the pixel circuit includes a first portion; in the same sub-pixel of the first sub-pixel group, along the second direction, the first portion is located on the side of the light-emitting device away from the first edge, and the first portion is electrically connected to the first voltage signal line.
[0018] In one implementation of the first aspect, the first voltage signal line includes a first sub-voltage signal line, which extends between two adjacent sub-pixels of the same first pixel unit; wherein, the end of the first sub-voltage signal line near the first edge is located between the first portions of two adjacent pixel circuits in the first pixel unit.
[0019] Secondly, embodiments of this application provide a display device, including a display panel as provided in the first aspect.
[0020] In one implementation of the second aspect, the display device is composed of multiple display panels as provided in the first aspect, wherein at least two display panels are spliced together along a second direction, the second direction intersecting the first direction.
[0021] In this embodiment, the electrostatic discharge (ESD) protection unit can be disposed between two adjacent sub-pixels of the first sub-pixel group. That is, the ESD protection unit can be located within the display area of the display panel. This eliminates the need for a certain border width on the first edge of the display panel to accommodate the ESD protection unit, thus reducing the border width on the first edge. Furthermore, since there is no need to place the ESD protection unit between the first sub-pixel group and the first edge of the display panel, the border threshold width reserved on the first edge of the display panel to prevent damage to the ESD protection unit can be avoided. This further reduces the border width on the first edge, thereby facilitating the achievement of an extremely narrow border for the display panel. [Attached Image Description]
[0022] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0023] Figure 1 A schematic diagram of a display panel provided in an embodiment of this application;
[0024] Figure 2 This is a schematic diagram of yet another display panel provided in an embodiment of this application;
[0025] Figure 3 This is a schematic diagram illustrating the connection between a display panel and a circuit board, provided in an embodiment of this application.
[0026] Figure 4 A schematic diagram of yet another display panel provided in an embodiment of this application;
[0027] Figure 5 A schematic diagram of yet another display panel provided in an embodiment of this application;
[0028] Figure 6 This is a partial layout diagram of a first sub-pixel group provided in an embodiment of this application;
[0029] Figure 7 A schematic diagram of a pixel circuit provided in an embodiment of this application;
[0030] Figure 8 for Figure 7 The image shows a timing diagram of a pixel circuit.
[0031] Figure 9 A schematic diagram of yet another display panel provided in an embodiment of this application;
[0032] Figure 10 for Figure 9 A schematic diagram of the first sub-pixel group in the middle;
[0033] Figure 11 A schematic diagram of yet another pixel circuit provided in an embodiment of this application;
[0034] Figure 12 A schematic diagram of the layout of a first pixel unit provided in an embodiment of this application;
[0035] Figure 13 A schematic diagram of yet another display panel provided in an embodiment of this application;
[0036] Figure 14 A schematic diagram of a display device provided in an embodiment of this application;
[0037] Figure 15 This is a schematic diagram of another display device provided in an embodiment of this application.
Detailed Implementation Methods
[0038] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.
[0039] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.
[0040] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.
[0041] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.
[0042] In the description of this specification, it should be understood that the terms "substantially", "approximately", "about", "about", "generally", "largely" used in the claims and embodiments of this application refer to values that can be generally agreed upon within a reasonable range of process operations or tolerances, rather than a precise value.
[0043] It should be understood that although the terms "first," "second," etc., may be used to describe directions, edges, etc. in the embodiments of this application, these directions, edges, etc., should not be limited to these terms. These terms are only used to distinguish directions, edges, etc., from each other. For example, without departing from the scope of the embodiments of this application, a first direction may also be referred to as a second direction, and similarly, a second direction may also be referred to as a first direction.
[0044] In the field of display technology, the pixel array in a display panel typically includes multiple columns of data lines and multiple rows of gate lines intersecting the data lines. When displaying a frame, the gate lines sequentially output enable signals to control the transistors in the pixel array to turn on, and at the same time, the data lines provide data signals to the pixel units in the corresponding rows of the pixel array.
[0045] In display panels, to prevent data cables from being damaged by electrostatic discharge (ESD), an ESD protection unit is typically installed and electrically connected to the far end of the data cable. However, in related technologies, the ESD protection unit is usually located in the bezel area of the display panel, requiring the data cable in the display area to extend a predetermined length into the bezel area to connect with the ESD protection unit. Furthermore, during large-panel cutting, a certain bezel threshold width needs to be reserved to avoid cutting into the ESD protection unit. This results in a relatively large bezel area for the display panel, which is not conducive to achieving an extremely narrow bezel.
[0046] Through meticulous and in-depth research, the applicant in this case has provided a solution to the problems existing in the prior art.
[0047] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of this application.
[0048] This application embodiment provides a display panel 01, such as Figure 1 As shown, the display panel 01 includes multiple sub-pixels 10 and multiple electrostatic discharge protection units 20. The electrostatic discharge protection units 20 are used to protect important components in the display panel 01 from electrostatic damage.
[0049] For example, the electrostatic discharge protection unit 20 can be electrically connected to the data line to protect the data line in the display panel 01 from electrostatic discharge.
[0050] Specifically, the electrostatic discharge protection unit 20 can be electrically connected to the data line one by one, and the electrostatic discharge protection unit 20 is electrically connected to the far end of the data line.
[0051] Of course, in some other embodiments, the electrostatic discharge protection unit 20 may also be electrically connected to the grid line to protect the grid line from electrostatic breakdown.
[0052] The display panel 01 includes a first edge A1, and the sub-pixels 10 adjacent to the first edge A1 form a first sub-pixel group P1. Each sub-pixel 10 in the first sub-pixel group P1 is arranged along a first direction X.
[0053] Optionally, the first direction X is the row direction in the display panel 01, and the first edge A1 extends along the row direction of the display panel 01, that is, the first sub-pixel group P1 can be the first row of sub-pixels in the display panel 01 adjacent to the first edge A1.
[0054] It should be noted that in the embodiments of this application, the first edge A1 is a cutting edge of the display panel 01, that is, the first edge A1 is an outermost edge of the display panel 01, and the first edge A1 may be the upper edge of the display panel 01.
[0055] In the first sub-pixel group P1, an electrostatic discharge protection unit 20 is provided between at least two partially adjacent sub-pixels 10.
[0056] In other words, the electrostatic discharge protection unit 20 can be disposed between two adjacent sub-pixels 10 in the first sub-pixel group P1. Here, the electrostatic discharge protection unit 20 is disposed between two adjacent sub-pixels 10, meaning that the projections of the two adjacent sub-pixels 10 in the first direction X overlap with the projection of the electrostatic discharge protection unit 20 in the first direction X.
[0057] In this embodiment, the electrostatic discharge protection unit 20 can be disposed between two adjacent sub-pixels 10 of the first sub-pixel group P1. That is, the electrostatic discharge protection unit 20 can be located in the display area of the display panel 01. Therefore, it is not necessary to set a certain border width on the first edge A1 side of the display panel 01 to place the electrostatic discharge protection unit 20, which is beneficial to reducing the border width of the display panel 01 on the first edge A1 side. At the same time, since it is not necessary to set the electrostatic discharge protection unit 20 between the first sub-pixel group P1 and the first edge A1 of the display panel 01, it is also possible to avoid the border threshold width reserved on the first edge A1 side of the display panel 01 to damage the electrostatic discharge protection unit 20. This is beneficial to further reduce the border width of the display panel 01 on the first edge A1 side, thereby facilitating the realization of an extremely narrow border of the display panel 01.
[0058] Figure 2 This is a schematic diagram of yet another display panel provided in an embodiment of this application. Figure 3 This is a schematic diagram illustrating the connection between a display panel and a circuit board, provided in an embodiment of this application.
[0059] like Figure 2 As shown, in one embodiment of this application, the display panel 01 includes a second edge A2, which is disposed opposite to the first edge A1 along a second direction Y, and the second direction Y intersects with the first direction X.
[0060] Optionally, the second direction Y is the column direction of the display panel 01.
[0061] It should be noted that in the embodiments of this application, the second edge A2 is a cutting edge of the display panel 01, that is, the second edge A2 is an outermost edge of the display panel 01, and the second edge A2 may be the lower edge of the display panel 01.
[0062] The display panel 01 includes a pin BY located on the side of the display panel 01 near the second edge A2. The pin BY is used for electrical connection with the circuit board 02. The circuit board 02 is used to provide various signals to the display panel 01 to drive its display. Exemplarily, the circuit board 02 can be a flexible printed circuit (FPC), a chip on film (COF), or a transition printed circuit board, etc.
[0063] In this embodiment, the signal provided by the circuit board 02 enters the display panel 01 through the second edge A2. The first edge A1 can be the far edge of the display panel 01 that receives the signal. The number of traces on the first edge A1 side of the display panel 01 is relatively small, which makes it possible to set the electrostatic discharge protection unit 20 in the first sub-pixel group P1 near the first edge A1.
[0064] In one implementation of the embodiments of this application, such as Figure 3 As shown, circuit board 02 can be located on one side of the backlight surface of display panel 01, and pin BY is electrically connected to circuit board 02 via side trace CL. Of course, in some other embodiments, circuit board 02 can also be directly bonded to pin BY, and then circuit board 02 is bent to the backlight side of display panel 01.
[0065] Figure 4 This is a schematic diagram of yet another display panel provided for embodiments of this application.
[0066] In one embodiment of this application, such as Figure 4 As shown, sub-pixel 10 includes pixel circuit 11 and light-emitting device 12. In the first sub-pixel group P1, electrostatic discharge protection unit 20 is located between adjacent light-emitting devices 12.
[0067] Please continue to refer to this. Figure 4 The display panel 01 also includes multiple first signal lines DL1, which extend along the second direction Y and are arranged along the first direction X.
[0068] The first signal line DL1 is electrically connected to the pixel circuit 11 in the sub-pixel 10 and can be used to transmit data signals to the pixel circuit 11. That is, the first signal line DL1 can be a data line in the display panel 01.
[0069] It is understood that the pixel circuits 11 in the same column of sub-pixels 10 can be electrically connected to the same first signal line DL1. The first signal line DL1 usually extends from the second edge A2 side to the pixel circuits 11 adjacent to the first edge A1. That is, in the first sub-pixel group P1, the first signal line DL1 is usually included between two adjacent pixel circuits 11.
[0070] Therefore, in this embodiment, the electrostatic discharge protection unit 20 is placed between adjacent light-emitting devices 12 in the first sub-pixel group P1, which can avoid the tightness of the wiring space between the pixel circuits 11 and is beneficial to the fabrication of the display panel 01.
[0071] In one application scenario of this application embodiment, the electrostatic discharge protection unit 20 can be electrically connected to the first signal line DL1 in a one-to-one correspondence, in order to protect the first signal line DL1 from electrostatic breakdown.
[0072] Specifically, such as Figure 4 As shown, the electrostatic discharge protection unit 20 can be electrically connected to one end of the first signal line DL1 near the first edge A1 (the far end of the first signal line DL1) to protect the first signal line DL1 from electrostatic breakdown without affecting the normal signal transmission of the first signal line DL1.
[0073] In one embodiment of this application, please continue to refer to Figure 1 The display panel 01 also includes a third edge A3 and a fourth edge A4 disposed opposite to each other along the first direction X. The first pixel group P1 includes a sub-pixel 10 adjacent to the third edge A3, and there is no electrostatic discharge protection unit 20 on the side of the first pixel group P1 near the third edge A3.
[0074] It should be noted that, in the embodiments of this application, the third edge A3 and the fourth edge A4 are two cutting edges of the display panel 01 that are arranged opposite to each other along the first direction X. That is, the third edge A3 and the fourth edge A4 are the two outermost edges of the display panel 01, and the third edge A3 and the fourth edge A4 can be the left edge and the right edge of the display panel 01, respectively.
[0075] In this embodiment, the electrostatic discharge protection unit 20 is no longer provided on the side of the first sub-pixel group P1 near the third edge A3. Therefore, it is unnecessary to provide a certain border width on the third edge A3 side of the display panel 01 to accommodate the electrostatic discharge protection unit 20, which helps to reduce the border width of the display panel 01 on the third edge A3 side. Simultaneously, since it is unnecessary to provide the electrostatic discharge protection unit 20 between the first sub-pixel group P1 and the third edge A3 of the display panel 01, it also avoids the need to reserve a border threshold width on the third edge A3 side of the display panel 01 to prevent damage to the electrostatic discharge protection unit 20. This further helps to reduce the border width of the display panel 01 on the third edge A3 side, thereby facilitating the further realization of an extremely narrow border for the display panel 01.
[0076] Furthermore, since the electrostatic discharge protection unit 20 can be electrically connected to the first signal line DL1, when the electrostatic discharge protection unit 20 is no longer provided on the side of the first sub-pixel group P1 near the third edge A3, the first signal line DL1 can also be no longer provided on the side of the first sub-pixel group P1 near the third edge A3. The first signal line DL1 electrically connected to the sub-pixel adjacent to the third edge A3 can be provided on the side of the sub-pixel 10 away from the third edge A3, thereby reducing the bezel width provided on the third edge side A3 of the display panel 01 in order to place the first signal line DL1, which is beneficial to further realize the extremely narrow bezel of the display panel 01.
[0077] Please continue to refer to this. Figure 1 In one embodiment of this application, the first pixel group P1 further includes a sub-pixel 10 adjacent to the fourth edge A4, and there is no electrostatic discharge protection unit 20 on the side of the first pixel group P1 near the fourth edge A4.
[0078] In this embodiment, the electrostatic discharge protection unit 20 is no longer provided on the side of the first sub-pixel group P1 near the fourth edge A4. Therefore, it is unnecessary to provide a certain border width on the fourth edge A4 side of the display panel 01 to accommodate the electrostatic discharge protection unit 20, which helps to reduce the border width of the display panel 01 on the fourth edge A4 side. Simultaneously, since it is unnecessary to provide the electrostatic discharge protection unit 20 between the first sub-pixel group P1 and the fourth edge A4 of the display panel 01, it also avoids reserving a border threshold width on the fourth edge A4 side of the display panel 01 to prevent damage to the electrostatic discharge protection unit 20. This further helps to reduce the border width of the display panel 01 on the fourth edge A4 side, thereby facilitating the further realization of an extremely narrow border for the display panel 01.
[0079] Furthermore, since the electrostatic discharge protection unit 20 can be electrically connected to the first signal line DL1, when the electrostatic discharge protection unit 20 is no longer provided on the side of the first sub-pixel group P1 near the fourth edge A4, the first signal line DL1 can also be no longer provided on the side of the first sub-pixel group P1 near the fourth edge A4. The first signal line DL1 electrically connected to the sub-pixel adjacent to the fourth edge A4 can be provided on the side of the sub-pixel 10 away from the fourth edge A4, thereby reducing the bezel width provided on the fourth edge side A4 of the display panel 01 in order to place the first signal line DL1, which is beneficial to further realize the extremely narrow bezel of the display panel 01.
[0080] Figure 5 This is a schematic diagram of yet another display panel provided in an embodiment of this application. Figure 6 This is a partial layout diagram of a first sub-pixel group provided in an embodiment of this application.
[0081] In one embodiment of this application, such as Figure 4 and Figure 5 As shown, sub-pixel 10 includes pixel circuit 11 and light-emitting device 12, and pixel circuit 11 is used to drive light-emitting device 12 to emit light.
[0082] In the same sub-pixel 10 of the first sub-pixel group P1, along the second direction Y, the pixel circuit 11 is located on the side of the light-emitting device 12 away from the first edge A1, and the second direction Y intersects with the first direction X.
[0083] Optionally, the first direction X is the row direction in the display panel 01, and the second direction Y is the column direction in the display panel 01.
[0084] In this embodiment, the light-emitting device 12 can be a sub-millimeter light-emitting diode (Mini-LED), and the pixel circuit 11 can be a common 7T1C circuit (including seven transistors and one storage capacitor). Of course, in some other embodiments, the pixel circuit 11 can also include more transistors and storage capacitors than the 7T1C circuit, for example, the pixel circuit 11 can be a 13T2C circuit (including thirteen transistors and two storage capacitors).
[0085] It should be noted that, among the sub-pixels 10 outside the first sub-pixel group P1, along the second direction Y, the pixel circuit 11 of the same sub-pixel 10 can be located on the side of its included light-emitting device 12 closer to the first edge A1. Of course, among the sub-pixels 10 outside the first sub-pixel group P1, along the second direction Y, the pixel circuit 11 of the same sub-pixel 10 can also be located on the side of its included light-emitting device 12 farther from the first edge A1. This application embodiment does not specifically limit this.
[0086] Combination Figure 5 and Figure 6As shown, the display panel 01 also includes multiple second signal lines DL2 extending along the second direction Y, and the second signal lines DL2 are electrically connected to the sub-pixel 10.
[0087] Specifically, such as Figure 6 As shown, the second signal line DL2 can be electrically connected to the pixel circuit 11 or the light-emitting device 12 via a connecting line extending along the second direction X. The second signal line DL2 includes a first voltage signal line PVDD and a second voltage signal line PVEE. The first voltage signal line PVDD can be electrically connected to the pixel circuit 11, and the second voltage signal line PVEE is electrically connected to the light-emitting device 12.
[0088] Furthermore, the light-emitting device 12 may include two connection points Z1 and Z2. Connection point Z1 is electrically connected to the pixel circuit 11, and connection point Z2 is electrically connected to the second voltage signal line PVEE. Connection point Z2 is located on the side of connection point Z1 away from the first edge A1, so as to ensure that in the first sub-pixel group P1, the second voltage signal line PVEE does not need to extend to the area close to the first edge A1, so that there is sufficient space between two adjacent light-emitting devices 12.
[0089] In this embodiment, the pixel circuit 11 of the sub-pixel 10 in the first sub-pixel group P1 is located on the side of the light-emitting device 12 that it is electrically connected to, away from the first edge A1. Therefore, the first voltage signal line PVDD electrically connected to the pixel circuit 11 does not need to extend to the area close to the first edge A1. Compared with the arrangement where the pixel circuit 11 is located on the side of the light-emitting device 12 close to the first edge A1, this embodiment shortens the extension length of the first voltage signal line PVDD and does not need to extend to the area between two adjacent light-emitting devices 12. This provides space for the electrostatic discharge protection unit 20 to be placed between two adjacent light-emitting devices 12 in the first sub-pixel group P1.
[0090] Furthermore, since the pixel circuit 11 in the sub-pixel 10 of the first sub-pixel group P1 is located on the side of the light-emitting device 12 away from the first edge A1, there is no need to set up the pixel circuit 11 (such as transistors or storage capacitors) on the side of the light-emitting device 12 close to the first edge A1 in the first sub-pixel group P1. That is, there is no need to set up the pixel circuit 11 between the light-emitting device 12 adjacent to the first edge A1 and the first edge A1. Therefore, there is no need to set up the pixel circuit 11 trace between two adjacent light-emitting devices 12 in the first sub-pixel group P1, so that the number of traces between two adjacent light-emitting devices 12 in the first sub-pixel group P1 is very small or even non-existent, thus reserving space for the electrostatic discharge protection unit 20 to be set between any two adjacent light-emitting devices 12.
[0091] In this embodiment of the application, an electrostatic discharge protection unit 20 can be provided between any two adjacent sub-pixels 10 in the first sub-pixel group P1.
[0092] Figure 7 This is a schematic diagram of a pixel circuit provided in an embodiment of this application. Figure 8 for Figure 7 The diagram shows a timing diagram of a pixel circuit.
[0093] To illustrate the technical solutions of the embodiments of this application more clearly, the following is combined with... Figure 7 and Figure 8 right Figure 7 The working process of the pixel circuit shown will be explained.
[0094] like Figure 7 As shown, the pixel circuit 11 includes a driving transistor Md, a data voltage writing transistor M1, a power supply voltage writing transistor M2, a first reset transistor M3, a threshold voltage grabbing transistor M4, a light emission control transistor M5, and a second reset transistor M6. The driving transistor Md is used to provide light emission driving current for the light emission device 12.
[0095] Specifically, the source of the data voltage writing transistor M1 is electrically connected to the first signal line DL1, the drain is electrically connected to the source of the driving transistor Md, and the gate is electrically connected to the first scan line S1; the source of the power supply voltage writing transistor M2 is electrically connected to the first voltage signal line PVDD, the drain is electrically connected to the source of the driving transistor Md, and the gate is electrically connected to the light emission control signal line EM; the source of the first reset transistor M3 is electrically connected to the reset signal line SL1, the drain is electrically connected to the gate of the driving transistor Md, and the gate is electrically connected to the second scan line S2; and the threshold voltage grabbing transistor M4... The source of the light-emitting control transistor M5 is electrically connected to the drain of the driving transistor Md, the drain is electrically connected to the gate of the driving transistor Md, and the gate is electrically connected to the first scan line S1; the source of the light-emitting control transistor M5 is electrically connected to the drain of the driving transistor Md, the drain is electrically connected to the first electrode of the light-emitting device 12, and the gate is electrically connected to the light-emitting control signal line EM; the source of the second reset transistor M6 is electrically connected to the reset signal line SL1, the drain is electrically connected to the first electrode of the light-emitting device 12, the gate is electrically connected to the first scan line S1, and the second electrode of the light-emitting device 12 is electrically connected to the second voltage signal line PVEE.
[0096] It should be noted that the following explanation uses P-type transistors as an example, where the data voltage writing transistor M1, the power supply voltage writing transistor M2, the first reset transistor M3, the threshold voltage grabbing transistor M4, the light emission control transistor M5, and the second reset transistor M6 are all data voltage writing transistors.
[0097] In a frame of the display panel 01, the operation of the pixel circuit 11 includes a reset phase t1, a data writing phase t2, and a light emission phase t3.
[0098] During the reset phase t1, the second scan line S2 transmits an enable signal (low level), turning on the first reset transistor M3. The first scan line S1 and the light-emitting control signal line EM transmit disable signals (high level), turning off the data voltage writing transistor M1, threshold voltage grabbing transistor M4, power supply voltage writing transistor M2, light-emitting control transistor M5, and the second reset transistor M6. Simultaneously, the reset signal line SL1 transmits the reset voltage Vref, which is transmitted through the enabled first reset transistor M3 to the gate of the driving transistor Md, completing the reset of the gate of the driving transistor Md.
[0099] During the data writing phase t2, the first scan line S1 transmits an enable signal (low level), turning on the data voltage writing transistor M1, threshold voltage grabbing transistor M4, and second reset transistor M6. The second scan line S2 and the light-emitting control signal line EM transmit enable signals (high level), turning off the first reset transistor M3, power supply voltage writing transistor M2, and light-emitting control transistor M5. Simultaneously, the first signal line DL1 transmits the data voltage Vdata. At the beginning of the data writing phase t2, the gate potential of the driving transistor Md is the reset voltage Vref, and the source potential is the data voltage Vdata. The potential difference between the source and gate of the driving transistor Md is (Vdata - Vref), which is greater than 0. Therefore, the driving transistor Md is turned on, and the data voltage Vdata is transmitted to the gate of the driving transistor Md through the turned-on driving transistor Md and the turned-on threshold voltage grabbing transistor M4, causing the gate potential of the driving transistor Md to gradually increase. When the gate potential of the driving transistor Md equals (Vdata - |Vth|), the driving transistor Md is turned off. Where Vth is the threshold voltage of the driving transistor Md.
[0100] Simultaneously, the reset voltage Vref resets the first electrode of the light-emitting device 12 through the activated second reset transistor M6. Optionally, the light-emitting device 12 is a sub-millimeter light-emitting diode (Mini-LED), and the reset voltage Vref resets the anode of the sub-millimeter light-emitting diode through the activated second reset transistor M6.
[0101] During the light-emitting stage t3, the first scan line S1 and the second scan line S2 transmit a turn-off signal, i.e., a high-level signal, turning off the data voltage writing transistor M1, the first reset transistor M3, the threshold voltage grabbing transistor M4, and the second reset transistor M6. The light-emitting control signal line EM transmits an turn-on signal, i.e., a low-level signal, turning on the power supply voltage writing transistor M2 and the light-emitting control transistor M5. Simultaneously, the first voltage signal line PVDD transmits the power supply voltage, i.e., the potential of the source of the driving transistor Md is the power supply voltage. Since the potential of the power supply voltage is greater than the potential of the data voltage Vdata, the driving transistor Md generates a driving current, which is transmitted to the light-emitting device 12 through the light-emitting control transistor M5, controlling the light-emitting device 12 to emit light.
[0102] It should be noted that, Figure 7 The first reset transistor M3 and the threshold voltage grabbing transistor M4 can be either single-gate or double-gate structures.
[0103] In one embodiment of this application, in the first sub-pixel group P1, the number of sub-pixels 10 is Q1, and the number of electrostatic discharge protection units 20 is Q2, where Q1 ≤ Q2. Specifically, an electrostatic discharge protection unit 20 is provided between any two adjacent sub-pixels 10 in the first sub-pixel group P1.
[0104] In this embodiment, the electrostatic discharge protection unit 20 can be disposed relatively evenly in the first sub-pixel group P1, which helps to ensure that the light-emitting devices 12 in the first sub-pixel group P1 can be disposed relatively evenly, thereby ensuring the brightness uniformity of the display panel 01.
[0105] It is understandable that the electrostatic discharge protection unit 20 can be electrically connected one-to-one with the data lines connecting the sub-pixels 10 to protect the data lines from electrostatic damage. Furthermore, to improve the display quality of the display panel 01, a bias voltage signal line electrically connected to the sub-pixels 10 is usually also provided. Therefore, in the first sub-pixel group P1, an electrostatic discharge protection unit 20 electrically connected to the bias voltage signal line can also be provided to protect the bias voltage signal line from electrostatic damage. Moreover, an electrostatic discharge protection unit 20 for protecting the scan lines (such as the first scan line S1 in the above embodiment) electrically connected to the pixel circuit 11 can also be provided in the first sub-pixel group P1. Therefore, in the first sub-pixel group P1, the number of electrostatic discharge protection units 20 is usually not less than the number of sub-pixels 10 included in the first sub-pixel group P1.
[0106] In this embodiment, since Q1≤Q2, the number of electrostatic discharge protection units 20 is greater than the number of gaps between two adjacent sub-pixels 10 in the first sub-pixel group P1. Therefore, the number of electrostatic discharge protection units 20 in some gaps is greater than the number of electrostatic discharge protection units 20 in other gaps.
[0107] For example, such as Figure 4 and Figure 5 As shown, the gap between two adjacent sub-pixels 10 in the first sub-pixel group P1 is M1. When Q1 = Q2, two electrostatic discharge protection units 20 can be set in one gap M1 in the first sub-pixel group P1, and one electrostatic discharge protection unit 20 can be set in other gaps M1.
[0108] For further information, please continue to refer to [link / reference]. Figure 5 In the display panel 01, three adjacent sub-pixels 10 along the first direction X can form a pixel Pix. The three sub-pixels 10 forming the pixel Pix can be blue sub-pixels, green sub-pixels, and red sub-pixels, respectively. The blue, red, and green sub-pixels are the three primary colors and can emit light to produce white dots. Full-color display is achieved by controlling the brightness ratio between each sub-pixel. Therefore, the pixel Pix can be the smallest unit for allocating color values in the display panel 01. The gap between adjacent pixel Pix can be set to be larger than the gap between sub-pixels 10 within the pixel Pix. When the electrostatic discharge protection unit 20 in the first sub-pixel group P1 is more than the gap M1, the number of electrostatic discharge protection units 20 set between two adjacent pixel Pix can be more than the number of electrostatic discharge protection units 20 set between adjacent sub-pixels 10 within the pixel Pix.
[0109] Figure 9 This is a schematic diagram of yet another display panel provided in an embodiment of this application. Figure 10 for Figure 9 A schematic diagram of the first sub-pixel group. Figure 11 This is a schematic diagram of yet another pixel circuit provided in an embodiment of this application. Figure 12 This is a schematic diagram of the layout of a first pixel unit provided in an embodiment of this application.
[0110] In one embodiment of this application, combined with Figure 9 and Figure 10 As shown, sub-pixel 10 includes pixel circuit 11 and light-emitting device 12, and pixel circuit 11 is used to drive light-emitting device 12 to emit light.
[0111] In the same sub-pixel 10 of the first sub-pixel group P1, along the second direction Y, part of the pixel circuit 11 is located on the side of the light-emitting device 12 closer to the first edge A1, and the other part of the pixel circuit 11 can be located on the side of the light-emitting device 12 away from the first edge A1. The second direction Y intersects with the first direction X, where the first direction X can be the row direction in the display panel 01, and the second direction Y can be the column direction in the display panel 01.
[0112] Specifically, such as Figure 10As shown, in the first sub-pixel group P1, the pixel circuit 11 may include a first part 11A and a second part 11B that are electrically connected to each other. The first part 11A is located on the side of the light-emitting device 12 away from the first edge A1, and the second part 11B is located on the side of the light-emitting device 12 close to the first edge A1.
[0113] In this embodiment, the light-emitting device 12 can be a sub-millimeter light-emitting diode (Mini-LED), and the pixel circuit 11 can be a common 7T1C circuit (including seven transistors and one storage capacitor). Of course, in some other embodiments, the pixel circuit 11 can also include more transistors and storage capacitors than the 7T1C circuit. For example, the pixel circuit 11 can also be a 13T2C circuit (including thirteen transistors and two storage capacitors).
[0114] In the first sub-pixel group P1, multiple adjacent sub-pixels 10 form a first pixel unit 100, and an electrostatic discharge protection unit 20 is located between two adjacent first pixel units 100. The electrostatic discharge protection unit 20 located between two adjacent first pixel units 100 is connected to the adjacent data lines respectively.
[0115] Optionally, the first pixel unit 100 includes three adjacent sub-pixels 10, and the three adjacent sub-pixels 10 emit different colors.
[0116] For example, the three sub-pixels 10 in the first pixel unit 100 can be a blue sub-pixel, a red sub-pixel, and a green sub-pixel, respectively. The blue, red, and green sub-pixels, as the three primary colors, can emit light to produce white dots, and full-color display can be achieved by controlling the brightness ratio between each sub-pixel.
[0117] Understandably, the pixel circuit 11 has a lot of traces, especially when it includes many transistors, making its structure relatively complex and connecting to many signal lines. In the first sub-pixel group P1, when a portion of the pixel circuit 11 is located on the side of the light-emitting device 12 closer to the first edge A1, the traces between this portion and the portion of the pixel circuit 11 located on the side of the light-emitting device 12 away from the first edge A1 typically need to pass through the gap between two adjacent light-emitting devices 12.
[0118] For example, such as Figure 11 As shown, the pixel circuit 11 includes transistors T1-T13 and capacitors C1 and C2. The connection method of transistors T1-T13 and capacitors C1 and C2 is as follows. Figure 11As shown, it will not be described again here. Among them, transistors T1-T7 and capacitor C1 can form the first part 11A of pixel circuit 11. The first part 11A is electrically connected to the first voltage signal line PVDD, the first fixed potential signal line Data, the reset signal line SL1, and the light-emitting device 12. The first part 11A is used to drive the light-emitting device 12 to emit light.
[0119] Transistors T8-T13 and capacitor C2 form the second part 11B of pixel circuit 11. The second part 11B is electrically connected to the first node N1 in the first part 11A. Furthermore, the second part 11B is also electrically connected to the first signal line DL1, the second fixed potential signal line VH2, the reset signal line SL1, and the pulse signal line Sweep. The pulse signal line Sweep can transmit a triangular wave signal. The second part 11B can be used to adjust the emission time of the light-emitting device 12.
[0120] Combination Figure 12 As shown, in the same first pixel unit 100, the traces between the first part 11A and the second part 11B of the pixel circuit 11 pass through the gap between two adjacent light-emitting devices 12. Furthermore, the connection lines between the second part 11B and the first signal line SL1, the reset signal line SL1, etc., can also pass through the gap between two adjacent light-emitting devices 12.
[0121] In this embodiment, the electrostatic discharge protection unit 20 is disposed between two adjacent first pixel units 100. This avoids the electrostatic discharge protection unit 20 occupying the gap between two adjacent light-emitting devices 12 in the same first pixel unit 100, ensuring a larger gap space between two adjacent light-emitting devices 12 in the same first pixel unit 100 to meet the routing requirements of the pixel circuit 11. At this time, the first signal line DL1 (data line) is routed from above the sub-pixel 10 to the corresponding electrostatic discharge protection unit 20 and electrically connected to it.
[0122] Moreover, the wiring of the pixel circuit 11 is mostly concentrated inside the first pixel unit 100, which makes the gap between two adjacent first pixel units 100 larger, thus providing space for the electrostatic discharge protection unit 20 to be placed between two adjacent first pixel units 100.
[0123] Figure 13 This is a schematic diagram of another display panel provided in an embodiment of this application.
[0124] In one implementation of the embodiments of this application, such as Figure 13 As shown, the display panel 01 includes multiple second signal lines DL2 extending along the second direction Y, and the second signal lines DL2 are electrically connected to the sub-pixels 10.
[0125] Combination Figure 12As shown, the second signal line DL2 can be electrically connected to the pixel circuit 11 or the light-emitting device 12 via a connecting line extending along the second direction X. The second signal line DL2 includes a first voltage signal line PVDD and a second voltage signal line PVEE. The first voltage signal line PVDD can be electrically connected to the pixel circuit 11, and the second voltage signal line PVEE is electrically connected to the light-emitting device 12.
[0126] The pixel circuit 11 includes a first part 11A in the same sub-pixel 10 of the first sub-pixel group P1, along the second direction Y. The first part 11A is located on the side of the light-emitting device 12 away from the first edge A1, and the first part 11A is electrically connected to the first voltage signal line PVDD.
[0127] It should be noted that, among the sub-pixels 10 outside the first sub-pixel group P1, along the second direction Y, the pixel circuits 11 of the same sub-pixel 10 can be located on the same side of the light-emitting devices 12 they include. For example Figure 13 In the sub-pixels 10 outside the first sub-pixel group P1, along the second direction Y, the pixel circuits 11 of the same sub-pixel 10 are all located on the side of the light-emitting device 12 included therein that is close to the first edge A1.
[0128] Of course, in the sub-pixels 10 outside the first sub-pixel group P1, along the second direction Y, the pixel circuit 11 of the same sub-pixel 10 may also be located on the side of its included light-emitting device 12 away from the first edge A1, or the pixel circuit 11 of the same sub-pixel 10 may be located on both sides of its included light-emitting device 12. This application embodiment does not specifically limit this.
[0129] In this implementation, in the first sub-pixel group P1, since the first voltage signal line PVDD is electrically connected to the first part 11A of the pixel circuit 11 which is far from the first edge A1, the first voltage signal line PVDD does not need to extend to the area close to the first edge A1. The extension length of the first voltage signal line PVDD can be shortened, thereby reserving space for the electrostatic discharge protection unit 20 to be set between two adjacent first pixel units 100.
[0130] Furthermore, the light-emitting device 12 may include two connection points Z1 and Z2. Connection point Z1 is electrically connected to the pixel circuit 11, and connection point Z2 is electrically connected to the second voltage signal line PVEE. Connection point Z2 is located on the side of connection point Z1 away from the first edge A1, so as to ensure that in the first sub-pixel group P1, the second voltage signal line PVEE does not need to extend to the area close to the first edge A1, so that there is sufficient space between two adjacent first pixel units 100.
[0131] In one embodiment of this application, please continue to refer to Figure 12The first voltage signal line PVDD includes a first sub-voltage signal line PVDD1, which extends between two adjacent sub-pixels 10 of the first pixel unit 100. The first sub-voltage signal line PVDD1 may be the portion of the first voltage signal line PVDD located inside the first pixel unit 100.
[0132] Among them, the end of the first sub-voltage signal line PVDD1 near the first edge A1 is located between the first portions 11A of two adjacent pixel circuits 11 in the first pixel unit 100.
[0133] In this embodiment, the first sub-voltage signal line PVDD1 is positioned between the first portions 11A of two adjacent pixel circuits 11 in the first pixel unit 100, near the first edge A1. This avoids the first sub-voltage signal line PVDD1 occupying the gap between two adjacent light-emitting devices 12 in the same first pixel unit 100, thereby further ensuring that the gap space between two adjacent light-emitting devices 12 in the same first pixel unit 100 is larger, so as to further meet the routing requirements of the pixel circuit 11.
[0134] In one embodiment of this application, please continue to refer to Figure 13 In the first sub-pixel group P1, the number of sub-pixels 10 is Q1, and the number of electrostatic discharge protection units 20 is Q2, where Q1 ≤ Q2. An electrostatic discharge protection unit 20 is provided between any two adjacent first pixel units 100 in the first sub-pixel group P1.
[0135] In this embodiment, the electrostatic discharge protection unit 20 can be disposed relatively evenly in the first sub-pixel group P1, which helps to ensure that the first pixel unit 100 in the first sub-pixel group P1 can be disposed relatively evenly, thereby ensuring the brightness uniformity of the display panel 01.
[0136] It is understood that the electrostatic discharge protection unit 20 can be electrically connected one-to-one with the data lines connecting the sub-pixels 10 to protect the data lines from electrostatic damage. Furthermore, to improve the display quality of the display panel 01, a bias voltage signal line electrically connected to the sub-pixels 10 is usually also provided. Therefore, in the first sub-pixel group P1, an electrostatic discharge protection unit 20 electrically connected to the bias voltage signal line is also provided to protect the bias voltage signal line from electrostatic damage. Moreover, an electrostatic discharge protection unit 20 for protecting the scan lines (such as the first scan line S1 in the above embodiment) electrically connected to the pixel circuit 11 can also be provided in the first sub-pixel group P1. Therefore, in the first sub-pixel group P1, the number of electrostatic discharge protection units 20 is usually not less than the number of sub-pixels 10 included in the first sub-pixel group P1.
[0137] In this embodiment of the application, since Q1≤Q2, the number of electrostatic discharge protection units 20 is greater than the number of gaps between two adjacent first pixel units 100 in the first sub-pixel group P1. Therefore, the number of electrostatic discharge protection units 20 in some gaps is greater than the number of electrostatic discharge protection units 20 in other gaps.
[0138] For example, such as Figure 13 As shown, the gap between two adjacent first pixel units 100 is M2. When Q1 = Q2, and the first pixel unit 100 includes three sub-pixels 10, the number of electrostatic discharge protection units 20 is three more than three times the number of gaps M2. In this case, four electrostatic discharge protection units 20 can be set in the three gaps M2, and three electrostatic discharge protection units 20 can be set in the other gaps M. This ensures that the first pixel units 100 can be distributed relatively evenly in the display panel 01.
[0139] Figure 14 This is a schematic diagram of a display device provided in an embodiment of this application.
[0140] like Figure 14 As shown, this application embodiment provides a display device 02, which includes a display panel 01 as provided in the above embodiment. The display device 02 provided in this application embodiment can be an electronic device such as a mobile phone, computer, television, smart wearable device (e.g., smartwatch), and in-vehicle display device, and this application embodiment does not specifically limit it.
[0141] In the display device 02, the electrostatic discharge protection unit 20 can be disposed between two adjacent sub-pixels 10 of the first sub-pixel group P1. That is, the electrostatic discharge protection unit 20 can be located in the display area of the display panel 01. Therefore, it is not necessary to set a certain border width on the first edge A1 side of the display panel 01 to place the electrostatic discharge protection unit 20, which is beneficial to reducing the border width of the display panel 01 on the first edge A1 side. At the same time, since it is not necessary to set the electrostatic discharge protection unit 20 between the first sub-pixel group P1 and the first edge A1 of the display panel 01, it is also possible to avoid the border threshold width reserved on the first edge A1 side of the display panel 01 to damage the electrostatic discharge protection unit 20. This is beneficial to further reduce the border width of the display panel 01 on the first edge A1 side, thereby facilitating the achievement of an extremely narrow border for the display panel 01.
[0142] Figure 15 This is a schematic diagram of another display device provided in an embodiment of this application.
[0143] In one embodiment of this application, such as Figure 15As shown, the display device 02 can be formed by splicing together multiple display panels 01 as provided in the above embodiments. At least two display panels 01 are spliced together along a second direction Y, which intersects with the first direction X. The second edge A2 of the preceding display panel 01 can be connected to the first edge A1 of the following display panel 01. Exemplarily, the spliced display device 02 can be a light-emitting diode splicing screen, a movie screen, a long-distance viewing electronic product, etc., and this application embodiment does not impose specific limitations.
[0144] In this embodiment of the application, as can be seen from the structure of the display panel 01, the border of the display panel 01 on the first edge A1 side is relatively small. Therefore, for two adjacent display panels 01 in the second direction Y, the sum of the widths occupied by the border of the first display panel 01 on the second edge A2 side and the border of the second display panel 01 on the first edge A1 side can be reduced. This is beneficial to make the pixel units in the entire spliced display device 02 tend to be evenly spaced, weaken the visual seams, and achieve seamless splicing between display panels 01.
[0145] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. A display panel, characterized in that, The display panel includes multiple sub-pixels and multiple electrostatic discharge protection units; The display panel includes a first edge, and the sub-pixels adjacent to the first edge form a first sub-pixel group. Each sub-pixel in the first sub-pixel group is arranged along a first direction. In the first sub-pixel group, at least some of the adjacent sub-pixels are provided with the electrostatic discharge protection unit. The sub-pixel includes a pixel circuit and a light-emitting device. In the first sub-pixel group, the electrostatic discharge protection unit is located between adjacent light-emitting devices.
2. The display panel of claim 1, wherein, The display panel includes a second edge, which is disposed opposite to the first edge along a second direction, and the second direction intersects the first direction; The display panel includes pins located on one side near the second edge, and the pins are used for electrical connection to a circuit board.
3. The display panel of claim 1, wherein, The display panel further includes a third edge and a fourth edge disposed opposite to each other along the first direction, and the first sub-pixel group includes the sub-pixels adjacent to the third edge; there is no electrostatic discharge protection unit on the side of the first sub-pixel group near the third edge.
4. The display panel of claim 3, wherein, The first sub-pixel group also includes the sub-pixel adjacent to the fourth edge; there is no electrostatic discharge protection unit on the side of the first sub-pixel group near the fourth edge.
5. The display panel according to claim 1, characterized in that, In the same sub-pixel of the first sub-pixel group, along the second direction, the pixel circuit is located on the side of the light-emitting device away from the first edge, and the second direction intersects the first direction.
6. The display panel of claim 5, wherein, In the first sub-pixel group, the number of sub-pixels is Q1, and the number of electrostatic discharge protection units is Q2, where Q1 ≤ Q2; In this configuration, an electrostatic discharge protection unit is provided between any two adjacent sub-pixels in the first sub-pixel group.
7. The display panel of claim 1, wherein, In the same sub-pixel of the first sub-pixel group, along the second direction, a portion of the pixel circuit is located on the side of the light-emitting device closer to the first edge, and the second direction intersects the first direction; In the first sub-pixel group, multiple adjacent sub-pixels form a first pixel unit, and the electrostatic discharge protection unit is located between two adjacent first pixel units.
8. The display panel of claim 7, wherein, In the first sub-pixel group, the number of sub-pixels is Q1, and the number of electrostatic discharge protection units is Q2, where Q1 ≤ Q2; The electrostatic discharge protection unit is provided between any two adjacent first pixel units.
9. The display panel of claim 7, wherein, The first pixel unit comprises three adjacent sub-pixels.
10. The display panel according to claim 7, characterized in that, The display panel includes a first voltage signal line, and the pixel circuit includes a first part; In the same sub-pixel of the first sub-pixel group, along the second direction, the first portion is located on the side of the light-emitting device away from the first edge, and the first portion is electrically connected to the first voltage signal line.
11. The display panel of claim 10, wherein, The first voltage signal line includes a first sub-voltage signal line, which extends to the space between two adjacent sub-pixels of the same first pixel unit; Wherein, the end of the first sub-voltage signal line near the first edge is located between the first portions of two adjacent pixel circuits in the first pixel unit.
12. A display device comprising: Includes the display panel as described in any one of claims 1-11.
13. The display device according to claim 12, characterized in that, It is composed of multiple display panels as described in any one of claims 1-11; wherein at least two of the display panels are spliced together along a second direction, the second direction intersecting with the first direction.