Power semiconductor device

Abstract

The present disclosure provides a power semiconductor device. The power semiconductor device includes a silicon carbide (SiC)-based semiconductor layer; a vertical drift region disposed to extend in a vertical direction inside the semiconductor layer and having a first conductivity type; a well region positioned at at least one side of the vertical drift region to contact the vertical drift region and having a second conductivity type; a recessed gate electrode extending from a surface of the semiconductor layer into the semiconductor layer and buried in the vertical drift region and the well region to cross the vertical drift region and the well region in a first direction; a source region positioned in the well region between the recessed gate electrodes and having the first conductivity type; and an insulating layer guard region surrounding a lower portion of the recessed gate electrode in the vertical drift region, respectively, and having the second conductivity type. The power semiconductor device of the present disclosure can mitigate electric field concentration to a corner of a gate layer, reduce a channel resistance, and increase a channel density.

Description

[0001] This application claims Korean Patent Application Nos. 10-2021-0089752, 10-2021-0152543, and 10-2021-0152543, filed with the Korean Intellectual Property Office on July 8, 2021, November 8, 2021, July 8, 2021, December 16, 2021, July 8, 2021, December 16, 2021, July 8, 2021, December 27, 2021, July 8, 2021, and January 21, 2022, respectively. The prior rights of applications No. 10-2021-0089762, No. 10-2021-0180982, No. 10-2021-0089773, No. 10-2021-0180983, No. 10-2021-0089774, No. 10-2021-0188767, No. 10-2021-0089780 and No. 10-2022-0009225 are hereby acknowledged and incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates to a semiconductor device, and more specifically, to a power semiconductor device capable of switching power transmission and a method for manufacturing the same. Background Technology

[0003] Power semiconductor devices are semiconductor devices that operate in high-voltage and high-current environments. They are used in applications requiring high-power switching, such as power conversion, power converters, or inverters. For example, power semiconductor devices can include insulated-gate bipolar transistors (IGBTs) or metal-oxide-semiconductor field-effect transistors (MOSFETs). Power semiconductor devices essentially require high voltage tolerance. Furthermore, recently, high-speed switching operation has become necessary for power semiconductor devices.

[0004] Therefore, investigations and studies have been conducted on power semiconductor devices using silicon carbide (SiC) instead of traditional silicon (Si). Compared to silicon, silicon carbide (SiC), as a wide-bandgap semiconductor material with a higher bandgap than silicon, maintains stability even at higher temperatures. Furthermore, silicon carbide (SiC) exhibits a significantly higher dielectric breakdown electric field than silicon (Si). Therefore, silicon carbide (SiC) can even operate stably at higher voltages. Thus, silicon carbide (SiC) has a higher breakdown voltage than silicon (Si) and exhibits excellent heat dissipation. Therefore, silicon carbide (SiC) can operate at high temperatures.

[0005] To increase the channel density of silicon carbide (SiC)-based power semiconductor devices, trench gate structures with vertical channel configurations have been investigated. However, trench gate structures suffer from the problem of electric field concentration at the trench corners. Summary of the Invention

[0006] This disclosure aims to solve the aforementioned problems in the prior art while maintaining the advantages of the prior art.

[0007] One aspect of this disclosure provides a silicon carbide (SiC) based power semiconductor device capable of reducing electric field concentration, increasing channel density, and reducing channel resistance, as well as a method for manufacturing the same. However, the above objective is an example, and the scope and spirit of this disclosure are not limited thereto.

[0008] The technical problems to be solved by this disclosure are not limited to those described above. Any other technical problems not mentioned herein will be clearly understood by those skilled in the art through the following description.

[0009] According to one aspect of this disclosure, a power semiconductor device may include: a semiconductor layer based on silicon carbide (SiC); a vertical drift region configured to extend vertically within the semiconductor layer and having a first conductivity type; a well region located at least on one side of the vertical drift region to contact the vertical drift region in the semiconductor layer and having a second conductivity type opposite to the first conductivity type; a plurality of recessed gate electrodes extending from the surface of the semiconductor layer into the semiconductor layer and buried in the vertical drift region and the well region to intersect the vertical drift region and the well region in a first direction; a plurality of source regions located in the well region between the plurality of recessed gate electrodes and having a first conductivity type; and a plurality of insulating layer protection zones located at least below the plurality of recessed gate electrodes in the vertical drift region and having a second conductivity type.

[0010] Preferably, the insulating layer protection zone can have the form of surrounding the lower part of the recessed gate electrode.

[0011] Preferably, the power semiconductor device may further include: a pillar region located in the semiconductor layer below the well region to contact the vertical drift region and the well region and having a second conductivity type.

[0012] Preferably, the first region of the vertical drift region may have a wider width than the second region of the vertical drift region. The first region contacts the pillar region, and the second region contacts the trap region.

[0013] Preferably, the power semiconductor device may further include: a horizontal drift region connected to the vertical drift region and positioned below the pillar region to contact the pillar region.

[0014] Preferably, the trap region and the source region can be positioned on opposite sides of the vertical drift region to be symmetrical about the vertical drift region.

[0015] Preferably, the power semiconductor device may further include a source contact region disposed outside the recessed gate electrode and connected to a plurality of source regions.

[0016] Preferably, the power semiconductor device may further include a well contact region located in the source contact region and connected to the well region.

[0017] Preferably, the power semiconductor device may further include a source electrode layer connected to the source contact region and the well contact region.

[0018] Preferably, the plurality of recessed gate electrodes can be positioned to extend into a portion of the well region while passing through the vertical drift region in a first direction, and can be configured to be spaced apart from each other in a second direction intersecting the first direction.

[0019] Preferably, the plurality of insulation layer protection zones may be positioned to intersect the entire portion of the vertical drift zone in a first direction, and may be positioned to be spaced apart from each other in a second direction without being connected to each other.

[0020] Preferably, the power semiconductor device may further include: a plate-shaped gate electrode positioned on the semiconductor layer, which simultaneously connects a plurality of recessed gate electrodes to each other.

[0021] Preferably, the plate-shaped gate electrode can be positioned on the semiconductor layer to cover the vertical drift region and multiple source regions.

[0022] Preferably, the multiple source regions can be positioned at a specific distance from the vertical drift region.

[0023] Preferably, multiple source regions can be positioned to contact the vertical drift region.

[0024] According to another aspect of this disclosure, a power semiconductor device may include: a semiconductor layer comprising silicon carbide (SiC); recessed gates extending from a surface of the semiconductor layer into the semiconductor layer; a drift region positioned in the semiconductor layer between the recessed gates and having a first conductivity type; a well region positioned between the recessed gates at at least one side of the drift region to contact the drift region and having a second conductivity type opposite to the first conductivity type; a source region positioned between the recessed gates in the well region and having a first conductivity type; a first pillar region positioned in the semiconductor layer below the drift region and the well region to connect to the drift region and having a first conductivity type; and a second pillar region connected to the well region in the semiconductor layer, positioned below the recessed gates, and having a second conductivity type.

[0025] Preferably, the second pillar region may surround the lower portion of the recessed gate.

[0026] Preferably, the first column area and the second column area can be arranged alternately in the first direction and in contact with each other.

[0027] Preferably, the first pillar region and the second pillar region can extend in a second direction intersecting the first direction to be longer than the recessed gate.

[0028] According to another aspect of this disclosure, a power semiconductor device may include: a semiconductor layer comprising silicon carbide (SiC) and having a first conductivity type; a recessed gate positioned in a trench extending from a surface of the semiconductor layer into the semiconductor layer; a first impurity region comprising impurities of a second conductivity type opposite to the first conductivity type and surrounding a lower corner region of the trench; and a second impurity region comprising impurities of the first conductivity type and positioned at opposite sides of the trench to contact opposite sides of the trench. Attached Figure Description

[0029] The above and other objects, features and advantages of this disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings:

[0030] Figure 1 This is a perspective view schematically illustrating the structure of a power semiconductor device according to an embodiment of the present disclosure;

[0031] Figure 2 It shows along Figure 1 A sectional view of the structure intercepted by line A-A';

[0032] Figure 3 It shows along Figure 2 A longitudinal sectional view of the structure intercepted by line B-B';

[0033] Figure 4 It shows along Figure 2 A longitudinal sectional view of the structure intercepted by line C-C';

[0034] Figure 5 It shows along Figure 2 A longitudinal sectional view of the structure intercepted by line D-D';

[0035] Figure 6 It is a graph showing the change of electric field according to the depth of the power semiconductor device;

[0036] Figure 7 This is a schematic perspective view illustrating the structure of a power semiconductor device according to another embodiment of the present disclosure;

[0037] Figure 8 This is a schematic perspective view illustrating the structure of a power semiconductor device according to another embodiment of the present disclosure;

[0038] Figure 9 It is shown Figure 8 A cross-sectional view of the structure of the plate-shaped gate;

[0039] Figure 10 This is a schematic perspective view illustrating the structure of a power semiconductor device according to another embodiment of the present disclosure;

[0040] Figure 11 This is a schematic perspective view illustrating the structure of a power semiconductor device according to another embodiment of the present disclosure;

[0041] Figure 12 It shows along Figure 11 A sectional view of the structure intercepted by line E-E';

[0042] Figure 13 It shows along Figure 12 A longitudinal sectional view of the structure intercepted by line F-F';

[0043] Figure 14 It shows along Figure 12 A longitudinal sectional view of the structure intercepted by line G-G';

[0044] Figures 15 to 19 It is a schematic illustration of the materials used in manufacturing. Figure 1 A perspective view of a method for developing power semiconductor devices;

[0045] Figure 20 This is a schematic perspective view illustrating the structure of a power semiconductor device according to another embodiment of the present disclosure;

[0046] Figure 21 It shows along Figure 20 A sectional view of the structure intercepted by line A-A';

[0047] Figure 22 It shows along Figure 21A longitudinal sectional view of the structure intercepted by line B-B';

[0048] Figure 23 It shows along Figure 21 A longitudinal sectional view of the structure intercepted by line C-C';

[0049] Figure 24 It shows along Figure 21 A longitudinal sectional view of the structure intercepted by line D-D';

[0050] Figure 25 This is a schematic perspective view illustrating the structure of a power semiconductor device according to another embodiment of the present disclosure;

[0051] Figure 26 This is a schematic perspective view illustrating the structure of a power semiconductor device according to another embodiment of the present disclosure;

[0052] Figure 27 This is a schematic perspective view illustrating the structure of a power semiconductor device according to another embodiment of the present disclosure;

[0053] Figure 28 It shows along Figure 27 A sectional view of the structure intercepted by line E-E';

[0054] Figure 29 It shows along Figure 28 A longitudinal sectional view of the structure intercepted by line F-F';

[0055] Figure 30 It shows along Figure 28 A longitudinal sectional view of the structure intercepted by line G-G';

[0056] Figure 31 It shows along Figure 28 A longitudinal sectional view of the structure intercepted by line H-H';

[0057] Figures 32 to 34 This is a perspective view schematically illustrating a method for creating an insulating layer protection zone surrounding the lower portion of a recessed gate;

[0058] Figures 35 to 38 This is a perspective view schematically illustrating a method for manufacturing an insulating layer protection zone surrounding the lower portion of a recessed gate, according to another embodiment of this disclosure.

[0059] Figures 39 to 43 This is a perspective view schematically illustrating a method for manufacturing an insulating layer protection zone surrounding the lower portion of a recessed gate, according to another embodiment of this disclosure; and

[0060] Figure 44 This is a schematic perspective view illustrating the structure of a power semiconductor device according to another embodiment of the present disclosure. Detailed Implementation

[0061] In the following description, embodiments of the present disclosure will be illustrated with reference to the accompanying drawings. However, the present disclosure may be implemented in various different forms and should not be construed as being limited to the embodiments shown below. Rather, the following embodiments are provided as examples so that the present disclosure will be thorough and complete and will fully convey the concept of the present disclosure to those skilled in the art. For ease of illustration, the dimensions of certain components in the drawings may be enlarged or reduced. The same reference numerals will be assigned to the same components in the drawings.

[0062] Unless otherwise defined, all terms used herein should be interpreted as commonly understood by those skilled in the art. In the accompanying drawings, the dimensions of layers and regions have been exaggerated for ease of interpretation in relation to the general structure of this disclosure.

[0063] The same reference numerals denote the same components. It will be understood that when a component such as a layer, region, or substrate is referred to as being "on" another component, that component may be "directly" or "indirectly" on the other component, or one or more intermediate components may be present between that component and the other component. Conversely, when a component is described as being directly on another component, it should be understood that no intermediate components are placed between them.

[0064] Figure 1 This is a perspective view schematically illustrating the structure of a power semiconductor device according to an embodiment of the present disclosure. Figure 2 It shows along Figure 1 A sectional view of the structure cut by line A-A'. Figures 3 to 5 It shows along Figure 2 The longitudinal sectional view of the structure intercepted by lines B-B', C-C', and D-D'.

[0065] Reference Figures 1 to 5 The power semiconductor device 100 may include a semiconductor layer 105, a gate insulating layer 118, a gate electrode layer 120, an interlayer insulating layer 130, and a source electrode layer 140. For example, the power semiconductor device 100 may have a power MOSFET structure.

[0066] Semiconductor layer 105 may include a single semiconductor material layer or multiple semiconductor material layers. For example, semiconductor layer 105 may include a single epitaxial layer or multiple epitaxial layers. Alternatively, semiconductor layer 105 may include a single epitaxial layer or multiple epitaxial layers formed on a semiconductor substrate. For example, semiconductor layer 105 may include silicon carbide (SiC). Alternatively, semiconductor layer 105 may include at least one SiC epitaxial layer.

[0067] Silicon carbide (SiC) is a wide-bandgap semiconductor material with a higher bandgap than silicon (Si). Compared to silicon (Si), silicon carbide (SiC) maintains stability even at higher temperatures. Furthermore, silicon carbide (SiC) exhibits a significantly higher dielectric breakdown electric field than silicon (Si). Therefore, silicon carbide (SiC) can operate stably even at higher voltages. Thus, compared to silicon (Si), the power semiconductor device 100 having a silicon carbide-based semiconductor layer 105 exhibits superior heat dissipation characteristics and a higher breakdown voltage, and can exhibit stable operating characteristics at higher temperatures.

[0068] Such a semiconductor layer 105 may include a drift region 107. The drift region 107 may be formed of a first conductivity type (N-type) and may be formed by implanting an impurity of the first conductivity type into a portion of the semiconductor layer 105. For example, the drift region 107 may be formed by implanting an impurity of the first conductivity type into a SiC epitaxial layer.

[0069] When the power semiconductor device 100 is operating, the drift region 107 can provide a path for current movement. The drift region 107 may include a horizontal portion 107a and a vertical portion 107b. The horizontal portion 107a is formed to extend horizontally in the lower part of the semiconductor layer 105, thereby providing a horizontal path for current movement. The vertical portion 107b is formed to connect to the horizontal portion 107a and extend vertically (Z-direction) within the semiconductor layer 105, thereby providing a vertical path for current movement. For example, in the drift region 107, the horizontal portion 107a may correspond to a region located below the pillar region 111, while the vertical portion 107b may correspond to a region located in contact with the horizontal portion 107a, the well region 110, and the side of the pillar region 111.

[0070] In this case, the vertical portion 107b may include a plurality of regions (separate vertical portions) divided by the recessed gate electrode 120R. In the power semiconductor device according to this embodiment, each of the plurality of separate vertical portions 107b can be used as a vertical movement path for current.

[0071] Well region 110 may contact drift region 107 in semiconductor layer 105 and may include impurities of a second conductivity type (impurities of the second conductivity type). For example, well region 110 may be formed by implanting impurities of a second conductivity type (P-type) opposite to the first conductivity type into the SiC epitaxial layer.

[0072] For example, the trap region 110 can be formed around at least a portion of the drift region 107. For example, the trap region 110 can be formed around the upper part of the vertical portion 107b in the drift region 107. Although Figure 1The diagram shows that the trap region 110 is divided into two regions spaced a certain distance apart from each other in the Y direction by the vertical portion 107b, but various modifications are possible. For example, the trap region 110 may be provided in a fully encircling form to surround the side of the vertical portion 107b.

[0073] Pillar region 111 can be formed in semiconductor layer 105 below well region 110, such that pillar region 111 is connected to well region 110. Pillar region 111 can be formed to contact drift region 107 to form a super junction with drift region 107. For example, pillar region 111 can be disposed below well region 110, such that the top surface of pillar region 111 contacts well region 110, and the side and bottom surfaces of pillar region 111 contact the vertical portion 107b and horizontal portion 107a of drift region 107, respectively.

[0074] Pillar region 111 can be formed in semiconductor layer 105 with a conductivity type opposite to that of drift region 107, such that pillar region 111 and drift region 107 form a superjunction. For example, pillar region 111 may include impurities of a second conductivity type that are opposite to the impurity type of drift region 107 and the same as the impurity type of well region 110. For example, the doping concentration of the second conductivity type impurity in pillar region 111 may be equal to or less than the doping concentration of the second conductivity type impurity in well region 110.

[0075] According to an embodiment, the pillar region 111 can be formed to have a width narrower than that of the well region 110 in one direction (Y direction). For example, when the well region 110 and the pillar region 111 are spaced apart from each other on opposite sides of the vertical portion 107b, the distance between the spaced-apart pillar regions 111 (distance in the Y direction) can be greater than the distance between the spaced-apart well regions 110 (distance in the Y direction). Therefore, in the vertical portion 107b of the drift region 107, the area between the well regions 110 can have a smaller width (length in the Y direction) than the area between the pillar regions 111.

[0076] According to an embodiment, a plurality of pillar regions 111 and a plurality of drift regions 107 can be alternately arranged such that the side of each pillar region contacts the side of each drift region 107, thereby forming a superjunction structure. Furthermore, the plurality of pillar regions 111 and the plurality of drift regions 107 can be alternately arranged below a well region 110.

[0077] Source regions 112 can be formed inside well regions 110 and can be formed of a first conductivity type. For example, each source region 112 can be formed between recessed gate electrodes 120R inside well regions 110, and can be formed when impurities of the first conductivity type are implanted into a portion of well regions 110. Source regions 112 can be formed when impurities of the first conductivity type are implanted at a concentration higher than that of drift regions 107.

[0078] Each channel region 110a can be formed between the vertical portion 107b of the drift region 107 and each source region 112. The channel region 110a may include impurities of a second conductivity type. Because the channel region 110a includes impurities of a second conductivity type opposite to that of the source region 112 and the drift region 107, the channel region 110a can form a diode junction together with the source region 112 and the drift region 107. Accordingly, because charge movement is not permitted in the channel region 110a when the power semiconductor device 100 is not in operation, the channel region 110a can electrically isolate the vertical portion 107b of the drift region 107 from the source region 112. Conversely, when an operating voltage is applied to the gate electrode layer 120, charge movement is permitted in the channel region 110a because an inversion channel is formed within the channel region 110a. Therefore, the channel region 110a can electrically connect the vertical portion 107b of the drift region 107 to the source region 112.

[0079] Although Figure 1 Channel region 110a is shown as distinct from well region 110, but channel region 110a can be some of the well regions 110. For example, channel region 110a can correspond to the region of well region 110 located between the vertical portion 107b of drift region 107 and source region 112. The doping concentration of the second conductivity type impurity in channel region 110a can be equal to or different from the doping concentration of the second conductivity type impurity in well region 110 to adjust the threshold voltage.

[0080] According to an embodiment, the well region 110, pillar region 111, channel region 110a, and source region 112 can be formed symmetrically with respect to the vertical portion 107b of the drift region 107 in the Y direction. For example, each of the well region 110, pillar region 111, channel region 110a, and source region 112 may include a first portion and a second portion located on opposite sides of the vertical portion 107b of the drift region 107 in the Y direction. The well region 110, pillar region 111, and source region 112 can be separated from each other by the vertical portion 107b of the drift region 107, or they can be connected to each other to surround the vertical portion 107b of the drift region 107.

[0081] Furthermore, the drain region 102 may be formed in the semiconductor layer 105 below the drift region 107 and may include impurities of a first conductivity type. For example, the drain region 102 may include impurities of a first conductivity type implanted at a higher concentration than the impurity concentration of the first conductivity type in the drift region 107.

[0082] According to an embodiment, the drain region 102 can be provided as a SiC substrate of a first conductivity type. In this case, the drain region 102 can be formed as part of the semiconductor layer 105 or as a substrate separate from the semiconductor layer 105.

[0083] Because the semiconductor layer 105 is etched from its surface (top surface) to a specific depth within the semiconductor layer 105, at least one trench 116 can be formed. The at least one trench 116 may include a plurality of trenches spaced apart from each other in the X direction at a specific distance. The trench 116 may extend parallel to the Y direction to pass through the vertical portion 107b of the drift region 107 and the channel region 110a within the semiconductor layer 105.

[0084] Each of the channel regions 110a can be positioned between the trenches 116, and the area of ​​the vertical portion 107b of the drift region 107 that contacts the trap region 110 can be divided into multiple regions by the trenches 116. According to an embodiment, the vertical portion 107b of the drift region 107 can be positioned between the trenches 116 as a separator. The channel regions 110a can be positioned on opposite sides (opposite sides in the Y direction) of the vertical portion 107b provided as a separator. Furthermore, the source region 112 can be located on opposite sides of the channel regions 110a in the Y direction.

[0085] A gate insulating layer 118 may be formed at least on the inner surface of the trench 116. For example, the gate insulating layer 118 may be formed on the inner surface of the trench 116 and on the semiconductor layer 105 outside the trench 116. The thickness of the gate insulating layer 118 may be uniform, or the portion of the gate insulating layer 118 formed on the bottom surface of the trench 116 may be thicker than the portion of the gate insulating layer 118 formed on the sidewalls of the trench 116, such that the electric field is reduced at the bottom of the trench 116.

[0086] The gate insulating layer 118 may include an insulating material, such as silicon oxide, SiC oxide, silicon nitride, hafnium oxide, zirconium oxide, or aluminum oxide, or a stacked structure thereof.

[0087] A gate electrode layer 120 may be formed on the gate insulating layer 118 to fill the trench 116. Alternatively, the gate electrode layer 120 may be formed on the gate insulating layer 118 on the semiconductor layer 105 to at least cover the channel region 110a. For example, the gate electrode layer 120 may include a plurality of recessed gate electrodes 120R spaced apart from each other in the X direction and formed to be buried in the trench 116. Furthermore, the gate electrode layer 120 may include a plate-shaped gate electrode 120P provided in the form of a flat plate to connect the plurality of recessed gate electrodes 120R to each other while covering the channel region 110a.

[0088] According to this embodiment, the power semiconductor device 100 may have a structure disposed between a plurality of recessed gate electrodes 120R below the plate-shaped gate electrode 120P, wherein the source region 112, the channel region 110a, and the vertical portion 107b are connected to each other in the Y direction. For example, the channel region 110a and the source region 112 may be formed between the plurality of recessed gate electrodes 120R on opposite sidewalls of the vertical portion 107b extending in the Y direction, so as to be connected to each other. When the power semiconductor device 100 is operated, the vertical portion 107b, the channel region 110a, and the source region 112 of the drift region 107 connected to each other can be used as a current movement path.

[0089] As described above, according to this embodiment, the power semiconductor device 100 includes a multi-lateral channel structure with current movement paths formed between a plurality of recessed gate electrodes 120R, wherein the vertical portion 107b of the drift region 107, the channel region 110a, and the source region 112 are connected to each other, allowing more charges to move simultaneously. Furthermore, along the movement paths, the gate electrode layer 120 is formed around three surfaces (opposite surfaces in the X direction and a top surface) surrounding the vertical portion 107b, the channel region 110a, and the source region 112, allowing more charges to move simultaneously. The gate electrode layer 120 may include a conductive material, such as polysilicon, metal, metal nitride, or metal silicide, or may include a stacked structure thereof.

[0090] The well region 110 can be formed at a depth greater than the depth of the recessed gate electrode 120R to surround the side and bottom surfaces of the recessed gate electrode 120R.

[0091] An interlayer insulating layer 130 may be formed on the gate electrode layer 120. The interlayer insulating layer 130 may include an insulating material, such as an oxide layer, a nitride layer, or a stacked structure thereof, for electrical insulation between the gate electrode layer 120 and the source electrode layer 140.

[0092] The source electrode layer 140 may be formed on the interlayer insulating layer 130 and may be electrically connected to the source region 112. The source electrode layer 140 may include a conductive material such as a metal.

[0093] Although the above description has been made according to the embodiments, wherein the first conductivity type and the second conductivity type are N-type and P-type, the first conductivity type and the second conductivity type can be P-type and N-type. More specifically, when the power semiconductor device 100 is an N-type MOSFET, the drift region 107 can be an N-region, the source region 112 and the drain region 102 can be N+ regions, and the well region 110, the pillar region 111 and the channel region 110a can be P-regions.

[0094] When the power semiconductor device 100 is in operation, current can flow vertically from the drain region 102 along the vertical portion 107b of the drift region 107, and then flow through the channel region 110a to the source region 112.

[0095] In the power semiconductor device 100 described above, the recessed gate electrodes 120R in the trench 116 can be densely arranged in parallel as strips or lines, and the channel region 110a can be placed between the recessed gate electrodes 120R, thereby increasing the channel density.

[0096] Furthermore, in the power semiconductor device 100 according to this embodiment, the well region 110 may be formed around the lower portion of the trench 116, thereby reducing electric field concentration at the lower corner of the gate electrode layer 120. Additionally, according to this embodiment, the power semiconductor device 100 may include an insulating layer protection zone 115 recessed around the lower portion of each gate electrode 120R in the vertical portion 107b of the drift region 107. The insulating layer protection zone 115 may include impurities of a second conductivity type.

[0097] When an operating voltage is applied to the gate electrode layer 120, the electric field can concentrate at the lower corner of the recessed gate electrode 120R. When the electric field is concentrated, the gate insulating layer 118 in the relevant region may be subjected to stress, which may lead to dielectric breakdown of the gate insulating layer 118. Therefore, according to this embodiment, as the electric field concentrates at the corner of the gate insulating layer 118, the lower portion of the recessed gate electrode 120R formed in the well region 110 can be surrounded by the P-type well region 110, and the lower portion of the recessed gate electrode 120R formed in the vertical portion 107b of the drift region 107 can be surrounded by the P-type insulating layer protection zone 115, thereby preventing dielectric breakdown of the gate insulating layer 118.

[0098] According to this embodiment, in the power semiconductor device 100, because current flows through the vertical portion 107b of the drift region 107, the current travel path is reduced when the insulating layer protection zone 115 is formed, thereby increasing the resistance (JFET resistance). However, in the power semiconductor device 100 according to this embodiment, the JFET resistance can be reduced by using a pillar region 111 that forms a superjunction together with the drift region 107. For example, according to this embodiment, as described below... Figure 6 As shown, the amount of charge in column region 111 and the amount of charge in drift region 107 are adjusted to reduce the JFET resistance.

[0099] Figure 6 It is a graph showing the change of electric field according to the depth of the power semiconductor device.

[0100] Reference Figure 6When the charge Qp of pillar region 111 is greater than the charge Qn of drift region 107, and when the power semiconductor device 100 is operating, the breakdown voltage can be increased by allowing the maximum electric field to be formed in drift region 107, which is on the same line as the bottom surface of pillar region 111. Figure 6 As shown, the intensity gradient of the electric field between position "A" and position "B" can be controlled by adjusting the charge Qp of column region 111.

[0101] For example, by making the doping concentration of the second conductivity type of impurity in pillar region 111 higher than the doping concentration of the first conductivity type of impurity in drift region 107, the charge Qp of pillar region 111 can become greater than the charge Qn of drift region 107, thereby improving the breakdown voltage characteristics of power semiconductor device 100 and reducing JFET resistance.

[0102] Figure 7 This is a schematic perspective view illustrating the structure of a power semiconductor device according to another embodiment of the present disclosure.

[0103] The power semiconductor device 100a according to this embodiment is partially modified as follows: Figures 1 to 5 The power semiconductor device 100 shown is formed based on its structure. Therefore, repeated descriptions of the structure will be omitted to avoid redundancy.

[0104] Reference Figure 7 According to this embodiment, the power semiconductor device 100a may have a source region 112' formed to contact the vertical portion 107b of the drift region 107. The source region 112' may include impurities of the same first conductivity type as the impurities in the source region 112.

[0105] In the structure of the SiC semiconductor layer 105, the negative charge generated when forming a carbon cluster on the gate insulating layer 118 creates a potential barrier in the current flow path, thereby blocking current movement. Therefore, as in this embodiment, even if the source region 112' is formed to contact the vertical portion 107b of the drift region 107, an accumulation channel can be formed to allow current flow when an operating voltage is applied to the gate electrode layer 120. In this case, the operating voltage can be significantly lower than that used for... Figure 1 The operating voltage of the inverse channel is formed in the channel region 110a.

[0106] Figure 8 This is a schematic perspective view illustrating the structure of a power semiconductor device according to another embodiment of the present disclosure. Figure 9 It is shown Figure 8 A cross-sectional view of the structure of a plate-shaped gate.

[0107] The power semiconductor device 100b according to this embodiment is partially modified as follows: Figures 1 to 5 The power semiconductor device 100 shown is formed based on its structure. Therefore, repeated descriptions of the structure will be omitted to avoid redundancy.

[0108] Reference Figure 8 and Figure 9 In the power semiconductor device 100b according to this embodiment, the plate-shaped gate 120P' can be as follows: Figure 9 The figures shown are formed individually, rather than as a single flat plate.

[0109] For example, as mentioned above Figure 1 or Figure 7 The plate-shaped gate electrode (or plate-shaped gate) 120P shown is provided in the form of a plate to cover the entire portion of the vertical portion 107b and the channel region 110a and source region 112 provided on opposite sides of the vertical portion 107b. However, according to this embodiment, the plate-shaped gate 120P' may be provided in a form where there is no gate electrode layer on the vertical portion 107b. In other words, the gate electrode layer 120 has the form in which the recessed gate 120R exists only on the opposite sidewalls (opposite sidewalls in the X direction) of the vertical portion 107b, and with respect to the channel region 110a and the source region 112, the recessed gate 120R and the plate-shaped gate 120P' may be in the form of an inverted U-shape surrounding the three surfaces of the channel region 110a and the source region 112.

[0110] As described above, according to this embodiment, since no electrode material (gate electrode layer) is formed on the vertical portion 107b, the parasitic capacitance caused by the electrode material can be reduced.

[0111] Figure 10 This is a schematic perspective view illustrating the structure of a power semiconductor device according to another embodiment of the present disclosure.

[0112] Reference Figure 10 The power semiconductor device 100c may have an insulating layer protection zone 115 formed extending into the well region 110. When with... Figure 1 Compared to the power semiconductor device shown, except that the insulating layer protection zone 115 extends further into the well region 110 in the Y direction, the power semiconductor device 100c can have the same Figure 1 The same components as the power semiconductor device 100.

[0113] Although Figure 10 The diagram shows that the insulating layer protection zone 115 is separated from each other within the well region 110, but the well region 110 and the insulating layer protection zone 115 contain impurities of the same conductivity type. Therefore, when the well region 110 and the insulating layer protection zone 115 are formed at substantially the same concentration, the insulating layer protection zone 115 is not separated from each other within the well region 110, similar to... Figure 1The power semiconductor device 100 shown is illustrated.

[0114] Figure 11 This is a schematic perspective view illustrating the structure of a power semiconductor device according to another embodiment of the present disclosure. Figure 12 It shows along Figure 11 A sectional view of the structure intercepted by line E-E'. Figures 13 to 14 It shows along Figure 12 The longitudinal sectional view of the structure cut by lines F-F' and G-G'.

[0115] According to this embodiment, the power semiconductor device 100d is achieved by employing or partially modifying... Figure 1 The power semiconductor device 100 is formed. Therefore, repeated descriptions will be omitted to avoid redundancy.

[0116] Reference Figures 11 to 14 The power semiconductor device 100d may include at least one gate region GR1 or GR2 and a contact region CR.

[0117] The gate regions GR1 and GR2 of the gate electrode layer 120 may include those described above. Figure 1 , Figure 7 , Figure 8 or Figure 10 The structure shown. Figure 11 The gate regions GR1 and GR2 are shown to include, as follows Figure 1 An embodiment of the structure shown is presented. Therefore, details of the gate regions GR1 and GR2 will be omitted.

[0118] Contact regions CR for connecting the source regions 112 of gate regions GR1 and GR2 to the source electrode layer 140 can be located on one side of each of the gate regions GR1 and GR2. The contact regions CR may include a drift region 107a, a well region 110, a pillar region 111, a source contact region 112a, a well contact region 114, and the source electrode layer 140.

[0119] The drift region 107a, well region 110, and pillar region 111 of the contact region CR can be integrally formed with the drift region 107a, well region 110, and pillar region 111 of the gate regions GR1 and GR2, respectively. In other words, the drift region 107a of the gate regions GR1 and GR2 is integrally formed with the drift region 107a of the contact region CR, the well region 110 of the gate regions GR1 and GR2 is integrally formed with the well region 110 of the contact region CR, and the pillar region 111 of the gate regions GR1 and GR2 is integrally formed with the pillar region 111 of the contact region CR.

[0120] Source contact region 112a is used to connect source region 112 to source electrode layer 140. Source contact region 112a may be positioned in the Y direction between gate regions GR1 and GR2 and may be integrally formed with source region 112. For example, source region 112 may extend to contact region CR. The extended source region 112 may be commonly and integrally connected to the outside of recessed gate electrode 120R. In this case, the portion commonly and integrally connected to the outside of recessed gate electrode 120R may be source contact region 112a. Therefore, source contact region 112a may be a part of source region 112. Source region 112 can be electrically connected to source electrode layer 140 through source contact region 112a.

[0121] A sink contact region 114 may be formed in a source contact region 112a. For example, a sink contact region 114 may extend from a sink region 110 through a source contact region 112a. At least one sink contact region 114 may be formed in a source contact region 112a.

[0122] The well contact region 114 may include impurities of a second conductivity type. For example, the well contact region 114 may be doped with impurities of a second conductivity type at a higher concentration than that of the well region 110 to reduce the contact resistance when connected to the source electrode layer 140. The well contact region 114 may be a P+ region.

[0123] The source electrode layer 140 of the contact region CR can be formed as a source electrode layer 140 integrally connected to the gate regions GR1 and GR2. The source electrode layer 140 can be jointly connected to the source contact region 112a and the well contact region 114.

[0124] The plate-shaped gate electrodes 120P of gate regions GR1 and GR2 can be formed to extend in the Y direction to the boundary region between the contact region CR and the gate regions GR1 and GR2. For example, as Figure 13 As shown, the plate-shaped gate electrode 120P can extend more longitudinally in the Y direction, so that the plate-shaped gate electrode 120P is closer to the contact region CR than the recessed gate electrode 120R. The recessed gate electrode 120R can be formed to extend into a portion of the well region 110, while passing through the vertical portion 107b of the drift region 107 in the Y direction.

[0125] The source regions 112 formed between the recessed gate electrodes 120R can be connected together to the source contact region 112a. The insulating layer protection zone 115 can be formed at the vertical portion 107b of the drift region 107 to surround the lower portion of each recessed gate electrode 120R.

[0126] Although Figures 11 to 14The diagram shows that source contact region 112a and well contact region 114 are formed only on one side of each of the vertical portions 107b of drift region 107. However, when source region 112 and well region 110 are divided into multiple regions, source contact region 112a and well contact region 114 can be formed in each of the divided regions. For example, when source region 112 and well region 110 located on opposite sides of vertical portion 107b are electrically connected to each other, contact region CR can be as follows: Figure 11 The contact region CR shown is formed only on one side of the vertical portion 107b. Conversely, when the source region 112 and the sink region 110 provided on opposite sides of the vertical portion 107b are electrically isolated from each other, the contact region CR can be formed on opposite sides of the vertical portion 107b.

[0127] because Figure 11 The power semiconductor device 100d may include two gate regions GR1 and GR2 and a contact region CR formed between the gate regions GR1 and GR2, thus the contact region CR is connected to both gate regions GR1 and GR2. However, the power semiconductor device 100d may also include one gate region GR1 or GR2 and a contact region CR formed on one side of the gate region GR1 or GR2. In this case, the contact region CR may be formed on one side of the gate region GR1 or GR2 in the Y direction or X direction.

[0128] Furthermore, the power semiconductor device 100d may include a plurality of gate regions and a plurality of contact regions disposed between the gate regions. For example, the power semiconductor device 100d may include at least three gate regions arranged to be spaced apart from each other by a specific distance in the Y direction, and a plurality of contact regions, each contact region being disposed between adjacent gate regions. In this case, the structure of the adjacent gate regions and the contact regions disposed between the adjacent gate regions can be similar to... Figures 11 to 14 The structures are the same.

[0129] Figures 15 to 19 It is a schematic illustration of the materials used in manufacturing. Figure 1 A perspective view of a method for developing power semiconductor devices.

[0130] Reference Figure 15 A drift region 107' having a first conductivity type can be formed in the SiC semiconductor layer 105. For example, the drift region 107' can be formed on a drain region 102 having a first conductivity type. According to an embodiment, the drain region 102 can be provided in the form of a substrate of the first conductivity type, and the drift region 107' can be formed on the substrate in the form of one or more epitaxial layers. The first conductivity type can be N-type.

[0131] Next, refer to Figure 16The well region 110 and the pillar region 111 can be formed by injecting impurities of a second conductivity type into the drift region 107'. For example, after forming a mask pattern (photoresist pattern) on the drift region 107' to open up the area for the well region 110, impurities of a second conductivity type are injected into the drift region 107' at a specific depth to form the vertical portion 107b and the well region 110.

[0132] The trap region 110 may be formed on at least one side of the vertical portion 107b. For example, the trap region 110 may be formed on the opposite side of the vertical portion 107b in the Y direction, or it may be formed around the vertical portion 107b.

[0133] Subsequently, pillar region 111 can be formed by implanting impurities of a second conductivity type into the drift region 107' below the well region 110. For example, after removing the mask pattern used when forming the well region 110 and forming a mask pattern on the drift region 107' to define the pillar region 111, impurities of a second conductivity type are implanted into the lower part of the well region 110 to form the pillar region 111. In this case, the pillar region 111 can be formed such that a drift region 107a of a specific thickness exists below the pillar region 111. As described above, the pillar region 111 of the second conductivity type can be formed with a bottom surface and side surfaces that contact the horizontal portion 107a and the vertical portion 107b of each drift region 107, thereby forming a superjunction. The pillar region 111 can be formed with a top surface that contacts the well region 110. The second conductivity type can be P-type, which is the opposite of the first conductivity type.

[0134] Although the above embodiments have been described as forming a well region 110 first and a pillar region 111 below the well region 110, the pillar region 111 can be formed first and the well region 110 can be formed on the pillar region 111.

[0135] Subsequently, a source region 112' having a first conductivity type can be formed in the well region 110. For example, the source region 112' can be formed by implanting an impurity of the first conductivity type into the well region 110. The source region 112' can actually be formed at a specific depth from the surface of the semiconductor layer 105, and can be formed in the form of a strip extending longitudinally in the X direction. The source region 112' can be formed at a specific distance from the vertical portion 107b. In this case, the portion of the well region 110 located between the source region 112' and the vertical portion 107b can be a channel region 110a'. Alternatively, such as Figure 7 As shown, the source region 112' can be formed to contact the vertical portion 107b.

[0136] Alternatively, after the impurities are injected, a heat treatment step that activates or diffuses the impurities can be performed.

[0137] Next, refer to Figure 17After forming a mask pattern on the semiconductor layer 105 to define the region of the trench 116, the semiconductor layer 105 is etched to a specific depth using the mask pattern as an etching mask, thereby forming trenches 116 arranged to be spaced apart from each other in the X direction. The trenches 116 may be formed to extend in the Y direction with a length sufficient to pass through the vertical portion 107b and the channel region 110a' and source region 112' located on opposite sides of the vertical portion 107b.

[0138] The channel region 110a' and source region 112' are divided into multiple regions by the trench 116, thereby forming multiple channel regions 110a and multiple source regions 112. Furthermore, even the vertical portion 107b can be divided into multiple regions by the trench 116. The regions of the vertical portion 107b provided in the form of separators divided by the trench 116, and the channel regions 110a and source regions 112 connected to each associated vertical portion 107b, can serve as current flow paths. In other words, according to this embodiment, the power semiconductor device can include multiple current flow paths connected in parallel with each other, allowing a larger amount of current to flow at once.

[0139] The trench 116 can be formed to a depth less than that of the well region 110, such that the lower part of the trench 116 is surrounded by the well region 110.

[0140] Next, refer to Figure 19 A second conductivity type (P-type) impurity is implanted into the region of the vertical portion 107b of the drift region 107 in the trench 116 to form an insulating layer protection zone 115 in the vertical portion 107b to surround the lower portion of the trench 116. For example, after forming a mask pattern above the semiconductor layer 105 to expose the vertical portion 107b of the drift region 107 in the trench 116, a P-type impurity can be implanted into the exposed region. In this case, the angle for implanting ions is adjusted to form an insulating layer protection zone (P-type impurity region) 115 implanted with P-type impurities in the vertical portion 107b to surround the lower portion of the trench. The insulating layer protection zones 115 can be formed to intersect the entire portion of the vertical portion 107b in the Y direction and to be spaced apart from each other in the X direction without being connected to each other. When the lower portions of some trenches 116 are not rounded, the P-type impurity regions 115 can be formed to be located below each trench 116 without completely surrounding the lower portion of the trench 116.

[0141] Subsequently, refer to Figure 19 A gate insulating layer 118 can be formed on the bottom surface and side surfaces of each trench 116. The gate insulating layer 118 can be formed on the semiconductor layer 105, which is outside the trench 116. The gate insulating layer 118 can be formed to include an oxide to oxidize the semiconductor layer 105, or it can be formed by depositing an insulating material such as an oxide or a nitride on the semiconductor layer 105.

[0142] Subsequently, gate electrode layers 120R and 120P can be formed on the gate insulating layer 118, thereby burying the trench 116. For example, gate electrode layers 120R and 120P may include a recessed gate electrode 120R and a plate-shaped gate electrode 120P, wherein the recessed gate electrode 120R is formed to be buried in the trench 116, and the plate-shaped gate electrode 120P is arranged in a plate form to connect multiple recessed gate electrodes 120R to each other while covering the channel region 110a. Therefore, the plate-shaped gate electrode 120P and the recessed gate electrode 120R can be formed in the form of a "∩" to surround the three surfaces (top surface and opposite side surfaces) of the vertical portion 107b of the drift region 107, the source region 112, and the channel region 110a. The gate electrode layer 120 can be formed by implanting impurities into polysilicon, or it can be formed to include a conductive metal or a metal silicide.

[0143] The lower part of the recessed gate electrode 120R can be formed to be surrounded by a well region 110 of the second conductivity type and an insulating layer protection zone 115, thereby preventing dielectric breakdown of the gate insulating layer 118 caused by electric field concentration at the corner of the gate insulating layer 118.

[0144] Subsequently, an interlayer insulating layer 130 can be formed on the plate-shaped gate electrode 120P, and a source electrode layer 140 can be formed on the interlayer insulating layer 130. For example, the source electrode layer 140 may include a conductive layer, such as a metal layer.

[0145] Figure 20 This is a schematic perspective view illustrating the structure of a power semiconductor device according to another embodiment of the present disclosure; Figure 21 It shows along Figure 20 A sectional view of the structure cut by line A-A'. Figures 22 to 24 It shows along Figure 21 The longitudinal sectional view of the structure intercepted by lines B-B', C-C', and D-D'.

[0146] Reference Figures 20 to 24 The power semiconductor device 200 may include a semiconductor layer 205, a gate insulating layer 218, a gate electrode layer 220, an interlayer insulating layer 230, and a source electrode layer 240. For example, the power semiconductor device 200 may have a power MOSFET structure.

[0147] Semiconductor layer 205 may include at least one semiconductor material layer. For example, semiconductor layer 205 may include one or more epitaxial layers. Alternatively, semiconductor layer 205 may include a single epitaxial layer or multiple epitaxial layers formed on a semiconductor substrate. For example, semiconductor layer 205 may include silicon carbide (SiC). Alternatively, semiconductor layer 205 may include at least one SiC epitaxial layer.

[0148] Because silicon carbide (SiC) has a higher band gap than silicon (Si), it maintains stability even at higher temperatures compared to Si. Furthermore, SiC exhibits a significantly higher dielectric breakdown electric field than Si. Therefore, SiC can operate stably even at higher voltages. Thus, compared to Si, the power semiconductor device 200 having a semiconductor layer 205 including silicon carbide (SiC) can exhibit superior heat dissipation characteristics, a higher breakdown voltage, and stable operating characteristics at higher temperatures.

[0149] Semiconductor layer 205 may include drift region 207, N-pillar region 211N, and P-pillar region 211P. In the following text, N-pillar region 211N and P-pillar region 211P may be referred to as the first pillar region and the second pillar region, respectively.

[0150] Drift region 207 and N-pillar region 211N can be formed as a first conductivity type (N-type) and can be formed by implanting impurities of the first conductivity type into a portion of semiconductor layer 205. For example, drift region 207 and N-pillar region 211N can be formed by implanting impurities of the first conductivity type into a SiC epitaxial layer. The impurity doping concentration of drift region 207 can be equal to the impurity doping concentration of N-pillar region 211N. Drift region 207 and N-pillar region 211N can be formed together by the same process (e.g., impurity implantation process) or by separate processes.

[0151] Drift regions 207 can be formed between recessed gates 220R and spaced apart from each other in the X direction, such that opposite sides of the drift regions 207 in the X direction contact the gate insulating layer 218. Each drift region 207 can be formed such that opposite sides of the drift region 207 in the Y direction contact the well region 210. Each drift region 207 can be formed to extend in the Z direction to provide a vertical current movement path.

[0152] The N-pillar region 211N can be positioned below the well region 210 and the drift region 207, such that the top surface of the N-pillar region 211N contacts the well region 210 and the drift region 207. For example, the N-pillar region 211N can be formed to extend longitudinally in the Y direction, such that the top surface of the N-pillar region 211N contacts the drift region 207 and the well region 210 located on opposite sides of the drift region 207.

[0153] The N-pillar regions 211N, together with the drift region 207, provide a path for current movement. In other words, the top surface of each N-pillar region 211N is connected to a corresponding portion of the bottom surface of the drift region 207. Therefore, when the semiconductor device 200 is operating, current can flow through the N-pillar regions 211N and the drift region 207 in the vertical direction (Z direction).

[0154] P-pillar region 211P can be formed as a second conductivity type (P-type) opposite to the first conductivity type. P-pillar region 211P can be positioned between N-pillar regions 211N such that opposite sides of P-pillar region 211N contact N-pillar regions 211N in the X direction. P-pillar region 211P can be formed to extend longitudinally in the Y direction in the same form as N-pillar regions 211N. For example, P-pillar regions 211P and N-pillar regions 211N can be formed alternately and continuously, while contacting each other in the X direction. Each P-pillar region 211P can be positioned below the well region 210 and the recessed gate 220R. For example, P-pillar region 211P can be formed to contact the well region 210 and the drift region 207, while surrounding the lower portion of the trench 216 in which the recessed gate 220R is formed (the region forming the edge of the P-pillar region 211P). P-pillar region 211P can be formed to contact drift region 207 and N-pillar region 211N to form a superjunction with drift region 207 and N-pillar region 211N.

[0155] In semiconductor layer 205, well region 210 can be formed having a side surface in contact with drift region 207 and a bottom surface in contact with N-pillar region 211N and P-pillar region 211P. Well region 210 may include impurities of the same second conductivity type as the impurities in P-pillar region 211P. For example, well region 210 can be formed by implanting impurities of the second conductivity type into the SiC epitaxial layer. The impurity doping concentration of well region 210 can be equal to or higher than the impurity doping concentration of P-pillar region 211P.

[0156] The well region 210 may be located between the recessed gates 220R and may be positioned on opposite sides of the drift region 207 in the Y direction. Each well region 210 may include a channel region 210a. Although according to this embodiment the well region 210 is only located between the recessed gates 220R, the well region 210 may be as follows: Figure 27 The regions shown are integrally connected to each other at a location extending further along the Y direction (the outer portion of the recessed gate in the Y direction). Furthermore, the interconnected well regions 210 can be formed to surround the drift region 107 in an all-around configuration.

[0157] Source region 212 can be formed in well region 210 and can be formed of a first conductivity type. For example, source region 212 can be formed on opposite sides of drift region 207 to be spaced apart from drift region 207 in each well region 210, and can be formed by implanting impurities of the first conductivity type into well region 210. The impurity doping concentration of source region 212 can be higher than that of drift region 207 and N-pillar region 211N.

[0158] Although, according to this embodiment, the source region 212 is located only between the recessed gates 220R, the source region 212 can be described as follows: Figure 27As shown, they are integrally connected to each other at a location extending further along the Y direction (the outer portion recessed into the gate). Furthermore, when the well region 210 is formed to surround the drift region 207 in a fully encircling shape, the source regions 212 connected to each other can also be formed to surround the drift region 207 in a fully encircling shape.

[0159] In the well region 210, a channel region 210a can be positioned between the drift region 207 and the source region 212. The channel region 210a can include impurities of the same second conductivity type as the well region 210. Because the channel region 210a includes impurities of the second conductivity type opposite to that of the source region 212 and the drift region 207, the channel region 210a can form a diode junction together with the source region 212 and the drift region 207. Therefore, because the channel region 210a does not allow charge movement when the power semiconductor device 200 is not operating, the channel region 210a can electrically isolate the drift region 207 from the source region 212. Conversely, when an operating voltage is applied to the gate electrode layer 220, the channel region 210a allows charge movement because an inversion channel is formed inside the channel region 210a. Therefore, the channel region 210a can electrically connect the drift region 207 to the source region 212.

[0160] Although Figure 20 Channel region 210a is shown as distinct from well region 210, but channel region 210a can be some of the well region 210. Channel region 210a can correspond to the region in well region 210 located between drift region 207 and source region 212. The impurity doping concentration of channel region 210a can be equal to or different from the impurity doping concentration of well region 210 to adjust the threshold voltage.

[0161] According to an embodiment, the well region 210, the channel region 210a, and the source region 212 may be formed symmetrically about the drift region 207 in the Y direction. For example, each of the well region 210, the channel region 210a, and the source region 212 may include a first portion and a second portion located on opposite sides of the drift region 207 in the Y direction. The well region 210 and the source region 212 may be separated from each other by the drift region 207, or they may be connected to each other to surround the drift region 207.

[0162] Furthermore, drain region 202 may be formed in semiconductor layer 205 beneath pillar regions 211N and 211P and may include impurities of a first conductivity type. For example, drain region 202 may include impurities of a first conductivity type implanted at a doping concentration higher than that of the first conductivity type impurities in N pillar region 211N and drift region 207.

[0163] According to an embodiment, the drain region 202 can be configured as a SiC substrate of a first conductivity type. In this case, the drain region 202 can be formed as part of the semiconductor layer 205 or as a substrate separate from the semiconductor layer 205.

[0164] At least one trench 216 may be formed to be recessed from the surface of the semiconductor layer 205 into the semiconductor layer 205 to a specific depth. The at least one trench 216 may include a plurality of trenches spaced apart from each other in the X direction. The trench 216 may extend parallel to each other for a specific length in the Y direction, such that the trench 216 contacts the drift region 207 in the semiconductor layer 205 and the channel region 210a and source region 212 located on opposite sides of the drift region 207.

[0165] Channel regions 210a can be positioned between grooves 216. Drift regions 207 can be spaced apart from each other by the grooves 216. According to an embodiment, drift regions 207 can be provided as separators between the grooves 216, and channel regions 210a can be symmetrically positioned relative to each other on opposite sides of each drift region 207 in the Y direction. Source region 212 can be positioned on one side of channel region 210a.

[0166] A gate insulating layer 218 may be formed on at least the inner surface (side surface and bottom surface) of the trench 216. For example, the gate insulating layer 218 may be formed on the inner surface of the trench 216 and on the semiconductor layer 205 outside the trench 216. The overall thickness of the gate insulating layer 218 may be uniform, or the portion of the gate insulating layer 218 formed on the bottom surface of the trench 216 may be thicker than the portion of the gate insulating layer 218 formed on the side surface of the trench 216, thereby reducing the electric field at the bottom surface of the trench 216.

[0167] The gate insulating layer 218 may include an insulating material, such as silicon oxide, SiC oxide, silicon nitride, hafnium oxide, zirconium oxide, or aluminum oxide, or a stacked structure thereof.

[0168] A gate electrode layer 220 may be formed on the gate insulating layer 218 to fill the trench 216. Alternatively, the gate electrode layer 220 may be formed on the gate insulating layer 218 on the semiconductor layer 205 to at least cover the channel region 210a. For example, the gate electrode layer 220 may include a plurality of recessed gate electrodes 220R spaced apart from each other in the X direction and formed to be buried in the trench 216. Furthermore, the gate electrode layer 220 may include a plate-shaped gate electrode 220P, which is disposed on the semiconductor layer 205 in a plate-like form to connect the plurality of recessed gate electrodes 220R to each other while simultaneously covering the channel region 210a.

[0169] According to this embodiment, the power semiconductor device 200 may have a structure disposed between a plurality of recessed gate electrodes 220R below the plate-shaped gate electrode 220P, wherein the source region 212, the channel region 210a, and the drift region 207 are connected to each other in the Y direction. For example, the channel region 210a is disposed between the recessed gate electrodes 220R such that the channel region 210a contacts the opposite side surface of the drift region 207 in the Y direction, and the source region 212 may be formed to be connected to a side surface of each channel region 210a. When the power semiconductor device 200 is operated, the interconnected drift region 207, channel region 210a, and source region 212 can serve as a current flow path.

[0170] As described above, according to this embodiment, the power semiconductor device 200 includes a polygonal channel structure with current movement paths, wherein the drift region 207, the channel region 210a, and the source region 212 are interconnected and formed between a plurality of gate electrodes 220R, allowing more charges to move simultaneously. Furthermore, along the current movement paths, the gate electrode layer 220 is formed around three surfaces (the top surface and the opposing surface in the X direction) surrounding the drift region 207, the channel region 210a, and the source region 212, allowing more charges to move simultaneously. The gate electrode layer 220 may include a conductive material, such as polysilicon, metal, metal nitride, or metal silicide, or may include a stacked structure thereof.

[0171] Interlayer insulating layer 230 may be formed on gate electrode layer 220. Interlayer insulating layer 230 may include insulating material for electrical insulation between gate electrode layer 220 and source electrode layer 240, such as oxide layer, nitride layer or stacked structure thereof.

[0172] The source electrode layer 240 may be formed on the interlayer insulating layer 230 and may be electrically connected to the source region 212. The source electrode layer 240 may include a conductive material such as a metal.

[0173] Although the above description states that the first and second conductivity types are N-type and P-type according to the above embodiments, the first and second conductivity types can be both P-type and N-type. More specifically, when the power semiconductor device 200 is an N-type MOSFET, the drift region 207 and the N-pillar region 211N can be N-regions, the source region 212 and the drain region 202 can be N+regions, and the well region 210, the P-pillar region 211P, and the channel region 210a can be P-regions.

[0174] According to this embodiment, in the power semiconductor device 200, when current flows from the drain region 202 to the source region 212, the current can flow in the vertical direction (Z direction) along the N-pillar region 211N and the drift region 207, and flow to the source region 212 through the channel region 210a.

[0175] In the power semiconductor device 200 according to this embodiment, the recessed gates 220R in the trench 216 can be densely arranged in parallel as strips or lines, and the channel region 210a can be placed between the recessed gates 220R, thereby increasing the channel density.

[0176] When an operating voltage is applied to the gate electrode layer 220, the electric field can concentrate at the lower corner of the recessed gate 220R. When the electric field is concentrated, the gate insulating layer 218 in the relevant region may be subjected to severe stress, which may lead to dielectric breakdown of the gate insulating layer 218. Furthermore, in the power semiconductor device 200 according to this embodiment, the P-pillar region 211P can be formed around the lower part of the trench 216, thereby reducing the electric field concentration at the lower corner of the gate electrode layer 220 and preventing dielectric breakdown of the gate insulating layer 218.

[0177] In the power semiconductor device 200 according to this embodiment, the width (length in the X direction) of the N-pillar region 211N, which serves as the current travel path, is narrowed due to the P-pillar region 211P, thereby increasing the resistance (JFET resistance). However, in the power semiconductor device 200 according to this embodiment, as... Figure 6 As shown, the JFET resistance can be reduced by adjusting the amount of charge in the P-pillar region 211P and the amount of charge in the N-channel region 211N.

[0178] Figure 25 This is a schematic perspective view illustrating the structure of a power semiconductor device according to another embodiment of the present disclosure.

[0179] The power semiconductor device 200a according to this embodiment is partially modified as follows: Figures 20 to 24 The power semiconductor device 200 shown is formed based on its structure. Therefore, repeated descriptions of the structure will be omitted to avoid redundancy.

[0180] Reference Figure 25 In the power semiconductor device 200a according to this embodiment, the plate-shaped gate 220P' can be configured as follows: Figure 8 and Figure 9 The form shown is a separate form rather than a single flat plate.

[0181] However, according to this embodiment, the plate-shaped gate 220P' can be provided without a gate electrode layer on the drift region 207. In other words, the gate electrode layer 220 with respect to the drift region 207 has the form in which the recessed gate 220R exists only on the opposite sidewalls of the drift region 207, and with respect to the channel region 210a and the source region 212, it can have the form in which the recessed gate 220R and the plate-shaped gate 220P' surround the three surfaces of the channel region 210a and the source region 212 in an inverted U-shape.

[0182] Figure 26This is a schematic perspective view illustrating the structure of a power semiconductor device according to another embodiment of the present disclosure.

[0183] The power semiconductor device 200b according to this embodiment is partially modified as follows: Figures 20 to 24 The power semiconductor device 200 shown is formed based on its structure. Therefore, repeated descriptions of the structure will be omitted to avoid redundancy.

[0184] Reference Figure 26 According to this embodiment, the power semiconductor device 200b may have a source region 212' formed in contact with the drift region 207. The source region 212' may include impurities of the same first conductivity type as the source region 212.

[0185] In the structure of the SiC semiconductor layer 205, the negative charge generated when forming carbon clusters on the gate insulating layer 218 creates a potential barrier in the current movement path, thereby blocking current flow. Therefore, as in this embodiment, even if the source region 212' is formed to contact the drift region 207, an accumulation channel can be formed to allow current flow when an operating voltage is applied to the gate electrode layer 220. In this case, the operating voltage can be significantly lower than that used for... Figure 19 The operating voltage of the inverse channel is formed in the channel region 210a.

[0186] Figure 27 This is a schematic perspective view illustrating the structure of a power semiconductor device according to another embodiment of the present disclosure. Figure 28 It shows along Figure 27 A sectional view of the structure cut by line E-E'. Figures 29 to 31 It shows along Figure 28 The longitudinal sectional view of the structure cut by lines F-F', G-G' and H-H'.

[0187] According to this embodiment, the power semiconductor device 200c is achieved by employing or partially modifying... Figure 20 It is formed by power semiconductor devices 200. Therefore, repeated descriptions will be omitted to avoid redundancy.

[0188] Reference Figures 27 to 31 The power semiconductor device 200c may include at least one gate region GR1 or GR2 and a contact region CR.

[0189] The gate regions GR1 and GR2, including the gate electrode layer 220, may include, as described above, the following: Figure 20 , Figure 25 or Figure 26 The structure shown. Figure 27 The gate regions GR1 and GR2 are shown to include, as follows Figure 20 An embodiment of the structure shown is presented. Therefore, details of the gate regions GR1 and GR2 will be omitted.

[0190] The contact region CR used to connect the source region 212 of the gate regions GR1 and GR2 to the source electrode layer 240 can be located between the gate regions GR1 and GR2. When the power semiconductor device 200c includes only one gate region GR1 or GR2, the contact region CR can be located on one side of the relevant gate region GR1 or GR2.

[0191] The contact region CR may include an N-pillar region 211N, a P-pillar region 211P, a well region 210, a source contact region 212a, a well contact region 214, and a source electrode layer 240.

[0192] The N-pillar region 211N and P-pillar region 211P of the contact region CR can be integrally formed with the N-pillar region 211N and P-pillar region 211P of each of the gate regions GR1 and GR2. For example, the N-pillar region 211N and P-pillar region 211P can extend longitudinally in the Y direction across the gate regions GR1 and GR2 and the contact region CR.

[0193] The well region 210 of the contact region CR can be formed integrally with the well regions 210 of the gate regions GR1 and GR2. For example, the well regions 210 of the gate regions GR1 and GR2 can extend into the contact region CR in the Y direction, and the extended well regions 210 can be connected together and integrally to the outside of the recessed gate 220R.

[0194] Source contact region 212a is used to connect source region 212 to source electrode layer 240. Source contact region 212a can be integrally formed with source regions 212 of gate regions GR1 and GR2. For example, source regions 212 of gate regions GR1 and GR2 can extend in the Y direction to contact region CR, and the extended source regions 212 can be commonly and integrally connected to the outside of recessed gate 220R. In this case, the portion commonly and integrally connected to the outside of recessed gate 220R can be source contact region 212a. Therefore, source contact region 212a can be a part of source region 212. Source region 212 can be electrically connected to source electrode layer 240 through source contact region 212a.

[0195] The sink contact region 214 may be formed within the source contact region 212a. For example, the sink contact region 214 may extend from the sink region 210 through the source contact region 212a. The sink contact region 214 may be formed within one or more source contact regions 212a.

[0196] The well contact region 214 may include impurities of a second conductivity type. For example, the well contact region 214 may be doped with impurities of a second conductivity type at a higher concentration than that of the well region 210 to reduce the contact resistance when connected to the source electrode layer 240. For example, the well contact region 214 may be a P+ region.

[0197] The source electrode layer 240 of the contact region CR can be integrally connected with the source electrode layers 240 of the gate regions GR1 and GR2. The source electrode layers 240 can be jointly connected to the source contact region 212a and the well contact region 214.

[0198] The plate-shaped gate electrode 220P of each of the gate regions GR1 and GR2 can be formed to extend in the Y direction to the boundary region between the contact region CR and each of the gate regions GR1 and GR2. For example, as Figure 27 As shown, the plate-shaped gate electrode 220P can extend more longitudinally in the Y direction, so that the plate-shaped gate electrode 220P is closer to the contact area CR compared to the recessed gate electrode 220R.

[0199] Although Figures 27 to 31 The diagram shows that the source contact region 212a and the well contact region 214 are formed only on one side of each drift region 207. However, when the source region 212 and the well region 210 are divided by the drift region 207, the source contact region 212a and the well contact region 214 can be formed on opposite sides of the drift region 207. For example, when the source region 212 and the well region 210 located on opposite sides of the drift region 207 are electrically connected to each other, as... Figure 27 As shown, the contact region CR can be formed only on one side of the drift region 207. Conversely, when the source region 212 and the well region 210 located on opposite sides of the drift region 207 are electrically isolated from each other, the contact region CR can be formed on opposite sides of the drift region 207.

[0200] because Figure 27 The power semiconductor device 200c may include two gate regions GR1 and GR2 and a contact region CR formed between the gate regions GR1 and GR2, thus the contact region CR is connected to both gate regions GR1 and GR2. However, the power semiconductor device 200c may also include a gate region GR1 or GR2 and a contact region CR formed on one side of the gate region GR1 or GR2. In this case, the contact region CR may be formed on one side of the gate region GR1 or GR2 in the X direction or Y direction.

[0201] Furthermore, the power semiconductor device 200c may include a plurality of gate regions and a plurality of contact regions disposed between the gate regions. For example, the power semiconductor device 200c may include at least three gate regions arranged to be spaced apart from each other by a specific distance in the Y direction, and a plurality of contact regions, each contact region being disposed between adjacent gate regions. In this case, the structure of the adjacent gate regions and the contact regions disposed between the adjacent gate regions can be similar to... Figures 27 to 31 The structures are the same.

[0202] Figures 32 to 34 This is a perspective view schematically illustrating a method for creating an insulating layer protection zone surrounding the lower portion of a recessed gate.

[0203] Reference Figure 32 A mask pattern 305 can be formed on a semiconductor layer 303 implanted with impurities of a first conductivity type to define a region for a trench for a recessed gate. In this case, the mask pattern 305 may include a photoresist layer pattern. For example, after forming a photoresist layer on the semiconductor layer 303, a mask pattern 305 for exposing the surface of the trench region for a recessed gate can be formed on the semiconductor layer 303 by performing an exposure process and a development process.

[0204] Semiconductor layer 303 may include at least one semiconductor material layer. For example, semiconductor layer 303 may include one or more epitaxial layers. Alternatively, semiconductor layer 303 may include a single epitaxial layer or multiple epitaxial layers formed on a semiconductor substrate. For example, semiconductor layer 303 may include silicon carbide (SiC). Alternatively, semiconductor layer 303 may include at least one SiC epitaxial layer. When an operating current is applied to gate electrode layer 320, semiconductor layer 303 can provide a current flow path.

[0205] Subsequently, by using mask pattern 305 as an ion implantation barrier layer, impurities of the second conductivity type can be implanted into semiconductor layer 303 to form sacrificial impurity region 315' in semiconductor layer 303. Sacrificial impurity region 315' can be formed deeper than the gate trench to be formed in subsequent processes, and the lower portion of sacrificial impurity region 315' can be formed to have a width greater than the width of the gate trench. For example, by adjusting the implantation angle when implanting impurities, sacrificial impurity region 315' can be formed such that the width of the lower region of sacrificial impurity region 315' is greater than the width of the upper region of sacrificial impurity region 315', similar to the shape of a light bulb.

[0206] Next, refer to Figure 33 The trench 316 for the gate and the insulating layer protection zone 315 can be formed by etching the semiconductor layer 303 to a specific depth using a mask pattern 305 as an etch barrier layer. In this case, the trench 316 can be formed such that the bottom surface of the trench 316 is higher than the bottom surface of the sacrificial impurity region 315'. For example, because the photoresist layer pattern used as an ion implantation barrier layer is used as an etch barrier layer, the semiconductor layer 303 is etched to a depth shallower than the bottom surface of the sacrificial impurity region 315'. Therefore, the area for the trench 316 can be removed from the sacrificial impurity region 315', and only the area of ​​the sacrificial impurity region 315' surrounding the lower corner region of the trench 316 is retained to form the insulating layer protection zone 315.

[0207] As mentioned above Figure 18As shown, after a trench is first formed in the semiconductor layer 303, impurities are implanted into the lower part of the trench. Impurities reflected from the inner surface of the trench can be implanted into the outer portion of the trench sidewalls. In other words, regions of impurities with a second conductivity type are even formed on the outer portion of the trench sidewalls and in the lower part of the trench, thereby severely interrupting the flow of current. Therefore, according to this embodiment, after impurities are first implanted into the semiconductor layer 303, a trench 316 is formed such that the lower part of the trench remains in the relevant impurity region.

[0208] Subsequently, refer to Figure 34 A gate insulating layer 318 can be formed on the bottom and side surfaces of each trench 316. The gate insulating layer 318 can be formed on the semiconductor layer 303, which serves as the exterior of the trench 316. The gate insulating layer 318 can be formed by including an oxide to oxidize the semiconductor layer 303, or it can be formed by depositing an insulating material such as an oxide or nitride on the semiconductor layer 303. The overall thickness of the gate insulating layer 318 can be uniform, or the portion of the gate insulating layer 318 formed on the bottom surface of the trench 316 can be thicker than the portion of the gate insulating layer 318 formed on the sidewalls of the trench 316, such that the electric field is reduced at the bottom of the trench 316.

[0209] Subsequently, a gate electrode layer 320 can be formed by depositing a gate electrode material on the gate insulating layer 318, thereby creating a buried trench 316. The gate electrode layer 320 can be formed by implanting impurities into polysilicon, or it can be formed to include a conductive metal or a metal silicide.

[0210] Figures 35 to 38 This is a perspective view schematically illustrating a method for manufacturing an insulating layer protection zone surrounding the lower portion of a recessed gate, according to another embodiment of this disclosure.

[0211] Reference Figure 35 A mask pattern 405 can be formed on a semiconductor layer 403 implanted with impurities of a first conductivity type to define a region for a trench used as a gate. In this case, the mask pattern 403 may include a photoresist layer pattern. For example, after a photoresist layer is formed on the semiconductor layer 403, a mask pattern 405 for exposing the surface of the trench region for the gate can be formed on the semiconductor layer 403 by performing an exposure process and a development process.

[0212] Semiconductor layer 403 may include at least one semiconductor material layer. For example, semiconductor layer 403 may include one or more epitaxial layers. Alternatively, semiconductor layer 403 may include a single epitaxial layer or multiple epitaxial layers formed on a semiconductor substrate. For example, semiconductor layer 403 may include silicon carbide (SiC). Alternatively, semiconductor layer 403 may include at least one SiC epitaxial layer.

[0213] Subsequently, by using mask pattern 405 as an ion implantation barrier layer, impurities of the second conductivity type can be implanted into semiconductor layer 403 at a higher concentration to form a sacrificial impurity region 415' in semiconductor layer 403. The first sacrificial impurity region 415' can be formed to be deeper than the gate trench to be formed in subsequent processes, and the lower part of the first sacrificial impurity region 415' can be formed to have a width greater than the width of the gate trench.

[0214] However, when impurities are implanted at a higher concentration, the first sacrificial impurity region 415' can be formed over a wider area than the region of the gate trench to be formed in a subsequent process due to impurity diffusion. For example, the first sacrificial impurity region 415' may not be formed only around the lower part of the gate trench to be formed in a subsequent process, but may be formed to have a size that completely surrounds the gate trench. In this case, the resistance in the current movement path (JFET resistance) may increase significantly when the power semiconductor device is operating.

[0215] Next, refer to Figure 36 To prevent the increase in resistance caused by impurity diffusion, a mask pattern 405 is used as an ion implantation barrier layer to implant impurities of the first conductivity type into the semiconductor layer 403. For example, a second sacrificial impurity region 415' can be formed by implanting impurities of the first conductivity type into the semiconductor layer 403, such that only the lower part of the first sacrificial impurity region 415' is retained to a specific height, while the remaining part of the first sacrificial impurity region 415' is removed.

[0216] Next, refer to Figure 37 The trench 416 for the gate and the insulating layer protection zone 415 can be formed by etching the semiconductor layer 403 and the second sacrificial impurity region 415" using a mask pattern 405 as an etch barrier layer. In this case, the bottom surface of the trench 416 for the gate is lower than the top surface of the second sacrificial impurity region 415" and higher than the bottom surface of the second sacrificial impurity region 415".

[0217] For example, a photoresist layer pattern used as an ion implantation barrier layer is used as an etch barrier layer to form a trench 416 for the gate. In this case, the trench 416 for the gate can be formed to a depth to which the lower part (lower corner) of the trench 416 is surrounded by a second sacrificial impurity region 415".

[0218] When impurities are injected into the trench, after the trench is first formed in the semiconductor layer 403, impurities reflected from the inner surface of the trench may be injected into the outer portion of the trench sidewalls, such that the region of impurities with the second conductivity type only surrounds the lower part of the trench 416. In other words, the region of impurities with the second conductivity type is even formed on the outer portion of the trench sidewalls and the lower part of the trench, thereby severely interrupting the flow of current. Therefore, according to this embodiment, after the insulating layer protection zone 415 is first formed on the semiconductor layer 403, the trench 416 for the gate is formed.

[0219] Subsequently, refer to Figure 38 A gate insulating layer 418 can be formed on the bottom and side surfaces of each trench 416 for the gate. The gate insulating layer 418 can be formed on a semiconductor layer 403, which serves as the exterior of the trench 416. The gate insulating layer 418 can be formed comprising an oxide formed by oxidizing the semiconductor layer 403, or it can be formed by depositing an insulating material such as an oxide or nitride on the semiconductor layer 403. The overall thickness of the gate insulating layer 418 can be uniform, or the portion of the gate insulating layer 418 formed on the bottom surface of the trench 416 can be thicker than the portion of the gate insulating layer 418 formed on the sidewalls of the trench 416, thereby reducing the electric field at the bottom of the trench 316.

[0220] Subsequently, a gate electrode layer 420 can be formed by depositing a gate electrode material on the gate insulating layer 418 to bury the trench 416 for the gate. The gate electrode layer 420 can be formed by implanting impurities into polysilicon, or it can be formed to include a conductive metal or a metal silicide.

[0221] Figures 39 to 43 This is a perspective view schematically illustrating a method for manufacturing an insulating layer protection zone surrounding the lower portion of a recessed gate, according to another embodiment of this disclosure.

[0222] Reference Figure 39 A mask pattern 532 can be formed on the semiconductor layer 510.

[0223] For example, after forming an insulating layer (e.g., an oxide layer) (not shown) over the entire portion of semiconductor layer 510, the insulating layer is patterned to expose the area used to form an insulating layer protected zone, thereby forming a hard mask pattern 532. The patterning of the insulating layer can be performed by a photolithography process.

[0224] In this case, the mask pattern 532 may include a photoresist layer pattern. For example, after a photoresist layer is formed on the semiconductor layer 510, the photoresist layer pattern 532 can be formed by performing an exposure and development process to expose the area for forming an insulating layer protection zone.

[0225] The semiconductor layer 510 may include a structure in which a silicon carbide (SiC) substrate layer 510a and a SiC epitaxial layer 510b, comprising impurities of a first conductivity type, are stacked. The silicon carbide (SiC) substrate layer 510a may include a higher concentration of first conductivity type (N+) impurities, and the epitaxial layer 510b may include a lower concentration of first conductivity type (N-) impurities.

[0226] Subsequently, by using mask pattern 532 as an ion implantation barrier layer, impurities of the second conductivity type are implanted into semiconductor layer 510, forming sacrificial impurity region 512' in semiconductor layer 510. Sacrificial impurity region 512' can be formed deeper than the bottom surface of the trench for the gate to be formed in subsequent processes. Sacrificial impurity region 512' may include a higher concentration of impurities of the second conductivity type (P+).

[0227] However, when a higher concentration of impurities is implanted into the epitaxial layer 510b, the first sacrificial impurity region 512' can be formed over a wider area than the region of the trench where the gate is to be formed in a subsequent process due to impurity diffusion. For example, the first sacrificial impurity region 512' may not be formed only around the lower part of the trench where the gate is to be formed in a subsequent process, but may be formed with dimensions that completely surround the trench used for the gate. In this case, the resistance (JFET resistance) in the current movement path may increase significantly when the power semiconductor device is operating.

[0228] Next, refer to Figure 40 In order to prevent the increase in resistance caused by the diffusion of impurities, mask pattern 532 is used again as an ion implantation barrier layer to implant impurities of the first conductivity type into semiconductor layer 510.

[0229] For example, since the impurity region 514 for impurity removal is formed by implanting an impurity of a first conductivity type into the semiconductor layer 510, the remaining portion of the first sacrificial impurity region 512' except for the lower region is removed, thus a second sacrificial impurity region 512' can be formed. In this case, the impurity region 514 to be removed may include impurities with a concentration higher than that of the epitaxial layer 510b.

[0230] Reference Figure 41 Spacers 534 can be formed on the side surface of the mask pattern 532.

[0231] For example, after conformally forming an insulating layer (not shown) on the mask pattern 532 and the portion of the semiconductor layer 510 exposed by the mask pattern 532, anisotropic etching is performed on the insulating layer of the spacer to expose the surface of the semiconductor layer 510, so that the spacer 534 can be formed on the sidewall of the mask pattern 532.

[0232] Next, refer to Figure 42 The trench 516 for the gate and the insulating layer protection zone 512 can be formed by etching the impurity region 514 to be removed and the second sacrificial impurity region 512” to a specific depth using a mask pattern 532 and spacers 534 as etch barrier layers. In this case, the trench 516 for the gate can be formed such that the bottom surface of the trench 516 is located in the insulating layer protection zone 512.

[0233] According to this embodiment, after the spacer 534 is formed on the side surface of the mask pattern 532, the mask pattern 532 and the spacer 534 are used as an etching barrier layer to form a trench 516 for the gate. Therefore, the trench 516 for the gate can be formed with a width W2 that is narrower than the width W1 of the area exposed by the mask pattern 532.

[0234] When using mask pattern 532 as an etch barrier layer to form trenches for the gate, the first sacrificial impurity region 512' must be formed as described above. Figure 38 The trench width for the gate is such that the insulating layer protection zone 512 fully surrounds the lower corner region of the trench for the gate. In this case, when the spacing between adjacent trenches for the gate is narrow, the first sacrificial impurity regions 512' of the adjacent trenches for the gate engage with each other, which interrupts the movement of current. Therefore, when the spacing between adjacent trenches for the gate is sufficiently wide, the channel density of the power semiconductor device may be reduced.

[0235] Conversely, according to this embodiment, when spacers 534 formed on the side surface of the mask pattern 532 are used, the width W2 of the gate trench 516 can be narrower than the width W1 of the area exposed by the mask pattern 532, thereby increasing the width of the insulating layer protection zone 512. Therefore, the channel density of the power semiconductor device can be increased.

[0236] Subsequently, refer to Figure 43 After removing the mask pattern 532 and spacers 534, a gate insulating layer 522 can be formed on the bottom and side surfaces of each trench 516 for the gate. The gate insulating layer 522 can be formed on the semiconductor layer 510, which serves as the exterior of the trench 516 for the gate.

[0237] The gate insulating layer 522 may be formed as an oxide formed by oxidizing the semiconductor layer 510, or it may be formed by depositing an insulating material such as an oxide or nitride on the semiconductor layer 510. The overall thickness of the gate insulating layer 522 may be uniform, or the portion of the gate insulating layer 522 formed on the bottom surface of the trench 516 may be thicker than the portion of the gate insulating layer 522 formed on the sidewalls of the trench 516, thereby reducing the electric field at the bottom of the trench 516.

[0238] Subsequently, a gate electrode layer 524 can be formed by depositing a gate electrode material on the gate insulating layer 522 to bury the trench 516 for the gate. The gate electrode layer 524 can be formed by implanting impurities into polysilicon, or it can be formed to include a conductive metal or a metal silicide.

[0239] Figure 44 This is a schematic perspective view illustrating the structure of a power semiconductor device according to another embodiment of the present disclosure.

[0240] Reference Figure 44 The power semiconductor device 100c' is structurally similar to the insulating layer protection zone 115'. Figure 10 The power semiconductor device 100c differs from the power semiconductor device 100c'. For example, the insulating layer protection zone 115' of the power semiconductor device 100c' can be formed differently from the one described above. Figure 43 The insulation layer protection zone 512 has the same shape.

[0241] As described above, according to embodiments of the present disclosure, in power semiconductor devices and methods for manufacturing them, the concentration of electric field at the corners of the gate layer can be reduced, the channel resistance can be reduced, and the channel density can be increased, thereby improving integration.

[0242] Of course, these effects are exemplary, and the scope of this disclosure is not limited by these effects.

[0243] However, this is merely an exemplary embodiment, and it will be understood that those skilled in the art can make various modifications and other equivalent embodiments based on this. The scope of protection of this disclosure will be defined by the technical solutions disclosed herein.

[0244] While this disclosure has been described above with reference to exemplary embodiments and accompanying drawings, this disclosure is not limited thereto. Various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of this disclosure as claimed in the technical solutions of this disclosure.

Claims

1. A power semiconductor device, comprising: Semiconductor layer, which is based on silicon carbide (SiC); A vertical drift region is configured to extend vertically within the semiconductor layer and have a first conductivity type; A well region, which is located on both sides of the vertical drift region to contact the vertical drift region in the semiconductor layer and has a second conductivity type opposite to the first conductivity type; Multiple recessed gate electrodes extend from the surface of the semiconductor layer into the semiconductor layer and are buried in the vertical drift region and the well region to intersect the vertical drift region and the well region in a first direction perpendicular to the vertical direction; Multiple source regions, which are positioned in the well region between the multiple recessed gate electrodes and have the first conductivity type; as well as Multiple insulating layer protection zones, each positioned at least below the multiple recessed gate electrodes within the vertical drift region, and having the second conductivity type, The power semiconductor device further includes a plate-shaped gate electrode, which is positioned on the semiconductor layer and connects the plurality of recessed gate electrodes to each other. The plate-shaped gate electrode has a width that is wider than the width of the vertical drift region.

2. The power semiconductor device of claim 1, wherein the insulating layer protection zone surrounds the lower portion of the recessed gate electrode.

3. The power semiconductor device according to claim 1, further comprising: A pillar region, which is positioned in the semiconductor layer below the well region to contact the vertical drift region and the well region, and has the second conductivity type.

4. The power semiconductor device of claim 3, wherein the first region of the vertical drift region has a wider width than the second region of the vertical drift region, the first region is in contact with the pillar region, and the second region is in contact with the well region.

5. The power semiconductor device according to claim 3, further comprising: A horizontal drift region, which is connected to the vertical drift region and positioned below the column region to contact the column region.

6. The power semiconductor device of claim 1, wherein the well region and the source region are positioned on opposite sides of the vertical drift region to be symmetrical about the vertical drift region.

7. The power semiconductor device according to claim 1, further comprising: A source contact region is disposed outside the recessed gate electrode and connected to the plurality of source regions.

8. The power semiconductor device according to claim 7, further comprising: A sink contact region, which is located in the source contact region and connected to the sink region.

9. The power semiconductor device according to claim 8, further comprising: A source electrode layer that is connected to the source contact region and the sink contact region.

10. The power semiconductor device of claim 1, wherein the plurality of recessed gate electrodes are positioned to extend into a portion of the well region while passing through the vertical drift region in a first direction, and are configured to be spaced apart from each other in a second direction intersecting the first direction.

11. The power semiconductor device of claim 1, wherein the plurality of insulating layer protection zones are positioned to intersect the entire portion of the vertical drift region in a first direction and are positioned to be spaced apart from each other in a second direction intersecting the first direction, without being connected to each other.

12. The power semiconductor device of claim 1, wherein the plate-shaped gate electrode is positioned on the semiconductor layer to cover the vertical drift region and the plurality of source regions.

13. The power semiconductor device of claim 1, wherein the plurality of source regions are positioned spaced apart from the vertical drift region.

14. The power semiconductor device of claim 1, wherein the plurality of source regions are positioned in contact with the vertical drift region.

15. A power semiconductor device, comprising: Semiconductor layer, which includes silicon carbide (SiC); A recessed gate electrode extends from the surface of the semiconductor layer into the semiconductor layer; A drift region, which is located in the semiconductor layer between the recessed gate electrodes and has a first conductivity type; A well region, positioned between the recessed gate electrodes on both sides of the drift region to contact the drift region, and having a second conductivity type opposite to the first conductivity type; A source region, which is positioned between the recessed gate electrodes in the well region and has a first conductivity type; A first pillar region is positioned in the semiconductor layer below the drift region and the well region to connect to the drift region and the well region, and has the first conductivity type; as well as A second pillar region, which is connected to the well region in the semiconductor layer, positioned below the recessed gate electrode, and having the second conductivity type, The power semiconductor device further includes a plate-shaped gate electrode, which is positioned on the semiconductor layer and connects the plurality of recessed gate electrodes to each other. The plate-shaped gate electrode has a width that is wider than the width of the drift region.

16. The power semiconductor device of claim 15, wherein the second pillar region surrounds the lower portion of the recessed gate electrode.

17. The power semiconductor device of claim 15, wherein the first pillar region and the second pillar region are alternately arranged in a first direction and are in contact with each other.

18. The power semiconductor device of claim 17, wherein the first pillar region and the second pillar region extend in a second direction intersecting the first direction for a length longer than the recessed gate electrode.

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